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* target/riscv: Add asserts for out-of-bound accessAtish Patra2024-08-061-0/+4
* target/riscv: Relax fld alignment requirementLIU Zhiwei2024-08-061-4/+14
* target/riscv: Add MXLEN check for F/D/Q applies to zama16bLIU Zhiwei2024-08-061-2/+6
* target/riscv: Remove redundant insn length check for zama16bLIU Zhiwei2024-08-063-6/+6
* Merge tag 'pull-tcg-20240723' of https://gitlab.com/rth7680/qemu into stagingRichard Henderson2024-07-231-14/+17
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| * target/riscv: Simplify probing in vext_ldffRichard Henderson2024-07-231-14/+17
* | target/riscv: Restrict semihosting to TCGPhilippe Mathieu-Daudé2024-07-221-2/+2
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* target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSRYu-Ming Chang2024-07-183-9/+58
* target/riscv: Expose the Smcntrpmf configAtish Patra2024-07-181-0/+1
* target/riscv: Do not setup pmu timer if OF is disabledAtish Patra2024-07-181-12/+44
* target/riscv: More accurately model priv mode filtering.Rajnesh Kanwal2024-07-183-4/+33
* target/riscv: Start counters from both mhpmcounter and mcountinhibitRajnesh Kanwal2024-07-182-24/+54
* target/riscv: Enforce WARL behavior for scounteren/hcounterenAtish Patra2024-07-181-2/+10
* target/riscv: Save counter values during countinhibit updateAtish Patra2024-07-183-16/+24
* target/riscv: Implement privilege mode filtering for cycle/instretAtish Patra2024-07-185-37/+194
* target/riscv: Only set INH fields if priv mode is availableAtish Patra2024-07-181-4/+25
* target/riscv: Add cycle & instret privilege mode filtering supportKaiwen Xue2024-07-182-1/+149
* target/riscv: Add cycle & instret privilege mode filtering definitionsKaiwen Xue2024-07-182-0/+35
* target/riscv: Add cycle & instret privilege mode filtering propertiesKaiwen Xue2024-07-182-0/+2
* target/riscv: Fix the predicate functions for mhpmeventhX CSRsAtish Patra2024-07-181-29/+38
* target/riscv: Combine set_mode and set_virt functions.Rajnesh Kanwal2024-07-183-41/+35
* target/riscv/kvm: update KVM regs to Linux 6.10-rc5Daniel Henrique Barboza2024-07-181-0/+2
* target/riscv: Validate the mode in write_vstvecJiayi Li2024-07-181-1/+6
* target/riscv: Expose zabha extension as a cpu propertyLIU Zhiwei2024-07-181-0/+2
* target/riscv: Add amocas.[b|h] for ZabhaLIU Zhiwei2024-07-182-0/+16
* target/riscv: Move gen_cmpxchg before adding amocas.[b|h]LIU Zhiwei2024-07-182-13/+13
* target/riscv: Add AMO instructions for ZabhaLIU Zhiwei2024-07-184-1/+155
* target/riscv: Move gen_amo before implement ZabhaLIU Zhiwei2024-07-182-21/+21
* target/riscv: Support Zama16b extensionLIU Zhiwei2024-07-186-22/+57
* target/riscv: Add zcmop extensionLIU Zhiwei2024-07-186-0/+39
* target/riscv: Add zimop extensionLIU Zhiwei2024-07-185-0/+52
* target: Set TCGCPUOps::cpu_exec_halt to target's has_work implementationPeter Maydell2024-07-113-1/+6
* target/riscv: Apply modularized matching conditions for icount triggerAlvin Chang2024-06-271-1/+1
* target/riscv: Apply modularized matching conditions for watchpointAlvin Chang2024-06-271-20/+6
* target/riscv: Add functions for common matching conditions of triggerAlvin Chang2024-06-271-23/+78
* target/riscv: Remove extension auto-update check statementsFrank Chang2024-06-261-119/+0
* target/riscv: Add Zc extension implied ruleFrank Chang2024-06-261-0/+34
* target/riscv: Add multi extension implied rulesFrank Chang2024-06-261-0/+340
* target/riscv: Add MISA extension implied rulesFrank Chang2024-06-261-1/+49
* target/riscv: Introduce extension implied rule helpersFrank Chang2024-06-261-0/+121
* target/riscv: Introduce extension implied rules definitionFrank Chang2024-06-262-0/+31
* target/riscv: fix instructions count handling in icount modeClément Léger2024-06-261-13/+17
* target/riscv: Fix froundnx.h nanbox checkBranislav Brzak2024-06-261-1/+1
* target/riscv: Support the version for ss1p13Fea.Wang2024-06-262-1/+9
* target/riscv: Reserve exception codes for sw-check and hw-errFea.Wang2024-06-261-0/+2
* target/riscv: Add MEDELEGH, HEDELEGH csrs for RV32Fea.Wang2024-06-262-0/+33
* target/riscv: Add 'P1P13' bit in SMSTATEEN0Fea.Wang2024-06-262-0/+9
* target/riscv: Define macros and variables for ss1p13Fea.Wang2024-06-262-1/+4
* target/riscv: Reuse the conversion function of priv_specJim Shu2024-06-263-10/+6
* target/riscv/kvm: handle the exit with debug reasonChao Du2024-06-261-0/+20
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