| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | target/sparc: Restrict STQF to sparcv9 |   Richard Henderson | 2024-08-20 | 2 | -2/+2 |
| * | sparc/ldst_helper: make range overlap check more readable |   Yao Xingtao | 2024-07-23 | 1 | -3/+2 |
| * | target: Set TCGCPUOps::cpu_exec_halt to target's has_work implementation |   Peter Maydell | 2024-07-11 | 1 | -0/+1 |
| * | target/sparc: use signed denominator in sdiv helper |   Clément Chigot | 2024-06-19 | 1 | -1/+1 |
| * | target/sparc: Enable VIS4 feature bit | Richard Henderson | 2024-06-05 | 1 | -0/+3 |
| * | target/sparc: Implement monitor ASIs | Richard Henderson | 2024-06-05 | 3 | -0/+16 |
| * | target/sparc: Implement MWAIT | Richard Henderson | 2024-06-05 | 2 | -0/+12 |
| * | target/sparc: Implement SUBXC, SUBXCcc | Richard Henderson | 2024-06-05 | 2 | -0/+16 |
| * | target/sparc: Implement FPMIN, FPMAX | Richard Henderson | 2024-06-05 | 2 | -0/+28 |
| * | target/sparc: Implement VIS4 comparisons | Richard Henderson | 2024-06-05 | 4 | -47/+153 |
| * | target/sparc: Implement 8-bit FPADD, FPADDS, and FPADDUS | Richard Henderson | 2024-06-05 | 2 | -0/+20 |
| * | target/sparc: Implement FALIGNDATAi | Richard Henderson | 2024-06-05 | 2 | -3/+31 |
| * | target/sparc: Add feature bit for VIS4 | Richard Henderson | 2024-06-05 | 2 | -0/+3 |
| * | target/sparc: Implement IMA extension | Richard Henderson | 2024-06-05 | 4 | -0/+31 |
| * | target/sparc: Enable VIS3 feature bit | Richard Henderson | 2024-06-05 | 1 | -0/+3 |
| * | target/sparc: Implement XMULX | Richard Henderson | 2024-06-05 | 4 | -0/+19 |
| * | target/sparc: Implement UMULXHI | Richard Henderson | 2024-06-05 | 2 | -0/+9 |
| * | target/sparc: Implement PDISTN | Richard Henderson | 2024-06-05 | 2 | -0/+12 |
| * | target/sparc: Implement MOVsTOw, MOVdTOx, MOVwTOs, MOVxTOd | Richard Henderson | 2024-06-05 | 2 | -0/+42 |
| * | target/sparc: Implement LZCNT | Richard Henderson | 2024-06-05 | 2 | -0/+19 |
| * | target/sparc: Implement LDXEFSR | Richard Henderson | 2024-06-05 | 4 | -2/+17 |
| * | target/sparc: Implement FSLL, FSRL, FSRA, FSLAS | Richard Henderson | 2024-06-05 | 4 | -0/+58 |
| * | target/sparc: Implement FPCMPEQ8, FPCMPNE8, FPCMPULE8, FPCMPUGT8 | Richard Henderson | 2024-06-05 | 4 | -0/+58 |
| * | target/sparc: Implement FPADDS, FPSUBS | Richard Henderson | 2024-06-05 | 2 | -0/+91 |
| * | target/sparc: Implement FPADD64, FPSUB64 | Richard Henderson | 2024-06-05 | 2 | -0/+5 |
| * | target/sparc: Implement FMEAN16 | Richard Henderson | 2024-06-05 | 4 | -0/+53 |
| * | target/sparc: Implement FLCMP | Richard Henderson | 2024-06-05 | 4 | -0/+86 |
| * | target/sparc: Implement FHADD, FHSUB, FNHADD, FNADD, FNMUL | Richard Henderson | 2024-06-05 | 4 | -0/+160 |
| * | target/sparc: Implement FCHKSM16 | Richard Henderson | 2024-06-05 | 4 | -0/+57 |
| * | target/sparc: Implement CMASK instructions | Richard Henderson | 2024-06-05 | 4 | -0/+58 |
| * | target/sparc: Implement ADDXC, ADDXCcc | Richard Henderson | 2024-06-05 | 2 | -0/+17 |
| * | target/sparc: Add feature bits for VIS 3 | Richard Henderson | 2024-06-05 | 2 | -0/+5 |
| * | target/sparc: Implement FMAf extension | Richard Henderson | 2024-06-05 | 6 | -6/+123 |
| * | target/sparc: Use gvec for VIS1 parallel add/sub | Richard Henderson | 2024-06-05 | 1 | -4/+18 |
| * | target/sparc: Remove cpu_fpr[] | Richard Henderson | 2024-06-05 | 1 | -74/+84 |
| * | target/sparc: Remove gen_dest_fpr_D | Richard Henderson | 2024-06-05 | 1 | -16/+11 |
| * | target/sparc: Perform DFPREG/QFPREG in decodetree | Richard Henderson | 2024-06-05 | 2 | -114/+151 |
| * | target/sparc: Fix helper_fmul8ulx16 | Richard Henderson | 2024-06-05 | 1 | -4/+4 |
| * | target/sparc: Fix do_dc | Richard Henderson | 2024-06-05 | 1 | -0/+1 |
| * | target/sparc: Rewrite gen_edge | Richard Henderson | 2024-06-05 | 1 | -61/+37 |
| * | target/sparc: Fix ARRAY8 | Richard Henderson | 2024-06-05 | 1 | -18/+35 |
| * | accel/tcg: Provide default implementation of disas_log | Richard Henderson | 2024-05-15 | 1 | -9/+0 |
| * | Merge tag 'qemu-sparc-20240506' of https://github.com/mcayland/qemu into staging | Richard Henderson | 2024-05-06 | 5 | -189/+208 |
| |\ |
|
| | * | target/sparc: Split out do_ms16b | Richard Henderson | 2024-05-05 | 1 | -54/+24 |
| | * | target/sparc: Fix FPMERGE | Richard Henderson | 2024-05-05 | 3 | -15/+16 |
| | * | target/sparc: Fix FMULD8*X16 | Richard Henderson | 2024-05-05 | 3 | -52/+44 |
| | * | target/sparc: Fix FMUL8x16A{U,L} | Richard Henderson | 2024-05-05 | 3 | -40/+48 |
| | * | target/sparc: Fix FMUL8x16 | Richard Henderson | 2024-05-05 | 3 | -6/+26 |
| | * | target/sparc: Fix FEXPAND | Richard Henderson | 2024-05-05 | 4 | -6/+24 |
| | * | target/sparc/cpu: Avoid spaces by default in the CPU names |   Thomas Huth | 2024-05-05 | 1 | -28/+28 |
