aboutsummaryrefslogtreecommitdiffstats
path: root/target (follow)
Commit message (Expand)AuthorAgeFilesLines
* Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into stagingRichard Henderson2024-07-046-23/+109
|\
| * target/i386/SEV: implement mask_cpuid_featuresPaolo Bonzini2024-07-042-0/+37
| * target/i386: add support for masking CPUID features in confidential guestsPaolo Bonzini2024-07-042-0/+29
| * target/i386: add avx-vnni-int16 featurePaolo Bonzini2024-07-031-1/+1
| * i386/sev: Fallback to the default SEV device if none provided in sev_get_capabilities()Michal Privoznik2024-07-031-5/+5
| * i386/sev: Fix error message in sev_get_capabilities()Michal Privoznik2024-07-031-1/+1
| * target/i386: do not include undefined bits in the AMD topoext leafPaolo Bonzini2024-07-032-0/+7
| * target/i386: SEV: fix formatting of CPUID mismatch messagePaolo Bonzini2024-07-031-3/+3
| * target/i386: drop AMD machine check bits from Intel CPUIDPaolo Bonzini2024-07-031-4/+19
| * target/i386: pass X86CPU to x86_cpu_get_supported_feature_wordPaolo Bonzini2024-07-033-9/+7
* | Merge tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu into stagingRichard Henderson2024-07-032-11/+2
|\ \ | |/ |/|
| * hw/i386/fw_cfg: Add etc/e820 to fw_cfg lateDavid Woodhouse2024-07-032-11/+2
* | Merge tag 'hw-misc-20240702' of https://github.com/philmd/qemu into stagingRichard Henderson2024-07-021-22/+1
|\ \
| * | hvf: Drop ifdef for macOS versions older than 12.0Akihiko Odaki2024-07-021-22/+1
| |/
* | target/arm: Enable FEAT_Debugv8p8 for -cpu maxGustavo Romero2024-07-012-4/+4
* | target/arm: Move initialization of debug ID registersGustavo Romero2024-07-012-3/+30
* | target/arm: Fix indentationGustavo Romero2024-07-011-1/+1
* | target/arm: Delete dead code from disas_simd_indexedRichard Henderson2024-07-011-93/+0
* | target/arm: Convert FCMLA to decodetreeRichard Henderson2024-07-012-170/+74
* | target/arm: Convert FCADD to decodetreeRichard Henderson2024-07-012-23/+13
* | target/arm: Add data argument to do_fp3_vectorRichard Henderson2024-07-011-26/+26
* | target/arm: Convert BFMMLA, SMMLA, UMMLA, USMMLA to decodetreeRichard Henderson2024-07-012-28/+12
* | target/arm: Convert BFMLALB, BFMLALT to decodetreeRichard Henderson2024-07-012-48/+31
* | target/arm: Convert BFDOT to decodetreeRichard Henderson2024-07-012-15/+7
* | target/arm: Convert SUDOT, USDOT to decodetreeRichard Henderson2024-07-012-27/+11
* | target/arm: Convert SDOT, UDOT to decodetreeRichard Henderson2024-07-012-26/+35
* | target/arm: Convert SQRDMLAH, SQRDMLSH to decodetreeRichard Henderson2024-07-014-124/+180
* | target/arm: Fix FJCVTZS vs flush-to-zeroRichard Henderson2024-07-011-9/+9
* | target/arm: Fix SQDMULH (by element) with Q=0Richard Henderson2024-07-011-8/+16
* | target/arm: Fix VCMLA Dd, Dn, Dm[idx]Richard Henderson2024-07-011-2/+2
|/
* target/i386: Advertise MWAIT iff host supportsZide Chen2024-06-302-14/+9
* target/i386/sev: Fix printf formatsRichard Henderson2024-06-281-6/+11
* target/i386/sev: Use size_t for object sizesRichard Henderson2024-06-282-9/+9
* target/i386: SEV: store pointer to decoded id_auth in SevSnpGuestPaolo Bonzini2024-06-281-5/+8
* target/i386: SEV: rename sev_snp_guest->id_authPaolo Bonzini2024-06-281-6/+6
* target/i386: SEV: store pointer to decoded id_block in SevSnpGuestPaolo Bonzini2024-06-281-5/+6
* target/i386: SEV: rename sev_snp_guest->id_blockPaolo Bonzini2024-06-281-6/+6
* target/i386: remove unused enumPaolo Bonzini2024-06-281-16/+0
* target/i386: give CC_OP_POPCNT low bits corresponding to MO_TLPaolo Bonzini2024-06-282-4/+12
* target/i386: use cpu_cc_dst for CC_OP_POPCNTPaolo Bonzini2024-06-284-6/+6
* target/i386: fix CC_OP dumpPaolo Bonzini2024-06-281-63/+64
* target/riscv: Apply modularized matching conditions for icount triggerAlvin Chang2024-06-271-1/+1
* target/riscv: Apply modularized matching conditions for watchpointAlvin Chang2024-06-271-20/+6
* target/riscv: Add functions for common matching conditions of triggerAlvin Chang2024-06-271-23/+78
* target/riscv: Remove extension auto-update check statementsFrank Chang2024-06-261-119/+0
* target/riscv: Add Zc extension implied ruleFrank Chang2024-06-261-0/+34
* target/riscv: Add multi extension implied rulesFrank Chang2024-06-261-0/+340
* target/riscv: Add MISA extension implied rulesFrank Chang2024-06-261-1/+49
* target/riscv: Introduce extension implied rule helpersFrank Chang2024-06-261-0/+121
* target/riscv: Introduce extension implied rules definitionFrank Chang2024-06-262-0/+31
Copyright © 1996 – 2023 Jason A. Donenfeld. All Rights Reverse Engineered.