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* tcg/loongarch64: Fix tcg_out_movi vs some pcrel pointersRichard Henderson2024-06-191-17/+15
* tcg/loongarch64: Enable v256 with LASXRichard Henderson2024-06-192-1/+4
* tcg/loongarch64: Support LASX in tcg_out_vec_opRichard Henderson2024-06-191-84/+135
* tcg/loongarch64: Split out vdvjukN in tcg_out_vec_opRichard Henderson2024-06-191-25/+31
* tcg/loongarch64: Remove temp_vec from tcg_out_vec_opRichard Henderson2024-06-191-5/+4
* tcg/loongarch64: Support LASX in tcg_out_{mov,ld,st}Richard Henderson2024-06-191-0/+19
* tcg/loongarch64: Split out vdvjvk in tcg_out_vec_opRichard Henderson2024-06-191-56/+63
* tcg/loongarch64: Support LASX in tcg_out_addsub_vecRichard Henderson2024-06-191-16/+20
* tcg/loongarch64: Simplify tcg_out_addsub_vecRichard Henderson2024-06-191-14/+15
* tcg/loongarch64: Support LASX in tcg_out_dupi_vecRichard Henderson2024-06-191-1/+6
* tcg/loongarch64: Use tcg_out_dup_vec in tcg_out_dupi_vecRichard Henderson2024-06-191-17/+1
* tcg/loongarch64: Support LASX in tcg_out_dupm_vecRichard Henderson2024-06-191-6/+24
* tcg/loongarch64: Support LASX in tcg_out_dup_vecRichard Henderson2024-06-191-3/+7
* tcg/loongarch64: Simplify tcg_out_dup_vecRichard Henderson2024-06-191-16/+6
* tcg/loongarch64: Support TCG_TYPE_V64Richard Henderson2024-06-192-3/+7
* tcg/loongarch64: Handle i32 and i64 moves between gr and frRichard Henderson2024-06-191-5/+17
* tcg/loongarch64: Use fp load/store for I32 and I64 into vector regsRichard Henderson2024-06-191-26/+10
* tcg/loongarch64: Import LASX, FP insnsRichard Henderson2024-06-191-3542/+1607
* tcg: Introduce TCG_TARGET_HAS_tst_vecRichard Henderson2024-05-221-0/+1
* tcg/loongarch64: Fill out tcg_out_{ld,st} for vector regsRichard Henderson2024-05-151-23/+80
* tcg: Add TCGConst argument to tcg_target_const_matchRichard Henderson2024-02-031-1/+2
* tcg: Introduce TCG_TARGET_HAS_tstRichard Henderson2024-02-031-0/+2
* tcg/loongarch64: Set vector registers call clobberedRichard Henderson2024-02-031-1/+1
* tcg/loongarch64: Fix tcg_out_mov() AbortedSong Gao2023-11-211-0/+3
* tcg: Remove TCG_TARGET_HAS_neg_{i32,i64}Richard Henderson2023-11-061-2/+0
* tcg/loongarch64: Implement neg opcodesRichard Henderson2023-11-062-2/+11
* tcg: Remove TCG_TARGET_HAS_movcond_{i32,i64}Richard Henderson2023-11-061-2/+0
* tcg/loongarch64: Use cpuinfo.hRichard Henderson2023-11-062-11/+5
* tcg/loongarch64: Use C_N2_I1 for INDEX_op_qemu_ld_a*_i128Richard Henderson2023-11-062-7/+12
* tcg/loongarch64: Use tcg_use_softmmuRichard Henderson2023-10-221-65/+61
* tcg: Correct invalid mentions of 'softmmu' by 'system-mode'Philippe Mathieu-Daudé2023-10-071-2/+2
* tcg/loongarch64: Fix buid errorgaosong2023-10-041-33/+35
* tcg: Add tcg_out_tb_start backend hookRichard Henderson2023-09-161-0/+5
* tcg/loongarch64: Implement 128-bit load & storeJiajie Chen2023-09-163-1/+62
* tcg/loongarch64: Lower rotli_vec to vrotriJiajie Chen2023-09-152-1/+22
* tcg/loongarch64: Lower rotv_vec ops to LSXJiajie Chen2023-09-152-1/+15
* tcg/loongarch64: Lower vector shift integer opsJiajie Chen2023-09-152-1/+22
* tcg/loongarch64: Lower bitsel_vec to vbitselJiajie Chen2023-09-153-2/+12
* tcg/loongarch64: Lower vector shift vector opsJiajie Chen2023-09-152-1/+25
* tcg/loongarch64: Lower vector saturated opsJiajie Chen2023-09-152-1/+33
* tcg/loongarch64: Lower vector min max opsJiajie Chen2023-09-152-1/+33
* tcg/loongarch64: Lower mul_vec to vmulJiajie Chen2023-09-152-1/+9
* tcg/loongarch64: Lower neg_vec to vnegJiajie Chen2023-09-152-1/+9
* tcg/loongarch64: Lower vector bitwise operationsJiajie Chen2023-09-153-4/+50
* tcg/loongarch64: Lower add/sub_vec to vadd/vsubJiajie Chen2023-09-153-0/+63
* tcg/loongarch64: Lower cmp_vec to vseq/vsle/vsltJiajie Chen2023-09-153-0/+67
* tcg: pass vece to tcg_target_const_match()Jiajie Chen2023-09-151-1/+1
* tcg/loongarch64: Lower basic tcg vec ops to LSXJiajie Chen2023-09-155-2/+270
* tcg/loongarch64: Import LSX instructionsJiajie Chen2023-09-151-1/+6018
* tcg: Introduce negsetcond opcodesRichard Henderson2023-08-241-0/+3
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