aboutsummaryrefslogtreecommitdiffstats
path: root/tcg (follow)
Commit message (Expand)AuthorAgeFilesLines
* tcg: Map code_gen_buffer with PROT_BTIRichard Henderson2023-09-161-11/+30
* tcg/aarch64: Emit BTI insns at jump landing padsRichard Henderson2023-09-161-15/+39
* tcg: Add tcg_out_tb_start backend hookRichard Henderson2023-09-1611-0/+53
* tcg: Add gvec compare with immediate and scalar operandRichard Henderson2023-09-161-0/+149
* tcg/loongarch64: Implement 128-bit load & storeJiajie Chen2023-09-163-1/+62
* tcg/loongarch64: Lower rotli_vec to vrotriJiajie Chen2023-09-152-1/+22
* tcg/loongarch64: Lower rotv_vec ops to LSXJiajie Chen2023-09-152-1/+15
* tcg/loongarch64: Lower vector shift integer opsJiajie Chen2023-09-152-1/+22
* tcg/loongarch64: Lower bitsel_vec to vbitselJiajie Chen2023-09-153-2/+12
* tcg/loongarch64: Lower vector shift vector opsJiajie Chen2023-09-152-1/+25
* tcg/loongarch64: Lower vector saturated opsJiajie Chen2023-09-152-1/+33
* tcg/loongarch64: Lower vector min max opsJiajie Chen2023-09-152-1/+33
* tcg/loongarch64: Lower mul_vec to vmulJiajie Chen2023-09-152-1/+9
* tcg/loongarch64: Lower neg_vec to vnegJiajie Chen2023-09-152-1/+9
* tcg/loongarch64: Lower vector bitwise operationsJiajie Chen2023-09-153-4/+50
* tcg/loongarch64: Lower add/sub_vec to vadd/vsubJiajie Chen2023-09-153-0/+63
* tcg/loongarch64: Lower cmp_vec to vseq/vsle/vsltJiajie Chen2023-09-153-0/+67
* tcg: pass vece to tcg_target_const_match()Jiajie Chen2023-09-1511-12/+12
* tcg/loongarch64: Lower basic tcg vec ops to LSXJiajie Chen2023-09-155-2/+270
* tcg/loongarch64: Import LSX instructionsJiajie Chen2023-09-151-1/+6018
* Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into stagingStefan Hajnoczi2023-09-071-1/+1
|\
| * configure, meson: remove target OS symbols from config-host.makPaolo Bonzini2023-09-071-1/+1
* | bulk: Do not declare function prototypes using 'extern' keywordPhilippe Mathieu-Daudé2023-08-311-2/+2
|/
* tcg/sparc64: Disable TCG_TARGET_HAS_extr_i64_i32Richard Henderson2023-08-292-12/+1
* tcg: Remove vecop_list check from tcg_gen_not_vecRichard Henderson2023-08-291-4/+3
* tcg: spelling fixesMichael Tokarev2023-08-243-7/+9
* tcg/tcg-op: Document wswap_i64() byte patternPhilippe Mathieu-Daudé2023-08-241-0/+5
* tcg/tcg-op: Document hswap_i32/64() byte patternPhilippe Mathieu-Daudé2023-08-241-7/+18
* tcg/tcg-op: Document bswap64_i64() byte patternPhilippe Mathieu-Daudé2023-08-241-0/+5
* tcg/tcg-op: Document bswap32_i64() byte patternPhilippe Mathieu-Daudé2023-08-241-1/+10
* tcg/tcg-op: Document bswap32_i32() byte patternPhilippe Mathieu-Daudé2023-08-241-0/+5
* tcg/tcg-op: Document bswap16_i64() byte patternPhilippe Mathieu-Daudé2023-08-241-8/+19
* tcg/tcg-op: Document bswap16_i32() byte patternPhilippe Mathieu-Daudé2023-08-241-8/+19
* tcg/i386: Implement negsetcond_*Richard Henderson2023-08-242-10/+26
* tcg/i386: Use shift in tcg_out_setcondRichard Henderson2023-08-241-0/+15
* tcg/i386: Clear dest first in tcg_out_setcond if possibleRichard Henderson2023-08-241-1/+16
* tcg/i386: Use CMP+SBB in tcg_out_setcondRichard Henderson2023-08-241-0/+50
* tcg/i386: Merge tcg_out_movcond{32,64}Richard Henderson2023-08-241-21/+7
* tcg/i386: Merge tcg_out_setcond{32,64}Richard Henderson2023-08-241-17/+7
* tcg/i386: Merge tcg_out_brcond{32,64}Richard Henderson2023-08-241-61/+49
* tcg/sparc64: Implement negsetcond_*Richard Henderson2023-08-242-12/+32
* tcg/s390x: Implement negsetcond_*Richard Henderson2023-08-242-28/+54
* tcg/riscv: Implement negsetcond_*Richard Henderson2023-08-242-2/+47
* tcg/arm: Implement negsetcond_i32Richard Henderson2023-08-242-1/+10
* tcg/aarch64: Implement negsetcond_*Richard Henderson2023-08-242-2/+14
* tcg/ppc: Use the Set Boolean ExtensionRichard Henderson2023-08-241-0/+22
* tcg/ppc: Implement negsetcond_*Richard Henderson2023-08-242-49/+82
* tcg: Use tcg_gen_negsetcond_*Richard Henderson2023-08-242-8/+4
* tcg: Introduce negsetcond opcodesRichard Henderson2023-08-2413-1/+102
* tcg: Unify TCG_TARGET_HAS_extr[lh]_i64_i32Richard Henderson2023-08-2411-22/+12
Copyright © 1996 – 2023 Jason A. Donenfeld. All Rights Reverse Engineered.