UHD: Add wait for flush in DMA FIFO destructor

Prevents failure to ACK on ctrl_iface.  When running back-to-back, the
initialization of the DMA FIFO can issue a clear while the previous
data is still being flushed, which can cause a truncated packet that
can end up locking up the chain and cause failure to ACK control
packets.

1 files changed, 1 insertions, 2 deletions

diff --git a/host/lib/usrp/cores/dma_fifo_core_3000.cpp b/host/lib/usrp/cores/dma_fifo_core_3000.cpp
index db36a336b..14019fa4c 100644
--- a/host/lib/usrp/cores/dma_fifo_core_3000.cpp
+++ b/host/lib/usrp/cores/dma_fifo_core_3000.cpp
@@ -244,8 +244,7 @@ public:
     }
 
     virtual ~dma_fifo_core_3000_impl() {
-        //Clear the FIFO and hold it in that state
-        _fifo_ctrl_reg.write(fifo_ctrl_reg_t::FLUSH_PKTS, 1);
+        flush();
     }
 
     virtual bool flush(uint32_t timeout_ms = 2000) {