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| author |   Wade Fife <wade.fife@ettus.com> | 2022-02-08 14:13:52 -0600 |
|---|---|---|
| committer |   Aaron Rossetto <aaron.rossetto@ni.com> | 2022-04-01 14:36:35 -0500 |
| commit | a1925dd48c57f70781c27b364e6b3d02dc61337c (patch) | |
| tree | 9d02f7650a7ea5647668b655b36b42232efa8554 | |
| parent | fpga: rfnoc: Change AWIDTH default for axi_ram_fifo (diff) | |
| download | uhd-a1925dd48c57f70781c27b364e6b3d02dc61337c.tar.xz uhd-a1925dd48c57f70781c27b364e6b3d02dc61337c.zip | |
fpga: n3xx: Fix DRAM FIFO address alignment
| -rw-r--r-- | fpga/usrp3/top/n3xx/n300_bist_image_core.yml | 4 | ||||
| -rw-r--r-- | fpga/usrp3/top/n3xx/n310_bist_image_core.yml | 4 | ||||
| -rw-r--r-- | fpga/usrp3/top/n3xx/n320_bist_image_core.yml | 4 |
3 files changed, 6 insertions, 6 deletions
diff --git a/fpga/usrp3/top/n3xx/n300_bist_image_core.yml b/fpga/usrp3/top/n3xx/n300_bist_image_core.yml index 0e9d97f55..d4abd6089 100644 --- a/fpga/usrp3/top/n3xx/n300_bist_image_core.yml +++ b/fpga/usrp3/top/n3xx/n300_bist_image_core.yml @@ -43,8 +43,8 @@ noc_blocks: NUM_PORTS: 4 MEM_DATA_W: 64 MEM_ADDR_W: 31 - FIFO_ADDR_BASE: "{30'h06000000, 30'h04000000, 30'h02000000, 30'h00000000}" - FIFO_ADDR_MASK: "{30'h01FFFFFF, 30'h01FFFFFF, 30'h01FFFFFF, 30'h01FFFFFF}" + FIFO_ADDR_BASE: "{31'h06000000, 31'h04000000, 31'h02000000, 31'h00000000}" + FIFO_ADDR_MASK: "{31'h01FFFFFF, 31'h01FFFFFF, 31'h01FFFFFF, 31'h01FFFFFF}" MEM_CLK_RATE: "303819444" # 166.666666 MHz * 21.875 / 4 / 3 = 303.819444 MHz # A list of all static connections in design diff --git a/fpga/usrp3/top/n3xx/n310_bist_image_core.yml b/fpga/usrp3/top/n3xx/n310_bist_image_core.yml index ea228372e..fa6710724 100644 --- a/fpga/usrp3/top/n3xx/n310_bist_image_core.yml +++ b/fpga/usrp3/top/n3xx/n310_bist_image_core.yml @@ -51,8 +51,8 @@ noc_blocks: NUM_PORTS: 4 MEM_DATA_W: 64 MEM_ADDR_W: 31 - FIFO_ADDR_BASE: "{30'h06000000, 30'h04000000, 30'h02000000, 30'h00000000}" - FIFO_ADDR_MASK: "{30'h01FFFFFF, 30'h01FFFFFF, 30'h01FFFFFF, 30'h01FFFFFF}" + FIFO_ADDR_BASE: "{31'h06000000, 31'h04000000, 31'h02000000, 31'h00000000}" + FIFO_ADDR_MASK: "{31'h01FFFFFF, 31'h01FFFFFF, 31'h01FFFFFF, 31'h01FFFFFF}" MEM_CLK_RATE: "303819444" # 166.666666 MHz * 21.875 / 4 / 3 = 303.819444 MHz # A list of all static connections in design diff --git a/fpga/usrp3/top/n3xx/n320_bist_image_core.yml b/fpga/usrp3/top/n3xx/n320_bist_image_core.yml index adf27b34e..95a1b5e68 100644 --- a/fpga/usrp3/top/n3xx/n320_bist_image_core.yml +++ b/fpga/usrp3/top/n3xx/n320_bist_image_core.yml @@ -45,8 +45,8 @@ noc_blocks: NUM_PORTS: 4 MEM_DATA_W: 64 MEM_ADDR_W: 31 - FIFO_ADDR_BASE: "{30'h06000000, 30'h04000000, 30'h02000000, 30'h00000000}" - FIFO_ADDR_MASK: "{30'h01FFFFFF, 30'h01FFFFFF, 30'h01FFFFFF, 30'h01FFFFFF}" + FIFO_ADDR_BASE: "{31'h06000000, 31'h04000000, 31'h02000000, 31'h00000000}" + FIFO_ADDR_MASK: "{31'h01FFFFFF, 31'h01FFFFFF, 31'h01FFFFFF, 31'h01FFFFFF}" MEM_CLK_RATE: "303819444" # 166.666666 MHz * 21.875 / 4 / 3 = 303.819444 MHz # A list of all static connections in design |