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| author |   Martin Braun <martin.braun@ettus.com> | 2020-08-14 10:20:55 +0200 |
|---|---|---|
| committer |   Wade Fife <wade.fife@ettus.com> | 2020-08-17 07:56:30 -0500 |
| commit | 9ed42affcaa88e026cb4f82807e69b546ed30c8c (patch) | |
| tree | 43be74c214866a18d13b6dbb7b49b058b31f0111 | |
| parent | fpga: e310: Fix device in image core YAML (diff) | |
| download | uhd-9ed42affcaa88e026cb4f82807e69b546ed30c8c.tar.xz uhd-9ed42affcaa88e026cb4f82807e69b546ed30c8c.zip | |
fpga: e320: Fix default YAML target to E320_1G
It was set to E320_HG, which is not a valid target, causing build errors
unless -t E320_1G was provided to rfnoc_image_builder.
| -rw-r--r-- | fpga/usrp3/top/e320/e320_rfnoc_image_core.yml | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/fpga/usrp3/top/e320/e320_rfnoc_image_core.yml b/fpga/usrp3/top/e320/e320_rfnoc_image_core.yml index 626bba4a7..57234c19b 100644 --- a/fpga/usrp3/top/e320/e320_rfnoc_image_core.yml +++ b/fpga/usrp3/top/e320/e320_rfnoc_image_core.yml @@ -7,7 +7,7 @@ version: 1.0 # File version rfnoc_version: 1.0 # RFNoC protocol version chdr_width: 64 # Bit width of the CHDR bus for this image device: 'e320' -default_target: 'E320_HG' +default_target: 'E320_1G' |