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| author |   Grant Meyerhoff <grant.meyerhoff@ni.com> | 2023-08-31 10:32:00 -0500 |
|---|---|---|
| committer |   Aki Tomita <121511582+atomita-ni@users.noreply.github.com> | 2023-09-06 10:09:36 -0500 |
| commit | 2b47a83bfa4070ae7497558ca9434d59615c999d (patch) | |
| tree | 82d9d2a3d069555ad2a9957404abe535422266d9 | |
| parent | devtest: remove API calls that now error (diff) | |
| download | uhd-2b47a83bfa4070ae7497558ca9434d59615c999d.tar.xz uhd-2b47a83bfa4070ae7497558ca9434d59615c999d.zip | |
x4xx_bist: replace set_clock_source for x440
set_clock_source for x440 now errors due to potentially decreased spurious performance, the correct way to change clock source now with a new device initialization
| -rw-r--r-- | mpm/python/x4xx_bist | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/mpm/python/x4xx_bist b/mpm/python/x4xx_bist index 125191c4f..f0b73a85a 100644 --- a/mpm/python/x4xx_bist +++ b/mpm/python/x4xx_bist @@ -522,8 +522,14 @@ class X4XXBIST(bist.UsrpBIST): mpm_c.enable_ecpri_clocks(False) # Set the clock source back to internal, as the register values # for locking to the gty_rcv_clk cause the mboard to lose ref_lock - # to the nsync lmk. - mpm_c.set_clock_source('internal') + # to the nsync lmk. For x440 setting clock source must be done + # at device initialization. + if self.product_id == 'x440': + usrp_dev = None + usrp_dev = multi_usrp.MultiUSRP("type=x4xx,addr=localhost,clock_source=internal," + "master_clock_rate={}".format(str(mcr))) + else: + mpm_c.set_clock_source('internal') return result, {"pri_ref_selected": using_pri_ref, "dpll_locked": dpll_lock, |