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author | Martin Anderseck <martin.anderseck@ni.com> | 2023-09-04 16:52:05 +0200 |
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committer | Aki Tomita <121511582+atomita-ni@users.noreply.github.com> | 2023-09-06 18:39:25 -0500 |
commit | 512f6787d8ce9d47a0140bf0c5d6a57fd5dd7bf1 (patch) | |
tree | 494bbfaa8bb4177d9a1741bcf7d20db368407131 | |
parent | SelfCal: improve fbx input spur performance (diff) | |
download | uhd-512f6787d8ce9d47a0140bf0c5d6a57fd5dd7bf1.tar.xz uhd-512f6787d8ce9d47a0140bf0c5d6a57fd5dd7bf1.zip |
SelfCal: Lower threshold for signal recognition
Initially the threshold was suitable for the cal tone at the original
frequency of 100 MHz. Since this was changed and because it can be
configured via the cal_freq parameter anyway we need to take care to
allow lower input levels that we might have at different frequencies.
In addition we know that for the background calibration of the chip a
signal of >=-46 dBm is required, so by using -20 dBm (which corresponds
to the 14-bit dbFS value of 1465) we still have some margin to recognize
any broken components.
-rw-r--r-- | host/lib/include/uhdlib/usrp/dboard/fbx/fbx_dboard.hpp | 17 |
1 files changed, 15 insertions, 2 deletions
diff --git a/host/lib/include/uhdlib/usrp/dboard/fbx/fbx_dboard.hpp b/host/lib/include/uhdlib/usrp/dboard/fbx/fbx_dboard.hpp index e516913b4..1d7d59ffe 100644 --- a/host/lib/include/uhdlib/usrp/dboard/fbx/fbx_dboard.hpp +++ b/host/lib/include/uhdlib/usrp/dboard/fbx/fbx_dboard.hpp @@ -95,8 +95,21 @@ public: 397.55e6, // tx_freq {0x7FFF, 0}, // output full scale dac mux 100, // delay - 4000, // under - 4192, // over + // From PG.269: "Threshold levels are set as 14-bit unsigned values, with any value + // from 0 to 16383 allowed. The maximum value, 16383 represents the absolute value of + // the full-scale input of the RF-ADC." + // X440 in loopback will usually receive a value of ~-11 dBm which translates to + // a threshold value of ~4000. The minimum value for a useful calibration is + // -40 dBFS according to Xilinx (~-46 dBm). So we pick a value in between (-20 dBm) + // to detect if anything is wrong in the signal path and translate this into the + // 14 bit dBm threshold value which is ~1465. The under value just needs to be slightly + // lower. Calculation from P_dBm to 14 bit threshold_value: + // P_rms = math.pow(10,(P_dBm-30)/10) + // u_peak_to_peak = 2 * math.sqrt(P_rms * 100 * 2) # 100 Ohm Differential + // # 14 bits threshold, full scale of ADC 1 Vppd ≙ 1 dBm (DS.926): + // threshold_value = u_peak_to_peak * math.pow(2,14) + 1365, // under + 1465, // over "calib_mode2", 2000, // 2 seconds were found to be sufficient }; |