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| author |   Javier Valenzuela <javier.valenzuela@ni.com> | 2023-07-26 14:38:02 +0000 |
|---|---|---|
| committer |   Aki Tomita <121511582+atomita-ni@users.noreply.github.com> | 2023-07-31 16:15:16 -0500 |
| commit | b4e14109d02313b6d7ae535338b123461722f4b2 (patch) | |
| tree | 9624364ea006b4785b86a9118d5b979f77379f7a | |
| parent | ci: select docker image repo directly at container endpoint definitions (diff) | |
| download | uhd-b4e14109d02313b6d7ae535338b123461722f4b2.tar.xz uhd-b4e14109d02313b6d7ae535338b123461722f4b2.zip | |
docs: update FPGA build docs
| -rw-r--r-- | fpga/docs/fpga.md | 4 | ||||
| -rw-r--r-- | fpga/docs/usrp3/build_instructions.md | 2 | ||||
| -rw-r--r-- | host/docs/images.dox | 13 |
3 files changed, 5 insertions, 14 deletions
diff --git a/fpga/docs/fpga.md b/fpga/docs/fpga.md index 40994c487..38eb9bca6 100644 --- a/fpga/docs/fpga.md +++ b/fpga/docs/fpga.md @@ -30,8 +30,8 @@ USRP devices. ### Generation 3 \li Directory: __usrp3__ -\li Devices: USRP B2X0, USRP X Series, USRP E3X0 -\li Tools: ISE from Xilinx, GNU make +\li Devices: USRP B2X0, USRP E3XX, USRP N3XX, USRP X3XX, USRP X4XX +\li Tools: Vivado/ISE from Xilinx, GNU make \li \subpage md_usrp3_build_instructions "Build Instructions" \li \subpage md_usrp3_simulation "Simulation" diff --git a/fpga/docs/usrp3/build_instructions.md b/fpga/docs/usrp3/build_instructions.md index 3f0663051..077d42480 100644 --- a/fpga/docs/usrp3/build_instructions.md +++ b/fpga/docs/usrp3/build_instructions.md @@ -96,7 +96,7 @@ The following additional packages are also required and can be selected in the G + `e31x`: For USRP E310 + `e320`: For USRP E320 + `n3xx`: For USRP N300/N310/N320 - + `x400`: For USRP X410 + + `x400`: For USRP X410/X440 - To add vivado to the PATH and to setup up the Ettus Xilinx build environment run + `source setupenv.sh` (If Vivado is installed in the default path /opt/Xilinx/Vivado) _OR_ diff --git a/host/docs/images.dox b/host/docs/images.dox index 21ff0ea22..9912cb60b 100644 --- a/host/docs/images.dox +++ b/host/docs/images.dox @@ -81,17 +81,8 @@ The build commands for a particular image can be found in USRP Xilinx FPGA images are built with either Vivado or one of two versions of ISE, depending on the device. -The build requires that you have a UNIX-like environment with `Make`. -Make sure that `xtclsh` from the Xilinx Vivado or ISE bin directory is in your `$PATH`. - -- Vivado 2017.4: USRP N3x0, USRP E3x0, USRP X3x0 -- Xilinx ISE 14.7: USRP B2x0, USRP B200mini, B200mini-i, B205mini-i, USRP N2x0 - -See `<uhd-repo-path>/fpga/usrp3/top/`. - -- Xilinx ISE 12.2: USRP B1x0, USRP E1x0, USRP2 [All of these devices are EOL as of 2018] - -See `<uhd-repo-path>/fpga/usrp2/top/`. +Refer to the \ref md_fpga "FPGA Manual" for setup and build instructions +relevant to your device family. \subsection images_building_zpu ZPU firmware builds |