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| author |   mkoop <marian.koop@ni.com> | 2023-09-06 14:27:55 +0200 |
|---|---|---|
| committer |   Aki Tomita <121511582+atomita-ni@users.noreply.github.com> | 2023-09-06 09:18:06 -0500 |
| commit | e93c9a119ec82408fde8c63c1452306af08b8b12 (patch) | |
| tree | 74e6557b4aec8f62ab362c3a48851d8b1a44e8c7 | |
| parent | docs: update remote streaming supported version (diff) | |
| download | uhd-e93c9a119ec82408fde8c63c1452306af08b8b12.tar.xz uhd-e93c9a119ec82408fde8c63c1452306af08b8b12.zip | |
docs: x440: Fixed incorrect use of paragraph elements
Replaced newly added paragraph with subsubsection elements that resulted into
an as warning declared build error when buildin on readthedocs.
The build service still uses doxygen 1.8.13, which failed to include content
into the generated html after the warning was reported. Newer version of
doxygen also report the warning/s but continue including content.
| -rw-r--r-- | host/docs/usrp_x4xx.dox | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/host/docs/usrp_x4xx.dox b/host/docs/usrp_x4xx.dox index 7692c89ef..717a83ba8 100644 --- a/host/docs/usrp_x4xx.dox +++ b/host/docs/usrp_x4xx.dox @@ -951,12 +951,12 @@ For a list of which arguments can be passed into make(), see Section The available master clock rates (MCR) depend on the FPGA image flavor that is currently installed on the device (see \ref x4xx_updating_fpga_types). -\paragraph x410_usage_mcrs USRP X410 +\subsubsection x410_usage_mcrs USRP X410 The USRP X410 has a few fixed MCR available for every image type: The 200 MHz images allow master clock rates of 245.76 MHz or 250 MHz. The 400 MHz images allow master clock rates of 491.52 MHz or 500 MHz. -\paragraph x440_usage_mcrs USRP X440 +\subsubsection x440_usage_mcrs USRP X440 The USRP X440 has a much broader range of available master clock rates, and supports a fixed set of rates between 125 Msps and 2 Gsps. The maximum available MCR is further dependent on the FPGA image type. The master clock rate depends @@ -1374,13 +1374,13 @@ convert the signal to a complex one). In the USRP X4x0 design all ADC and DAC converter rates are identical and use the same RFDC decimation/interpolation settings. -\paragraph x410_too_convrate USRP X410 +\subsubsection x410_too_convrate USRP X410 The USRP X410 only supports a few fixed master clock rates (see \ref x4xx_usage_mcrs), with predefined converter rates around 3 GHz, and uses in addition to the RFDC decimation/interpolation block also a 3/2 decimation (2/3 interpolation) block implemented in FPGA fabric. -\paragraph x440_too_convrate USRP X440 +\subsubsection x440_too_convrate USRP X440 The USRP X440 supports a large, finite number of master clock rates (see \ref x4xx_usage_mcrs), and utilizes converter rates between 1GHz and the maximum supported converter rate of 4.096 GHz. The smallest possible master clock rate |