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author | Wade Fife <wade.fife@ettus.com> | 2023-08-16 13:55:59 -0500 |
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committer | Aki Tomita <121511582+atomita-ni@users.noreply.github.com> | 2023-08-17 10:51:55 -0500 |
commit | f07f4373eca1aeab7bdeadce69de638be8bafba0 (patch) | |
tree | f6d9132f3f28828795ac8a6e09a3e07e49e42be3 | |
parent | docs: fix typo and consistency in usrpctl docs (diff) | |
download | uhd-f07f4373eca1aeab7bdeadce69de638be8bafba0.tar.xz uhd-f07f4373eca1aeab7bdeadce69de638be8bafba0.zip |
fpga: Clear clang-format settings for FPGA code
Vitis HLS uses its own version of clang that's different from what's
used by UHD. This change clears the clang-format settings for FPGA
code to be compatible with Vitis.
-rw-r--r-- | fpga/.clang-format | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/fpga/.clang-format b/fpga/.clang-format new file mode 100644 index 000000000..2aaf6b165 --- /dev/null +++ b/fpga/.clang-format @@ -0,0 +1,3 @@ +--- +Language: Cpp +... |