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* fpga: n3xx: Fix DRAM FIFO address alignmentWade Fife2022-04-013-6/+6
* fpga: rfnoc: Change AWIDTH default for axi_ram_fifoWade Fife2022-04-011-1/+1
* images: Add utilization report files to B2xx image filesMartin Braun2022-04-011-4/+8
* fpga: b2xx: Generate utilization report filesMartin Braun2022-04-012-18/+24
* fpga: x400: zbx: cpld: Bump ZBX regmap copyrightJavier Valenzuela2022-04-0111-11/+11
* fpga: x400: cpld: Bump CMI wrapper copyrightJavier Valenzuela2022-04-012-2/+2
* fpga: ci: Increase PR pipeline timeoutWade Fife2022-04-011-3/+3
* fpga: docs: Add B205mini FPGA infoWade Fife2022-04-011-9/+11
* fpga: n3xx: rh: cpld: Refactor CPLD build processHumberto Jimenez2022-04-016-24/+119
* fpga: Remove noc_shell_regs.vh and sim_rfnoc_lib.svhMartin Braun2022-04-016-1058/+1
* fpga: x400: cpld: Bump copyrightJavier Valenzuela2022-04-019-9/+9
* fpga: x400: Bump copyrightJavier Valenzuela2022-04-0111-11/+11
* fpga: hls: Add version to generated HLS IPWade Fife2022-04-011-2/+2
* fpga: tools: Fix adding directories for HDL sourceWade Fife2022-04-011-1/+1
* fpga: x400: Fix rfnoc_image_core.vh pathWade Fife2022-04-011-1/+1
* uhd: update git://github.com references to httpsSteven Koo2022-04-013-13/+13
* fpga: e320: Connect CTRL_IN pins to FPGAMartin Braun2022-04-012-1/+12
* fpga: e320: Remove copy/paste from N310 codeMartin Braun2022-04-011-9/+0
* images: Add the utilization report for X410 images (X4_200)Martin Braun2022-04-011-1/+3
* fpga: x300: Fix time register readbackWade Fife2022-04-011-2/+2
* fpga: Revert "Add ability to get time from Radio block"Aaron Rossetto2021-12-023-26/+2
* fpga: Add ability to get time from Radio blockmichael-west2021-11-303-2/+26
* fpga: rfnoc: Add RFNoC CHDR resize moduleWade Fife2021-11-087-0/+2031
* fpga: rfnoc: Add CHDR management util functionsWade Fife2021-11-081-4/+85
* x410: correct 100GbE link speedAndrew Lynch2021-11-082-2/+2
* fpga: lib: Clean up axi_muxWade Fife2021-11-081-91/+160
* fpga: rfnoc: Add labels to axi_switch generate blocksWade Fife2021-11-081-36/+67
* fpga: rfnoc: Add labels to chdr_mgmt_pkt_handlerWade Fife2021-11-081-30/+45
* fpga: rfnoc: Add documentation to chdr_xb_routing_tableWade Fife2021-11-081-46/+84
* fpga: Shorten line length for Launchpad linterAaron Rossetto2021-11-081-2/+4
* siggen: Fix direction of rotationWade Fife2021-11-084-35/+44
* fpga: x300: Update synchronizer constraintWade Fife2021-11-081-1/+1
* fpga: n3xx: Update synchronizer constraintWade Fife2021-11-081-3/+2
* fpga: lib: Update example constraint in synchronizerWade Fife2021-11-081-18/+40
* fpga: Update help message for setupenv.shWade Fife2021-11-081-5/+7
* fpga: Remove stale references to UHD_FPGA_DIRWade Fife2021-11-088-16/+8
* fpga: tools: Add UHD_FPGA_DIR definition to synthesisWade Fife2021-11-083-6/+11
* fpga: Set default part for sim in setupenv.shWade Fife2021-11-086-5/+24
* x300: Fix sfpp_io_core tuser widthWade Fife2021-11-081-1/+1
* fpga: Fix Xilinx bitfile parser for Python 3Martin Braun2021-11-081-31/+54
* fpga: rfnoc: Fix EOB loss in DUCWade Fife2021-11-087-218/+1858
* fpga: sim: Add PkgComplex, PkgMath, and PkgRandomWade Fife2021-11-085-0/+546
* fpga: lib: Clean up and document lib filesWade Fife2021-11-083-246/+411
* rfnoc: duc: Remove stale references to CORDICWade Fife2021-11-081-18/+15
* N3xx: Fix White Rabbitmichael-west2021-11-081-0/+10
* fpga: x400: Remove stale information in register mapHumberto Jimenez2021-11-083-9/+9
* fpga: ci: Add testbench pipelineWade Fife2021-11-082-0/+106
* sim: Update chdr_16sc_to_sc12 testbenchmichael-west2021-09-021-137/+159
* fpga: Re-order error and data packetsmichael-west2021-09-021-2/+28
* fpga: Fix sc16 to sc12 convertermichael-west2021-09-021-62/+80
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