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authorJason-JH.Lin <jason-jh.lin@mediatek.com>2023-12-15 15:00:24 +0800
committerJassi Brar <jaswinder.singh@linaro.org>2024-01-13 23:08:51 -0600
commit060177644136bdefd887c61043220f7eb63c2fe6 (patch)
treed05a9a4b654aa21fda8fbad046d4fc565c445fc0
parentdt-bindings: mailbox: qcom-ipcc: document the X1E80100 Inter-Processor Communication Controller (diff)
downloadwireguard-linux-060177644136bdefd887c61043220f7eb63c2fe6.tar.xz
wireguard-linux-060177644136bdefd887c61043220f7eb63c2fe6.zip
mailbox: mtk-cmdq: Rename gce_plat variable with SoC name postfix
Rename gce_plat variable postfix from 'v1~v7' to SoC names. Signed-off-by: Jason-JH.Lin <jason-jh.lin@mediatek.com> Reviewed-by: CK Hu <ck.hu@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
-rw-r--r--drivers/mailbox/mtk-cmdq-mailbox.c24
1 files changed, 12 insertions, 12 deletions
diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c b/drivers/mailbox/mtk-cmdq-mailbox.c
index c9009b729ab2..6b1e8df8485e 100644
--- a/drivers/mailbox/mtk-cmdq-mailbox.c
+++ b/drivers/mailbox/mtk-cmdq-mailbox.c
@@ -705,42 +705,42 @@ static const struct dev_pm_ops cmdq_pm_ops = {
cmdq_runtime_resume, NULL)
};
-static const struct gce_plat gce_plat_v2 = {
+static const struct gce_plat gce_plat_mt8173 = {
.thread_nr = 16,
.shift = 0,
.control_by_sw = false,
.gce_num = 1
};
-static const struct gce_plat gce_plat_v3 = {
+static const struct gce_plat gce_plat_mt8183 = {
.thread_nr = 24,
.shift = 0,
.control_by_sw = false,
.gce_num = 1
};
-static const struct gce_plat gce_plat_v4 = {
+static const struct gce_plat gce_plat_mt6779 = {
.thread_nr = 24,
.shift = 3,
.control_by_sw = false,
.gce_num = 1
};
-static const struct gce_plat gce_plat_v5 = {
+static const struct gce_plat gce_plat_mt8192 = {
.thread_nr = 24,
.shift = 3,
.control_by_sw = true,
.gce_num = 1
};
-static const struct gce_plat gce_plat_v6 = {
+static const struct gce_plat gce_plat_mt8195 = {
.thread_nr = 24,
.shift = 3,
.control_by_sw = true,
.gce_num = 2
};
-static const struct gce_plat gce_plat_v7 = {
+static const struct gce_plat gce_plat_mt8186 = {
.thread_nr = 24,
.shift = 3,
.control_by_sw = true,
@@ -749,12 +749,12 @@ static const struct gce_plat gce_plat_v7 = {
};
static const struct of_device_id cmdq_of_ids[] = {
- {.compatible = "mediatek,mt8173-gce", .data = (void *)&gce_plat_v2},
- {.compatible = "mediatek,mt8183-gce", .data = (void *)&gce_plat_v3},
- {.compatible = "mediatek,mt8186-gce", .data = (void *)&gce_plat_v7},
- {.compatible = "mediatek,mt6779-gce", .data = (void *)&gce_plat_v4},
- {.compatible = "mediatek,mt8192-gce", .data = (void *)&gce_plat_v5},
- {.compatible = "mediatek,mt8195-gce", .data = (void *)&gce_plat_v6},
+ {.compatible = "mediatek,mt8173-gce", .data = (void *)&gce_plat_mt8173},
+ {.compatible = "mediatek,mt8183-gce", .data = (void *)&gce_plat_mt8183},
+ {.compatible = "mediatek,mt8186-gce", .data = (void *)&gce_plat_mt8186},
+ {.compatible = "mediatek,mt6779-gce", .data = (void *)&gce_plat_mt6779},
+ {.compatible = "mediatek,mt8192-gce", .data = (void *)&gce_plat_mt8192},
+ {.compatible = "mediatek,mt8195-gce", .data = (void *)&gce_plat_mt8195},
{}
};