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authorRodrigo Vivi <rodrigo.vivi@intel.com>2024-02-21 10:54:53 -0500
committerRodrigo Vivi <rodrigo.vivi@intel.com>2024-02-23 09:07:18 -0500
commit0be4e0a5203d38d40d3de44c9dab6c3acc44fef5 (patch)
tree3fbbccf04c72c99e882f62b2d4717eb61668ff64
parentdrm/i915/lnl: Program PKGC_LATENCY register (diff)
downloadwireguard-linux-0be4e0a5203d38d40d3de44c9dab6c3acc44fef5.tar.xz
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drm/i915: Fix doc build issue on intel_cdclk.c
Fixing some doc build issues: Documentation/gpu/i915:222: drivers/gpu/drm/i915/display/intel_cdclk.c:69: ERROR: Unexpected indentation. Documentation/gpu/i915:222: ./drivers/gpu/drm/i915/display/intel_cdclk.c:70: WARNING: Block quote ends without a blank line; unexpected unindent. v2: Minimize the empty lines (Gustavo) Closes: https://lore.kernel.org/all/20240219161747.0e867406@canb.auug.org.au/ Fixes: 79e2ea2eaaa6 ("drm/i915/cdclk: Document CDCLK update methods") Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Gustavo Sousa <gustavo.sousa@intel.com> Reported-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240221155453.94208-1-rodrigo.vivi@intel.com
-rw-r--r--drivers/gpu/drm/i915/display/intel_cdclk.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 30dae4fef6cb..ed89b86ea625 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -65,6 +65,7 @@
*
* Several methods exist to change the CDCLK frequency, which ones are
* supported depends on the platform:
+ *
* - Full PLL disable + re-enable with new VCO frequency. Pipes must be inactive.
* - CD2X divider update. Single pipe can be active as the divider update
* can be synchronized with the pipe's start of vblank.