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| author |   Shengjiu Wang <shengjiu.wang@nxp.com> | 2022-05-05 15:34:07 +0800 |
|---|---|---|
| committer |   Mark Brown <broonie@kernel.org> | 2022-05-05 13:24:48 +0100 |
| commit | 101b096bc2549618f18bc08ae3a0e364b3c8fff1 (patch) | |
| tree | f32e916bad850f75ccc1421a651cb95c4dfce0b3 | |
| parent | ASoC: ti: davinci-mcasp: Add dma-type for bcdma (diff) | |
| download | wireguard-linux-101b096bc2549618f18bc08ae3a0e364b3c8fff1.tar.xz wireguard-linux-101b096bc2549618f18bc08ae3a0e364b3c8fff1.zip | |
ASoC: fsl_micfil: fix the naming style for mask definition
Remove the _SHIFT for the mask definition.
Fixes: 17f2142bae4b ("ASoC: fsl_micfil: use GENMASK to define register bit fields")
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Link: https://lore.kernel.org/r/1651736047-28809-1-git-send-email-shengjiu.wang@nxp.com
Signed-off-by: Mark Brown <broonie@kernel.org>
| -rw-r--r-- | sound/soc/fsl/fsl_micfil.h | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/sound/soc/fsl/fsl_micfil.h b/sound/soc/fsl/fsl_micfil.h index 08901827047d..053caba3caf3 100644 --- a/sound/soc/fsl/fsl_micfil.h +++ b/sound/soc/fsl/fsl_micfil.h @@ -74,9 +74,9 @@ #define MICFIL_FIFO_STAT_FIFOX_UNDER(ch) BIT((ch) + 8) /* MICFIL HWVAD0 Control 1 Register -- REG_MICFIL_VAD0_CTRL1*/ -#define MICFIL_VAD0_CTRL1_CHSEL_SHIFT GENMASK(26, 24) -#define MICFIL_VAD0_CTRL1_CICOSR_SHIFT GENMASK(19, 16) -#define MICFIL_VAD0_CTRL1_INITT_SHIFT GENMASK(12, 8) +#define MICFIL_VAD0_CTRL1_CHSEL GENMASK(26, 24) +#define MICFIL_VAD0_CTRL1_CICOSR GENMASK(19, 16) +#define MICFIL_VAD0_CTRL1_INITT GENMASK(12, 8) #define MICFIL_VAD0_CTRL1_ST10 BIT(4) #define MICFIL_VAD0_CTRL1_ERIE BIT(3) #define MICFIL_VAD0_CTRL1_IE BIT(2) @@ -106,7 +106,7 @@ /* MICFIL HWVAD0 Zero-Crossing Detector - REG_MICFIL_VAD0_ZCD */ #define MICFIL_VAD0_ZCD_ZCDTH GENMASK(25, 16) -#define MICFIL_VAD0_ZCD_ZCDADJ_SHIFT GENMASK(11, 8) +#define MICFIL_VAD0_ZCD_ZCDADJ GENMASK(11, 8) #define MICFIL_VAD0_ZCD_ZCDAND BIT(4) #define MICFIL_VAD0_ZCD_ZCDAUT BIT(2) #define MICFIL_VAD0_ZCD_ZCDEN BIT(0) |