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| author |   Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> | 2025-04-08 11:31:58 +0200 |
|---|---|---|
| committer |   Bjorn Andersson <andersson@kernel.org> | 2025-04-08 16:54:56 -0500 |
| commit | 17268faf29992d37033d6ad1a5ed5d924f2430d8 (patch) | |
| tree | 1ac3fb3800c7ed3a2b9fb6b75b44b78b5a07628d | |
| parent | Linux 6.15-rc1 (diff) | |
| download | wireguard-linux-17268faf29992d37033d6ad1a5ed5d924f2430d8.tar.xz wireguard-linux-17268faf29992d37033d6ad1a5ed5d924f2430d8.zip | |
ARM: dts: qcom: msm8226: Use the header with DSI phy clock IDs
Use the header with DSI phy clock IDs to make code more readable.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250408-dts-qcom-dsi-phy-clocks-v2-1-73b482a6dd02@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
| -rw-r--r-- | arch/arm/boot/dts/qcom/qcom-msm8226.dtsi | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi index 64c8ac94f352..c84320ef5ca2 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi @@ -6,6 +6,7 @@ /dts-v1/; #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/qcom,dsi-phy-28nm.h> #include <dt-bindings/clock/qcom,gcc-msm8974.h> #include <dt-bindings/clock/qcom,mmcc-msm8974.h> #include <dt-bindings/clock/qcom,rpmcc.h> @@ -983,8 +984,8 @@ <&gcc GPLL0_VOTE>, <&gcc GPLL1_VOTE>, <&rpmcc RPM_SMD_GFX3D_CLK_SRC>, - <&mdss_dsi0_phy 1>, - <&mdss_dsi0_phy 0>; + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, + <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>; clock-names = "xo", "mmss_gpll0_vote", "gpll0_vote", @@ -1060,8 +1061,8 @@ assigned-clocks = <&mmcc BYTE0_CLK_SRC>, <&mmcc PCLK0_CLK_SRC>; - assigned-clock-parents = <&mdss_dsi0_phy 0>, - <&mdss_dsi0_phy 1>; + assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; clocks = <&mmcc MDSS_MDP_CLK>, <&mmcc MDSS_AHB_CLK>, |