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| author |   Sai Prakash Ranjan <quic_saipraka@quicinc.com> | 2022-01-28 13:17:16 +0530 |
|---|---|---|
| committer |   Bjorn Andersson <bjorn.andersson@linaro.org> | 2022-02-10 18:31:05 -0600 |
| commit | 1dc3e50eb68031bc8fc56829c7ac46c89dfbe237 (patch) | |
| tree | 21667845678bbf042534132a7bcdfd7a84c168d6 | |
| parent | arm64: dts: qcom: ipq6018: drop the clock-frequency property (diff) | |
| download | wireguard-linux-1dc3e50eb68031bc8fc56829c7ac46c89dfbe237.tar.xz wireguard-linux-1dc3e50eb68031bc8fc56829c7ac46c89dfbe237.zip | |
arm64: dts: qcom: sm8450: Add LLCC/system-cache-controller node
Add a DT node for Last level cache (aka. system cache) controller
which provides control over the last level cache present on SM8450
SoC.
Signed-off-by: Sai Prakash Ranjan <quic_saipraka@quicinc.com>
Tested-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/7995d003b77d5e066658af5b2cfa22ccb40b6cf7.1643355594.git.quic_saipraka@quicinc.com
| -rw-r--r-- | arch/arm64/boot/dts/qcom/sm8450.dtsi | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index eccbfeea943b..0cd5af8c03bd 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -1353,6 +1353,13 @@ qcom,bcm-voters = <&apps_bcm_voter>; }; + system-cache-controller@19200000 { + compatible = "qcom,sm8450-llcc"; + reg = <0 0x19200000 0 0x580000>, <0 0x19a00000 0 0x80000>; + reg-names = "llcc_base", "llcc_broadcast_base"; + interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; + }; + ufs_mem_hc: ufshc@1d84000 { compatible = "qcom,sm8450-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; |