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authorMarco Felsch <m.felsch@pengutronix.de>2022-09-30 14:48:10 +0200
committerSakari Ailus <sakari.ailus@linux.intel.com>2022-10-27 14:38:04 +0300
commit22168675bae75e158c459ef2dee3b6ebd52a80ed (patch)
treebdb716e03686b78132b933e08f00728d55881163
parentphy: dphy: refactor get_default_config (diff)
downloadwireguard-linux-22168675bae75e158c459ef2dee3b6ebd52a80ed.tar.xz
wireguard-linux-22168675bae75e158c459ef2dee3b6ebd52a80ed.zip
phy: dphy: add support to calculate the timing based on hs_clk_rate
For MIPI-CSI sender use-case it is common to specify the allowed link-frequencies which should be used for the MIPI link and is half the hs-clock rate. This commit adds a helper to calculate the D-PHY timing based on the hs-clock rate so we don't need to calculate the timings within the driver. Signed-off-by: Marco Felsch <m.felsch@pengutronix.de> Acked-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
-rw-r--r--drivers/phy/phy-core-mipi-dphy.c22
-rw-r--r--include/linux/phy/phy-mipi-dphy.h3
2 files changed, 21 insertions, 4 deletions
diff --git a/drivers/phy/phy-core-mipi-dphy.c b/drivers/phy/phy-core-mipi-dphy.c
index ba365bc77407..f4956a417a47 100644
--- a/drivers/phy/phy-core-mipi-dphy.c
+++ b/drivers/phy/phy-core-mipi-dphy.c
@@ -20,16 +20,18 @@
static int phy_mipi_dphy_calc_config(unsigned long pixel_clock,
unsigned int bpp,
unsigned int lanes,
+ unsigned long long hs_clk_rate,
struct phy_configure_opts_mipi_dphy *cfg)
{
- unsigned long long hs_clk_rate;
unsigned long long ui;
if (!cfg)
return -EINVAL;
- hs_clk_rate = pixel_clock * bpp;
- do_div(hs_clk_rate, lanes);
+ if (!hs_clk_rate) {
+ hs_clk_rate = pixel_clock * bpp;
+ do_div(hs_clk_rate, lanes);
+ }
ui = ALIGN(PSEC_PER_SEC, hs_clk_rate);
do_div(ui, hs_clk_rate);
@@ -81,11 +83,23 @@ int phy_mipi_dphy_get_default_config(unsigned long pixel_clock,
unsigned int lanes,
struct phy_configure_opts_mipi_dphy *cfg)
{
- return phy_mipi_dphy_calc_config(pixel_clock, bpp, lanes, cfg);
+ return phy_mipi_dphy_calc_config(pixel_clock, bpp, lanes, 0, cfg);
}
EXPORT_SYMBOL(phy_mipi_dphy_get_default_config);
+int phy_mipi_dphy_get_default_config_for_hsclk(unsigned long long hs_clk_rate,
+ unsigned int lanes,
+ struct phy_configure_opts_mipi_dphy *cfg)
+{
+ if (!hs_clk_rate)
+ return -EINVAL;
+
+ return phy_mipi_dphy_calc_config(0, 0, lanes, hs_clk_rate, cfg);
+
+}
+EXPORT_SYMBOL(phy_mipi_dphy_get_default_config_for_hsclk);
+
/*
* Validate D-PHY configuration according to MIPI D-PHY specification
* (v1.2, Section Section 6.9 "Global Operation Timing Parameters").
diff --git a/include/linux/phy/phy-mipi-dphy.h b/include/linux/phy/phy-mipi-dphy.h
index a877ffee845d..1ac128d78dfe 100644
--- a/include/linux/phy/phy-mipi-dphy.h
+++ b/include/linux/phy/phy-mipi-dphy.h
@@ -279,6 +279,9 @@ int phy_mipi_dphy_get_default_config(unsigned long pixel_clock,
unsigned int bpp,
unsigned int lanes,
struct phy_configure_opts_mipi_dphy *cfg);
+int phy_mipi_dphy_get_default_config_for_hsclk(unsigned long long hs_clk_rate,
+ unsigned int lanes,
+ struct phy_configure_opts_mipi_dphy *cfg);
int phy_mipi_dphy_config_validate(struct phy_configure_opts_mipi_dphy *cfg);
#endif /* __PHY_MIPI_DPHY_H_ */