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| author |   Jiansong Chen <Jiansong.Chen@amd.com> | 2020-08-25 15:39:57 +0800 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2020-08-26 16:40:19 -0400 |
| commit | 22dd44f47cf74c2891c359976f308941a3736605 (patch) | |
| tree | 924bb98ba30965a4579f38b829b35a7d8411b995 | |
| parent | drm/amdkfd: fix set kfd node ras properties value (diff) | |
| download | wireguard-linux-22dd44f47cf74c2891c359976f308941a3736605.tar.xz wireguard-linux-22dd44f47cf74c2891c359976f308941a3736605.zip | |
drm/amdgpu: use MODE1 reset for navy_flounder by default
Switch default gpu reset method to MODE1 for navy_flounder.
Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/nv.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c index 33a6d2d5fc16..4d1402356262 100644 --- a/drivers/gpu/drm/amd/amdgpu/nv.c +++ b/drivers/gpu/drm/amd/amdgpu/nv.c @@ -364,6 +364,7 @@ nv_asic_reset_method(struct amdgpu_device *adev) switch (adev->asic_type) { case CHIP_SIENNA_CICHLID: + case CHIP_NAVY_FLOUNDER: return AMD_RESET_METHOD_MODE1; default: if (smu_baco_is_support(smu)) |