diff options
| author |   Chen-Yu Tsai <wenst@chromium.org> | 2023-06-09 15:29:04 +0800 |
|---|---|---|
| committer |   Matthias Brugger <matthias.bgg@gmail.com> | 2023-06-15 13:14:58 +0200 |
| commit | 263d2fd02afc57909959616c234d8ff09f52d6ae (patch) | |
| tree | d3f74d691dc2e5882299150a988010a708ef3d5d | |
| parent | arm64: dts: mediatek: mt8186: Wire up CPU frequency/voltage scaling (diff) | |
| download | wireguard-linux-263d2fd02afc57909959616c234d8ff09f52d6ae.tar.xz wireguard-linux-263d2fd02afc57909959616c234d8ff09f52d6ae.zip | |
arm64: dts: mediatek: mt8186: Add GPU speed bin NVMEM cells
On the MT8186, the chip is binned for different GPU voltages at the
highest OPPs. The binning value is stored in the efuse.
Add the NVMEM cell, and tie it to the GPU.
Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20230609072906.2784594-4-wenst@chromium.org
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
| -rw-r--r-- | arch/arm64/boot/dts/mediatek/mt8186.dtsi | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi index e2becf2fe79f..3762a70ccafb 100644 --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi @@ -1519,6 +1519,11 @@ reg = <0 0x11cb0000 0 0x1000>; #address-cells = <1>; #size-cells = <1>; + + gpu_speedbin: gpu-speed-bin@59c { + reg = <0x59c 0x4>; + bits = <0 3>; + }; }; mipi_tx0: dsi-phy@11cc0000 { @@ -1551,6 +1556,8 @@ <&spm MT8186_POWER_DOMAIN_MFG3>; power-domain-names = "core0", "core1"; #cooling-cells = <2>; + nvmem-cells = <&gpu_speedbin>; + nvmem-cell-names = "speed-bin"; status = "disabled"; }; |