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author | 2025-05-12 16:57:23 -0500 | |
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committer | 2025-05-15 21:31:56 +0900 | |
commit | 2de72bb42c149ba7908291bd3dd46e315a7fe65f (patch) | |
tree | c0129e91e9a0bd00f536ce08f574550e523fe6ce | |
parent | dt-bindings: ata: Convert ti,dm816-ahci to DT schema (diff) | |
download | wireguard-linux-2de72bb42c149ba7908291bd3dd46e315a7fe65f.tar.xz wireguard-linux-2de72bb42c149ba7908291bd3dd46e315a7fe65f.zip |
dt-bindings: ata: Convert st,ahci to DT schema
Convert the ST AHCI SATA Controller to DT schema format.
The phy-names changes from "ahci_phy" to "sata-phy" with the inclusion
of ahci-common.yaml. That's an ABI change, but the Linux driver at least
ignores the names. The binding uses "ports-implemented" property, so
including ahci-common.yaml is required.
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Damien Le Moal <dlemoal@kernel.org>
-rw-r--r-- | Documentation/devicetree/bindings/ata/ahci-st.txt | 35 | ||||
-rw-r--r-- | Documentation/devicetree/bindings/ata/st,ahci.yaml | 72 |
2 files changed, 72 insertions, 35 deletions
diff --git a/Documentation/devicetree/bindings/ata/ahci-st.txt b/Documentation/devicetree/bindings/ata/ahci-st.txt deleted file mode 100644 index 909c9935360d..000000000000 --- a/Documentation/devicetree/bindings/ata/ahci-st.txt +++ /dev/null @@ -1,35 +0,0 @@ -STMicroelectronics STi SATA controller - -This binding describes a SATA device. - -Required properties: - - compatible : Must be "st,ahci" - - reg : Physical base addresses and length of register sets - - interrupts : Interrupt associated with the SATA device - - interrupt-names : Associated name must be; "hostc" - - clocks : The phandle for the clock - - clock-names : Associated name must be; "ahci_clk" - - phys : The phandle for the PHY port - - phy-names : Associated name must be; "ahci_phy" - -Optional properties: - - resets : The power-down, soft-reset and power-reset lines of SATA IP - - reset-names : Associated names must be; "pwr-dwn", "sw-rst" and "pwr-rst" - -Example: - - /* Example for stih407 family silicon */ - sata0: sata@9b20000 { - compatible = "st,ahci"; - reg = <0x9b20000 0x1000>; - interrupts = <GIC_SPI 159 IRQ_TYPE_NONE>; - interrupt-names = "hostc"; - phys = <&phy_port0 PHY_TYPE_SATA>; - phy-names = "ahci_phy"; - resets = <&powerdown STIH407_SATA0_POWERDOWN>, - <&softreset STIH407_SATA0_SOFTRESET>, - <&softreset STIH407_SATA0_PWR_SOFTRESET>; - reset-names = "pwr-dwn", "sw-rst", "pwr-rst"; - clocks = <&clk_s_c0_flexgen CLK_ICN_REG>; - clock-names = "ahci_clk"; - }; diff --git a/Documentation/devicetree/bindings/ata/st,ahci.yaml b/Documentation/devicetree/bindings/ata/st,ahci.yaml new file mode 100644 index 000000000000..6e8e4b4f3d6c --- /dev/null +++ b/Documentation/devicetree/bindings/ata/st,ahci.yaml @@ -0,0 +1,72 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/ata/st,ahci.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STMicroelectronics STi SATA controller + +maintainers: + - Patrice Chotard <patrice.chotard@foss.st.com> + +allOf: + - $ref: ahci-common.yaml# + +properties: + compatible: + const: st,ahci + + interrupt-names: + items: + - const: hostc + + clocks: + maxItems: 1 + + clock-names: + items: + - const: ahci_clk + + resets: + items: + - description: Power-down line + - description: Soft-reset line + - description: Power-reset line + + reset-names: + items: + - const: pwr-dwn + - const: sw-rst + - const: pwr-rst + +required: + - compatible + - interrupt-names + - phys + - phy-names + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/phy/phy.h> + #include <dt-bindings/reset/stih407-resets.h> + #include <dt-bindings/clock/stih407-clks.h> + + sata@9b20000 { + compatible = "st,ahci"; + reg = <0x9b20000 0x1000>; + interrupts = <GIC_SPI 159 IRQ_TYPE_NONE>; + interrupt-names = "hostc"; + phys = <&phy_port0 PHY_TYPE_SATA>; + phy-names = "sata-phy"; + resets = <&powerdown STIH407_SATA0_POWERDOWN>, + <&softreset STIH407_SATA0_SOFTRESET>, + <&softreset STIH407_SATA0_PWR_SOFTRESET>; + reset-names = "pwr-dwn", "sw-rst", "pwr-rst"; + clocks = <&clk_s_c0_flexgen CLK_ICN_REG>; + clock-names = "ahci_clk"; + }; |