diff options
| author |   sunliming <sunliming@kylinos.cn> | 2022-07-19 09:56:22 +0800 |
|---|---|---|
| committer |   Abhinav Kumar <quic_abhinavk@quicinc.com> | 2022-07-20 12:05:52 -0700 |
| commit | 2f25a1fb4ec516c5ad67afd754334b491b9f09a5 (patch) | |
| tree | 9ff063a81d417181ae297aa2c757dfbaf1ed198f | |
| parent | drm/msm/dp: make eDP panel as the first connected connector (diff) | |
| download | wireguard-linux-2f25a1fb4ec516c5ad67afd754334b491b9f09a5.tar.xz wireguard-linux-2f25a1fb4ec516c5ad67afd754334b491b9f09a5.zip | |
drm/msm/dsi: fix the inconsistent indenting
Fix the inconsistent indenting in function msm_dsi_dphy_timing_calc_v3().
Fix the following smatch warnings:
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c:350 msm_dsi_dphy_timing_calc_v3() warn: inconsistent indenting
Fixes: f1fa7ff44056 ("drm/msm/dsi: implement auto PHY timing calculator for 10nm PHY")
Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: sunliming <sunliming@kylinos.cn>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/494662/
Link: https://lore.kernel.org/r/20220719015622.646718-1-sunliming@kylinos.cn
Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
| -rw-r--r-- | drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c index a39de3bdc7fa..56dfa2d24be1 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c @@ -347,7 +347,7 @@ int msm_dsi_dphy_timing_calc_v3(struct msm_dsi_dphy_timing *timing, } else { timing->shared_timings.clk_pre = linear_inter(tmax, tmin, pcnt2, 0, false); - timing->shared_timings.clk_pre_inc_by_2 = 0; + timing->shared_timings.clk_pre_inc_by_2 = 0; } timing->ta_go = 3; |