diff options
| author |   Sung Joon Kim <sungjoon.kim@amd.com> | 2024-04-18 16:59:36 -0400 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2024-04-30 09:57:37 -0400 |
| commit | 35df442d813d9a6c766b116d3799eff4757eb59c (patch) | |
| tree | f87468015136731fb8857f06ad424ed3d4059f13 | |
| parent | drm/amd/display: Change ASSR disable sequence (diff) | |
| download | wireguard-linux-35df442d813d9a6c766b116d3799eff4757eb59c.tar.xz wireguard-linux-35df442d813d9a6c766b116d3799eff4757eb59c.zip | |
drm/amd/display: Disable seamless boot on 128b/132b encoding
[why]
preOS will not support display mode programming and link training
for UHBR rates.
[how]
If we detect a sink that's UHBR capable, disable seamless boot
Reviewed-by: Anthony Koo <anthony.koo@amd.com>
Acked-by: Wayne Lin <wayne.lin@amd.com>
Signed-off-by: Sung Joon Kim <sungjoon.kim@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/core/dc.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index a8eb286ee4ff..9f56b2743f80 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -1838,6 +1838,9 @@ bool dc_validate_boot_timing(const struct dc *dc, return false; } + if (link->dpcd_caps.channel_coding_cap.bits.DP_128b_132b_SUPPORTED) + return false; + if (dc->link_srv->edp_is_ilr_optimization_required(link, crtc_timing)) { DC_LOG_EVENT_LINK_TRAINING("Seamless boot disabled to optimize eDP link rate\n"); return false; |