diff options
| author |   Linus Torvalds <torvalds@linux-foundation.org> | 2022-08-02 08:15:25 -0700 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2022-08-02 08:15:25 -0700 |
| commit | 3976d758e045ed0485e0e665fb3b6692572576d7 (patch) | |
| tree | 11918dfab24b4daa98293d49dc089809b5dd6e92 | |
| parent | Merge tag 'arm-drivers-6.0' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc (diff) | |
| parent | dt-bindings: soc: bcm: use absolute path to other schema (diff) | |
| download | wireguard-linux-3976d758e045ed0485e0e665fb3b6692572576d7.tar.xz wireguard-linux-3976d758e045ed0485e0e665fb3b6692572576d7.zip | |
Merge tag 'arm-dt-6.0' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM DT updates from Arnd Bergmann:
"As usual, the bulk of the changes for the SoC tree are devicetree file
updates, and most of these changes are for 64-bit embedded machines.
As before, there are a ton of style cleanups, and additional hardware
support for existing machines.
Looking only at the new SoC, the notable additions are:
- A whole family of Broadcom broadband SoCs, both 32-bit and 64-bit:
BCM63178, BCM63158, BCM4912, BCM6858, BCM6878, BCM6846, BCM63146,
BCM6856, BCM6855, BCM6756, BCM63148, and BCM6813. Each SoC comes
with a corresponding reference board.
- The new NXP i.MX93 SoC, the follow-up to the popular i.MX6 and
i.MX8 embedded SoCs, now using Cortex-A55 cores and the Ethos-U65
NPU.
- Qualcomm Snapdragon 8cx Gen3 (SC8280XP), the current high end of
Arm based Laptop SoCs, and its automotive cousin, the SA8540P. The
SC8280XP is used in the Lenovo Thinkpad X13s laptop that also gets
added here in addition to the reference boards.
- Allwinner H616, a newer version of the H6 SoC, targeted at
Set-top-box applications. It comes with dts files for the Orange Pi
zero2 single-board computer and the X96 Mate set-top-box
- Marvell Prestera 98DX2530 (AlleyCat5), a network switch chip in the
Armada SoC family based on the Cortex-A55 core.
New machines based on previously supported SoCs include:
- Several new machines on NXP i.MX platforms: multiple Toradex
Colibri boards using the "Iris" and "Ixora" carriers, DH
electronics i.MX8M Plus DHCOM and PDK2, TQ-Systems TQMa8MPQL, and
phytech phyBOARD-Polis-i.MX8MM.
- Google Chameleon v3 FPGA board based on Intel Arria10 and Stratix
10 Software Virtual platform, both in the SoCFPGA platform.
- Two new wireless devices based on Broadcom SoCs: The Asus GT-AX6000
Router and the Cisco Meraki MR26 access point
- Improved Chromebook support for both the Mediatek and Qualcomm SoC
families brought added machines: Acer Chromebook 514 (MT8192), Acer
Chromebook Spin 513 (MT8195) and a couple of SC7180 based machines
including the Lenovo IdeaPad Chromebook Duet 3.
- Xiaomi Mi Mix2s, LG G7 and LG V35 are mobile phones based on
Qualcomm SDM845, while Mi 5s Plus is based on MSM8996.
- Finally, there are a few development board on other chips: PCB8309
(Microchip lan966x), Radxa Rock Pi S (Rockchips RK3308) DH DRC
Compact (ST STM32MP1) and Inforce IFC6560 (Qualcomm SDM660)"
* tag 'arm-dt-6.0' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (829 commits)
dt-bindings: soc: bcm: use absolute path to other schema
dt-bindings: soc: bcm: drop quotes when not needed
dt-bindings: soc: microchip: use absolute path to other schema
dt-bindings: soc: microchip: drop quotes when not needed
ARM: dts: lan966x: keep lan966 entries alphabetically sorted
ARM: dts: lan966x: add support for pcb8309
dt-bindings: arm: at91: add lan966 pcb8309 board
ARM: dts: lan966x: Enable network driver on pcb8291
ARM: dts: lan966x: Disable can0 on pcb8291
ARM: dts: lan966x: Add gpio-restart
dt-bindings: arm: aspeed: add Aspeed Evaluation boards
arm64: dts: qcom: Add support for Xiaomi Mi Mix2s
dt-bindings: arm: qcom: Add Xiaomi Mi Mix2s bindings
dt-bindings: arm: qcom: Document lg,judyln and lg,judyp devices
dt-bindings: arm: qcom: add missing SM6350 board compatibles
dt-bindings: arm: qcom: add missing SM6125 board compatibles
dt-bindings: arm: qcom: add missing SDM845 board compatibles
dt-bindings: arm: qcom: add missing SDM636 board compatibles
dt-bindings: arm: qcom: add missing SDM630 board compatibles
dt-bindings: arm: qcom: add missing QCS404 board compatibles
...
1011 files changed, 35493 insertions, 6584 deletions
diff --git a/Documentation/arm/google/chromebook-boot-flow.rst b/Documentation/arm/google/chromebook-boot-flow.rst new file mode 100644 index 000000000000..36da77684bba --- /dev/null +++ b/Documentation/arm/google/chromebook-boot-flow.rst @@ -0,0 +1,69 @@ +.. SPDX-License-Identifier: GPL-2.0 + +====================================== +Chromebook Boot Flow +====================================== + +Most recent Chromebooks that use device tree are using the opensource +depthcharge_ bootloader. Depthcharge_ expects the OS to be packaged as a `FIT +Image`_ which contains an OS image as well as a collection of device trees. It +is up to depthcharge_ to pick the right device tree from the `FIT Image`_ and +provide it to the OS. + +The scheme that depthcharge_ uses to pick the device tree takes into account +three variables: + +- Board name, specified at depthcharge_ compile time. This is $(BOARD) below. +- Board revision number, determined at runtime (perhaps by reading GPIO + strappings, perhaps via some other method). This is $(REV) below. +- SKU number, read from GPIO strappings at boot time. This is $(SKU) below. + +For recent Chromebooks, depthcharge_ creates a match list that looks like this: + +- google,$(BOARD)-rev$(REV)-sku$(SKU) +- google,$(BOARD)-rev$(REV) +- google,$(BOARD)-sku$(SKU) +- google,$(BOARD) + +Note that some older Chromebooks use a slightly different list that may +not include SKU matching or may prioritize SKU/rev differently. + +Note that for some boards there may be extra board-specific logic to inject +extra compatibles into the list, but this is uncommon. + +Depthcharge_ will look through all device trees in the `FIT Image`_ trying to +find one that matches the most specific compatible. It will then look +through all device trees in the `FIT Image`_ trying to find the one that +matches the *second most* specific compatible, etc. + +When searching for a device tree, depthcharge_ doesn't care where the +compatible string falls within a device tree's root compatible string array. +As an example, if we're on board "lazor", rev 4, SKU 0 and we have two device +trees: + +- "google,lazor-rev5-sku0", "google,lazor-rev4-sku0", "qcom,sc7180" +- "google,lazor", "qcom,sc7180" + +Then depthcharge_ will pick the first device tree even though +"google,lazor-rev4-sku0" was the second compatible listed in that device tree. +This is because it is a more specific compatible than "google,lazor". + +It should be noted that depthcharge_ does not have any smarts to try to +match board or SKU revisions that are "close by". That is to say that +if depthcharge_ knows it's on "rev4" of a board but there is no "rev4" +device tree then depthcharge_ *won't* look for a "rev3" device tree. + +In general when any significant changes are made to a board the board +revision number is increased even if none of those changes need to +be reflected in the device tree. Thus it's fairly common to see device +trees with multiple revisions. + +It should be noted that, taking into account the above system that +depthcharge_ has, the most flexibility is achieved if the device tree +supporting the newest revision(s) of a board omits the "-rev{REV}" +compatible strings. When this is done then if you get a new board +revision and try to run old software on it then we'll at pick the +newest device tree we know about. + +.. _depthcharge: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/depthcharge/ +.. _`FIT Image`: https://doc.coreboot.org/lib/payloads/fit.html diff --git a/Documentation/arm/index.rst b/Documentation/arm/index.rst index 2bda5461a80b..495ada7915e1 100644 --- a/Documentation/arm/index.rst +++ b/Documentation/arm/index.rst @@ -31,6 +31,8 @@ SoC-specific documents .. toctree:: :maxdepth: 1 + google/chromebook-boot-flow + ixp4xx marvell diff --git a/Documentation/devicetree/bindings/arm/altera.yaml b/Documentation/devicetree/bindings/arm/altera.yaml index 5e2017c0a051..e6de1d7f516c 100644 --- a/Documentation/devicetree/bindings/arm/altera.yaml +++ b/Documentation/devicetree/bindings/arm/altera.yaml @@ -25,7 +25,14 @@ properties: items: - enum: - altr,socfpga-arria10-socdk - - enclustra,mercury-aa1 + - const: altr,socfpga-arria10 + - const: altr,socfpga + + - description: Mercury+ AA1 boards + items: + - enum: + - google,chameleon-v3 + - const: enclustra,mercury-aa1 - const: altr,socfpga-arria10 - const: altr,socfpga @@ -47,6 +54,7 @@ properties: items: - enum: - altr,socfpga-stratix10-socdk + - altr,socfpga-stratix10-swvp - const: altr,socfpga-stratix10 - description: SoCFPGA VT diff --git a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml new file mode 100644 index 000000000000..1895ce9de461 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml @@ -0,0 +1,87 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/aspeed/aspeed.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Aspeed SoC based boards + +maintainers: + - Joel Stanley <joel@jms.id.au> + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - description: AST2400 based boards + items: + - enum: + - facebook,galaxy100-bmc + - facebook,wedge100-bmc + - facebook,wedge40-bmc + - microsoft,olympus-bmc + - quanta,q71l-bmc + - tyan,palmetto-bmc + - yadro,vesnin-bmc + - const: aspeed,ast2400 + + - description: AST2500 based boards + items: + - enum: + - amd,ethanolx-bmc + - ampere,mtjade-bmc + - aspeed,ast2500-evb + - asrock,e3c246d4i-bmc + - asrock,romed8hm3-bmc + - bytedance,g220a-bmc + - facebook,cmm-bmc + - facebook,minipack-bmc + - facebook,tiogapass-bmc + - facebook,yamp-bmc + - facebook,yosemitev2-bmc + - facebook,wedge400-bmc + - hxt,stardragon4800-rep2-bmc + - ibm,mihawk-bmc + - ibm,mowgli-bmc + - ibm,romulus-bmc + - ibm,swift-bmc + - ibm,witherspoon-bmc + - ingrasys,zaius-bmc + - inspur,fp5280g2-bmc + - inspur,nf5280m6-bmc + - inspur,on5263m5-bmc + - intel,s2600wf-bmc + - inventec,lanyang-bmc + - lenovo,hr630-bmc + - lenovo,hr855xg2-bmc + - portwell,neptune-bmc + - qcom,centriq2400-rep-bmc + - supermicro,x11spi-bmc + - tyan,s7106-bmc + - tyan,s8036-bmc + - yadro,nicole-bmc + - yadro,vegman-n110-bmc + - yadro,vegman-rx20-bmc + - yadro,vegman-sx20-bmc + - const: aspeed,ast2500 + + - description: AST2600 based boards + items: + - enum: + - aspeed,ast2600-evb + - aspeed,ast2600-evb-a1 + - facebook,bletchley-bmc + - facebook,cloudripper-bmc + - facebook,elbert-bmc + - facebook,fuji-bmc + - ibm,everest-bmc + - ibm,rainier-bmc + - ibm,tacoma-bmc + - inventec,transformer-bmc + - jabil,rbp-bmc + - nuvia,dc-scm-bmc + - quanta,s6q-bmc + - const: aspeed,ast2600 + +additionalProperties: true diff --git a/Documentation/devicetree/bindings/arm/atmel-at91.yaml b/Documentation/devicetree/bindings/arm/atmel-at91.yaml index 4e495e03264b..2b7848bb7769 100644 --- a/Documentation/devicetree/bindings/arm/atmel-at91.yaml +++ b/Documentation/devicetree/bindings/arm/atmel-at91.yaml @@ -163,9 +163,11 @@ properties: - const: microchip,sama7g5 - const: microchip,sama7 - - description: Microchip LAN9662 PCB8291 Evaluation Board. + - description: Microchip LAN9662 Evaluation Boards. items: - - const: microchip,lan9662-pcb8291 + - enum: + - microchip,lan9662-pcb8291 + - microchip,lan9662-pcb8309 - const: microchip,lan9662 - const: microchip,lan966 diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.yaml b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.yaml index 8b7e87fb6c34..958df32b4899 100644 --- a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.yaml +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.yaml @@ -87,6 +87,13 @@ properties: - const: brcm,bcm53012 - const: brcm,bcm4708 + - description: BCM53015 based boards + items: + - enum: + - meraki,mr26 + - const: brcm,bcm53015 + - const: brcm,bcm4708 + - description: BCM53016 based boards items: - enum: diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,bcmbca.yaml b/Documentation/devicetree/bindings/arm/bcm/brcm,bcmbca.yaml index 5fb455840417..324e59104360 100644 --- a/Documentation/devicetree/bindings/arm/bcm/brcm,bcmbca.yaml +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,bcmbca.yaml @@ -28,6 +28,99 @@ properties: - const: brcm,bcm47622 - const: brcm,bcmbca + - description: BCM4912 based boards + items: + - enum: + - asus,gt-ax6000 + - brcm,bcm94912 + - const: brcm,bcm4912 + - const: brcm,bcmbca + + - description: BCM63138 based boards + items: + - enum: + - brcm,bcm963138 + - brcm,BCM963138DVT + - const: brcm,bcm63138 + - const: brcm,bcmbca + + - description: BCM63146 based boards + items: + - enum: + - brcm,bcm963146 + - const: brcm,bcm63146 + - const: brcm,bcmbca + + - description: BCM63148 based boards + items: + - enum: + - brcm,bcm963148 + - const: brcm,bcm63148 + - const: brcm,bcmbca + + - description: BCM63158 based boards + items: + - enum: + - brcm,bcm963158 + - const: brcm,bcm63158 + - const: brcm,bcmbca + + - description: BCM63178 based boards + items: + - enum: + - brcm,bcm963178 + - const: brcm,bcm63178 + - const: brcm,bcmbca + + - description: BCM6756 based boards + items: + - enum: + - brcm,bcm96756 + - const: brcm,bcm6756 + - const: brcm,bcmbca + + - description: BCM6813 based boards + items: + - enum: + - brcm,bcm96813 + - const: brcm,bcm6813 + - const: brcm,bcmbca + + - description: BCM6846 based boards + items: + - enum: + - brcm,bcm96846 + - const: brcm,bcm6846 + - const: brcm,bcmbca + + - description: BCM6855 based boards + items: + - enum: + - brcm,bcm96855 + - const: brcm,bcm6855 + - const: brcm,bcmbca + + - description: BCM6856 based boards + items: + - enum: + - brcm,bcm96856 + - const: brcm,bcm6856 + - const: brcm,bcmbca + + - description: BCM6858 based boards + items: + - enum: + - brcm,bcm96858 + - const: brcm,bcm6858 + - const: brcm,bcmbca + + - description: BCM6878 based boards + items: + - enum: + - brcm,bcm96878 + - const: brcm,bcm6878 + - const: brcm,bcmbca + additionalProperties: true ... diff --git a/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt b/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt deleted file mode 100644 index a87ec15e28d2..000000000000 --- a/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt +++ /dev/null @@ -1,271 +0,0 @@ -NXP i.MX System Controller Firmware (SCFW) --------------------------------------------------------------------- - -The System Controller Firmware (SCFW) is a low-level system function -which runs on a dedicated Cortex-M core to provide power, clock, and -resource management. It exists on some i.MX8 processors. e.g. i.MX8QM -(QM, QP), and i.MX8QX (QXP, DX). - -The AP communicates with the SC using a multi-ported MU module found -in the LSIO subsystem. The current definition of this MU module provides -5 remote AP connections to the SC to support up to 5 execution environments -(TZ, HV, standard Linux, etc.). The SC side of this MU module interfaces -with the LSIO DSC IP bus. The SC firmware will communicate with this MU -using the MSI bus. - -System Controller Device Node: -============================================================ - -The scu node with the following properties shall be under the /firmware/ node. - -Required properties: -------------------- -- compatible: should be "fsl,imx-scu". -- mbox-names: should include "tx0", "tx1", "tx2", "tx3", - "rx0", "rx1", "rx2", "rx3"; - include "gip3" if want to support general MU interrupt. -- mboxes: List of phandle of 4 MU channels for tx, 4 MU channels for - rx, and 1 optional MU channel for general interrupt. - All MU channels must be in the same MU instance. - Cross instances are not allowed. The MU instance can only - be one of LSIO MU0~M4 for imx8qxp and imx8qm. Users need - to make sure use the one which is not conflict with other - execution environments. e.g. ATF. - Note: - Channel 0 must be "tx0" or "rx0". - Channel 1 must be "tx1" or "rx1". - Channel 2 must be "tx2" or "rx2". - Channel 3 must be "tx3" or "rx3". - General interrupt rx channel must be "gip3". - e.g. - mboxes = <&lsio_mu1 0 0 - &lsio_mu1 0 1 - &lsio_mu1 0 2 - &lsio_mu1 0 3 - &lsio_mu1 1 0 - &lsio_mu1 1 1 - &lsio_mu1 1 2 - &lsio_mu1 1 3 - &lsio_mu1 3 3>; - See Documentation/devicetree/bindings/mailbox/fsl,mu.yaml - for detailed mailbox binding. - -Note: Each mu which supports general interrupt should have an alias correctly -numbered in "aliases" node. -e.g. -aliases { - mu1 = &lsio_mu1; -}; - -i.MX SCU Client Device Node: -============================================================ - -Client nodes are maintained as children of the relevant IMX-SCU device node. - -Power domain bindings based on SCU Message Protocol ------------------------------------------------------------- - -This binding for the SCU power domain providers uses the generic power -domain binding[2]. - -Required properties: -- compatible: Should be one of: - "fsl,imx8qm-scu-pd", - "fsl,imx8qxp-scu-pd" - followed by "fsl,scu-pd" - -- #power-domain-cells: Must be 1. Contains the Resource ID used by - SCU commands. - See detailed Resource ID list from: - include/dt-bindings/firmware/imx/rsrc.h - -Clock bindings based on SCU Message Protocol ------------------------------------------------------------- - -This binding uses the common clock binding[1]. - -Required properties: -- compatible: Should be one of: - "fsl,imx8dxl-clk" - "fsl,imx8qm-clk" - "fsl,imx8qxp-clk" - followed by "fsl,scu-clk" -- #clock-cells: Should be 2. - Contains the Resource and Clock ID value. -- clocks: List of clock specifiers, must contain an entry for - each required entry in clock-names -- clock-names: Should include entries "xtal_32KHz", "xtal_24MHz" - -The clock consumer should specify the desired clock by having the clock -ID in its "clocks" phandle cell. - -See the full list of clock IDs from: -include/dt-bindings/clock/imx8qxp-clock.h - -Pinctrl bindings based on SCU Message Protocol ------------------------------------------------------------- - -This binding uses the i.MX common pinctrl binding[3]. - -Required properties: -- compatible: Should be one of: - "fsl,imx8qm-iomuxc", - "fsl,imx8qxp-iomuxc", - "fsl,imx8dxl-iomuxc". - -Required properties for Pinctrl sub nodes: -- fsl,pins: Each entry consists of 3 integers which represents - the mux and config setting for one pin. The first 2 - integers <pin_id mux_mode> are specified using a - PIN_FUNC_ID macro, which can be found in - <dt-bindings/pinctrl/pads-imx8qm.h>, - <dt-bindings/pinctrl/pads-imx8qxp.h>, - <dt-bindings/pinctrl/pads-imx8dxl.h>. - The last integer CONFIG is the pad setting value like - pull-up on this pin. - - Please refer to i.MX8QXP Reference Manual for detailed - CONFIG settings. - -[1] Documentation/devicetree/bindings/clock/clock-bindings.txt -[2] Documentation/devicetree/bindings/power/power-domain.yaml -[3] Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt - -RTC bindings based on SCU Message Protocol ------------------------------------------------------------- - -Required properties: -- compatible: should be "fsl,imx8qxp-sc-rtc"; - -OCOTP bindings based on SCU Message Protocol ------------------------------------------------------------- -Required properties: -- compatible: Should be one of: - "fsl,imx8qm-scu-ocotp", - "fsl,imx8qxp-scu-ocotp". -- #address-cells: Must be 1. Contains byte index -- #size-cells: Must be 1. Contains byte length - -Optional Child nodes: - -- Data cells of ocotp: - Detailed bindings are described in bindings/nvmem/nvmem.txt - -Watchdog bindings based on SCU Message Protocol ------------------------------------------------------------- - -Required properties: -- compatible: should be: - "fsl,imx8qxp-sc-wdt" - followed by "fsl,imx-sc-wdt"; -Optional properties: -- timeout-sec: contains the watchdog timeout in seconds. - -SCU key bindings based on SCU Message Protocol ------------------------------------------------------------- - -Required properties: -- compatible: should be: - "fsl,imx8qxp-sc-key" - followed by "fsl,imx-sc-key"; -- linux,keycodes: See Documentation/devicetree/bindings/input/input.yaml - -Thermal bindings based on SCU Message Protocol ------------------------------------------------------------- - -Required properties: -- compatible: Should be : - "fsl,imx8qxp-sc-thermal" - followed by "fsl,imx-sc-thermal"; - -- #thermal-sensor-cells: See Documentation/devicetree/bindings/thermal/thermal-sensor.yaml - for a description. - -Example (imx8qxp): -------------- -aliases { - mu1 = &lsio_mu1; -}; - -lsio_mu1: mailbox@5d1c0000 { - ... - #mbox-cells = <2>; -}; - -firmware { - scu { - compatible = "fsl,imx-scu"; - mbox-names = "tx0", "tx1", "tx2", "tx3", - "rx0", "rx1", "rx2", "rx3", - "gip3"; - mboxes = <&lsio_mu1 0 0 - &lsio_mu1 0 1 - &lsio_mu1 0 2 - &lsio_mu1 0 3 - &lsio_mu1 1 0 - &lsio_mu1 1 1 - &lsio_mu1 1 2 - &lsio_mu1 1 3 - &lsio_mu1 3 3>; - - clk: clk { - compatible = "fsl,imx8qxp-clk", "fsl,scu-clk"; - #clock-cells = <2>; - }; - - iomuxc { - compatible = "fsl,imx8qxp-iomuxc"; - - pinctrl_lpuart0: lpuart0grp { - fsl,pins = < - SC_P_UART0_RX_ADMA_UART0_RX 0x06000020 - SC_P_UART0_TX_ADMA_UART0_TX 0x06000020 - >; - }; - ... - }; - - ocotp: imx8qx-ocotp { - compatible = "fsl,imx8qxp-scu-ocotp"; - #address-cells = <1>; - #size-cells = <1>; - - fec_mac0: mac@2c4 { - reg = <0x2c4 8>; - }; - }; - - pd: imx8qx-pd { - compatible = "fsl,imx8qxp-scu-pd", "fsl,scu-pd"; - #power-domain-cells = <1>; - }; - - rtc: rtc { - compatible = "fsl,imx8qxp-sc-rtc"; - }; - - scu_key: scu-key { - compatible = "fsl,imx8qxp-sc-key", "fsl,imx-sc-key"; - linux,keycodes = <KEY_POWER>; - }; - - watchdog { - compatible = "fsl,imx8qxp-sc-wdt", "fsl,imx-sc-wdt"; - timeout-sec = <60>; - }; - - tsens: thermal-sensor { - compatible = "fsl,imx8qxp-sc-thermal", "fsl,imx-sc-thermal"; - #thermal-sensor-cells = <1>; - }; - }; -}; - -serial@5a060000 { - ... - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lpuart0>; - clocks = <&uart0_clk IMX_SC_R_UART_0 IMX_SC_PM_CLK_PER>; - clock-names = "ipg"; - power-domains = <&pd IMX_SC_R_UART_0>; -}; diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index ef524378d449..7431579ab0e8 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -321,6 +321,7 @@ properties: - enum: - toradex,apalis_imx6q-ixora # Apalis iMX6Q/D Module on Ixora Carrier Board - toradex,apalis_imx6q-ixora-v1.1 # Apalis iMX6Q/D Module on Ixora V1.1 Carrier Board + - toradex,apalis_imx6q-ixora-v1.2 # Apalis iMX6Q/D Module on Ixora V1.2 Carrier Board - toradex,apalis_imx6q-eval # Apalis iMX6Q/D Module on Apalis Evaluation Board - const: toradex,apalis_imx6q - const: fsl,imx6q @@ -670,30 +671,30 @@ properties: - description: i.MX6ULL Boards with Toradex Colibri iMX6ULL Modules items: - enum: - - toradex,colibri-imx6ull-aster # Colibri iMX6ULL Module on Aster Carrier Board - - toradex,colibri-imx6ull-eval # Colibri iMX6ULL Module on Colibri Evaluation Board V3 - - toradex,colibri-imx6ull-iris # Colibri iMX6ULL Module on Iris Carrier Board - - toradex,colibri-imx6ull-iris-v2 # Colibri iMX6ULL Module on Iris V2 Carrier Board + - toradex,colibri-imx6ull-aster # Aster Carrier Board + - toradex,colibri-imx6ull-eval # Colibri Evaluation Board V3 + - toradex,colibri-imx6ull-iris # Iris Carrier Board + - toradex,colibri-imx6ull-iris-v2 # Iris V2 Carrier Board - const: toradex,colibri-imx6ull # Colibri iMX6ULL Module - const: fsl,imx6ull - description: i.MX6ULL Boards with Toradex Colibri iMX6ULL 1GB (eMMC) Module items: - enum: - - toradex,colibri-imx6ull-emmc-aster # Colibri iMX6ULL 1G (eMMC) on Aster Carrier Board - - toradex,colibri-imx6ull-emmc-eval # Colibri iMX6ULL 1G (eMMC) on Colibri Evaluation B. V3 - - toradex,colibri-imx6ull-emmc-iris # Colibri iMX6ULL 1G (eMMC) on Iris Carrier Board - - toradex,colibri-imx6ull-emmc-iris-v2 # Colibri iMX6ULL 1G (eMMC) on Iris V2 Carrier Board + - toradex,colibri-imx6ull-emmc-aster # Aster Carrier Board + - toradex,colibri-imx6ull-emmc-eval # Colibri Evaluation B. V3 + - toradex,colibri-imx6ull-emmc-iris # Iris Carrier Board + - toradex,colibri-imx6ull-emmc-iris-v2 # Iris V2 Carrier Board - const: toradex,colibri-imx6ull-emmc # Colibri iMX6ULL 1GB (eMMC) Module - const: fsl,imx6ull - description: i.MX6ULL Boards with Toradex Colibri iMX6ULL Wi-Fi / BT Modules items: - enum: - - toradex,colibri-imx6ull-wifi-eval # Colibri iMX6ULL Wi-Fi / BT M. on Colibri Eval. B. V3 - - toradex,colibri-imx6ull-wifi-aster # Colibri iMX6ULL Wi-Fi / BT M. on Aster Carrier Board - - toradex,colibri-imx6ull-wifi-iris # Colibri iMX6ULL Wi-Fi / BT M. on Iris Carrier Board - - toradex,colibri-imx6ull-wifi-iris-v2 # Colibri iMX6ULL Wi-Fi / BT M. on Iris V2 Carrier Board + - toradex,colibri-imx6ull-wifi-eval # Colibri Eval. B. V3 + - toradex,colibri-imx6ull-wifi-aster # Aster Carrier Board + - toradex,colibri-imx6ull-wifi-iris # Iris Carrier Board + - toradex,colibri-imx6ull-wifi-iris-v2 # Iris V2 Carrier Board - const: toradex,colibri-imx6ull-wifi # Colibri iMX6ULL Wi-Fi / BT Module - const: fsl,imx6ull @@ -738,6 +739,8 @@ properties: - enum: - toradex,colibri-imx7s-aster # Module on Aster Carrier Board - toradex,colibri-imx7s-eval-v3 # Module on Colibri Evaluation Board V3 + - toradex,colibri-imx7s-iris # Module on Iris Carrier Board + - toradex,colibri-imx7s-iris-v2 # Module on Iris Carrier Board V2 - const: toradex,colibri-imx7s - const: fsl,imx7s @@ -789,8 +792,10 @@ properties: - description: i.MX7D Boards with Toradex Colibri i.MX7D Module items: - enum: - - toradex,colibri-imx7d-aster # Colibri iMX7D Module on Aster Carrier Board - - toradex,colibri-imx7d-eval-v3 # Colibri iMX7D Module on Colibri Evaluation Board V3 + - toradex,colibri-imx7d-aster # Aster Carrier Board + - toradex,colibri-imx7d-eval-v3 # Colibri Evaluation Board V3 + - toradex,colibri-imx7d-iris # Iris Carrier Board + - toradex,colibri-imx7d-iris-v2 # Iris Carrier Board V2 - const: toradex,colibri-imx7d - const: fsl,imx7d @@ -799,6 +804,8 @@ properties: - enum: - toradex,colibri-imx7d-emmc-aster # Module on Aster Carrier Board - toradex,colibri-imx7d-emmc-eval-v3 # Module on Colibri Evaluation Board V3 + - toradex,colibri-imx7d-emmc-iris # Module on Iris Carrier Board + - toradex,colibri-imx7d-emmc-iris-v2 # Module on Iris Carrier Board V2 - const: toradex,colibri-imx7d-emmc - const: fsl,imx7d @@ -865,6 +872,12 @@ properties: - const: toradex,verdin-imx8mm # Verdin iMX8M Mini Module - const: fsl,imx8mm + - description: PHYTEC phyCORE-i.MX8MM SoM based boards + items: + - const: phytec,imx8mm-phyboard-polis-rdk # phyBOARD-Polis RDK + - const: phytec,imx8mm-phycore-som # phyCORE-i.MX8MM SoM + - const: fsl,imx8mm + - description: Variscite VAR-SOM-MX8MM based boards items: - const: variscite,var-som-mx8mm-symphony @@ -914,6 +927,8 @@ properties: - description: i.MX8MP based Boards items: - enum: + - dh,imx8mp-dhcom-som # i.MX8MP DHCOM SoM + - dh,imx8mp-dhcom-pdk2 # i.MX8MP DHCOM SoM on PDK2 board - fsl,imx8mp-evk # i.MX8MP EVK Board - gateworks,imx8mp-gw74xx # i.MX8MP Gateworks Board - toradex,verdin-imx8mp # Verdin iMX8M Plus Modules @@ -952,6 +967,18 @@ properties: - const: toradex,verdin-imx8mp # Verdin iMX8M Plus Module - const: fsl,imx8mp + - description: + TQMa8MPxL is a series of LGA SOM featuring NXP i.MX8MP system-on-chip + variants. It is designed to be soldered on different carrier boards. + All CPU variants use the same device tree hence only one compatible + is needed. MBa8MPxL mainboard can be used as starterkit or in a boxed + version as an industrial computing device. + items: + - enum: + - tq,imx8mp-tqma8mpql-mba8mpxl # TQ-Systems GmbH i.MX8MP TQMa8MPQL SOM on MBa8MPxL + - const: tq,imx8mp-tqma8mpql # TQ-Systems GmbH i.MX8MP TQMa8MPQL SOM + - const: fsl,imx8mp + - description: i.MX8MQ based Boards items: - enum: @@ -1020,6 +1047,12 @@ properties: - fsl,imx8ulp-evk # i.MX8ULP EVK Board - const: fsl,imx8ulp + - description: i.MX93 based Boards + items: + - enum: + - fsl,imx93-11x11-evk # i.MX93 11x11 EVK Board + - const: fsl,imx93 + - description: Freescale Vybrid Platform Device Tree Bindings diff --git a/Documentation/devicetree/bindings/arm/marvell/marvell,ac5.yaml b/Documentation/devicetree/bindings/arm/marvell/marvell,ac5.yaml new file mode 100644 index 000000000000..8960fb8b2b2f --- /dev/null +++ b/Documentation/devicetree/bindings/arm/marvell/marvell,ac5.yaml @@ -0,0 +1,32 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/marvell/marvell,ac5.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell Alleycat5/5X Platforms + +maintainers: + - Chris Packham <chris.packham@alliedtelesis.co.nz> + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - description: Alleycat5 (98DX25xx) Reference Design + items: + - enum: + - marvell,rd-ac5 + - const: marvell,ac5 + + - description: Alleycat5X (98DX35xx) Reference Design + items: + - enum: + - marvell,rd-ac5x + - const: marvell,ac5x + - const: marvell,ac5 + +additionalProperties: true + +... diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Documentation/devicetree/bindings/arm/mediatek.yaml index 4a2bd9759c47..07c0ea94e850 100644 --- a/Documentation/devicetree/bindings/arm/mediatek.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek.yaml @@ -131,6 +131,36 @@ properties: - enum: - mediatek,mt8183-evb - const: mediatek,mt8183 + - description: Google Hayato + items: + - const: google,hayato-rev1 + - const: google,hayato + - const: mediatek,mt8192 + - description: Google Spherion (Acer Chromebook 514) + items: + - const: google,spherion-rev3 + - const: google,spherion-rev2 + - const: google,spherion-rev1 + - const: google,spherion-rev0 + - const: google,spherion + - const: mediatek,mt8192 + - description: Acer Tomato (Acer Chromebook Spin 513 CP513-2H) + items: + - enum: + - google,tomato-rev2 + - google,tomato-rev1 + - const: google,tomato + - const: mediatek,mt8195 + - description: Acer Tomato rev3 - 4 (Acer Chromebook Spin 513 CP513-2H) + items: + - const: google,tomato-rev4 + - const: google,tomato-rev3 + - const: google,tomato + - const: mediatek,mt8195 + - items: + - enum: + - mediatek,mt8186-evb + - const: mediatek,mt8186 - items: - enum: - mediatek,mt8192-evb diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.yaml index 611f666f359d..8585f6f18f69 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.yaml @@ -26,6 +26,7 @@ properties: - mediatek,mt8135-pericfg - mediatek,mt8173-pericfg - mediatek,mt8183-pericfg + - mediatek,mt8186-pericfg - mediatek,mt8195-pericfg - mediatek,mt8516-pericfg - const: syscon diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 6208558e1036..fb1d00bcc847 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -38,18 +38,24 @@ description: | msm8992 msm8994 msm8996 + msm8998 + qcs404 sa8155p sa8540p sc7180 sc7280 sc8180x sc8280xp + sda660 sdm630 sdm632 + sdm636 sdm660 sdm845 sdx55 sdx65 + sm6125 + sm6350 sm7225 sm8150 sm8250 @@ -90,6 +96,11 @@ description: | A dragonboard board v0.1 of subtype 1 with an apq8074 SoC version 2, made in foundry 2. + There are many devices in the list below that run the standard ChromeOS + bootloader setup and use the open source depthcharge bootloader to boot the + OS. These devices do not use the scheme described above. For details, see: + https://docs.kernel.org/arm/google/chromebook-boot-flow.html + properties: $nodename: const: "/" @@ -153,28 +164,50 @@ properties: - const: qcom,msm8974 - items: - - enum: - - alcatel,idol347 - - const: qcom,msm8916-mtp/1 - const: qcom,msm8916-mtp + - const: qcom,msm8916-mtp/1 - const: qcom,msm8916 - items: - enum: - - longcheer,l8150 + - alcatel,idol347 + - asus,z00l + - huawei,g7 + - longcheer,l8910 - samsung,a3u-eur - samsung,a5u-eur + - samsung,j5 + - samsung,serranove + - wingtech,wt88047 + - const: qcom,msm8916 + + - items: + - const: longcheer,l8150 + - const: qcom,msm8916-v1-qrd/9-v1 - const: qcom,msm8916 - items: - enum: + - lg,bullhead + - microsoft,talkman + - xiaomi,libra + - const: qcom,msm8992 + + - items: + - enum: - sony,karin_windy + - const: qcom,apq8094 + + - items: + - enum: + - huawei,angler + - microsoft,cityman + - sony,ivy-row - sony,karin-row - sony,satsuki-row - sony,sumire-row - sony,suzuran-row - - qcom,msm8994 - - const: qcom,apq8094 + - const: qcom,msm8994 - items: - enum: @@ -190,11 +223,26 @@ properties: - sony,kagura-row - sony,keyaki-row - xiaomi,gemini + - xiaomi,natrium - xiaomi,scorpio - const: qcom,msm8996 - items: - enum: + - asus,novago-tp370ql + - fxtec,pro1 + - hp,envy-x2 + - lenovo,miix-630 + - oneplus,cheeseburger + - oneplus,dumpling + - qcom,msm8998-mtp + - sony,xperia-lilac + - sony,xperia-maple + - sony,xperia-poplar + - const: qcom,msm8998 + + - items: + - enum: - qcom,ipq4019-ap-dk01.1-c1 - qcom,ipq4019-ap-dk04.1-c3 - qcom,ipq4019-ap-dk07.1-c1 @@ -214,19 +262,317 @@ properties: - qcom,ipq8074-hk10-c2 - const: qcom,ipq8074 - - items: + - description: Qualcomm Technologies, Inc. SC7180 IDP + items: - enum: - qcom,sc7180-idp - const: qcom,sc7180 - - items: - - enum: - - qcom,sc7280-crd - - qcom,sc7280-idp - - qcom,sc7280-idp2 - - google,hoglin - - google,piglin - - google,senor + - description: HP Chromebook x2 11c (rev1 - 2) + items: + - const: google,coachz-rev1 + - const: google,coachz-rev2 + - const: qcom,sc7180 + + - description: HP Chromebook x2 11c (newest rev) + items: + - const: google,coachz + - const: qcom,sc7180 + + - description: HP Chromebook x2 11c with LTE (rev1 - 2) + items: + - const: google,coachz-rev1-sku0 + - const: google,coachz-rev2-sku0 + - const: qcom,sc7180 + + - description: HP Chromebook x2 11c with LTE (newest rev) + items: + - const: google,coachz-sku0 + - const: qcom,sc7180 + + - description: Lenovo Chromebook Duet 5 13 (rev2) + items: + - const: google,homestar-rev2 + - const: google,homestar-rev23 + - const: qcom,sc7180 + + - description: Lenovo Chromebook Duet 5 13 (rev3) + items: + - const: google,homestar-rev3 + - const: qcom,sc7180 + + - description: Lenovo Chromebook Duet 5 13 (newest rev) + items: + - const: google,homestar + - const: qcom,sc7180 + + - description: Google Kingoftown (rev0) + items: + - const: google,kingoftown-rev0 + - const: qcom,sc7180 + + - description: Google Kingoftown (newest rev) + items: + - const: google,kingoftown + - const: qcom,sc7180 + + - description: Acer Chromebook Spin 513 (rev0) + items: + - const: google,lazor-rev0 + - const: qcom,sc7180 + + - description: Acer Chromebook Spin 513 (rev1 - 2) + items: + - const: google,lazor-rev1 + - const: google,lazor-rev2 + - const: qcom,sc7180 + + - description: Acer Chromebook Spin 513 (rev3 - 8) + items: + - const: google,lazor-rev3 + - const: google,lazor-rev4 + - const: google,lazor-rev5 + - const: google,lazor-rev6 + - const: google,lazor-rev7 + - const: google,lazor-rev8 + - const: qcom,sc7180 + + - description: Acer Chromebook Spin 513 (newest rev) + items: + - const: google,lazor + - const: qcom,sc7180 + + - description: Acer Chromebook Spin 513 with KB Backlight (rev1 - 2) + items: + - const: google,lazor-rev1-sku2 + - const: google,lazor-rev2-sku2 + - const: qcom,sc7180 + + - description: Acer Chromebook Spin 513 with KB Backlight (rev3 - 8) + items: + - const: google,lazor-rev3-sku2 + - const: google,lazor-rev4-sku2 + - const: google,lazor-rev5-sku2 + - const: google,lazor-rev6-sku2 + - const: google,lazor-rev7-sku2 + - const: google,lazor-rev8-sku2 + - const: qcom,sc7180 + + - description: Acer Chromebook Spin 513 with KB Backlight (newest rev) + items: + - const: google,lazor-sku2 + - const: qcom,sc7180 + + - description: Acer Chromebook Spin 513 with LTE (rev1 - 2) + items: + - const: google,lazor-rev1-sku0 + - const: google,lazor-rev2-sku0 + - const: qcom,sc7180 + + - description: Acer Chromebook Spin 513 with LTE (rev3 - 8) + items: + - const: google,lazor-rev3-sku0 + - const: google,lazor-rev4-sku0 + - const: google,lazor-rev5-sku0 + - const: google,lazor-rev6-sku0 + - const: google,lazor-rev7-sku0 + - const: google,lazor-rev8-sku0 + - const: qcom,sc7180 + + - description: Acer Chromebook Spin 513 with LTE (newest rev) + items: + - const: google,lazor-sku0 + - const: qcom,sc7180 + + - description: Acer Chromebook 511 (rev4 - rev8) + items: + - const: google,lazor-rev4-sku4 + - const: google,lazor-rev5-sku4 + - const: google,lazor-rev6-sku4 + - const: google,lazor-rev7-sku4 + - const: google,lazor-rev8-sku4 + - const: qcom,sc7180 + + - description: Acer Chromebook 511 (newest rev) + items: + - const: google,lazor-sku4 + - const: qcom,sc7180 + + - description: Acer Chromebook 511 without Touchscreen (rev4) + items: + - const: google,lazor-rev4-sku5 + - const: qcom,sc7180 + + - description: Acer Chromebook 511 without Touchscreen (rev5 - rev8) + items: + - const: google,lazor-rev5-sku5 + - const: google,lazor-rev5-sku6 + - const: google,lazor-rev6-sku6 + - const: google,lazor-rev7-sku6 + - const: google,lazor-rev8-sku6 + - const: qcom,sc7180 + + - description: Acer Chromebook 511 without Touchscreen (newest rev) + items: + - const: google,lazor-sku6 + - const: qcom,sc7180 + + - description: Google Mrbland with AUO panel (rev0) + items: + - const: google,mrbland-rev0-sku0 + - const: qcom,sc7180 + + - description: Google Mrbland with AUO panel (newest rev) + items: + - const: google,mrbland-sku1536 + - const: qcom,sc7180 + + - description: Google Mrbland with BOE panel (rev0) + items: + - const: google,mrbland-rev0-sku16 + - const: qcom,sc7180 + + - description: Google Mrbland with BOE panel (newest rev) + items: + - const: google,mrbland-sku1024 + - const: google,mrbland-sku768 + - const: qcom,sc7180 + + - description: Google Pazquel with Parade (newest rev) + items: + - const: google,pazquel-sku5 + - const: qcom,sc7180 + + - description: Google Pazquel with TI (newest rev) + items: + - const: google,pazquel-sku1 + - const: qcom,sc7180 + + - description: Google Pazquel with LTE and Parade (newest rev) + items: + - const: google,pazquel-sku4 + - const: qcom,sc7180 + + - description: Google Pazquel with LTE and TI (newest rev) + items: + - const: google,pazquel-sku0 + - const: google,pazquel-sku2 + - const: qcom,sc7180 + + - description: Sharp Dynabook Chromebook C1 (rev1) + items: + - const: google,pompom-rev1 + - const: qcom,sc7180 + + - description: Sharp Dynabook Chromebook C1 (rev2) + items: + - const: google,pompom-rev2 + - const: qcom,sc7180 + + - description: Sharp Dynabook Chromebook C1 (newest rev) + items: + - const: google,pompom + - const: qcom,sc7180 + + - description: Sharp Dynabook Chromebook C1 with LTE (rev1) + items: + - const: google,pompom-rev1-sku0 + - const: qcom,sc7180 + + - description: Sharp Dynabook Chromebook C1 with LTE (rev2) + items: + - const: google,pompom-rev2-sku0 + - const: qcom,sc7180 + + - description: Sharp Dynabook Chromebook C1 with LTE (newest rev) + items: + - const: google,pompom-sku0 + - const: qcom,sc7180 + + - description: Google Quackingstick (newest rev) + items: + - const: google,quackingstick-sku1537 + - const: qcom,sc7180 + + - description: Google Quackingstick with LTE (newest rev) + items: + - const: google,quackingstick-sku1536 + - const: qcom,sc7180 + + - description: Google Trogdor (newest rev) + items: + - const: google,trogdor + - const: qcom,sc7180 + + - description: Google Trogdor with LTE (newest rev) + items: + - const: google,trogdor-sku0 + - const: qcom,sc7180 + + - description: Lenovo IdeaPad Chromebook Duet 3 with BOE panel (rev0) + items: + - const: google,wormdingler-rev0-sku16 + - const: qcom,sc7180 + + - description: Lenovo IdeaPad Chromebook Duet 3 with BOE panel (newest rev) + items: + - const: google,wormdingler-sku1024 + - const: qcom,sc7180 + + - description: Lenovo IdeaPad Chromebook Duet 3 with BOE panel and rt5682s (newest rev) + items: + - const: google,wormdingler-sku1025 + - const: qcom,sc7180 + + - description: Lenovo IdeaPad Chromebook Duet 3 with INX panel (rev0) + items: + - const: google,wormdingler-rev0-sku0 + - const: qcom,sc7180 + + - description: Lenovo IdeaPad Chromebook Duet 3 with INX panel (newest rev) + items: + - const: google,wormdingler-sku0 + - const: qcom,sc7180 + + - description: Lenovo IdeaPad Chromebook Duet 3 with INX panel and rt5682s (newest rev) + items: + - const: google,wormdingler-sku1 + - const: qcom,sc7180 + + - description: Qualcomm Technologies, Inc. sc7280 CRD platform (rev3 - 4) + items: + - const: qcom,sc7280-crd + - const: google,hoglin-rev3 + - const: google,hoglin-rev4 + - const: google,piglin-rev3 + - const: google,piglin-rev4 + - const: qcom,sc7280 + + - description: Qualcomm Technologies, Inc. sc7280 CRD platform (newest rev) + items: + - const: google,hoglin + - const: qcom,sc7280 + + - description: Qualcomm Technologies, Inc. sc7280 IDP SKU1 platform + items: + - const: qcom,sc7280-idp + - const: google,senor + - const: qcom,sc7280 + + - description: Qualcomm Technologies, Inc. sc7280 IDP SKU2 platform + items: + - const: qcom,sc7280-idp2 + - const: google,piglin + - const: qcom,sc7280 + + - description: Google Herobrine (newest rev) + items: + - const: google,herobrine + - const: qcom,sc7280 + + - description: Google Villager (newest rev) + items: + - const: google,villager - const: qcom,sc7280 - items: @@ -238,16 +584,36 @@ properties: - items: - enum: + - lenovo,thinkpad-x13s + - qcom,sc8280xp-crd - qcom,sc8280xp-qrd - const: qcom,sc8280xp - items: - enum: + - sony,discovery-row + - sony,kirin-row + - sony,pioneer-row + - sony,voyager-row + - const: qcom,sdm630 + + - items: + - enum: + - inforce,ifc6560 + - const: qcom,sda660 + + - items: + - enum: - fairphone,fp3 - const: qcom,sdm632 - items: - enum: + - sony,mermaid-row + - const: qcom,sdm636 + + - items: + - enum: - xiaomi,lavender - const: qcom,sdm660 @@ -271,6 +637,13 @@ properties: - items: - enum: + - qcom,qcs404-evb-1000 + - qcom,qcs404-evb-4000 + - const: qcom,qcs404-evb + - const: qcom,qcs404 + + - items: + - enum: - qcom,sa8155p-adp - const: qcom,sa8155p @@ -281,24 +654,62 @@ properties: - items: - enum: + - lenovo,yoga-c630 + - lg,judyln + - lg,judyp + - oneplus,enchilada + - oneplus,fajita + - qcom,sdm845-mtp + - shift,axolotl + - samsung,w737 + - sony,akari-row + - sony,akatsuki-row + - sony,apollo-row + - thundercomm,db845c + - xiaomi,beryllium + - xiaomi,polaris + - const: qcom,sdm845 + + - items: + - enum: + - sony,pdx201 + - const: qcom,sm6125 + + - items: + - enum: + - sony,pdx213 + - const: qcom,sm6350 + + - items: + - enum: - fairphone,fp4 - const: qcom,sm7225 - items: - enum: + - microsoft,surface-duo + - qcom,sm8150-hdk - qcom,sm8150-mtp + - sony,bahamut-generic + - sony,griffin-generic - const: qcom,sm8150 - items: - enum: - qcom,qrb5165-rb5 + - qcom,sm8250-hdk - qcom,sm8250-mtp + - sony,pdx203-generic + - sony,pdx206-generic - const: qcom,sm8250 - items: - enum: + - microsoft,surface-duo2 - qcom,sm8350-hdk - qcom,sm8350-mtp + - sony,pdx214-generic + - sony,pdx215-generic - const: qcom,sm8350 - items: diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index cf9eb1e8326a..7811ba64149c 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -554,6 +554,11 @@ properties: - const: vamrs,rk3399pro-vmarc-som - const: rockchip,rk3399pro + - description: Radxa ROCK Pi S + items: + - const: radxa,rockpis + - const: rockchip,rk3308 + - description: Radxa Rock2 Square items: - const: radxa,rock2-square diff --git a/Documentation/devicetree/bindings/arm/samsung/samsung-soc.yaml b/Documentation/devicetree/bindings/arm/samsung/samsung-soc.yaml new file mode 100644 index 000000000000..653f85997643 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/samsung/samsung-soc.yaml @@ -0,0 +1,40 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/samsung/samsung-soc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung S3C, S5P and Exynos SoC compatibles naming convention + +maintainers: + - Krzysztof Kozlowski <krzk@kernel.org> + +description: | + Guidelines for new compatibles for SoC blocks/components. + When adding new compatibles in new bindings, use the format:: + samsung,SoC-IP + + For example:: + samsung,exynos5433-cmu-isp + +select: + properties: + compatible: + pattern: "^samsung,.*(s3c|s5pv|exynos)[0-9a-z]+.*$" + required: + - compatible + +properties: + compatible: + oneOf: + - description: Preferred naming style for compatibles of SoC components + pattern: "^samsung,(s3c|s5pv|exynos|exynosautov)[0-9]+-.*$" + + # Legacy compatibles with wild-cards - list cannot grow with new bindings: + - enum: + - samsung,exynos4x12-pinctrl + - samsung,exynos4x12-usb2-phy + - samsung,s3c64xx-pinctrl + - samsung,s3c64xx-wakeup-eint + +additionalProperties: true diff --git a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml index 8b31565fee59..4c605bccc474 100644 --- a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml +++ b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml @@ -59,12 +59,18 @@ properties: - prt,prtt1s # Protonic PRTT1S - const: st,stm32mp151 - - description: DH STM32MP153 SoM based Boards + - description: DH STM32MP153 DHCOM SoM based Boards items: - const: dh,stm32mp153c-dhcom-drc02 - const: dh,stm32mp153c-dhcom-som - const: st,stm32mp153 + - description: DH STM32MP153 DHCOR SoM based Boards + items: + - const: dh,stm32mp153c-dhcor-drc-compact + - const: dh,stm32mp153c-dhcor-som + - const: st,stm32mp153 + - items: - enum: - shiratech,stm32mp157a-iot-box # IoT Box diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml b/Documentation/devicetree/bindings/arm/sunxi.yaml index 95278a6a9a8e..0c2356778208 100644 --- a/Documentation/devicetree/bindings/arm/sunxi.yaml +++ b/Documentation/devicetree/bindings/arm/sunxi.yaml @@ -863,6 +863,11 @@ properties: - const: yones-toptech,bs1078-v2 - const: allwinner,sun6i-a31s + - description: X96 Mate TV box + items: + - const: hechuang,x96-mate + - const: allwinner,sun50i-h616 + - description: Xunlong OrangePi items: - const: xunlong,orangepi @@ -963,4 +968,9 @@ properties: - const: xunlong,orangepi-zero-plus2-h3 - const: allwinner,sun8i-h3 + - description: Xunlong OrangePi Zero 2 + items: + - const: xunlong,orangepi-zero2 + - const: allwinner,sun50i-h616 + additionalProperties: true diff --git a/Documentation/devicetree/bindings/arm/sunxi/allwinner,sun4i-a10-mbus.yaml b/Documentation/devicetree/bindings/arm/sunxi/allwinner,sun4i-a10-mbus.yaml index 8eee312c2e6f..99566688d033 100644 --- a/Documentation/devicetree/bindings/arm/sunxi/allwinner,sun4i-a10-mbus.yaml +++ b/Documentation/devicetree/bindings/arm/sunxi/allwinner,sun4i-a10-mbus.yaml @@ -29,10 +29,20 @@ properties: compatible: enum: - allwinner,sun5i-a13-mbus + - allwinner,sun8i-a33-mbus + - allwinner,sun8i-a50-mbus + - allwinner,sun8i-a83t-mbus - allwinner,sun8i-h3-mbus - allwinner,sun8i-r40-mbus + - allwinner,sun8i-v3s-mbus + - allwinner,sun8i-v536-mbus + - allwinner,sun20i-d1-mbus - allwinner,sun50i-a64-mbus + - allwinner,sun50i-a100-mbus - allwinner,sun50i-h5-mbus + - allwinner,sun50i-h6-mbus + - allwinner,sun50i-h616-mbus + - allwinner,sun50i-r329-mbus reg: minItems: 1 @@ -81,13 +91,13 @@ required: - dma-ranges if: - properties: - compatible: - contains: - enum: - - allwinner,sun8i-h3-mbus - - allwinner,sun50i-a64-mbus - - allwinner,sun50i-h5-mbus + not: + properties: + compatible: + contains: + enum: + - allwinner,sun5i-a13-mbus + - allwinner,sun8i-r40-mbus then: properties: diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra-ccplex-cluster.yaml b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra-ccplex-cluster.yaml index 8c6543b5c0dc..711bb4d08c60 100644 --- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra-ccplex-cluster.yaml +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra-ccplex-cluster.yaml @@ -40,7 +40,6 @@ required: - compatible - reg - nvidia,bpmp - - status examples: - | diff --git a/Documentation/devicetree/bindings/clock/allwinner,sun8i-a83t-de2-clk.yaml b/Documentation/devicetree/bindings/clock/allwinner,sun8i-a83t-de2-clk.yaml index e79eeac5f086..17caf78f0ccf 100644 --- a/Documentation/devicetree/bindings/clock/allwinner,sun8i-a83t-de2-clk.yaml +++ b/Documentation/devicetree/bindings/clock/allwinner,sun8i-a83t-de2-clk.yaml @@ -28,6 +28,9 @@ properties: - items: - const: allwinner,sun8i-r40-de2-clk - const: allwinner,sun8i-h3-de2-clk + - items: + - const: allwinner,sun20i-d1-de2-clk + - const: allwinner,sun50i-h5-de2-clk reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/clock/fsl,scu-clk.yaml b/Documentation/devicetree/bindings/clock/fsl,scu-clk.yaml new file mode 100644 index 000000000000..f2c48460a399 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/fsl,scu-clk.yaml @@ -0,0 +1,43 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/fsl,scu-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: i.MX SCU Client Device Node - Clock bindings based on SCU Message Protocol + +maintainers: + - Abel Vesa <abel.vesa@nxp.com> + +description: i.MX SCU Client Device Node + Client nodes are maintained as children of the relevant IMX-SCU device node. + This binding uses the common clock binding. + (Documentation/devicetree/bindings/clock/clock-bindings.txt) + The clock consumer should specify the desired clock by having the clock + ID in its "clocks" phandle cell. See the full list of clock IDs from + include/dt-bindings/clock/imx8qxp-clock.h + +properties: + compatible: + items: + - enum: + - fsl,imx8dxl-clk + - fsl,imx8qm-clk + - fsl,imx8qxp-clk + - const: fsl,scu-clk + + '#clock-cells': + const: 2 + +required: + - compatible + - '#clock-cells' + +additionalProperties: false + +examples: + - | + clock-controller { + compatible = "fsl,imx8qxp-clk", "fsl,scu-clk"; + #clock-cells = <2>; + }; diff --git a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml index 31497677e8de..7a8d375e055e 100644 --- a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml @@ -4,18 +4,19 @@ $id: http://devicetree.org/schemas/clock/qcom,dispcc-sm8x50.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Qualcomm Display Clock & Reset Controller Binding for SM8150/SM8250 +title: Qualcomm Display Clock & Reset Controller Binding for SM8150/SM8250/SM8350 maintainers: - Jonathan Marek <jonathan@marek.ca> description: | Qualcomm display clock control module which supports the clocks, resets and - power domains on SM8150 and SM8250. + power domains on SM8150/SM8250/SM8350. See also: dt-bindings/clock/qcom,dispcc-sm8150.h dt-bindings/clock/qcom,dispcc-sm8250.h + dt-bindings/clock/qcom,dispcc-sm8350.h properties: compatible: @@ -23,6 +24,7 @@ properties: - qcom,sc8180x-dispcc - qcom,sm8150-dispcc - qcom,sm8250-dispcc + - qcom,sm8350-dispcc clocks: items: diff --git a/Documentation/devicetree/bindings/clock/qcom,gpucc-sm8350.yaml b/Documentation/devicetree/bindings/clock/qcom,gpucc-sm8350.yaml new file mode 100644 index 000000000000..0a0546c079a9 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,gpucc-sm8350.yaml @@ -0,0 +1,72 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,gpucc-sm8350.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Graphics Clock & Reset Controller Binding + +maintainers: + - Robert Foss <robert.foss@linaro.org> + +description: | + Qualcomm graphics clock control module which supports the clocks, resets and + power domains on Qualcomm SoCs. + + See also: + dt-bindings/clock/qcom,gpucc-sm8350.h + +properties: + compatible: + enum: + - qcom,sm8350-gpucc + + clocks: + items: + - description: Board XO source + - description: GPLL0 main branch source + - description: GPLL0 div branch source + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + '#power-domain-cells': + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - '#clock-cells' + - '#reset-cells' + - '#power-domain-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,gcc-sm8350.h> + #include <dt-bindings/clock/qcom,rpmh.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + clock-controller@3d90000 { + compatible = "qcom,sm8350-gpucc"; + reg = <0 0x03d90000 0 0x9000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml new file mode 100644 index 000000000000..268f4c6ae0ee --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml @@ -0,0 +1,80 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sm8450-camcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Camera Clock & Reset Controller Binding for SM8450 + +maintainers: + - Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> + +description: | + Qualcomm camera clock control module which supports the clocks, resets and + power domains on SM8450. + + See also include/dt-bindings/clock/qcom,sm8450-camcc.h + +properties: + compatible: + const: qcom,sm8450-camcc + + clocks: + items: + - description: Camera AHB clock from GCC + - description: Board XO source + - description: Board active XO source + - description: Sleep clock source + + power-domains: + maxItems: 1 + description: + A phandle and PM domain specifier for the MMCX power domain. + + required-opps: + description: + A phandle to an OPP node describing required MMCX performance point. + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + '#power-domain-cells': + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - power-domains + - required-opps + - '#clock-cells' + - '#reset-cells' + - '#power-domain-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,gcc-sm8450.h> + #include <dt-bindings/clock/qcom,rpmh.h> + #include <dt-bindings/power/qcom-rpmpd.h> + clock-controller@ade0000 { + compatible = "qcom,sm8450-camcc"; + reg = <0xade0000 0x20000>; + clocks = <&gcc GCC_CAMERA_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>; + power-domains = <&rpmhpd SM8450_MMCX>; + required-opps = <&rpmhpd_opp_low_svs>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... diff --git a/Documentation/devicetree/bindings/clock/samsung,exynos7885-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynos7885-clock.yaml index 5073e569a47f..006d33a9e0f1 100644 --- a/Documentation/devicetree/bindings/clock/samsung,exynos7885-clock.yaml +++ b/Documentation/devicetree/bindings/clock/samsung,exynos7885-clock.yaml @@ -33,6 +33,7 @@ properties: enum: - samsung,exynos7885-cmu-top - samsung,exynos7885-cmu-core + - samsung,exynos7885-cmu-fsys - samsung,exynos7885-cmu-peri clocks: @@ -92,6 +93,32 @@ allOf: properties: compatible: contains: + const: samsung,exynos7885-cmu-fsys + + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: CMU_FSYS bus clock (from CMU_TOP) + - description: MMC_CARD clock (from CMU_TOP) + - description: MMC_EMBD clock (from CMU_TOP) + - description: MMC_SDIO clock (from CMU_TOP) + - description: USB30DRD clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: dout_fsys_bus + - const: dout_fsys_mmc_card + - const: dout_fsys_mmc_embd + - const: dout_fsys_mmc_sdio + - const: dout_fsys_usb30drd + + - if: + properties: + compatible: + contains: const: samsung,exynos7885-cmu-peri then: diff --git a/Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.yaml b/Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.yaml index f8c474227807..242fe922b035 100644 --- a/Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.yaml +++ b/Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.yaml @@ -78,6 +78,7 @@ if: contains: enum: - st,stm32mp1-rcc-secure + - st,stm32mp13-rcc then: properties: clocks: diff --git a/Documentation/devicetree/bindings/cpufreq/qcom-cpufreq-nvmem.yaml b/Documentation/devicetree/bindings/cpufreq/qcom-cpufreq-nvmem.yaml index a9a776da5505..10b3a7a4af36 100644 --- a/Documentation/devicetree/bindings/cpufreq/qcom-cpufreq-nvmem.yaml +++ b/Documentation/devicetree/bindings/cpufreq/qcom-cpufreq-nvmem.yaml @@ -63,8 +63,8 @@ additionalProperties: true examples: - | / { - model = "Qualcomm Technologies, Inc. QCS404"; - compatible = "qcom,qcs404"; + model = "Qualcomm Technologies, Inc. QCS404 EVB 1000"; + compatible = "qcom,qcs404-evb-1000", "qcom,qcs404-evb", "qcom,qcs404"; #address-cells = <2>; #size-cells = <2>; diff --git a/Documentation/devicetree/bindings/firmware/fsl,scu.yaml b/Documentation/devicetree/bindings/firmware/fsl,scu.yaml new file mode 100644 index 000000000000..b40b0ef56978 --- /dev/null +++ b/Documentation/devicetree/bindings/firmware/fsl,scu.yaml @@ -0,0 +1,210 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/firmware/fsl,scu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP i.MX System Controller Firmware (SCFW) + +maintainers: + - Dong Aisheng <aisheng.dong@nxp.com> + +description: + The System Controller Firmware (SCFW) is a low-level system function + which runs on a dedicated Cortex-M core to provide power, clock, and + resource management. It exists on some i.MX8 processors. e.g. i.MX8QM + (QM, QP), and i.MX8QX (QXP, DX). + The AP communicates with the SC using a multi-ported MU module found + in the LSIO subsystem. The current definition of this MU module provides + 5 remote AP connections to the SC to support up to 5 execution environments + (TZ, HV, standard Linux, etc.). The SC side of this MU module interfaces + with the LSIO DSC IP bus. The SC firmware will communicate with this MU + using the MSI bus. + +properties: + compatible: + const: fsl,imx-scu + + clock-controller: + description: + Clock controller node that provides the clocks controlled by the SCU + $ref: /schemas/clock/fsl,scu-clk.yaml + + ocotp: + description: + OCOTP controller node provided by the SCU + $ref: /schemas/nvmem/fsl,scu-ocotp.yaml + + keys: + description: + Keys provided by the SCU + $ref: /schemas/input/fsl,scu-key.yaml + + mboxes: + description: + A list of phandles of TX MU channels followed by a list of phandles of + RX MU channels. The list may include at the end one more optional MU + channel for general interrupt. The number of expected tx and rx + channels is 1 TX and 1 RX channels if MU instance is "fsl,imx8-mu-scu" + compatible, 4 TX and 4 RX channels otherwise. All MU channels must be + within the same MU instance. Cross instances are not allowed. The MU + instance can only be one of LSIO MU0~M4 for imx8qxp and imx8qm. Users + need to ensure that one is used that does not conflict with other + execution environments such as ATF. + oneOf: + - items: + - description: TX0 MU channel + - description: RX0 MU channel + - items: + - description: TX0 MU channel + - description: RX0 MU channel + - description: optional MU channel for general interrupt + - items: + - description: TX0 MU channel + - description: TX1 MU channel + - description: TX2 MU channel + - description: TX3 MU channel + - description: RX0 MU channel + - description: RX1 MU channel + - description: RX2 MU channel + - description: RX3 MU channel + - items: + - description: TX0 MU channel + - description: TX1 MU channel + - description: TX2 MU channel + - description: TX3 MU channel + - description: RX0 MU channel + - description: RX1 MU channel + - description: RX2 MU channel + - description: RX3 MU channel + - description: optional MU channel for general interrupt + + mbox-names: + oneOf: + - items: + - const: tx0 + - const: rx0 + - items: + - const: tx0 + - const: rx0 + - const: gip3 + - items: + - const: tx0 + - const: tx1 + - const: tx2 + - const: tx3 + - const: rx0 + - const: rx1 + - const: rx2 + - const: rx3 + - items: + - const: tx0 + - const: tx1 + - const: tx2 + - const: tx3 + - const: rx0 + - const: rx1 + - const: rx2 + - const: rx3 + - const: gip3 + + pinctrl: + description: + Pin controller provided by the SCU + $ref: /schemas/pinctrl/fsl,scu-pinctrl.yaml + + power-controller: + description: + Power domains controller node that provides the power domains + controlled by the SCU + $ref: /schemas/power/fsl,scu-pd.yaml + + rtc: + description: + RTC controller provided by the SCU + $ref: /schemas/rtc/fsl,scu-rtc.yaml + + thermal-sensor: + description: + Thermal sensor provided by the SCU + $ref: /schemas/thermal/fsl,scu-thermal.yaml + + watchdog: + description: + Watchdog controller provided by the SCU + $ref: /schemas/watchdog/fsl,scu-wdt.yaml + +required: + - compatible + - mbox-names + - mboxes + +additionalProperties: false + +examples: + - | + #include <dt-bindings/firmware/imx/rsrc.h> + #include <dt-bindings/input/input.h> + #include <dt-bindings/pinctrl/pads-imx8qxp.h> + + firmware { + system-controller { + compatible = "fsl,imx-scu"; + mbox-names = "tx0", "tx1", "tx2", "tx3", + "rx0", "rx1", "rx2", "rx3", + "gip3"; + mboxes = <&lsio_mu1 0 0 &lsio_mu1 0 1 &lsio_mu1 0 2 &lsio_mu1 0 3 + &lsio_mu1 1 0 &lsio_mu1 1 1 &lsio_mu1 1 2 &lsio_mu1 1 3 + &lsio_mu1 3 3>; + + clock-controller { + compatible = "fsl,imx8qxp-clk", "fsl,scu-clk"; + #clock-cells = <2>; + }; + + pinctrl { + compatible = "fsl,imx8qxp-iomuxc"; + + pinctrl_lpuart0: lpuart0grp { + fsl,pins = < + IMX8QXP_UART0_RX_ADMA_UART0_RX 0x06000020 + IMX8QXP_UART0_TX_ADMA_UART0_TX 0x06000020 + >; + }; + }; + + ocotp { + compatible = "fsl,imx8qxp-scu-ocotp"; + #address-cells = <1>; + #size-cells = <1>; + + fec_mac0: mac@2c4 { + reg = <0x2c4 6>; + }; + }; + + power-controller { + compatible = "fsl,imx8qxp-scu-pd", "fsl,scu-pd"; + #power-domain-cells = <1>; + }; + + rtc { + compatible = "fsl,imx8qxp-sc-rtc"; + }; + + keys { + compatible = "fsl,imx8qxp-sc-key", "fsl,imx-sc-key"; + linux,keycodes = <KEY_POWER>; + }; + + watchdog { + compatible = "fsl,imx8qxp-sc-wdt", "fsl,imx-sc-wdt"; + timeout-sec = <60>; + }; + + thermal-sensor { + compatible = "fsl,imx8qxp-sc-thermal", "fsl,imx-sc-thermal"; + #thermal-sensor-cells = <1>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/gpio/gpio-zynq.yaml b/Documentation/devicetree/bindings/gpio/gpio-zynq.yaml index 378da2649e66..29c27eadbac8 100644 --- a/Documentation/devicetree/bindings/gpio/gpio-zynq.yaml +++ b/Documentation/devicetree/bindings/gpio/gpio-zynq.yaml @@ -11,7 +11,11 @@ maintainers: properties: compatible: - const: xlnx,zynq-gpio-1.0 + enum: + - xlnx,zynq-gpio-1.0 + - xlnx,zynqmp-gpio-1.0 + - xlnx,versal-gpio-1.0 + - xlnx,pmc-gpio-1.0 reg: maxItems: 1 @@ -24,6 +28,11 @@ properties: gpio-controller: true + gpio-line-names: + description: strings describing the names of each gpio line + minItems: 58 + maxItems: 174 + interrupt-controller: true "#interrupt-cells": @@ -32,6 +41,54 @@ properties: clocks: maxItems: 1 + power-domains: + maxItems: 1 + +allOf: + - if: + properties: + compatible: + enum: + - xlnx,zynqmp-gpio-1.0 + then: + properties: + gpio-line-names: + minItems: 174 + maxItems: 174 + + - if: + properties: + compatible: + enum: + - xlnx,zynq-gpio-1.0 + then: + properties: + gpio-line-names: + minItems: 118 + maxItems: 118 + + - if: + properties: + compatible: + enum: + - xlnx,versal-gpio-1.0 + then: + properties: + gpio-line-names: + minItems: 58 + maxItems: 58 + + - if: + properties: + compatible: + enum: + - xlnx,pmc-gpio-1.0 + then: + properties: + gpio-line-names: + minItems: 116 + maxItems: 116 + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/arm/renesas,prr.yaml b/Documentation/devicetree/bindings/hwinfo/renesas,prr.yaml index 1f80767da38b..792f371cec03 100644 --- a/Documentation/devicetree/bindings/arm/renesas,prr.yaml +++ b/Documentation/devicetree/bindings/hwinfo/renesas,prr.yaml @@ -1,7 +1,7 @@ -# SPDX-License-Identifier: GPL-2.0 +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- -$id: http://devicetree.org/schemas/arm/renesas,prr.yaml# +$id: http://devicetree.org/schemas/hwinfo/renesas,prr.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Renesas Product Register diff --git a/Documentation/devicetree/bindings/i2c/marvell,mv64xxx-i2c.yaml b/Documentation/devicetree/bindings/i2c/marvell,mv64xxx-i2c.yaml index f771c09aabfc..0ec033e48830 100644 --- a/Documentation/devicetree/bindings/i2c/marvell,mv64xxx-i2c.yaml +++ b/Documentation/devicetree/bindings/i2c/marvell,mv64xxx-i2c.yaml @@ -21,10 +21,18 @@ properties: - enum: - allwinner,sun8i-a23-i2c - allwinner,sun8i-a83t-i2c + - allwinner,sun8i-v536-i2c - allwinner,sun50i-a64-i2c - - allwinner,sun50i-a100-i2c - allwinner,sun50i-h6-i2c + - const: allwinner,sun6i-a31-i2c + - description: Allwinner SoCs with offload support + items: + - enum: + - allwinner,sun20i-d1-i2c + - allwinner,sun50i-a100-i2c - allwinner,sun50i-h616-i2c + - allwinner,sun50i-r329-i2c + - const: allwinner,sun8i-v536-i2c - const: allwinner,sun6i-a31-i2c - const: marvell,mv64xxx-i2c - const: marvell,mv78230-i2c diff --git a/Documentation/devicetree/bindings/input/fsl,scu-key.yaml b/Documentation/devicetree/bindings/input/fsl,scu-key.yaml new file mode 100644 index 000000000000..e6266d188266 --- /dev/null +++ b/Documentation/devicetree/bindings/input/fsl,scu-key.yaml @@ -0,0 +1,40 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/input/fsl,scu-key.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: i.MX SCU Client Device Node - SCU key bindings based on SCU Message Protocol + +maintainers: + - Dong Aisheng <aisheng.dong@nxp.com> + +description: i.MX SCU Client Device Node + Client nodes are maintained as children of the relevant IMX-SCU device node. + +allOf: + - $ref: input.yaml# + +properties: + compatible: + items: + - const: fsl,imx8qxp-sc-key + - const: fsl,imx-sc-key + + linux,keycodes: + maxItems: 1 + +required: + - compatible + - linux,keycodes + +additionalProperties: false + +examples: + - | + #include <dt-bindings/input/input.h> + + keys { + compatible = "fsl,imx8qxp-sc-key", "fsl,imx-sc-key"; + linux,keycodes = <KEY_POWER>; + }; diff --git a/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml b/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml index 6a4831fd3616..55fc620c72cd 100644 --- a/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml +++ b/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml @@ -22,6 +22,7 @@ properties: - enum: - allwinner,sun20i-d1-emac - allwinner,sun50i-h6-emac + - allwinner,sun50i-h616-emac0 - const: allwinner,sun50i-a64-emac reg: diff --git a/Documentation/devicetree/bindings/net/pcs/renesas,rzn1-miic.yaml b/Documentation/devicetree/bindings/net/pcs/renesas,rzn1-miic.yaml new file mode 100644 index 000000000000..2d33bbab7163 --- /dev/null +++ b/Documentation/devicetree/bindings/net/pcs/renesas,rzn1-miic.yaml @@ -0,0 +1,171 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/pcs/renesas,rzn1-miic.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/N1 MII converter + +maintainers: + - Clément Léger <clement.leger@bootlin.com> + +description: | + This MII converter is present on the Renesas RZ/N1 SoC family. It is + responsible to do MII passthrough or convert it to RMII/RGMII. + +properties: + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + compatible: + items: + - enum: + - renesas,r9a06g032-miic + - const: renesas,rzn1-miic + + reg: + maxItems: 1 + + clocks: + items: + - description: MII reference clock + - description: RGMII reference clock + - description: RMII reference clock + - description: AHB clock used for the MII converter register interface + + clock-names: + items: + - const: mii_ref + - const: rgmii_ref + - const: rmii_ref + - const: hclk + + renesas,miic-switch-portin: + description: MII Switch PORTIN configuration. This value should use one of + the values defined in dt-bindings/net/pcs-rzn1-miic.h. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [1, 2] + + power-domains: + maxItems: 1 + +patternProperties: + "^mii-conv@[0-5]$": + type: object + description: MII converter port + + properties: + reg: + description: MII Converter port number. + enum: [1, 2, 3, 4, 5] + + renesas,miic-input: + description: Converter input port configuration. This value should use + one of the values defined in dt-bindings/net/pcs-rzn1-miic.h. + $ref: /schemas/types.yaml#/definitions/uint32 + + required: + - reg + - renesas,miic-input + + additionalProperties: false + + allOf: + - if: + properties: + reg: + const: 1 + then: + properties: + renesas,miic-input: + const: 0 + - if: + properties: + reg: + const: 2 + then: + properties: + renesas,miic-input: + enum: [1, 11] + - if: + properties: + reg: + const: 3 + then: + properties: + renesas,miic-input: + enum: [7, 10] + - if: + properties: + reg: + const: 4 + then: + properties: + renesas,miic-input: + enum: [4, 6, 9, 13] + - if: + properties: + reg: + const: 5 + then: + properties: + renesas,miic-input: + enum: [3, 5, 8, 12] + +required: + - '#address-cells' + - '#size-cells' + - compatible + - reg + - clocks + - clock-names + - power-domains + +additionalProperties: false + +examples: + - | + #include <dt-bindings/net/pcs-rzn1-miic.h> + #include <dt-bindings/clock/r9a06g032-sysctrl.h> + + eth-miic@44030000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,r9a06g032-miic", "renesas,rzn1-miic"; + reg = <0x44030000 0x10000>; + clocks = <&sysctrl R9A06G032_CLK_MII_REF>, + <&sysctrl R9A06G032_CLK_RGMII_REF>, + <&sysctrl R9A06G032_CLK_RMII_REF>, + <&sysctrl R9A06G032_HCLK_SWITCH_RG>; + clock-names = "mii_ref", "rgmii_ref", "rmii_ref", "hclk"; + renesas,miic-switch-portin = <MIIC_GMAC2_PORT>; + power-domains = <&sysctrl>; + + mii_conv1: mii-conv@1 { + renesas,miic-input = <MIIC_GMAC1_PORT>; + reg = <1>; + }; + + mii_conv2: mii-conv@2 { + renesas,miic-input = <MIIC_SWITCH_PORTD>; + reg = <2>; + }; + + mii_conv3: mii-conv@3 { + renesas,miic-input = <MIIC_SWITCH_PORTC>; + reg = <3>; + }; + + mii_conv4: mii-conv@4 { + renesas,miic-input = <MIIC_SWITCH_PORTB>; + reg = <4>; + }; + + mii_conv5: mii-conv@5 { + renesas,miic-input = <MIIC_SWITCH_PORTA>; + reg = <5>; + }; + }; diff --git a/Documentation/devicetree/bindings/nvmem/fsl,scu-ocotp.yaml b/Documentation/devicetree/bindings/nvmem/fsl,scu-ocotp.yaml new file mode 100644 index 000000000000..682688299b26 --- /dev/null +++ b/Documentation/devicetree/bindings/nvmem/fsl,scu-ocotp.yaml @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/nvmem/fsl,scu-ocotp.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: i.MX SCU Client Device Node - OCOTP bindings based on SCU Message Protocol + +maintainers: + - Dong Aisheng <aisheng.dong@nxp.com> + +description: i.MX SCU Client Device Node + Client nodes are maintained as children of the relevant IMX-SCU device node. + +allOf: + - $ref: nvmem.yaml# + +properties: + compatible: + enum: + - fsl,imx8qm-scu-ocotp + - fsl,imx8qxp-scu-ocotp + +patternProperties: + '^mac@[0-9a-f]*$': + type: object + description: + MAC address. + + properties: + reg: + description: + Byte offset within OCOTP where the MAC address is stored + maxItems: 1 + + required: + - reg + + additionalProperties: false + +required: + - compatible + +unevaluatedProperties: false + +examples: + - | + ocotp { + compatible = "fsl,imx8qxp-scu-ocotp"; + #address-cells = <1>; + #size-cells = <1>; + + fec_mac0: mac@2c4 { + reg = <0x2c4 6>; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml index bfce850c2035..0681b9a3965f 100644 --- a/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml @@ -127,20 +127,17 @@ patternProperties: additionalProperties: false - "^vcc-p[a-hlm]-supply$": + "^vcc-p[a-ilm]-supply$": description: Power supplies for pin banks. required: - "#gpio-cells" - - "#interrupt-cells" - compatible - reg - - interrupts - clocks - clock-names - gpio-controller - - interrupt-controller allOf: # FIXME: We should have the pin bank supplies here, but not a lot of @@ -149,6 +146,19 @@ allOf: - $ref: "pinctrl.yaml#" - if: + not: + properties: + compatible: + enum: + - allwinner,sun50i-h616-r-pinctrl + + then: + required: + - "#interrupt-cells" + - interrupts + - interrupt-controller + + - if: properties: compatible: enum: diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,scu-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/fsl,scu-pinctrl.yaml new file mode 100644 index 000000000000..45ea565ce238 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/fsl,scu-pinctrl.yaml @@ -0,0 +1,74 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/fsl,scu-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: i.MX SCU Client Device Node - Pinctrl bindings based on SCU Message Protocol + +maintainers: + - Dong Aisheng <aisheng.dong@nxp.com> + +description: i.MX SCU Client Device Node + Client nodes are maintained as children of the relevant IMX-SCU device node. + This binding uses the i.MX common pinctrl binding. + (Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt) + +allOf: + - $ref: pinctrl.yaml# + +properties: + compatible: + enum: + - fsl,imx8qm-iomuxc + - fsl,imx8qxp-iomuxc + - fsl,imx8dxl-iomuxc + +patternProperties: + 'grp$': + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + + properties: + fsl,pins: + description: + each entry consists of 3 integers and represents the pin ID, the mux value + and pad setting for the pin. The first 2 integers - pin_id and mux_val - are + specified using a PIN_FUNC_ID macro, which can be found in + <include/dt-bindings/pinctrl/pads-imx8qxp.h>. The last integer is + the pad setting value like pull-up on this pin. Please refer to the + appropriate i.MX8 Reference Manual for detailed pad CONFIG settings. + $ref: /schemas/types.yaml#/definitions/uint32-matrix + items: + items: + - description: | + "pin_id" indicates the pin ID + - description: | + "mux_val" indicates the mux value to be applied. + - description: | + "pad_setting" indicates the pad configuration value to be applied. + + required: + - fsl,pins + + additionalProperties: false + +required: + - compatible + +additionalProperties: false + +examples: + - | + pinctrl { + compatible = "fsl,imx8qxp-iomuxc"; + + pinctrl_lpuart0: lpuart0grp { + fsl,pins = < + 111 0 0x06000020 + 112 0 0x06000020 + >; + }; + }; diff --git a/Documentation/devicetree/bindings/power/fsl,scu-pd.yaml b/Documentation/devicetree/bindings/power/fsl,scu-pd.yaml new file mode 100644 index 000000000000..1f72b18ca0fc --- /dev/null +++ b/Documentation/devicetree/bindings/power/fsl,scu-pd.yaml @@ -0,0 +1,41 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/power/fsl,scu-pd.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: i.MX SCU Client Device Node - Power domain bindings based on SCU Message Protocol + +maintainers: + - Dong Aisheng <aisheng.dong@nxp.com> + +description: i.MX SCU Client Device Node + Client nodes are maintained as children of the relevant IMX-SCU device node. + Power domain bindings based on SCU Message Protocol + +allOf: + - $ref: power-domain.yaml# + +properties: + compatible: + items: + - enum: + - fsl,imx8qm-scu-pd + - fsl,imx8qxp-scu-pd + - const: fsl,scu-pd + + '#power-domain-cells': + const: 1 + +required: + - compatible + - '#power-domain-cells' + +additionalProperties: false + +examples: + - | + power-controller { + compatible = "fsl,imx8qxp-scu-pd", "fsl,scu-pd"; + #power-domain-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/rtc/fsl,scu-rtc.yaml b/Documentation/devicetree/bindings/rtc/fsl,scu-rtc.yaml new file mode 100644 index 000000000000..8c102b70d735 --- /dev/null +++ b/Documentation/devicetree/bindings/rtc/fsl,scu-rtc.yaml @@ -0,0 +1,31 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/rtc/fsl,scu-rtc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: i.MX SCU Client Device Node - RTC bindings based on SCU Message Protocol + +maintainers: + - Dong Aisheng <aisheng.dong@nxp.com> + +description: i.MX SCU Client Device Node + Client nodes are maintained as children of the relevant IMX-SCU device node. + +allOf: + - $ref: rtc.yaml# + +properties: + compatible: + const: fsl,imx8qxp-sc-rtc + +required: + - compatible + +additionalProperties: false + +examples: + - | + rtc { + compatible = "fsl,imx8qxp-sc-rtc"; + }; diff --git a/Documentation/devicetree/bindings/soc/bcm/brcm,bcm2835-pm.txt b/Documentation/devicetree/bindings/soc/bcm/brcm,bcm2835-pm.txt deleted file mode 100644 index 72ff033565e5..000000000000 --- a/Documentation/devicetree/bindings/soc/bcm/brcm,bcm2835-pm.txt +++ /dev/null @@ -1,46 +0,0 @@ -BCM2835 PM (Power domains, watchdog) - -The PM block controls power domains and some reset lines, and includes -a watchdog timer. This binding supersedes the brcm,bcm2835-pm-wdt -binding which covered some of PM's register range and functionality. - -Required properties: - -- compatible: Should be "brcm,bcm2835-pm" -- reg: Specifies base physical address and size of the two - register ranges ("PM" and "ASYNC_BRIDGE" in that - order) -- clocks: a) v3d: The V3D clock from CPRMAN - b) peri_image: The PERI_IMAGE clock from CPRMAN - c) h264: The H264 clock from CPRMAN - d) isp: The ISP clock from CPRMAN -- #reset-cells: Should be 1. This property follows the reset controller - bindings[1]. -- #power-domain-cells: Should be 1. This property follows the power domain - bindings[2]. - -Optional properties: - -- timeout-sec: Contains the watchdog timeout in seconds -- system-power-controller: Whether the watchdog is controlling the - system power. This node follows the power controller bindings[3]. - -[1] Documentation/devicetree/bindings/reset/reset.txt -[2] Documentation/devicetree/bindings/power/power-domain.yaml -[3] Documentation/devicetree/bindings/power/power-controller.txt - -Example: - -pm { - compatible = "brcm,bcm2835-pm", "brcm,bcm2835-pm-wdt"; - #power-domain-cells = <1>; - #reset-cells = <1>; - reg = <0x7e100000 0x114>, - <0x7e00a000 0x24>; - clocks = <&clocks BCM2835_CLOCK_V3D>, - <&clocks BCM2835_CLOCK_PERI_IMAGE>, - <&clocks BCM2835_CLOCK_H264>, - <&clocks BCM2835_CLOCK_ISP>; - clock-names = "v3d", "peri_image", "h264", "isp"; - system-power-controller; -}; diff --git a/Documentation/devicetree/bindings/soc/bcm/brcm,bcm2835-pm.yaml b/Documentation/devicetree/bindings/soc/bcm/brcm,bcm2835-pm.yaml new file mode 100644 index 000000000000..e28ef198a801 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/bcm/brcm,bcm2835-pm.yaml @@ -0,0 +1,86 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/bcm/brcm,bcm2835-pm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: BCM2835 PM (Power domains, watchdog) + +description: | + The PM block controls power domains and some reset lines, and includes a + watchdog timer. + +maintainers: + - Nicolas Saenz Julienne <nsaenz@kernel.org> + +allOf: + - $ref: /schemas/watchdog/watchdog.yaml# + +properties: + compatible: + items: + - enum: + - brcm,bcm2835-pm + - brcm,bcm2711-pm + - const: brcm,bcm2835-pm-wdt + + reg: + minItems: 2 + maxItems: 3 + + reg-names: + minItems: 2 + items: + - const: pm + - const: asb + - const: rpivid_asb + + "#power-domain-cells": + const: 1 + + "#reset-cells": + const: 1 + + clocks: + minItems: 4 + maxItems: 4 + + clock-names: + items: + - const: v3d + - const: peri_image + - const: h264 + - const: isp + + system-power-controller: + type: boolean + + timeout-sec: true + +required: + - compatible + - reg + - "#power-domain-cells" + - "#reset-cells" + - clocks + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/bcm2835.h> + + watchdog@7e100000 { + compatible = "brcm,bcm2835-pm", "brcm,bcm2835-pm-wdt"; + #power-domain-cells = <1>; + #reset-cells = <1>; + reg = <0x7e100000 0x114>, + <0x7e00a000 0x24>; + reg-names = "pm", "asb"; + clocks = <&clocks BCM2835_CLOCK_V3D>, + <&clocks BCM2835_CLOCK_PERI_IMAGE>, + <&clocks BCM2835_CLOCK_H264>, + <&clocks BCM2835_CLOCK_ISP>; + clock-names = "v3d", "peri_image", "h264", "isp"; + system-power-controller; + }; diff --git a/Documentation/devicetree/bindings/soc/microchip/atmel,at91rm9200-tcb.yaml b/Documentation/devicetree/bindings/soc/microchip/atmel,at91rm9200-tcb.yaml index 597d67fba92f..33748a061898 100644 --- a/Documentation/devicetree/bindings/soc/microchip/atmel,at91rm9200-tcb.yaml +++ b/Documentation/devicetree/bindings/soc/microchip/atmel,at91rm9200-tcb.yaml @@ -1,8 +1,8 @@ # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2 --- -$id: "http://devicetree.org/schemas/soc/microchip/atmel,at91rm9200-tcb.yaml#" -$schema: "http://devicetree.org/meta-schemas/core.yaml#" +$id: http://devicetree.org/schemas/soc/microchip/atmel,at91rm9200-tcb.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# title: Atmel Timer Counter Block @@ -75,7 +75,7 @@ patternProperties: "^pwm@[0-2]$": description: The timer block channels that are used as PWMs. - $ref: ../../pwm/pwm.yaml# + $ref: /schemas/pwm/pwm.yaml# type: object properties: compatible: diff --git a/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml b/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml index b0dae51e1d42..04ffee3a7c59 100644 --- a/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml +++ b/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml @@ -1,8 +1,8 @@ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- -$id: "http://devicetree.org/schemas/soc/microchip/microchip,mpfs-sys-controller.yaml#" -$schema: "http://devicetree.org/meta-schemas/core.yaml#" +$id: http://devicetree.org/schemas/soc/microchip/microchip,mpfs-sys-controller.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# title: Microchip PolarFire SoC (MPFS) MSS (microprocessor subsystem) system controller diff --git a/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml b/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml index c30a6437030d..13bb8dfcefe6 100644 --- a/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml +++ b/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml @@ -49,9 +49,6 @@ properties: reg: maxItems: 1 - assigned-clock-parents: true - assigned-clocks: true - '#clock-cells': const: 1 @@ -77,14 +74,20 @@ properties: Must be identical to the that of the parent interrupt controller. const: 3 + reboot-mode: + $ref: /schemas/power/reset/syscon-reboot-mode.yaml + type: object + description: + Reboot mode to alter bootloader behavior for the next boot + syscon-poweroff: - $ref: "../../power/reset/syscon-poweroff.yaml#" + $ref: /schemas/power/reset/syscon-poweroff.yaml# type: object description: Node for power off method syscon-reboot: - $ref: "../../power/reset/syscon-reboot.yaml#" + $ref: /schemas/power/reset/syscon-reboot.yaml# type: object description: Node for reboot method diff --git a/Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml b/Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml index fde886a8cf43..60b49562ff69 100644 --- a/Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml +++ b/Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml @@ -22,8 +22,12 @@ properties: pattern: "^usi@[0-9a-f]+$" compatible: - enum: - - samsung,exynos850-usi # for USIv2 (Exynos850, ExynosAutoV9) + oneOf: + - items: + - const: samsung,exynosautov9-usi + - const: samsung,exynos850-usi + - enum: + - samsung,exynos850-usi reg: true diff --git a/Documentation/devicetree/bindings/thermal/fsl,scu-thermal.yaml b/Documentation/devicetree/bindings/thermal/fsl,scu-thermal.yaml new file mode 100644 index 000000000000..f9e4b3c8d0ee --- /dev/null +++ b/Documentation/devicetree/bindings/thermal/fsl,scu-thermal.yaml @@ -0,0 +1,38 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/thermal/fsl,scu-thermal.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: i.MX SCU Client Device Node - Thermal bindings based on SCU Message Protocol + +maintainers: + - Dong Aisheng <aisheng.dong@nxp.com> + +description: i.MX SCU Client Device Node + Client nodes are maintained as children of the relevant IMX-SCU device node. + +allOf: + - $ref: thermal-sensor.yaml# + +properties: + compatible: + items: + - const: fsl,imx8qxp-sc-thermal + - const: fsl,imx-sc-thermal + + '#thermal-sensor-cells': + const: 1 + +required: + - compatible + - '#thermal-sensor-cells' + +additionalProperties: false + +examples: + - | + thermal-sensor { + compatible = "fsl,imx8qxp-sc-thermal", "fsl,imx-sc-thermal"; + #thermal-sensor-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/timer/nvidia,tegra186-timer.yaml b/Documentation/devicetree/bindings/timer/nvidia,tegra186-timer.yaml new file mode 100644 index 000000000000..db8b5595540f --- /dev/null +++ b/Documentation/devicetree/bindings/timer/nvidia,tegra186-timer.yaml @@ -0,0 +1,109 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/timer/nvidia,tegra186-timer.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: NVIDIA Tegra186 timer + +maintainers: + - Thierry Reding <treding@nvidia.com> + +description: > + The Tegra timer provides 29-bit timer counters and a 32-bit timestamp + counter. Each NV timer selects its timing reference signal from the 1 MHz + reference generated by USEC, TSC or either clk_m or OSC. Each TMR can be + programmed to generate one-shot, periodic, or watchdog interrupts. + + +properties: + compatible: + oneOf: + - const: nvidia,tegra186-timer + description: > + The Tegra186 timer provides ten 29-bit timer counters. + - const: nvidia,tegra234-timer + description: > + The Tegra234 timer provides sixteen 29-bit timer counters. + + reg: + maxItems: 1 + + interrupts: true + +allOf: + - if: + properties: + compatible: + contains: + const: nvidia,tegra186-timer + then: + properties: + interrupts: + maxItems: 10 + description: > + One per each timer channels 0 through 9. + + - if: + properties: + compatible: + contains: + const: nvidia,tegra234-timer + then: + properties: + interrupts: + maxItems: 16 + description: > + One per each timer channels 0 through 15. + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + + timer@3010000 { + compatible = "nvidia,tegra186-timer"; + reg = <0x03010000 0x000e0000>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; + }; + + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + + timer@2080000 { + compatible = "nvidia,tegra234-timer"; + reg = <0x02080000 0x00121000>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; + }; diff --git a/Documentation/devicetree/bindings/usb/allwinner,sun4i-a10-musb.yaml b/Documentation/devicetree/bindings/usb/allwinner,sun4i-a10-musb.yaml index 933fa356d2ce..e5dbf4169bc9 100644 --- a/Documentation/devicetree/bindings/usb/allwinner,sun4i-a10-musb.yaml +++ b/Documentation/devicetree/bindings/usb/allwinner,sun4i-a10-musb.yaml @@ -20,6 +20,7 @@ properties: - items: - enum: - allwinner,sun8i-a83t-musb + - allwinner,sun20i-d1-musb - allwinner,sun50i-h6-musb - const: allwinner,sun8i-a33-musb - items: diff --git a/Documentation/devicetree/bindings/usb/atmel-usb.txt b/Documentation/devicetree/bindings/usb/atmel-usb.txt index f512f0290728..12183ef47ee4 100644 --- a/Documentation/devicetree/bindings/usb/atmel-usb.txt +++ b/Documentation/devicetree/bindings/usb/atmel-usb.txt @@ -87,6 +87,9 @@ Required properties: "atmel,at91sam9g45-udc" "atmel,sama5d3-udc" "microchip,sam9x60-udc" + "microchip,lan9662-udc" + For "microchip,lan9662-udc" the fallback "atmel,sama5d3-udc" + is required. - reg: Address and length of the register set for the device - interrupts: Should contain usba interrupt - clocks: Should reference the peripheral and host clocks diff --git a/Documentation/devicetree/bindings/usb/generic-ehci.yaml b/Documentation/devicetree/bindings/usb/generic-ehci.yaml index 1e84e1b7ab27..25a6c14618e1 100644 --- a/Documentation/devicetree/bindings/usb/generic-ehci.yaml +++ b/Documentation/devicetree/bindings/usb/generic-ehci.yaml @@ -38,6 +38,7 @@ properties: - allwinner,sun8i-h3-ehci - allwinner,sun8i-r40-ehci - allwinner,sun9i-a80-ehci + - allwinner,sun20i-d1-ehci - aspeed,ast2400-ehci - aspeed,ast2500-ehci - aspeed,ast2600-ehci diff --git a/Documentation/devicetree/bindings/usb/generic-ohci.yaml b/Documentation/devicetree/bindings/usb/generic-ohci.yaml index bb6bbd5f129d..180361b79f52 100644 --- a/Documentation/devicetree/bindings/usb/generic-ohci.yaml +++ b/Documentation/devicetree/bindings/usb/generic-ohci.yaml @@ -28,6 +28,7 @@ properties: - allwinner,sun8i-h3-ohci - allwinner,sun8i-r40-ohci - allwinner,sun9i-a80-ohci + - allwinner,sun20i-d1-ohci - brcm,bcm3384-ohci - brcm,bcm63268-ohci - brcm,bcm6328-ohci diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 0496773a3c4d..ff0ac853cb82 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -510,6 +510,8 @@ patternProperties: description: Haoyu Microelectronic Co. Ltd. "^hardkernel,.*": description: Hardkernel Co., Ltd + "^hechuang,.*": + description: Shenzhen Hechuang Intelligent Co. "^hideep,.*": description: HiDeep Inc. "^himax,.*": @@ -1101,6 +1103,8 @@ patternProperties: description: SGX Sensortech "^sharp,.*": description: Sharp Corporation + "^shift,.*": + description: SHIFT GmbH "^shimafuji,.*": description: Shimafuji Electric, Inc. "^shiratech,.*": diff --git a/Documentation/devicetree/bindings/watchdog/fsl,scu-wdt.yaml b/Documentation/devicetree/bindings/watchdog/fsl,scu-wdt.yaml new file mode 100644 index 000000000000..f84c45d687d7 --- /dev/null +++ b/Documentation/devicetree/bindings/watchdog/fsl,scu-wdt.yaml @@ -0,0 +1,34 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/watchdog/fsl,scu-wdt.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: i.MX SCU Client Device Node - Watchdog bindings based on SCU Message Protocol + +maintainers: + - Dong Aisheng <aisheng.dong@nxp.com> + +description: i.MX SCU Client Device Node + Client nodes are maintained as children of the relevant IMX-SCU device node. + +allOf: + - $ref: watchdog.yaml# + +properties: + compatible: + items: + - const: fsl,imx8qxp-sc-wdt + - const: fsl,imx-sc-wdt + +required: + - compatible + +unevaluatedProperties: false + +examples: + - | + watchdog { + compatible = "fsl,imx8qxp-sc-wdt", "fsl,imx-sc-wdt"; + timeout-sec = <60>; + }; diff --git a/MAINTAINERS b/MAINTAINERS index da9777c407d0..1c8ac3444c88 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1899,6 +1899,7 @@ L: linux-aspeed@lists.ozlabs.org (moderated for non-subscribers) S: Supported Q: https://patchwork.ozlabs.org/project/linux-aspeed/list/ T: git git://git.kernel.org/pub/scm/linux/kernel/git/joel/aspeed.git +F: Documentation/devicetree/bindings/arm/aspeed/ F: arch/arm/boot/dts/aspeed-* F: arch/arm/mach-aspeed/ N: aspeed @@ -2621,6 +2622,8 @@ Q: http://patchwork.kernel.org/project/linux-renesas-soc/list/ C: irc://irc.libera.chat/renesas-soc T: git git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel.git next F: Documentation/devicetree/bindings/arm/renesas.yaml +F: Documentation/devicetree/bindings/hwinfo/renesas,prr.yaml +F: Documentation/devicetree/bindings/soc/renesas/ F: arch/arm64/boot/dts/renesas/ F: drivers/soc/renesas/ F: include/linux/soc/renesas/ @@ -2739,6 +2742,7 @@ Q: http://patchwork.kernel.org/project/linux-renesas-soc/list/ C: irc://irc.libera.chat/renesas-soc T: git git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel.git next F: Documentation/devicetree/bindings/arm/renesas.yaml +F: Documentation/devicetree/bindings/soc/renesas/ F: arch/arm/boot/dts/emev2* F: arch/arm/boot/dts/gr-peach* F: arch/arm/boot/dts/iwg20d-q7* diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 5112f493f494..b327059c83da 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -135,6 +135,7 @@ dtb-$(CONFIG_ARCH_BCM_5301X) += \ bcm47094-luxul-xwr-3150-v1.dtb \ bcm47094-netgear-r8500.dtb \ bcm47094-phicomm-k3.dtb \ + bcm53015-meraki-mr26.dtb \ bcm53016-meraki-mr32.dtb \ bcm94708.dtb \ bcm94709.dtb \ @@ -146,8 +147,6 @@ dtb-$(CONFIG_ARCH_BCM_53573) += \ bcm47189-luxul-xap-810.dtb \ bcm47189-tenda-ac9.dtb \ bcm947189acdbmr.dtb -dtb-$(CONFIG_ARCH_BCM_63XX) += \ - bcm963138dvt.dtb dtb-$(CONFIG_ARCH_BCM_CYGNUS) += \ bcm911360_entphn.dtb \ bcm911360k.dtb \ @@ -182,7 +181,15 @@ dtb-$(CONFIG_ARCH_BERLIN) += \ dtb-$(CONFIG_ARCH_BRCMSTB) += \ bcm7445-bcm97445svmb.dtb dtb-$(CONFIG_ARCH_BCMBCA) += \ - bcm947622.dtb + bcm947622.dtb \ + bcm963138.dtb \ + bcm963138dvt.dtb \ + bcm963148.dtb \ + bcm963178.dtb \ + bcm96756.dtb \ + bcm96846.dtb \ + bcm96855.dtb \ + bcm96878.dtb dtb-$(CONFIG_ARCH_CLPS711X) += \ ep7211-edb7211.dtb dtb-$(CONFIG_ARCH_DAVINCI) += \ @@ -550,6 +557,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6q-apalis-eval.dtb \ imx6q-apalis-ixora.dtb \ imx6q-apalis-ixora-v1.1.dtb \ + imx6q-apalis-ixora-v1.2.dtb \ imx6q-apf6dev.dtb \ imx6q-arm2.dtb \ imx6q-b450v3.dtb \ @@ -741,8 +749,12 @@ dtb-$(CONFIG_SOC_IMX7D) += \ imx7d-cl-som-imx7.dtb \ imx7d-colibri-aster.dtb \ imx7d-colibri-emmc-aster.dtb \ + imx7d-colibri-emmc-iris.dtb \ + imx7d-colibri-emmc-iris-v2.dtb \ imx7d-colibri-emmc-eval-v3.dtb \ imx7d-colibri-eval-v3.dtb \ + imx7d-colibri-iris.dtb \ + imx7d-colibri-iris-v2.dtb \ imx7d-flex-concentrator.dtb \ imx7d-flex-concentrator-mfg.dtb \ imx7d-mba7.dtb \ @@ -762,6 +774,8 @@ dtb-$(CONFIG_SOC_IMX7D) += \ imx7d-zii-rpu2.dtb \ imx7s-colibri-aster.dtb \ imx7s-colibri-eval-v3.dtb \ + imx7s-colibri-iris.dtb \ + imx7s-colibri-iris-v2.dtb \ imx7s-mba7.dtb \ imx7s-warp.dtb dtb-$(CONFIG_SOC_IMX7ULP) += \ @@ -770,9 +784,10 @@ dtb-$(CONFIG_SOC_IMX7ULP) += \ dtb-$(CONFIG_SOC_IMXRT) += \ imxrt1050-evk.dtb dtb-$(CONFIG_SOC_LAN966) += \ - lan966x-pcb8291.dtb \ lan966x-kontron-kswitch-d10-mmt-6g-2gs.dtb \ - lan966x-kontron-kswitch-d10-mmt-8g.dtb + lan966x-kontron-kswitch-d10-mmt-8g.dtb \ + lan966x-pcb8291.dtb \ + lan966x-pcb8309.dtb dtb-$(CONFIG_SOC_LS1021A) += \ ls1021a-iot.dtb \ ls1021a-moxa-uc-8410a.dtb \ @@ -1148,7 +1163,7 @@ dtb-$(CONFIG_ARCH_S5PV210) += \ s5pv210-torbreck.dtb dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += \ socfpga_arria5_socdk.dtb \ - socfpga_arria10_mercury_aa1.dtb \ + socfpga_arria10_chameleonv3.dtb \ socfpga_arria10_socdk_nand.dtb \ socfpga_arria10_socdk_qspi.dtb \ socfpga_arria10_socdk_sdmmc.dtb \ @@ -1192,6 +1207,7 @@ dtb-$(CONFIG_ARCH_STM32) += \ stm32mp151a-prtt1c.dtb \ stm32mp151a-prtt1s.dtb \ stm32mp153c-dhcom-drc02.dtb \ + stm32mp153c-dhcor-drc-compact.dtb \ stm32mp157a-avenger96.dtb \ stm32mp157a-dhcor-avenger96.dtb \ stm32mp157a-dk1.dtb \ @@ -1558,7 +1574,6 @@ dtb-$(CONFIG_ARCH_ASPEED) += \ aspeed-ast2600-evb.dtb \ aspeed-bmc-amd-ethanolx.dtb \ aspeed-bmc-ampere-mtjade.dtb \ - aspeed-bmc-arm-centriq2400-rep.dtb \ aspeed-bmc-arm-stardragon4800-rep2.dtb \ aspeed-bmc-asrock-e3c246d4i.dtb \ aspeed-bmc-asrock-romed8hm3.dtb \ diff --git a/arch/arm/boot/dts/alpine.dtsi b/arch/arm/boot/dts/alpine.dtsi index 3b0675a1c460..4be9887033f9 100644 --- a/arch/arm/boot/dts/alpine.dtsi +++ b/arch/arm/boot/dts/alpine.dtsi @@ -154,7 +154,7 @@ reg = <0x0 0xfbc00000 0x0 0x100000>; interrupt-map-mask = <0xf800 0 0 7>; /* Add legacy interrupts for SATA devices only */ - interrupt-map = <0x4000 0 0 1 &gic 0 43 4>, + interrupt-map = <0x4000 0 0 1 &gic 0 43 4>, <0x4800 0 0 1 &gic 0 44 4>; /* 32 bit non prefetchable memory space */ diff --git a/arch/arm/boot/dts/am335x-boneblack-wireless.dts b/arch/arm/boot/dts/am335x-boneblack-wireless.dts index c72b09ab8da0..207d2b63e0eb 100644 --- a/arch/arm/boot/dts/am335x-boneblack-wireless.dts +++ b/arch/arm/boot/dts/am335x-boneblack-wireless.dts @@ -19,7 +19,7 @@ regulator-name = "wlan-en-regulator"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; - startup-delay-us= <70000>; + startup-delay-us = <70000>; /* WL_EN */ gpio = <&gpio3 9 0>; diff --git a/arch/arm/boot/dts/am335x-boneblack.dts b/arch/arm/boot/dts/am335x-boneblack.dts index 9312197316f0..b956e2f60fe0 100644 --- a/arch/arm/boot/dts/am335x-boneblack.dts +++ b/arch/arm/boot/dts/am335x-boneblack.dts @@ -168,3 +168,7 @@ "NC", "NC"; }; + +&baseboard_eeprom { + vcc-supply = <&ldo4_reg>; +}; diff --git a/arch/arm/boot/dts/am335x-boneblue.dts b/arch/arm/boot/dts/am335x-boneblue.dts index 147c00de3795..34579e98636e 100644 --- a/arch/arm/boot/dts/am335x-boneblue.dts +++ b/arch/arm/boot/dts/am335x-boneblue.dts @@ -106,7 +106,7 @@ regulator-name = "wlan-en-regulator"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; - startup-delay-us= <70000>; + startup-delay-us = <70000>; /* WL_EN */ gpio = <&gpio3 9 0>; diff --git a/arch/arm/boot/dts/am335x-bonegreen-wireless.dts b/arch/arm/boot/dts/am335x-bonegreen-wireless.dts index 215f279e476b..d388cffa1a4d 100644 --- a/arch/arm/boot/dts/am335x-bonegreen-wireless.dts +++ b/arch/arm/boot/dts/am335x-bonegreen-wireless.dts @@ -18,7 +18,7 @@ regulator-name = "wlan-en-regulator"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; - startup-delay-us= <70000>; + startup-delay-us = <70000>; /* WL_EN */ gpio = <&gpio0 26 0>; diff --git a/arch/arm/boot/dts/am335x-cm-t335.dts b/arch/arm/boot/dts/am335x-cm-t335.dts index d9f003d886bf..993b13420699 100644 --- a/arch/arm/boot/dts/am335x-cm-t335.dts +++ b/arch/arm/boot/dts/am335x-cm-t335.dts @@ -325,7 +325,7 @@ status = "okay"; tlv320aic23: codec@1a { compatible = "ti,tlv320aic23"; reg = <0x1a>; - #sound-dai-cells= <0>; + #sound-dai-cells = <0>; status = "okay"; }; }; @@ -491,7 +491,7 @@ status = "okay"; tx-num-evt = <1>; rx-num-evt = <1>; - #sound-dai-cells= <0>; + #sound-dai-cells = <0>; status = "okay"; }; diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts index b9745a2f0e4d..25c6ac9913d2 100644 --- a/arch/arm/boot/dts/am335x-evm.dts +++ b/arch/arm/boot/dts/am335x-evm.dts @@ -92,20 +92,18 @@ 0x0201006c>; /* DOWN */ }; - gpio_keys: volume_keys0 { + gpio_keys: volume-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; autorepeat; - switch9 { + switch-9 { label = "volume-up"; linux,code = <115>; gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; wakeup-source; }; - switch10 { + switch-10 { label = "volume-down"; linux,code = <114>; gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/am335x-guardian.dts b/arch/arm/boot/dts/am335x-guardian.dts index 1a7e187b1953..f6356266564c 100644 --- a/arch/arm/boot/dts/am335x-guardian.dts +++ b/arch/arm/boot/dts/am335x-guardian.dts @@ -33,8 +33,6 @@ pinctrl-names = "default"; pinctrl-0 = <&guardian_button_pins>; compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; select-button { label = "guardian-select-button"; diff --git a/arch/arm/boot/dts/am335x-moxa-uc-2100-common.dtsi b/arch/arm/boot/dts/am335x-moxa-uc-2100-common.dtsi index 92a0e98ec231..7b40ca9483ca 100644 --- a/arch/arm/boot/dts/am335x-moxa-uc-2100-common.dtsi +++ b/arch/arm/boot/dts/am335x-moxa-uc-2100-common.dtsi @@ -166,10 +166,8 @@ &buttons { pinctrl-names = "default"; pinctrl-0 = <&push_button_pins>; - #address-cells = <1>; - #size-cells = <0>; - button@0 { + button-0 { label = "push_button"; linux,code = <0x100>; gpios = <&gpio2 23 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/am335x-moxa-uc-8100-common.dtsi b/arch/arm/boot/dts/am335x-moxa-uc-8100-common.dtsi index e7e439a0630a..e0364adb8393 100644 --- a/arch/arm/boot/dts/am335x-moxa-uc-8100-common.dtsi +++ b/arch/arm/boot/dts/am335x-moxa-uc-8100-common.dtsi @@ -378,10 +378,8 @@ &buttons { pinctrl-names = "default"; pinctrl-0 = <&push_button_pins>; - #address-cells = <1>; - #size-cells = <0>; - button@0 { + button-0 { label = "push_button"; linux,code = <0x100>; gpios = <&gpio3 21 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/am335x-pcm-953.dtsi b/arch/arm/boot/dts/am335x-pcm-953.dtsi index 124026fa0d09..dae448040a97 100644 --- a/arch/arm/boot/dts/am335x-pcm-953.dtsi +++ b/arch/arm/boot/dts/am335x-pcm-953.dtsi @@ -54,14 +54,14 @@ pinctrl-names = "default"; pinctrl-0 = <&user_buttons_pins>; - button@0 { + button-0 { label = "home"; linux,code = <KEY_HOME>; gpios = <&gpio3 7 GPIO_ACTIVE_HIGH>; wakeup-source; }; - button@1 { + button-1 { label = "menu"; linux,code = <KEY_MENU>; gpios = <&gpio3 8 GPIO_ACTIVE_HIGH>; diff --git a/arch/arm/boot/dts/am335x-pepper.dts b/arch/arm/boot/dts/am335x-pepper.dts index b5e88e627bc1..8691eec33b61 100644 --- a/arch/arm/boot/dts/am335x-pepper.dts +++ b/arch/arm/boot/dts/am335x-pepper.dts @@ -596,24 +596,22 @@ &buttons { pinctrl-names = "default"; pinctrl-0 = <&user_buttons_pins>; - #address-cells = <1>; - #size-cells = <0>; - button0 { + button-0 { label = "home"; linux,code = <KEY_HOME>; gpios = <&gpio1 22 GPIO_ACTIVE_LOW>; wakeup-source; }; - button1 { + button-1 { label = "menu"; linux,code = <KEY_MENU>; gpios = <&gpio1 23 GPIO_ACTIVE_LOW>; wakeup-source; }; - buttons2 { + button-2 { label = "power"; linux,code = <KEY_POWER>; gpios = <&gpio0 7 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/am335x-sancloud-bbe-extended-wifi.dts b/arch/arm/boot/dts/am335x-sancloud-bbe-extended-wifi.dts index 246a1a9b3e44..a2676d10c24a 100644 --- a/arch/arm/boot/dts/am335x-sancloud-bbe-extended-wifi.dts +++ b/arch/arm/boot/dts/am335x-sancloud-bbe-extended-wifi.dts @@ -23,7 +23,7 @@ regulator-name = "wlan-en-regulator"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - startup-delay-us= <100000>; + startup-delay-us = <100000>; }; }; diff --git a/arch/arm/boot/dts/am335x-shc.dts b/arch/arm/boot/dts/am335x-shc.dts index 6b9877560741..c497200f9cb0 100644 --- a/arch/arm/boot/dts/am335x-shc.dts +++ b/arch/arm/boot/dts/am335x-shc.dts @@ -36,10 +36,10 @@ }; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; - back_button { + back-button { label = "Back Button"; gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>; linux,code = <KEY_BACK>; @@ -47,7 +47,7 @@ wakeup-source; }; - front_button { + front-button { label = "Front Button"; gpios = <&gpio1 25 GPIO_ACTIVE_HIGH>; linux,code = <KEY_FRONT>; diff --git a/arch/arm/boot/dts/am3517-evm-ui.dtsi b/arch/arm/boot/dts/am3517-evm-ui.dtsi index 7d8f32bf70db..75ad42179aee 100644 --- a/arch/arm/boot/dts/am3517-evm-ui.dtsi +++ b/arch/arm/boot/dts/am3517-evm-ui.dtsi @@ -70,61 +70,61 @@ compatible = "gpio-keys-polled"; poll-interval = <100>; - record { + key-record { label = "Record"; /* linux,code = <BTN_0>; */ gpios = <&tca6416_2 15 GPIO_ACTIVE_LOW>; }; - play { + key-play { label = "Play"; linux,code = <KEY_PLAY>; gpios = <&tca6416_2 14 GPIO_ACTIVE_LOW>; }; - Stop { + key-stop { label = "Stop"; linux,code = <KEY_STOP>; gpios = <&tca6416_2 13 GPIO_ACTIVE_LOW>; }; - fwd { + key-fwd { label = "FWD"; linux,code = <KEY_FASTFORWARD>; gpios = <&tca6416_2 12 GPIO_ACTIVE_LOW>; }; - rwd { + key-rwd { label = "RWD"; linux,code = <KEY_REWIND>; gpios = <&tca6416_2 11 GPIO_ACTIVE_LOW>; }; - shift { + key-shift { label = "Shift"; linux,code = <KEY_LEFTSHIFT>; gpios = <&tca6416_2 10 GPIO_ACTIVE_LOW>; }; - Mode { + key-mode { label = "Mode"; linux,code = <BTN_MODE>; gpios = <&tca6416_2 9 GPIO_ACTIVE_LOW>; }; - Menu { + key-menu { label = "Menu"; linux,code = <KEY_MENU>; gpios = <&tca6416_2 8 GPIO_ACTIVE_LOW>; }; - Up { + key-up { label = "Up"; linux,code = <KEY_UP>; gpios = <&tca6416_2 7 GPIO_ACTIVE_LOW>; }; - Down { + key-down { label = "Down"; linux,code = <KEY_DOWN>; gpios = <&tca6416_2 6 GPIO_ACTIVE_LOW>; @@ -137,14 +137,14 @@ tlv320aic23_1: codec@1a { compatible = "ti,tlv320aic23"; reg = <0x1a>; - #sound-dai-cells= <0>; + #sound-dai-cells = <0>; status = "okay"; }; tlv320aic23_2: codec@1b { compatible = "ti,tlv320aic23"; reg = <0x1b>; - #sound-dai-cells= <0>; + #sound-dai-cells = <0>; status = "okay"; }; }; @@ -154,7 +154,7 @@ tlv320aic23_3: codec@1a { compatible = "ti,tlv320aic23"; reg = <0x1a>; - #sound-dai-cells= <0>; + #sound-dai-cells = <0>; status = "okay"; }; diff --git a/arch/arm/boot/dts/am3517-evm.dts b/arch/arm/boot/dts/am3517-evm.dts index c8b80f156ec9..35b653014f2b 100644 --- a/arch/arm/boot/dts/am3517-evm.dts +++ b/arch/arm/boot/dts/am3517-evm.dts @@ -37,55 +37,55 @@ compatible = "gpio-keys-polled"; poll-interval = <100>; - user_pb { + button-user { label = "User Push Button"; linux,code = <BTN_0>; gpios = <&tca6416 5 GPIO_ACTIVE_LOW>; }; - user_sw_1 { + switch-1 { label = "User Switch 1"; linux,code = <BTN_1>; gpios = <&tca6416 8 GPIO_ACTIVE_LOW>; }; - user_sw_2 { + switch-2 { label = "User Switch 2"; linux,code = <BTN_2>; gpios = <&tca6416 9 GPIO_ACTIVE_LOW>; }; - user_sw_3 { + switch-3 { label = "User Switch 3"; linux,code = <BTN_3>; gpios = <&tca6416 10 GPIO_ACTIVE_LOW>; }; - user_sw_4 { + switch-4 { label = "User Switch 4"; linux,code = <BTN_4>; gpios = <&tca6416 11 GPIO_ACTIVE_LOW>; }; - user_sw_5 { + switch-5 { label = "User Switch 5"; linux,code = <BTN_5>; gpios = <&tca6416 12 GPIO_ACTIVE_LOW>; }; - user_sw_6 { + switch-6 { label = "User Switch 6"; linux,code = <BTN_6>; gpios = <&tca6416 13 GPIO_ACTIVE_LOW>; }; - user_sw_7 { + switch-7 { label = "User Switch 7"; linux,code = <BTN_7>; gpios = <&tca6416 14 GPIO_ACTIVE_LOW>; }; - user_sw_8 { + switch-8 { label = "User Switch 8"; linux,code = <BTN_8>; gpios = <&tca6416 15 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/am3874-iceboard.dts b/arch/arm/boot/dts/am3874-iceboard.dts index c9323d1df303..d039af879367 100644 --- a/arch/arm/boot/dts/am3874-iceboard.dts +++ b/arch/arm/boot/dts/am3874-iceboard.dts @@ -213,7 +213,7 @@ u48: pca9575@22 { compatible = "nxp,pca9575"; - reg=<0x22>; + reg = <0x22>; gpio-controller; #gpio-cells = <2>; @@ -232,7 +232,7 @@ u59: pca9575@23 { compatible = "nxp,pca9575"; - reg=<0x23>; + reg = <0x23>; gpio-controller; #gpio-cells = <2>; gpio-line-names = diff --git a/arch/arm/boot/dts/am437x-idk-evm.dts b/arch/arm/boot/dts/am437x-idk-evm.dts index 5a74b83145cf..123a95f87554 100644 --- a/arch/arm/boot/dts/am437x-idk-evm.dts +++ b/arch/arm/boot/dts/am437x-idk-evm.dts @@ -98,14 +98,12 @@ vin-supply = <&v1_5dreg>; }; - gpio_keys: gpio_keys { + gpio_keys: gpio-keys { compatible = "gpio-keys"; pinctrl-names = "default"; pinctrl-0 = <&gpio_keys_pins_default>; - #address-cells = <1>; - #size-cells = <0>; - switch0 { + switch-0 { label = "power-button"; linux,code = <KEY_POWER>; gpios = <&gpio4 2 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/am437x-l4.dtsi b/arch/arm/boot/dts/am437x-l4.dtsi index 8f2268c02778..415210b034ef 100644 --- a/arch/arm/boot/dts/am437x-l4.dtsi +++ b/arch/arm/boot/dts/am437x-l4.dtsi @@ -2407,7 +2407,7 @@ adc { #io-channel-cells = <1>; - compatible ="ti,am4372-adc"; + compatible = "ti,am4372-adc"; }; }; }; diff --git a/arch/arm/boot/dts/animeo_ip.dts b/arch/arm/boot/dts/animeo_ip.dts index 7da718abbd85..29936bfbeeb7 100644 --- a/arch/arm/boot/dts/animeo_ip.dts +++ b/arch/arm/boot/dts/animeo_ip.dts @@ -168,26 +168,24 @@ }; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - keyswitch_in { + key-switch-in { label = "keyswitch_in"; gpios = <&pioB 1 GPIO_ACTIVE_HIGH>; linux,code = <28>; wakeup-source; }; - error_in { + key-error-in { label = "error_in"; gpios = <&pioB 2 GPIO_ACTIVE_HIGH>; linux,code = <29>; wakeup-source; }; - btn { + key-s { label = "btn"; gpios = <&pioC 23 GPIO_ACTIVE_HIGH>; linux,code = <31>; diff --git a/arch/arm/boot/dts/armada-370-c200-v2.dts b/arch/arm/boot/dts/armada-370-c200-v2.dts index 1a4a09bdde63..84d40e1d70ef 100644 --- a/arch/arm/boot/dts/armada-370-c200-v2.dts +++ b/arch/arm/boot/dts/armada-370-c200-v2.dts @@ -75,25 +75,25 @@ pinctrl-0 = <&pmx_buttons>; pinctrl-names = "default"; - power { + button-power { label = "Power Button"; linux,code = <KEY_POWER>; gpios = <&gpio0 10 GPIO_ACTIVE_HIGH>; }; - reset { + button-reset { label = "Reset Button"; linux,code = <KEY_RESTART>; gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; }; - usb1 { + button-usb1 { label = "USB1 Button"; linux,code = <BTN_0>; gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; }; - usb2 { + button-usb2 { label = "USB2 Button"; linux,code = <BTN_1>; gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/armada-370-rd.dts b/arch/arm/boot/dts/armada-370-rd.dts index c910d157a686..6ba7699b69ed 100644 --- a/arch/arm/boot/dts/armada-370-rd.dts +++ b/arch/arm/boot/dts/armada-370-rd.dts @@ -84,8 +84,6 @@ gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; button { label = "Software Button"; linux,code = <KEY_POWER>; diff --git a/arch/arm/boot/dts/armada-370-seagate-nas-xbay.dtsi b/arch/arm/boot/dts/armada-370-seagate-nas-xbay.dtsi index b52634ecf1d9..866b8630d407 100644 --- a/arch/arm/boot/dts/armada-370-seagate-nas-xbay.dtsi +++ b/arch/arm/boot/dts/armada-370-seagate-nas-xbay.dtsi @@ -108,22 +108,20 @@ gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - power { + button-power { label = "Power button"; linux,code = <KEY_POWER>; gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; debounce-interval = <100>; }; - backup { + button-backup { label = "Backup button"; linux,code = <KEY_OPTION>; gpios = <&gpio0 31 GPIO_ACTIVE_LOW>; debounce-interval = <100>; }; - reset { + button-reset { label = "Reset Button"; linux,code = <KEY_RESTART>; gpios = <&gpio1 23 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/armada-370-seagate-personal-cloud.dtsi b/arch/arm/boot/dts/armada-370-seagate-personal-cloud.dtsi index 0abac5ffe45a..702a85af2078 100644 --- a/arch/arm/boot/dts/armada-370-seagate-personal-cloud.dtsi +++ b/arch/arm/boot/dts/armada-370-seagate-personal-cloud.dtsi @@ -83,22 +83,20 @@ gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - power { + button-power { label = "Power button"; linux,code = <KEY_POWER>; gpios = <&gpio1 19 GPIO_ACTIVE_HIGH>; debounce-interval = <100>; }; - reset { + button-reset { label = "Reset Button"; linux,code = <KEY_RESTART>; gpios = <&gpio1 23 GPIO_ACTIVE_LOW>; debounce-interval = <100>; }; - button { + button-usb { label = "USB VBUS error"; linux,code = <KEY_UNKNOWN>; gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/armada-381-netgear-gs110emx.dts b/arch/arm/boot/dts/armada-381-netgear-gs110emx.dts index 396172067f6a..095df5567c93 100644 --- a/arch/arm/boot/dts/armada-381-netgear-gs110emx.dts +++ b/arch/arm/boot/dts/armada-381-netgear-gs110emx.dts @@ -24,7 +24,7 @@ pinctrl-0 = <&front_button_pins>; pinctrl-names = "default"; - factory_default { + key-factory-default { label = "Factory Default"; gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; linux,code = <KEY_RESTART>; diff --git a/arch/arm/boot/dts/armada-385-clearfog-gtr.dtsi b/arch/arm/boot/dts/armada-385-clearfog-gtr.dtsi index 10ad46f29393..d1452a04e904 100644 --- a/arch/arm/boot/dts/armada-385-clearfog-gtr.dtsi +++ b/arch/arm/boot/dts/armada-385-clearfog-gtr.dtsi @@ -256,14 +256,14 @@ pinctrl-0 = <&cf_gtr_rear_button_pins &cf_gtr_front_button_pins>; pinctrl-names = "default"; - button_0 { + button-0 { label = "Rear Button"; gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; linux,can-disable; linux,code = <BTN_0>; }; - button_1 { + button-1 { label = "Front Button"; gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; linux,can-disable; diff --git a/arch/arm/boot/dts/armada-385-linksys.dtsi b/arch/arm/boot/dts/armada-385-linksys.dtsi index fb9c8a0b241c..116aca5e688f 100644 --- a/arch/arm/boot/dts/armada-385-linksys.dtsi +++ b/arch/arm/boot/dts/armada-385-linksys.dtsi @@ -53,13 +53,13 @@ pinctrl-0 = <&gpio_keys_pins>; pinctrl-names = "default"; - wps { + button-wps { label = "WPS"; linux,code = <KEY_WPS_BUTTON>; gpios = <&gpio0 24 GPIO_ACTIVE_LOW>; }; - reset { + button-reset { label = "Factory Reset Button"; linux,code = <KEY_RESTART>; gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/armada-385-turris-omnia.dts b/arch/arm/boot/dts/armada-385-turris-omnia.dts index f4878df39753..d1e0db6e5730 100644 --- a/arch/arm/boot/dts/armada-385-turris-omnia.dts +++ b/arch/arm/boot/dts/armada-385-turris-omnia.dts @@ -191,15 +191,13 @@ reg = <0x2b>; #address-cells = <1>; #size-cells = <0>; + status = "okay"; /* * LEDs are controlled by MCU (STM32F0) at * address 0x2b. * - * The driver does not support HW control mode - * for the LEDs yet. Disable the LEDs for now. - * - * Also LED functions are not stable yet: + * LED functions are not stable yet: * - there are 3 LEDs connected via MCU to PCIe * ports. One of these ports supports mSATA. * There is no mSATA nor PCIe function. @@ -210,7 +208,6 @@ * B. Again there is no such function defined. * For now we use LED_FUNCTION_INDICATOR */ - status = "disabled"; multi-led@0 { reg = <0x0>; @@ -397,7 +394,8 @@ phy1: ethernet-phy@1 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <1>; - marvell,reg-init = <3 18 0 0x4985>; + marvell,reg-init = <3 18 0 0x4985>, + <3 16 0xfff0 0x0001>; /* irq is connected to &pcawan pin 7 */ }; diff --git a/arch/arm/boot/dts/armada-388-clearfog-base.dts b/arch/arm/boot/dts/armada-388-clearfog-base.dts index 53b4bd35522a..f7daa3bc707e 100644 --- a/arch/arm/boot/dts/armada-388-clearfog-base.dts +++ b/arch/arm/boot/dts/armada-388-clearfog-base.dts @@ -19,7 +19,7 @@ pinctrl-0 = <&rear_button_pins>; pinctrl-names = "default"; - button_0 { + button-0 { /* The rear SW3 button */ label = "Rear Button"; gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/armada-388-clearfog.dts b/arch/arm/boot/dts/armada-388-clearfog.dts index 4140a5303b48..95299167dcf5 100644 --- a/arch/arm/boot/dts/armada-388-clearfog.dts +++ b/arch/arm/boot/dts/armada-388-clearfog.dts @@ -35,7 +35,7 @@ pinctrl-0 = <&rear_button_pins>; pinctrl-names = "default"; - button_0 { + button-0 { /* The rear SW3 button */ label = "Rear Button"; gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/armada-xp-axpwifiap.dts b/arch/arm/boot/dts/armada-xp-axpwifiap.dts index 3e77b4337802..5a74197be0ad 100644 --- a/arch/arm/boot/dts/armada-xp-axpwifiap.dts +++ b/arch/arm/boot/dts/armada-xp-axpwifiap.dts @@ -69,14 +69,12 @@ }; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; pinctrl-0 = <&keys_pin>; pinctrl-names = "default"; - reset { + button-reset { label = "Factory Reset Button"; linux,code = <KEY_SETUP>; gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts index 36932e3b781a..622ac40dd164 100644 --- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts +++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts @@ -172,20 +172,18 @@ }; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; pinctrl-0 = <&keys_pin>; pinctrl-names = "default"; - wps { + button-wps { label = "WPS"; linux,code = <KEY_WPS_BUTTON>; gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; }; - reset { + button-reset { label = "Factory Reset Button"; linux,code = <KEY_RESTART>; gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts index 0efcc166dabf..1ecf72a61bca 100644 --- a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts +++ b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts @@ -97,12 +97,10 @@ }; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - init { + button-init { label = "Init Button"; linux,code = <KEY_POWER>; gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>; diff --git a/arch/arm/boot/dts/aspeed-ast2500-evb.dts b/arch/arm/boot/dts/aspeed-ast2500-evb.dts index 1d24b394ea4c..a497dd135491 100644 --- a/arch/arm/boot/dts/aspeed-ast2500-evb.dts +++ b/arch/arm/boot/dts/aspeed-ast2500-evb.dts @@ -5,7 +5,7 @@ / { model = "AST2500 EVB"; - compatible = "aspeed,ast2500"; + compatible = "aspeed,ast2500-evb", "aspeed,ast2500"; aliases { serial4 = &uart5; diff --git a/arch/arm/boot/dts/aspeed-ast2600-evb-a1.dts b/arch/arm/boot/dts/aspeed-ast2600-evb-a1.dts index dd7148060c4a..d0a5c2ff0fec 100644 --- a/arch/arm/boot/dts/aspeed-ast2600-evb-a1.dts +++ b/arch/arm/boot/dts/aspeed-ast2600-evb-a1.dts @@ -5,6 +5,7 @@ / { model = "AST2600 A1 EVB"; + compatible = "aspeed,ast2600-evb-a1", "aspeed,ast2600"; /delete-node/regulator-vcc-sdhci0; /delete-node/regulator-vcc-sdhci1; diff --git a/arch/arm/boot/dts/aspeed-ast2600-evb.dts b/arch/arm/boot/dts/aspeed-ast2600-evb.dts index 5a6063bd4508..c698e6538269 100644 --- a/arch/arm/boot/dts/aspeed-ast2600-evb.dts +++ b/arch/arm/boot/dts/aspeed-ast2600-evb.dts @@ -8,7 +8,7 @@ / { model = "AST2600 EVB"; - compatible = "aspeed,ast2600"; + compatible = "aspeed,ast2600-evb-a1", "aspeed,ast2600"; aliases { serial4 = &uart5; diff --git a/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts b/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts index 1b2e7ad37566..82a6f14a45f0 100644 --- a/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts +++ b/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts @@ -100,91 +100,91 @@ gpio-keys { compatible = "gpio-keys"; - shutdown_ack { + event-shutdown-ack { label = "SHUTDOWN_ACK"; gpios = <&gpio ASPEED_GPIO(G, 2) GPIO_ACTIVE_LOW>; linux,code = <ASPEED_GPIO(G, 2)>; }; - reboot_ack { + event-reboot-ack { label = "REBOOT_ACK"; gpios = <&gpio ASPEED_GPIO(J, 3) GPIO_ACTIVE_LOW>; linux,code = <ASPEED_GPIO(J, 3)>; }; - S0_overtemp { + event-s0-overtemp { label = "S0_OVERTEMP"; gpios = <&gpio ASPEED_GPIO(G, 3) GPIO_ACTIVE_LOW>; linux,code = <ASPEED_GPIO(G, 3)>; }; - S0_hightemp { + event-s0-hightemp { label = "S0_HIGHTEMP"; gpios = <&gpio ASPEED_GPIO(J, 0) GPIO_ACTIVE_LOW>; linux,code = <ASPEED_GPIO(J, 0)>; }; - S0_cpu_fault { + event-s0-cpu-fault { label = "S0_CPU_FAULT"; gpios = <&gpio ASPEED_GPIO(J, 1) GPIO_ACTIVE_HIGH>; linux,code = <ASPEED_GPIO(J, 1)>; }; - S0_scp_auth_fail { + event-s0-scp-auth-fail { label = "S0_SCP_AUTH_FAIL"; gpios = <&gpio ASPEED_GPIO(J, 2) GPIO_ACTIVE_LOW>; linux,code = <ASPEED_GPIO(J, 2)>; }; - S1_scp_auth_fail { + event-s1-scp-auth-fail { label = "S1_SCP_AUTH_FAIL"; gpios = <&gpio ASPEED_GPIO(Z, 5) GPIO_ACTIVE_LOW>; linux,code = <ASPEED_GPIO(Z, 5)>; }; - S1_overtemp { + event-s1-overtemp { label = "S1_OVERTEMP"; gpios = <&gpio ASPEED_GPIO(Z, 6) GPIO_ACTIVE_LOW>; linux,code = <ASPEED_GPIO(Z, 6)>; }; - S1_hightemp { + event-s1-hightemp { label = "S1_HIGHTEMP"; gpios = <&gpio ASPEED_GPIO(AB, 0) GPIO_ACTIVE_LOW>; linux,code = <ASPEED_GPIO(AB, 0)>; }; - S1_cpu_fault { + event-s1-cpu-fault { label = "S1_CPU_FAULT"; gpios = <&gpio ASPEED_GPIO(Z, 1) GPIO_ACTIVE_HIGH>; linux,code = <ASPEED_GPIO(Z, 1)>; }; - id_button { + event-id { label = "ID_BUTTON"; gpios = <&gpio ASPEED_GPIO(Q, 5) GPIO_ACTIVE_LOW>; linux,code = <ASPEED_GPIO(Q, 5)>; }; - psu1_vin_good { + event-psu1-vin-good { label = "PSU1_VIN_GOOD"; gpios = <&gpio ASPEED_GPIO(H, 4) GPIO_ACTIVE_LOW>; linux,code = <ASPEED_GPIO(H, 4)>; }; - psu2_vin_good { + event-psu2-vin-good { label = "PSU2_VIN_GOOD"; gpios = <&gpio ASPEED_GPIO(H, 5) GPIO_ACTIVE_LOW>; linux,code = <ASPEED_GPIO(H, 5)>; }; - psu1_present { + event-psu1-present { label = "PSU1_PRESENT"; gpios = <&gpio ASPEED_GPIO(I, 0) GPIO_ACTIVE_LOW>; linux,code = <ASPEED_GPIO(I, 0)>; }; - psu2_present { + event-psu2-present { label = "PSU2_PRESENT"; gpios = <&gpio ASPEED_GPIO(I, 1) GPIO_ACTIVE_LOW>; linux,code = <ASPEED_GPIO(I, 1)>; diff --git a/arch/arm/boot/dts/aspeed-bmc-arm-centriq2400-rep.dts b/arch/arm/boot/dts/aspeed-bmc-arm-centriq2400-rep.dts deleted file mode 100644 index 3395de96ee11..000000000000 --- a/arch/arm/boot/dts/aspeed-bmc-arm-centriq2400-rep.dts +++ /dev/null @@ -1,225 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/dts-v1/; - -#include "aspeed-g5.dtsi" -#include <dt-bindings/gpio/aspeed-gpio.h> - -/ { - model = "Qualcomm Centriq 2400 REP AST2520"; - compatible = "qualcomm,centriq2400-rep-bmc", "aspeed,ast2500"; - - chosen { - stdout-path = &uart5; - bootargs = "console=ttyS4,115200 earlycon"; - }; - - memory@80000000 { - reg = <0x80000000 0x40000000>; - }; - - iio-hwmon { - compatible = "iio-hwmon"; - io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, - <&adc 4>, <&adc 5>, <&adc 6>, <&adc 8>; - }; - - iio-hwmon-battery { - compatible = "iio-hwmon"; - io-channels = <&adc 7>; - }; - - leds { - compatible = "gpio-leds"; - - uid_led { - label = "UID_LED"; - gpios = <&gpio ASPEED_GPIO(Q, 5) GPIO_ACTIVE_LOW>; - }; - - ras_error_led { - label = "RAS_ERROR_LED"; - gpios = <&gpio ASPEED_GPIO(F, 6) GPIO_ACTIVE_LOW>; - }; - - system_fault { - label = "System_fault"; - gpios = <&gpio ASPEED_GPIO(A, 1) GPIO_ACTIVE_LOW>; - }; - }; -}; - -&fmc { - status = "okay"; - flash@0 { - status = "okay"; - m25p,fast-read; - label = "bmc"; -#include "openbmc-flash-layout.dtsi" - }; -}; - -&spi1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi1_default>; - flash@0 { - status = "okay"; - }; -}; - -&spi2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi2ck_default - &pinctrl_spi2miso_default - &pinctrl_spi2mosi_default - &pinctrl_spi2cs0_default>; -}; - -&uart3 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_txd3_default &pinctrl_rxd3_default>; - current-speed = <115200>; -}; - -&uart5 { - status = "okay"; -}; - -&mac0 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rgmii1_default &pinctrl_mdio1_default>; -}; - -&i2c0 { - status = "okay"; -}; - -&i2c1 { - status = "okay"; - - tmp421@1e { - compatible = "ti,tmp421"; - reg = <0x1e>; - }; - tmp421@2a { - compatible = "ti,tmp421"; - reg = <0x2a>; - }; - tmp421@4e { - compatible = "ti,tmp421"; - reg = <0x4e>; - }; - tmp421@1c { - compatible = "ti,tmp421"; - reg = <0x1c>; - }; -}; - -&i2c2 { - status = "okay"; -}; - -&i2c3 { - status = "okay"; -}; - -&i2c4 { - status = "okay"; -}; - -&i2c5 { - status = "okay"; -}; - -&i2c6 { - status = "okay"; - - tmp421@1d { - compatible = "ti,tmp421"; - reg = <0x1d>; - }; - tmp421@1f { - compatible = "ti,tmp421"; - reg = <0x1f>; - }; - tmp421@4d { - compatible = "ti,tmp421"; - reg = <0x4d>; - }; - tmp421@4f { - compatible = "ti,tmp421"; - reg = <0x4f>; - }; - nvt210@4c { - compatible = "nvt210"; - reg = <0x4c>; - }; - eeprom@50 { - compatible = "atmel,24c128"; - reg = <0x50>; - pagesize = <128>; - }; -}; - -&i2c7 { - status = "okay"; -}; - -&i2c8 { - status = "okay"; - - pca9641@70 { - compatible = "nxp,pca9641"; - reg = <0x70>; - i2c-arb { - #address-cells = <1>; - #size-cells = <0>; - tmp421@1d { - compatible = "tmp421"; - reg = <0x1d>; - }; - adm1278@12 { - compatible = "adi,adm1278"; - reg = <0x12>; - Rsense = <500>; - }; - eeprom@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - }; - ds1100@58 { - compatible = "ds1100"; - reg = <0x58>; - }; - }; - }; -}; - -&i2c9 { - status = "okay"; -}; - -&vuart { - status = "okay"; -}; - -&gfx { - status = "okay"; -}; - -&pinctrl { - aspeed,external-nodes = <&gfx &lhc>; -}; - -&gpio { - pin_gpio_c7 { - gpio-hog; - gpios = <ASPEED_GPIO(C, 7) GPIO_ACTIVE_HIGH>; - output; - line-name = "BIOS_SPI_MUX_S"; - }; -}; diff --git a/arch/arm/boot/dts/aspeed-bmc-bytedance-g220a.dts b/arch/arm/boot/dts/aspeed-bmc-bytedance-g220a.dts index 0d1fb5ccfd36..f75cad41ae6f 100644 --- a/arch/arm/boot/dts/aspeed-bmc-bytedance-g220a.dts +++ b/arch/arm/boot/dts/aspeed-bmc-bytedance-g220a.dts @@ -100,7 +100,7 @@ gpio-keys { compatible = "gpio-keys"; - burn-in-signal { + event-burn-in-signal { label = "burn-in"; gpios = <&gpio ASPEED_GPIO(R, 5) GPIO_ACTIVE_LOW>; linux,code = <ASPEED_GPIO(R, 5)>; @@ -111,139 +111,139 @@ compatible = "gpio-keys-polled"; poll-interval = <1000>; - rear-riser1-presence { + event-rear-riser1-presence { label = "rear-riser1-presence"; gpios = <&pca0 1 GPIO_ACTIVE_LOW>; linux,code = <1>; }; - alrt-pvddq-cpu0 { + event-alrt-pvddq-cpu0 { label = "alrt-pvddq-cpu0"; gpios = <&pca0 8 GPIO_ACTIVE_LOW>; linux,code = <2>; }; - rear-riser0-presence { + event-rear-riser0-presence { label = "rear-riser0-presence"; gpios = <&pca0 9 GPIO_ACTIVE_LOW>; linux,code = <3>; }; - fault-pvddq-cpu0 { + event-fault-pvddq-cpu0 { label = "fault-pvddq-cpu0"; gpios = <&pca0 10 GPIO_ACTIVE_LOW>; linux,code = <4>; }; - alrt-pvddq-cpu1 { + event-alrt-pvddq-cpu1 { label = "alrt-pvddq-cpu1"; gpios = <&pca0 11 GPIO_ACTIVE_LOW>; linux,code = <5>; }; - fault-pvddq-cpu1 { + event-fault-pvddq-cpu1 { label = "alrt-pvddq-cpu1"; gpios = <&pca0 12 GPIO_ACTIVE_LOW>; linux,code = <6>; }; - fault-pvccin-cpu1 { + event-fault-pvccin-cpu1 { label = "fault-pvccin-cpuq"; gpios = <&pca0 13 GPIO_ACTIVE_LOW>; linux,code = <7>; }; - bmc-rom0-wp { + event-bmc-rom0-wp { label = "bmc-rom0-wp"; gpios = <&pca1 0 GPIO_ACTIVE_LOW>; linux,code = <8>; }; - bmc-rom1-wp { + event-bmc-rom1-wp { label = "bmc-rom1-wp"; gpios = <&pca1 1 GPIO_ACTIVE_LOW>; linux,code = <9>; }; - fan0-presence { + event-fan0-presence { label = "fan0-presence"; gpios = <&pca1 2 GPIO_ACTIVE_LOW>; linux,code = <10>; }; - fan1-presence { + event-fan1-presence { label = "fan1-presence"; gpios = <&pca1 3 GPIO_ACTIVE_LOW>; linux,code = <11>; }; - fan2-presence { + event-fan2-presence { label = "fan2-presence"; gpios = <&pca1 4 GPIO_ACTIVE_LOW>; linux,code = <12>; }; - fan3-presence { + event-fan3-presence { label = "fan3-presence"; gpios = <&pca1 5 GPIO_ACTIVE_LOW>; linux,code = <13>; }; - fan4-presence { + event-fan4-presence { label = "fan4-presence"; gpios = <&pca1 6 GPIO_ACTIVE_LOW>; linux,code = <14>; }; - fan5-presence { + event-fan5-presence { label = "fan5-presence"; gpios = <&pca1 7 GPIO_ACTIVE_LOW>; linux,code = <15>; }; - front-bp1-presence { + event-front-bp1-presence { label = "front-bp1-presence"; gpios = <&pca1 8 GPIO_ACTIVE_LOW>; linux,code = <16>; }; - rear-bp-presence { + event-rear-bp-presence { label = "rear-bp-presence"; gpios = <&pca1 9 GPIO_ACTIVE_LOW>; linux,code = <17>; }; - fault-pvccin-cpu0 { + event-fault-pvccin-cpu0 { label = "fault-pvccin-cpu0"; gpios = <&pca1 10 GPIO_ACTIVE_LOW>; linux,code = <18>; }; - alrt-p1v05-pvcc { + event-alrt-p1v05-pvcc { label = "alrt-p1v05-pvcc1"; gpios = <&pca1 11 GPIO_ACTIVE_LOW>; linux,code = <19>; }; - fault-p1v05-pvccio { + event-fault-p1v05-pvccio { label = "alrt-p1v05-pvcc1"; gpios = <&pca1 12 GPIO_ACTIVE_LOW>; linux,code = <20>; }; - alrt-p1v8-pvccio { + event-alrt-p1v8-pvccio { label = "alrt-p1v8-pvccio"; gpios = <&pca1 13 GPIO_ACTIVE_LOW>; linux,code = <21>; }; - fault-p1v8-pvccio { + event-fault-p1v8-pvccio { label = "fault-p1v8-pvccio"; gpios = <&pca1 14 GPIO_ACTIVE_LOW>; linux,code = <22>; }; - front-bp0-presence { + event-front-bp0-presence { label = "front-bp0-presence"; gpios = <&pca1 15 GPIO_ACTIVE_LOW>; linux,code = <23>; diff --git a/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts b/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts index 382da7934eaa..a6a2bc3b855c 100644 --- a/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts +++ b/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts @@ -189,29 +189,27 @@ gpio-keys-polled { compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; poll-interval = <1000>; - fan0-presence { + event-fan0-presence { label = "fan0-presence"; gpios = <&pca0 15 GPIO_ACTIVE_LOW>; linux,code = <15>; }; - fan1-presence { + event-fan1-presence { label = "fan1-presence"; gpios = <&pca0 14 GPIO_ACTIVE_LOW>; linux,code = <14>; }; - fan2-presence { + event-fan2-presence { label = "fan2-presence"; gpios = <&pca0 13 GPIO_ACTIVE_LOW>; linux,code = <13>; }; - fan3-presence { + event-fan3-presence { label = "fan3-presence"; gpios = <&pca0 12 GPIO_ACTIVE_LOW>; linux,code = <12>; diff --git a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts index 7213434695bf..bf59a9962379 100644 --- a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts +++ b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts @@ -179,41 +179,39 @@ gpio-keys-polled { compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; poll-interval = <1000>; - fan0-presence { + event-fan0-presence { label = "fan0-presence"; gpios = <&pca0 6 GPIO_ACTIVE_LOW>; linux,code = <6>; }; - fan1-presence { + event-fan1-presence { label = "fan1-presence"; gpios = <&pca0 7 GPIO_ACTIVE_LOW>; linux,code = <7>; }; - fan2-presence { + event-fan2-presence { label = "fan2-presence"; gpios = <&pca0 8 GPIO_ACTIVE_LOW>; linux,code = <8>; }; - fan3-presence { + event-fan3-presence { label = "fan3-presence"; gpios = <&pca0 9 GPIO_ACTIVE_LOW>; linux,code = <9>; }; - fan4-presence { + event-fan4-presence { label = "fan4-presence"; gpios = <&pca0 10 GPIO_ACTIVE_LOW>; linux,code = <10>; }; - fan5-presence { + event-fan5-presence { label = "fan5-presence"; gpios = <&pca0 11 GPIO_ACTIVE_LOW>; linux,code = <11>; diff --git a/arch/arm/boot/dts/aspeed-bmc-inspur-fp5280g2.dts b/arch/arm/boot/dts/aspeed-bmc-inspur-fp5280g2.dts index 60a39ea10ab1..208b0f094ed9 100644 --- a/arch/arm/boot/dts/aspeed-bmc-inspur-fp5280g2.dts +++ b/arch/arm/boot/dts/aspeed-bmc-inspur-fp5280g2.dts @@ -73,19 +73,19 @@ gpio-keys { compatible = "gpio-keys"; - checkstop { + event-checkstop { label = "checkstop"; gpios = <&gpio ASPEED_GPIO(B, 3) GPIO_ACTIVE_LOW>; linux,code = <ASPEED_GPIO(B, 3)>; }; - ps0-presence { + event-ps0-presence { label = "ps0-presence"; gpios = <&gpio ASPEED_GPIO(F, 0) GPIO_ACTIVE_LOW>; linux,code = <ASPEED_GPIO(F, 0)>; }; - ps1-presence { + event-ps1-presence { label = "ps1-presence"; gpios = <&gpio ASPEED_GPIO(F, 1) GPIO_ACTIVE_LOW>; linux,code = <ASPEED_GPIO(F, 1)>; @@ -97,49 +97,49 @@ compatible = "gpio-keys-polled"; poll-interval = <1000>; - fan0-presence { + event-fan0-presence { label = "fan0-presence"; gpios = <&pca1 0 GPIO_ACTIVE_LOW>; linux,code = <1>; }; - fan1-presence { + event-fan1-presence { label = "fan1-presence"; gpios = <&pca1 1 GPIO_ACTIVE_LOW>; linux,code = <2>; }; - fan2-presence { + event-fan2-presence { label = "fan2-presence"; gpios = <&pca1 2 GPIO_ACTIVE_LOW>; linux,code = <3>; }; - fan3-presence { + event-fan3-presence { label = "fan3-presence"; gpios = <&pca1 3 GPIO_ACTIVE_LOW>; linux,code = <4>; }; - fan4-presence { + event-fan4-presence { label = "fan4-presence"; gpios = <&pca1 4 GPIO_ACTIVE_LOW>; linux,code = <5>; }; - fan5-presence { + event-fan5-presence { label = "fan5-presence"; gpios = <&pca1 5 GPIO_ACTIVE_LOW>; linux,code = <6>; }; - fan6-presence { + event-fan6-presence { label = "fan6-presence"; gpios = <&pca1 6 GPIO_ACTIVE_LOW>; linux,code = <7>; }; - fan7-presence { + event-fan7-presence { label = "fan7-presence"; gpios = <&pca1 7 GPIO_ACTIVE_LOW>; linux,code = <8>; diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-mihawk.dts b/arch/arm/boot/dts/aspeed-bmc-opp-mihawk.dts index a52a289cee85..48776fb663fb 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-mihawk.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-mihawk.dts @@ -92,30 +92,31 @@ gpio-keys { compatible = "gpio-keys"; - air-water { + event-air-water { label = "air-water"; gpios = <&gpio ASPEED_GPIO(F, 6) GPIO_ACTIVE_LOW>; linux,code = <ASPEED_GPIO(F, 6)>; }; - checkstop { + event-checkstop { label = "checkstop"; gpios = <&gpio ASPEED_GPIO(J, 2) GPIO_ACTIVE_LOW>; linux,code = <ASPEED_GPIO(J, 2)>; }; - ps0-presence { + event-ps0-presence { label = "ps0-presence"; gpios = <&gpio ASPEED_GPIO(Z, 2) GPIO_ACTIVE_LOW>; linux,code = <ASPEED_GPIO(Z, 2)>; }; - ps1-presence { + event-ps1-presence { label = "ps1-presence"; gpios = <&gpio ASPEED_GPIO(Z, 0) GPIO_ACTIVE_LOW>; linux,code = <ASPEED_GPIO(Z, 0)>; }; - id-button { + + button-id { label = "id-button"; gpios = <&gpio ASPEED_GPIO(F, 1) GPIO_ACTIVE_LOW>; linux,code = <ASPEED_GPIO(F, 1)>; @@ -126,37 +127,37 @@ compatible = "gpio-keys-polled"; poll-interval = <1000>; - fan0-presence { + event-fan0-presence { label = "fan0-presence"; gpios = <&pca9552 9 GPIO_ACTIVE_LOW>; linux,code = <9>; }; - fan1-presence { + event-fan1-presence { label = "fan1-presence"; gpios = <&pca9552 10 GPIO_ACTIVE_LOW>; linux,code = <10>; }; - fan2-presence { + event-fan2-presence { label = "fan2-presence"; gpios = <&pca9552 11 GPIO_ACTIVE_LOW>; linux,code = <11>; }; - fan3-presence { + event-fan3-presence { label = "fan3-presence"; gpios = <&pca9552 12 GPIO_ACTIVE_LOW>; linux,code = <12>; }; - fan4-presence { + event-fan4-presence { label = "fan4-presence"; gpios = <&pca9552 13 GPIO_ACTIVE_LOW>; linux,code = <13>; }; - fan5-presence { + event-fan5-presence { label = "fan5-presence"; gpios = <&pca9552 14 GPIO_ACTIVE_LOW>; linux,code = <14>; diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-mowgli.dts b/arch/arm/boot/dts/aspeed-bmc-opp-mowgli.dts index 7d38d121ec6d..31ff19ef87a0 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-mowgli.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-mowgli.dts @@ -46,31 +46,31 @@ gpio-keys { compatible = "gpio-keys"; - air-water { + event-air-water { label = "air-water"; gpios = <&gpio ASPEED_GPIO(F, 6) GPIO_ACTIVE_LOW>; linux,code = <ASPEED_GPIO(F, 6)>; }; - checkstop { + event-checkstop { label = "checkstop"; gpios = <&gpio ASPEED_GPIO(J, 2) GPIO_ACTIVE_LOW>; linux,code = <ASPEED_GPIO(J, 2)>; }; - ps0-presence { + event-ps0-presence { label = "ps0-presence"; gpios = <&gpio ASPEED_GPIO(Z, 2) GPIO_ACTIVE_LOW>; linux,code = <ASPEED_GPIO(Z, 2)>; }; - ps1-presence { + event-ps1-presence { label = "ps1-presence"; gpios = <&gpio ASPEED_GPIO(Z, 0) GPIO_ACTIVE_LOW>; linux,code = <ASPEED_GPIO(Z, 0)>; }; - id-button { + button-id { label = "id-button"; gpios = <&gpio ASPEED_GPIO(F, 1) GPIO_ACTIVE_LOW>; linux,code = <ASPEED_GPIO(F, 1)>; @@ -81,31 +81,31 @@ compatible = "gpio-keys-polled"; poll-interval = <1000>; - fan0-presence { + event-fan0-presence { label = "fan0-presence"; gpios = <&pca9552 9 GPIO_ACTIVE_LOW>; linux,code = <9>; }; - fan1-presence { + event-fan1-presence { label = "fan1-presence"; gpios = <&pca9552 10 GPIO_ACTIVE_LOW>; linux,code = <10>; }; - fan2-presence { + event-fan2-presence { label = "fan2-presence"; gpios = <&pca9552 11 GPIO_ACTIVE_LOW>; linux,code = <11>; }; - fan3-presence { + event-fan3-presence { label = "fan3-presence"; gpios = <&pca9552 12 GPIO_ACTIVE_LOW>; linux,code = <12>; }; - fan4-presence { + event-fan4-presence { label = "fan4-presence"; gpios = <&pca9552 13 GPIO_ACTIVE_LOW>; linux,code = <13>; diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-nicole.dts b/arch/arm/boot/dts/aspeed-bmc-opp-nicole.dts index 3d4bdad27c2d..ac0d666ca10e 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-nicole.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-nicole.dts @@ -96,7 +96,7 @@ gpio-keys { compatible = "gpio-keys"; - checkstop { + event-checkstop { label = "checkstop"; gpios = <&gpio ASPEED_GPIO(J, 2) GPIO_ACTIVE_LOW>; linux,code = <ASPEED_GPIO(J, 2)>; diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts b/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts index cd660c1ff3f5..45631b47a7b3 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts @@ -73,7 +73,7 @@ gpio-keys { compatible = "gpio-keys"; - checkstop { + event-checkstop { label = "checkstop"; gpios = <&gpio ASPEED_GPIO(P, 5) GPIO_ACTIVE_LOW>; linux,code = <ASPEED_GPIO(P, 5)>; diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts b/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts index 084f54866f38..893e621ecab1 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts @@ -87,7 +87,7 @@ gpio-keys { compatible = "gpio-keys"; - checkstop { + event-checkstop { label = "checkstop"; gpios = <&gpio ASPEED_GPIO(J, 2) GPIO_ACTIVE_LOW>; linux,code = <ASPEED_GPIO(J, 2)>; diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-swift.dts b/arch/arm/boot/dts/aspeed-bmc-opp-swift.dts index 4816486c0c9e..bbf864f84d37 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-swift.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-swift.dts @@ -38,37 +38,37 @@ gpio-keys { compatible = "gpio-keys"; - air-water { + event-air-water { label = "air-water"; gpios = <&gpio ASPEED_GPIO(B, 5) GPIO_ACTIVE_LOW>; linux,code = <ASPEED_GPIO(B, 5)>; }; - checkstop { + event-checkstop { label = "checkstop"; gpios = <&gpio ASPEED_GPIO(J, 2) GPIO_ACTIVE_LOW>; linux,code = <ASPEED_GPIO(J, 2)>; }; - ps0-presence { + event-ps0-presence { label = "ps0-presence"; gpios = <&gpio ASPEED_GPIO(R, 7) GPIO_ACTIVE_LOW>; linux,code = <ASPEED_GPIO(R, 7)>; }; - ps1-presence { + event-ps1-presence { label = "ps1-presence"; gpios = <&gpio ASPEED_GPIO(N, 0) GPIO_ACTIVE_LOW>; linux,code = <ASPEED_GPIO(N, 0)>; }; - oppanel-presence { + event-oppanel-presence { label = "oppanel-presence"; gpios = <&gpio ASPEED_GPIO(A, 7) GPIO_ACTIVE_LOW>; linux,code = <ASPEED_GPIO(A, 7)>; }; - opencapi-riser-presence { + event-opencapi-riser-presence { label = "opencapi-riser-presence"; gpios = <&gpio ASPEED_GPIO(I, 0) GPIO_ACTIVE_LOW>; linux,code = <ASPEED_GPIO(I, 0)>; @@ -84,55 +84,55 @@ compatible = "gpio-keys-polled"; poll-interval = <1000>; - scm0-presence { + event-scm0-presence { label = "scm0-presence"; gpios = <&pca9552 6 GPIO_ACTIVE_LOW>; linux,code = <6>; }; - scm1-presence { + event-scm1-presence { label = "scm1-presence"; gpios = <&pca9552 7 GPIO_ACTIVE_LOW>; linux,code = <7>; }; - cpu0vrm-presence { + event-cpu0vrm-presence { label = "cpu0vrm-presence"; gpios = <&pca9552 12 GPIO_ACTIVE_LOW>; linux,code = <12>; }; - cpu1vrm-presence { + event-cpu1vrm-presence { label = "cpu1vrm-presence"; gpios = <&pca9552 13 GPIO_ACTIVE_LOW>; linux,code = <13>; }; - fan0-presence { + event-fan0-presence { label = "fan0-presence"; gpios = <&pca0 5 GPIO_ACTIVE_LOW>; linux,code = <5>; }; - fan1-presence { + event-fan1-presence { label = "fan1-presence"; gpios = <&pca0 6 GPIO_ACTIVE_LOW>; linux,code = <6>; }; - fan2-presence { + event-fan2-presence { label = "fan2-presence"; gpios = <&pca0 7 GPIO_ACTIVE_LOW>; linux,code = <7>; }; - fan3-presence { + event-fan3-presence { label = "fan3-presence"; gpios = <&pca0 8 GPIO_ACTIVE_LOW>; linux,code = <8>; }; - fanboost-presence { + event-fanboost-presence { label = "fanboost-presence"; gpios = <&pca0 9 GPIO_ACTIVE_LOW>; linux,code = <9>; diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts b/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts index 72b7a6639ed9..3f6010ef2b86 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts @@ -50,13 +50,13 @@ gpio-keys { compatible = "gpio-keys"; - ps0-presence { + event-ps0-presence { label = "ps0-presence"; gpios = <&gpio0 ASPEED_GPIO(H, 3) GPIO_ACTIVE_LOW>; linux,code = <ASPEED_GPIO(H, 3)>; }; - ps1-presence { + event-ps1-presence { label = "ps1-presence"; gpios = <&gpio0 ASPEED_GPIO(E, 5) GPIO_ACTIVE_LOW>; linux,code = <ASPEED_GPIO(E, 5)>; @@ -65,29 +65,27 @@ gpio-keys-polled { compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; poll-interval = <1000>; - fan0-presence { + event-fan0-presence { label = "fan0-presence"; gpios = <&pca0 4 GPIO_ACTIVE_LOW>; linux,code = <4>; }; - fan1-presence { + event-fan1-presence { label = "fan1-presence"; gpios = <&pca0 5 GPIO_ACTIVE_LOW>; linux,code = <5>; }; - fan2-presence { + event-fan2-presence { label = "fan2-presence"; gpios = <&pca0 6 GPIO_ACTIVE_LOW>; linux,code = <6>; }; - fan3-presence { + event-fan3-presence { label = "fan3-presence"; gpios = <&pca0 7 GPIO_ACTIVE_LOW>; linux,code = <7>; diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-vesnin.dts b/arch/arm/boot/dts/aspeed-bmc-opp-vesnin.dts index 328ef472c479..8a7fb55ab489 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-vesnin.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-vesnin.dts @@ -63,13 +63,13 @@ gpio-keys { compatible = "gpio-keys"; - button_checkstop { + event-checkstop { label = "checkstop"; linux,code = <74>; gpios = <&gpio ASPEED_GPIO(P, 5) GPIO_ACTIVE_LOW>; }; - button_identify { + event-identify { label = "identify"; linux,code = <152>; gpios = <&gpio ASPEED_GPIO(O, 7) GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts b/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts index 230f3584bcab..a20a532fc280 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts @@ -51,25 +51,25 @@ gpio-keys { compatible = "gpio-keys"; - air-water { + event-air-water { label = "air-water"; gpios = <&gpio ASPEED_GPIO(B, 5) GPIO_ACTIVE_LOW>; linux,code = <ASPEED_GPIO(B, 5)>; }; - checkstop { + event-checkstop { label = "checkstop"; gpios = <&gpio ASPEED_GPIO(J, 2) GPIO_ACTIVE_LOW>; linux,code = <ASPEED_GPIO(J, 2)>; }; - ps0-presence { + event-ps0-presence { label = "ps0-presence"; gpios = <&gpio ASPEED_GPIO(P, 7) GPIO_ACTIVE_LOW>; linux,code = <ASPEED_GPIO(P, 7)>; }; - ps1-presence { + event-ps1-presence { label = "ps1-presence"; gpios = <&gpio ASPEED_GPIO(N, 0) GPIO_ACTIVE_LOW>; linux,code = <ASPEED_GPIO(N, 0)>; @@ -85,25 +85,25 @@ compatible = "gpio-keys-polled"; poll-interval = <1000>; - fan0-presence { + event-fan0-presence { label = "fan0-presence"; gpios = <&pca0 4 GPIO_ACTIVE_LOW>; linux,code = <4>; }; - fan1-presence { + event-fan1-presence { label = "fan1-presence"; gpios = <&pca0 5 GPIO_ACTIVE_LOW>; linux,code = <5>; }; - fan2-presence { + event-fan2-presence { label = "fan2-presence"; gpios = <&pca0 6 GPIO_ACTIVE_LOW>; linux,code = <6>; }; - fan3-presence { + event-fan3-presence { label = "fan3-presence"; gpios = <&pca0 7 GPIO_ACTIVE_LOW>; linux,code = <7>; diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts b/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts index 7ae4ea0d2931..0cb7b20ff3ab 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts @@ -58,13 +58,13 @@ gpio-keys { compatible = "gpio-keys"; - checkstop { + event-checkstop { label = "checkstop"; gpios = <&gpio ASPEED_GPIO(F, 7) GPIO_ACTIVE_LOW>; linux,code = <ASPEED_GPIO(F, 7)>; }; - pcie-e2b-present{ + event-pcie-e2b-present{ label = "pcie-e2b-present"; gpios = <&gpio ASPEED_GPIO(E, 7) GPIO_ACTIVE_LOW>; linux,code = <ASPEED_GPIO(E, 7)>; diff --git a/arch/arm/boot/dts/aspeed-bmc-portwell-neptune.dts b/arch/arm/boot/dts/aspeed-bmc-portwell-neptune.dts index 61bc74b423cf..a5e64ccc2b3a 100644 --- a/arch/arm/boot/dts/aspeed-bmc-portwell-neptune.dts +++ b/arch/arm/boot/dts/aspeed-bmc-portwell-neptune.dts @@ -24,17 +24,17 @@ leds { compatible = "gpio-leds"; postcode0 { - label="BMC_UP"; + label = "BMC_UP"; gpios = <&gpio ASPEED_GPIO(H, 0) GPIO_ACTIVE_HIGH>; default-state = "on"; }; postcode1 { - label="BMC_HB"; + label = "BMC_HB"; gpios = <&gpio ASPEED_GPIO(H, 1) GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; postcode2 { - label="FAULT"; + label = "FAULT"; gpios = <&gpio ASPEED_GPIO(H, 2) GPIO_ACTIVE_HIGH>; }; // postcode3-7 are GPIOH3-H7 diff --git a/arch/arm/boot/dts/aspeed-bmc-quanta-s6q.dts b/arch/arm/boot/dts/aspeed-bmc-quanta-s6q.dts index 69e1bd256271..46cbba6305b8 100644 --- a/arch/arm/boot/dts/aspeed-bmc-quanta-s6q.dts +++ b/arch/arm/boot/dts/aspeed-bmc-quanta-s6q.dts @@ -65,19 +65,19 @@ compatible = "gpio-leds"; BMC_HEARTBEAT_N { - label="BMC_HEARTBEAT_N"; + label = "BMC_HEARTBEAT_N"; gpios = <&gpio0 ASPEED_GPIO(P, 7) GPIO_ACTIVE_LOW>; linux,default-trigger = "heartbeat"; }; BMC_LED_STATUS_AMBER_N { - label="BMC_LED_STATUS_AMBER_N"; + label = "BMC_LED_STATUS_AMBER_N"; gpios = <&gpio0 ASPEED_GPIO(S, 6) GPIO_ACTIVE_LOW>; default-state = "off"; }; FM_ID_LED_N { - label="FM_ID_LED_N"; + label = "FM_ID_LED_N"; gpios = <&gpio0 ASPEED_GPIO(B, 5) GPIO_ACTIVE_LOW>; default-state = "off"; }; diff --git a/arch/arm/boot/dts/at91-foxg20.dts b/arch/arm/boot/dts/at91-foxg20.dts index 7edf057047f8..9dfd5de808d1 100644 --- a/arch/arm/boot/dts/at91-foxg20.dts +++ b/arch/arm/boot/dts/at91-foxg20.dts @@ -155,10 +155,10 @@ }; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; - btn { + button { label = "Button"; gpios = <&pioC 4 GPIO_ACTIVE_LOW>; linux,code = <0x103>; diff --git a/arch/arm/boot/dts/at91-gatwick.dts b/arch/arm/boot/dts/at91-gatwick.dts index 5a81cab5fc3a..2c718cf84d7b 100644 --- a/arch/arm/boot/dts/at91-gatwick.dts +++ b/arch/arm/boot/dts/at91-gatwick.dts @@ -13,7 +13,7 @@ model = "Laird Workgroup Bridge 50N - Project Gatwick"; compatible = "laird,gatwick", "laird,wb50n", "atmel,sama5d31", "atmel,sama5d3", "atmel,sama5"; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; autorepeat; diff --git a/arch/arm/boot/dts/at91-kizbox.dts b/arch/arm/boot/dts/at91-kizbox.dts index 3b8812fcd854..307663b4eec2 100644 --- a/arch/arm/boot/dts/at91-kizbox.dts +++ b/arch/arm/boot/dts/at91-kizbox.dts @@ -28,19 +28,17 @@ }; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - reset { + button-reset { label = "PB_RST"; gpios = <&pioB 30 GPIO_ACTIVE_HIGH>; linux,code = <0x100>; wakeup-source; }; - user { + button-user { label = "PB_USER"; gpios = <&pioB 31 GPIO_ACTIVE_HIGH>; linux,code = <0x101>; diff --git a/arch/arm/boot/dts/at91-kizbox2-common.dtsi b/arch/arm/boot/dts/at91-kizbox2-common.dtsi index c08834ddf07b..e5e21dff882f 100644 --- a/arch/arm/boot/dts/at91-kizbox2-common.dtsi +++ b/arch/arm/boot/dts/at91-kizbox2-common.dtsi @@ -31,26 +31,24 @@ }; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - prog { + button-prog { label = "PB_PROG"; gpios = <&pioE 27 GPIO_ACTIVE_LOW>; linux,code = <0x102>; wakeup-source; }; - reset { + button-reset { label = "PB_RST"; gpios = <&pioE 29 GPIO_ACTIVE_LOW>; linux,code = <0x100>; wakeup-source; }; - user { + button-user { label = "PB_USER"; gpios = <&pioE 31 GPIO_ACTIVE_HIGH>; linux,code = <0x101>; diff --git a/arch/arm/boot/dts/at91-kizbox3-hs.dts b/arch/arm/boot/dts/at91-kizbox3-hs.dts index 2799b2a1f4d2..7075df6549e9 100644 --- a/arch/arm/boot/dts/at91-kizbox3-hs.dts +++ b/arch/arm/boot/dts/at91-kizbox3-hs.dts @@ -55,7 +55,7 @@ }; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; pinctrl-names = "default" , "default", "default", "default", "default" ; @@ -68,35 +68,35 @@ &pinctrl_pio_zbe_rst>; pinctrl-4 = <&pinctrl_pio_input>; - SW1 { + switch-1 { label = "SW1"; gpios = <&pioA PIN_PA29 GPIO_ACTIVE_LOW>; linux,code = <0x101>; wakeup-source; }; - SW2 { + switch-2 { label = "SW2"; gpios = <&pioA PIN_PA18 GPIO_ACTIVE_LOW>; linux,code = <0x102>; wakeup-source; }; - SW3 { + switch-3 { label = "SW3"; gpios = <&pioA PIN_PA22 GPIO_ACTIVE_LOW>; linux,code = <0x103>; wakeup-source; }; - SW7 { + switch-7 { label = "SW7"; gpios = <&pioA PIN_PA26 GPIO_ACTIVE_LOW>; linux,code = <0x107>; wakeup-source; }; - SW8 { + switch-8 { label = "SW8"; gpios = <&pioA PIN_PA24 GPIO_ACTIVE_LOW>; linux,code = <0x108>; @@ -186,7 +186,7 @@ &pioA { pinctrl_key_gpio_default: key_gpio_default { - pinmux= <PIN_PA22__GPIO>, + pinmux = <PIN_PA22__GPIO>, <PIN_PA24__GPIO>, <PIN_PA26__GPIO>, <PIN_PA29__GPIO>, diff --git a/arch/arm/boot/dts/at91-kizboxmini-common.dtsi b/arch/arm/boot/dts/at91-kizboxmini-common.dtsi index 9c622892c692..42640fe6b6d0 100644 --- a/arch/arm/boot/dts/at91-kizboxmini-common.dtsi +++ b/arch/arm/boot/dts/at91-kizboxmini-common.dtsi @@ -36,17 +36,15 @@ gpio_keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - prog { + key-prog { label = "PB_PROG"; gpios = <&pioC 17 GPIO_ACTIVE_LOW>; linux,code = <0x102>; wakeup-source; }; - reset { + key-reset { label = "PB_RST"; gpios = <&pioC 16 GPIO_ACTIVE_LOW>; linux,code = <0x100>; diff --git a/arch/arm/boot/dts/at91-nattis-2-natte-2.dts b/arch/arm/boot/dts/at91-nattis-2-natte-2.dts index 4f123477e631..f71377c9b757 100644 --- a/arch/arm/boot/dts/at91-nattis-2-natte-2.dts +++ b/arch/arm/boot/dts/at91-nattis-2-natte-2.dts @@ -18,7 +18,7 @@ gpio-keys { compatible = "gpio-keys"; - wakeup { + key-wakeup { label = "Wakeup"; linux,code = <10>; wakeup-source; diff --git a/arch/arm/boot/dts/at91-qil_a9260.dts b/arch/arm/boot/dts/at91-qil_a9260.dts index 969d990767fc..9d26f9996348 100644 --- a/arch/arm/boot/dts/at91-qil_a9260.dts +++ b/arch/arm/boot/dts/at91-qil_a9260.dts @@ -198,10 +198,8 @@ gpio_keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - user_pb { + button-user { label = "user_pb"; gpios = <&pioB 10 GPIO_ACTIVE_LOW>; linux,code = <28>; diff --git a/arch/arm/boot/dts/at91-sam9x60ek.dts b/arch/arm/boot/dts/at91-sam9x60ek.dts index 81ccb0636a00..81c38e101f58 100644 --- a/arch/arm/boot/dts/at91-sam9x60ek.dts +++ b/arch/arm/boot/dts/at91-sam9x60ek.dts @@ -76,16 +76,15 @@ }; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_key_gpio_default>; - status = "okay"; - sw1 { + button-1 { label = "SW1"; gpios = <&pioD 18 GPIO_ACTIVE_LOW>; - linux,code=<KEY_PROG1>; + linux,code = <KEY_PROG1>; wakeup-source; }; }; diff --git a/arch/arm/boot/dts/at91-sama5d27_som1.dtsi b/arch/arm/boot/dts/at91-sama5d27_som1.dtsi index a4623cc67cc1..8aa9e8dea337 100644 --- a/arch/arm/boot/dts/at91-sama5d27_som1.dtsi +++ b/arch/arm/boot/dts/at91-sama5d27_som1.dtsi @@ -15,7 +15,7 @@ compatible = "atmel,sama5d27-som1", "atmel,sama5d27", "atmel,sama5d2", "atmel,sama5"; aliases { - i2c0 = &i2c0; + i2c0 = &i2c0; }; clocks { @@ -83,6 +83,8 @@ macb0: ethernet@f8008000 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_macb0_default>; + #address-cells = <1>; + #size-cells = <0>; phy-mode = "rmii"; ethernet-phy@7 { diff --git a/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts b/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts index 08f0d4b995ff..0dc6ca377b0c 100644 --- a/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts +++ b/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts @@ -21,8 +21,8 @@ serial0 = &uart1; /* DBGU */ serial1 = &uart4; /* mikro BUS 1 */ serial2 = &uart2; /* mikro BUS 2 */ - i2c1 = &i2c1; - i2c2 = &i2c3; + i2c1 = &i2c1; + i2c2 = &i2c3; }; chosen { @@ -478,13 +478,13 @@ }; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_key_gpio_default>; - pb4 { + button { label = "USER"; gpios = <&pioA PIN_PA29 GPIO_ACTIVE_LOW>; linux,code = <KEY_PROG1>; diff --git a/arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi b/arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi index ba621783acdb..76b2025c67b4 100644 --- a/arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi +++ b/arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi @@ -194,6 +194,8 @@ &macb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_macb0_default>; + #address-cells = <1>; + #size-cells = <0>; phy-mode = "rmii"; ethernet-phy@0 { diff --git a/arch/arm/boot/dts/at91-sama5d27_wlsom1_ek.dts b/arch/arm/boot/dts/at91-sama5d27_wlsom1_ek.dts index 5e8755f22784..b665ddc6b0de 100644 --- a/arch/arm/boot/dts/at91-sama5d27_wlsom1_ek.dts +++ b/arch/arm/boot/dts/at91-sama5d27_wlsom1_ek.dts @@ -19,21 +19,20 @@ serial1 = &uart6; /* BT */ serial2 = &uart5; /* mikro BUS 2 */ serial3 = &uart3; /* mikro BUS 1 */ - i2c1 = &i2c1; + i2c1 = &i2c1; }; chosen { stdout-path = "serial0:115200n8"; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_key_gpio_default>; - status = "okay"; - sw4 { + button-1 { label = "USER BUTTON"; gpios = <&pioA PIN_PB2 GPIO_ACTIVE_LOW>; linux,code = <KEY_PROG1>; diff --git a/arch/arm/boot/dts/at91-sama5d2_icp.dts b/arch/arm/boot/dts/at91-sama5d2_icp.dts index 164201a8fbf2..6865be8d7787 100644 --- a/arch/arm/boot/dts/at91-sama5d2_icp.dts +++ b/arch/arm/boot/dts/at91-sama5d2_icp.dts @@ -24,8 +24,8 @@ serial1 = &uart1; /* mikro BUS 3 */ serial3 = &uart3; /* mikro BUS 2 */ serial5 = &uart7; /* flx2 */ - i2c0 = &i2c0; - i2c1 = &i2c1; + i2c0 = &i2c0; + i2c1 = &i2c1; }; chosen { @@ -42,14 +42,13 @@ }; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_key_gpio_default>; - status = "okay"; - sw4 { + button-1 { label = "USER_PB1"; gpios = <&pioA PIN_PD0 GPIO_ACTIVE_LOW>; linux,code = <KEY_PROG1>; diff --git a/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts b/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts index 8ed58af01391..76a711b167b0 100644 --- a/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts +++ b/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts @@ -20,9 +20,9 @@ aliases { serial0 = &uart0; /* DBGU */ - i2c0 = &i2c0; /* mikroBUS 1 */ - i2c1 = &i2c1; /* XPRO EXT1 */ - i2c2 = &i2c2; + i2c0 = &i2c0; /* mikroBUS 1 */ + i2c1 = &i2c1; /* XPRO EXT1 */ + i2c2 = &i2c2; }; chosen { @@ -139,6 +139,8 @@ macb0: ethernet@f8008000 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_macb0_default &pinctrl_macb0_phy_irq>; + #address-cells = <1>; + #size-cells = <0>; phy-mode = "rmii"; status = "okay"; @@ -394,13 +396,13 @@ }; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_key_gpio_default>; - bp1 { + button-1 { label = "PB_USER"; gpios = <&pioA PIN_PA10 GPIO_ACTIVE_LOW>; linux,code = <KEY_PROG1>; diff --git a/arch/arm/boot/dts/at91-sama5d2_xplained.dts b/arch/arm/boot/dts/at91-sama5d2_xplained.dts index cdfe891f9a9e..85949c24b687 100644 --- a/arch/arm/boot/dts/at91-sama5d2_xplained.dts +++ b/arch/arm/boot/dts/at91-sama5d2_xplained.dts @@ -147,6 +147,8 @@ macb0: ethernet@f8008000 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_macb0_default &pinctrl_macb0_phy_irq>; + #address-cells = <1>; + #size-cells = <0>; phy-mode = "rmii"; status = "okay"; @@ -205,10 +207,10 @@ regulator-state-mem { regulator-on-in-suspend; - regulator-suspend-min-microvolt=<1400000>; - regulator-suspend-max-microvolt=<1400000>; + regulator-suspend-min-microvolt = <1400000>; + regulator-suspend-max-microvolt = <1400000>; regulator-changeable-in-suspend; - regulator-mode=<ACT8945A_REGULATOR_MODE_LOWPOWER>; + regulator-mode = <ACT8945A_REGULATOR_MODE_LOWPOWER>; }; }; @@ -703,13 +705,13 @@ }; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_key_gpio_default>; - bp1 { + button { label = "PB_USER"; gpios = <&pioA PIN_PB9 GPIO_ACTIVE_LOW>; linux,code = <KEY_PROG1>; diff --git a/arch/arm/boot/dts/at91-sama5d3_xplained.dts b/arch/arm/boot/dts/at91-sama5d3_xplained.dts index a49c2966b41e..1f42a6a981bf 100644 --- a/arch/arm/boot/dts/at91-sama5d3_xplained.dts +++ b/arch/arm/boot/dts/at91-sama5d3_xplained.dts @@ -372,13 +372,13 @@ regulator-always-on; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_key_gpio>; - bp3 { + button { label = "PB_USER"; gpios = <&pioE 29 GPIO_ACTIVE_LOW>; linux,code = <KEY_PROG1>; diff --git a/arch/arm/boot/dts/at91-sama5d4_xplained.dts b/arch/arm/boot/dts/at91-sama5d4_xplained.dts index e519d2747936..f122f302f8e0 100644 --- a/arch/arm/boot/dts/at91-sama5d4_xplained.dts +++ b/arch/arm/boot/dts/at91-sama5d4_xplained.dts @@ -242,13 +242,13 @@ }; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_key_gpio>; - pb_user1 { + button { label = "pb_user1"; gpios = <&pioE 8 GPIO_ACTIVE_HIGH>; linux,code = <KEY_PROG1>; diff --git a/arch/arm/boot/dts/at91-sama5d4ek.dts b/arch/arm/boot/dts/at91-sama5d4ek.dts index 7017f626f362..fce4e93c6bee 100644 --- a/arch/arm/boot/dts/at91-sama5d4ek.dts +++ b/arch/arm/boot/dts/at91-sama5d4ek.dts @@ -269,13 +269,13 @@ }; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_key_gpio>; - pb_user1 { + button { label = "pb_user1"; gpios = <&pioE 13 GPIO_ACTIVE_HIGH>; linux,code = <0x100>; diff --git a/arch/arm/boot/dts/at91-sama7g5ek.dts b/arch/arm/boot/dts/at91-sama7g5ek.dts index 103544620fd7..de44da2e4aae 100644 --- a/arch/arm/boot/dts/at91-sama7g5ek.dts +++ b/arch/arm/boot/dts/at91-sama7g5ek.dts @@ -45,13 +45,13 @@ }; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_key_gpio_default>; - bp1 { + button { label = "PB_USER"; gpios = <&pioA PIN_PA12 GPIO_ACTIVE_LOW>; linux,code = <KEY_PROG1>; diff --git a/arch/arm/boot/dts/at91-wb45n.dts b/arch/arm/boot/dts/at91-wb45n.dts index 54d130c92185..ef73f727f7bd 100644 --- a/arch/arm/boot/dts/at91-wb45n.dts +++ b/arch/arm/boot/dts/at91-wb45n.dts @@ -12,13 +12,10 @@ model = "Laird Workgroup Bridge 45N - Atmel AT91SAM (dt)"; compatible = "laird,wb45n", "laird,wbxx", "atmel,at91sam9x5", "atmel,at91sam9"; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - irqbtn@18 { - reg = <18>; + button { label = "IRQBTN"; linux,code = <99>; gpios = <&pioB 18 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/at91-wb50n.dts b/arch/arm/boot/dts/at91-wb50n.dts index 89f0f717f7ed..ec2becf6133b 100644 --- a/arch/arm/boot/dts/at91-wb50n.dts +++ b/arch/arm/boot/dts/at91-wb50n.dts @@ -13,21 +13,17 @@ model = "Laird Workgroup Bridge 50N - Atmel SAMA5D"; compatible = "laird,wb50n", "atmel,sama5d31", "atmel,sama5d3", "atmel,sama5"; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - btn0@10 { - reg = <10>; + button-0 { label = "BTNESC"; linux,code = <1>; /* ESC button */ gpios = <&pioA 10 GPIO_ACTIVE_LOW>; wakeup-source; }; - irqbtn@31 { - reg = <31>; + button-1 { label = "IRQBTN"; linux,code = <99>; /* SysReq button */ gpios = <&pioE 31 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi index 7368347c9357..9d9820db9482 100644 --- a/arch/arm/boot/dts/at91sam9260.dtsi +++ b/arch/arm/boot/dts/at91sam9260.dtsi @@ -123,7 +123,7 @@ clock-names = "slow_xtal", "main_xtal"; }; - rstc@fffffd00 { + reset-controller@fffffd00 { compatible = "atmel,at91sam9260-rstc"; reg = <0xfffffd00 0x10>; clocks = <&pmc PMC_TYPE_CORE PMC_SLOW>; diff --git a/arch/arm/boot/dts/at91sam9260ek.dts b/arch/arm/boot/dts/at91sam9260ek.dts index 6381088ba24f..bb72f050a4fe 100644 --- a/arch/arm/boot/dts/at91sam9260ek.dts +++ b/arch/arm/boot/dts/at91sam9260ek.dts @@ -144,17 +144,17 @@ }; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; - btn3 { + button-3 { label = "Button 3"; gpios = <&pioA 30 GPIO_ACTIVE_LOW>; linux,code = <0x103>; wakeup-source; }; - btn4 { + button-4 { label = "Button 4"; gpios = <&pioA 31 GPIO_ACTIVE_LOW>; linux,code = <KEY_PROG1>; diff --git a/arch/arm/boot/dts/at91sam9261.dtsi b/arch/arm/boot/dts/at91sam9261.dtsi index 7adc36ca8a46..259aca565305 100644 --- a/arch/arm/boot/dts/at91sam9261.dtsi +++ b/arch/arm/boot/dts/at91sam9261.dtsi @@ -603,7 +603,7 @@ clock-names = "slow_xtal", "main_xtal"; }; - rstc@fffffd00 { + reset-controller@fffffd00 { compatible = "atmel,at91sam9260-rstc"; reg = <0xfffffd00 0x10>; clocks = <&slow_xtal>; diff --git a/arch/arm/boot/dts/at91sam9261ek.dts b/arch/arm/boot/dts/at91sam9261ek.dts index 6fb4fe49cf1c..88869ca874d1 100644 --- a/arch/arm/boot/dts/at91sam9261ek.dts +++ b/arch/arm/boot/dts/at91sam9261ek.dts @@ -211,31 +211,31 @@ }; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; - button_0 { + button-0 { label = "button_0"; gpios = <&pioA 27 GPIO_ACTIVE_LOW>; linux,code = <256>; wakeup-source; }; - button_1 { + button-1 { label = "button_1"; gpios = <&pioA 26 GPIO_ACTIVE_LOW>; linux,code = <257>; wakeup-source; }; - button_2 { + button-2 { label = "button_2"; gpios = <&pioA 25 GPIO_ACTIVE_LOW>; linux,code = <258>; wakeup-source; }; - button_3 { + button-3 { label = "button_3"; gpios = <&pioA 24 GPIO_ACTIVE_LOW>; linux,code = <259>; diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi index fe45d96239c9..c080df8c2312 100644 --- a/arch/arm/boot/dts/at91sam9263.dtsi +++ b/arch/arm/boot/dts/at91sam9263.dtsi @@ -151,7 +151,7 @@ clock-names = "t0_clk", "slow_clk"; }; - rstc@fffffd00 { + reset-controller@fffffd00 { compatible = "atmel,at91sam9260-rstc"; reg = <0xfffffd00 0x10>; clocks = <&slow_xtal>; diff --git a/arch/arm/boot/dts/at91sam9263ek.dts b/arch/arm/boot/dts/at91sam9263ek.dts index e732565913a4..ce8baff6a9f4 100644 --- a/arch/arm/boot/dts/at91sam9263ek.dts +++ b/arch/arm/boot/dts/at91sam9263ek.dts @@ -232,17 +232,17 @@ }; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; - left_click { + button-left-click { label = "left_click"; gpios = <&pioC 5 GPIO_ACTIVE_LOW>; linux,code = <272>; wakeup-source; }; - right_click { + button-right-click { label = "right_click"; gpios = <&pioC 4 GPIO_ACTIVE_LOW>; linux,code = <273>; diff --git a/arch/arm/boot/dts/at91sam9g20ek_common.dtsi b/arch/arm/boot/dts/at91sam9g20ek_common.dtsi index 85c17dd1c8d5..60d61291f344 100644 --- a/arch/arm/boot/dts/at91sam9g20ek_common.dtsi +++ b/arch/arm/boot/dts/at91sam9g20ek_common.dtsi @@ -234,17 +234,17 @@ }; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; - btn3 { + button-3 { label = "Button 3"; gpios = <&pioA 30 GPIO_ACTIVE_LOW>; linux,code = <0x103>; wakeup-source; }; - btn4 { + button-4 { label = "Button 4"; gpios = <&pioA 31 GPIO_ACTIVE_LOW>; linux,code = <KEY_PROG1>; diff --git a/arch/arm/boot/dts/at91sam9g25-gardena-smart-gateway.dts b/arch/arm/boot/dts/at91sam9g25-gardena-smart-gateway.dts index 7da70aeeb528..92f2c05c873f 100644 --- a/arch/arm/boot/dts/at91sam9g25-gardena-smart-gateway.dts +++ b/arch/arm/boot/dts/at91sam9g25-gardena-smart-gateway.dts @@ -23,7 +23,7 @@ gpio-keys { compatible = "gpio-keys"; - user_btn1 { + button { label = "USER_BTN1"; gpios = <&pioA 24 GPIO_ACTIVE_LOW>; linux,code = <KEY_PROG1>; diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi index 2ab730fd6472..09794561c7ce 100644 --- a/arch/arm/boot/dts/at91sam9g45.dtsi +++ b/arch/arm/boot/dts/at91sam9g45.dtsi @@ -137,7 +137,7 @@ clock-names = "slow_clk", "main_xtal"; }; - rstc@fffffd00 { + reset-controller@fffffd00 { compatible = "atmel,at91sam9g45-rstc"; reg = <0xfffffd00 0x10>; clocks = <&clk32k>; diff --git a/arch/arm/boot/dts/at91sam9m10g45ek.dts b/arch/arm/boot/dts/at91sam9m10g45ek.dts index e5db198a87a8..7f45e81ca165 100644 --- a/arch/arm/boot/dts/at91sam9m10g45ek.dts +++ b/arch/arm/boot/dts/at91sam9m10g45ek.dts @@ -343,48 +343,48 @@ }; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; - left_click { + button-left-click { label = "left_click"; gpios = <&pioB 6 GPIO_ACTIVE_LOW>; linux,code = <272>; wakeup-source; }; - right_click { + button-right-click { label = "right_click"; gpios = <&pioB 7 GPIO_ACTIVE_LOW>; linux,code = <273>; wakeup-source; }; - left { + button-left { label = "Joystick Left"; gpios = <&pioB 14 GPIO_ACTIVE_LOW>; linux,code = <105>; }; - right { + button-right { label = "Joystick Right"; gpios = <&pioB 15 GPIO_ACTIVE_LOW>; linux,code = <106>; }; - up { + button-up { label = "Joystick Up"; gpios = <&pioB 16 GPIO_ACTIVE_LOW>; linux,code = <103>; }; - down { + button-down { label = "Joystick Down"; gpios = <&pioB 17 GPIO_ACTIVE_LOW>; linux,code = <108>; }; - enter { + button-enter { label = "Joystick Press"; gpios = <&pioB 18 GPIO_ACTIVE_LOW>; linux,code = <28>; diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi index 0785389f5507..556f35ce49e3 100644 --- a/arch/arm/boot/dts/at91sam9n12.dtsi +++ b/arch/arm/boot/dts/at91sam9n12.dtsi @@ -126,7 +126,7 @@ interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; }; - rstc@fffffe00 { + reset-controller@fffffe00 { compatible = "atmel,at91sam9g45-rstc"; reg = <0xfffffe00 0x10>; clocks = <&clk32k>; diff --git a/arch/arm/boot/dts/at91sam9n12ek.dts b/arch/arm/boot/dts/at91sam9n12ek.dts index c905d7bfc771..4c644d4c6be7 100644 --- a/arch/arm/boot/dts/at91sam9n12ek.dts +++ b/arch/arm/boot/dts/at91sam9n12ek.dts @@ -226,10 +226,10 @@ }; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; - enter { + button-enter { label = "Enter"; gpios = <&pioB 3 GPIO_ACTIVE_LOW>; linux,code = <28>; diff --git a/arch/arm/boot/dts/at91sam9rl.dtsi b/arch/arm/boot/dts/at91sam9rl.dtsi index 730d1182c73e..12c634811820 100644 --- a/arch/arm/boot/dts/at91sam9rl.dtsi +++ b/arch/arm/boot/dts/at91sam9rl.dtsi @@ -766,7 +766,7 @@ clock-names = "slow_clk", "main_xtal"; }; - rstc@fffffd00 { + reset-controller@fffffd00 { compatible = "atmel,at91sam9260-rstc"; reg = <0xfffffd00 0x10>; clocks = <&clk32k>; diff --git a/arch/arm/boot/dts/at91sam9rlek.dts b/arch/arm/boot/dts/at91sam9rlek.dts index ddaadfec6751..a57351270551 100644 --- a/arch/arm/boot/dts/at91sam9rlek.dts +++ b/arch/arm/boot/dts/at91sam9rlek.dts @@ -248,17 +248,17 @@ }; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; - right_click { + button-right-click { label = "right_click"; gpios = <&pioB 0 GPIO_ACTIVE_LOW>; linux,code = <273>; wakeup-source; }; - left_click { + button-left-click { label = "left_click"; gpios = <&pioB 1 GPIO_ACTIVE_LOW>; linux,code = <272>; diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi index 395e883644cd..ea3b11336c79 100644 --- a/arch/arm/boot/dts/at91sam9x5.dtsi +++ b/arch/arm/boot/dts/at91sam9x5.dtsi @@ -134,7 +134,7 @@ clock-names = "slow_clk", "main_xtal"; }; - reset_controller: rstc@fffffe00 { + reset_controller: reset-controller@fffffe00 { compatible = "atmel,at91sam9g45-rstc"; reg = <0xfffffe00 0x10>; clocks = <&clk32k>; diff --git a/arch/arm/boot/dts/axm5516-cpus.dtsi b/arch/arm/boot/dts/axm5516-cpus.dtsi index 3bcf4e0a3c85..f13ef80b6637 100644 --- a/arch/arm/boot/dts/axm5516-cpus.dtsi +++ b/arch/arm/boot/dts/axm5516-cpus.dtsi @@ -73,7 +73,7 @@ device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <0x00>; - clock-frequency= <1400000000>; + clock-frequency = <1400000000>; cpu-release-addr = <0>; // Fixed by the boot loader }; @@ -81,7 +81,7 @@ device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <0x01>; - clock-frequency= <1400000000>; + clock-frequency = <1400000000>; cpu-release-addr = <0>; // Fixed by the boot loader }; @@ -89,7 +89,7 @@ device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <0x02>; - clock-frequency= <1400000000>; + clock-frequency = <1400000000>; cpu-release-addr = <0>; // Fixed by the boot loader }; @@ -97,7 +97,7 @@ device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <0x03>; - clock-frequency= <1400000000>; + clock-frequency = <1400000000>; cpu-release-addr = <0>; // Fixed by the boot loader }; @@ -105,7 +105,7 @@ device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <0x100>; - clock-frequency= <1400000000>; + clock-frequency = <1400000000>; cpu-release-addr = <0>; // Fixed by the boot loader }; @@ -113,7 +113,7 @@ device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <0x101>; - clock-frequency= <1400000000>; + clock-frequency = <1400000000>; cpu-release-addr = <0>; // Fixed by the boot loader }; @@ -121,7 +121,7 @@ device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <0x102>; - clock-frequency= <1400000000>; + clock-frequency = <1400000000>; cpu-release-addr = <0>; // Fixed by the boot loader }; @@ -129,7 +129,7 @@ device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <0x103>; - clock-frequency= <1400000000>; + clock-frequency = <1400000000>; cpu-release-addr = <0>; // Fixed by the boot loader }; @@ -137,7 +137,7 @@ device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <0x200>; - clock-frequency= <1400000000>; + clock-frequency = <1400000000>; cpu-release-addr = <0>; // Fixed by the boot loader }; @@ -145,7 +145,7 @@ device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <0x201>; - clock-frequency= <1400000000>; + clock-frequency = <1400000000>; cpu-release-addr = <0>; // Fixed by the boot loader }; @@ -153,7 +153,7 @@ device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <0x202>; - clock-frequency= <1400000000>; + clock-frequency = <1400000000>; cpu-release-addr = <0>; // Fixed by the boot loader }; @@ -161,7 +161,7 @@ device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <0x203>; - clock-frequency= <1400000000>; + clock-frequency = <1400000000>; cpu-release-addr = <0>; // Fixed by the boot loader }; @@ -169,7 +169,7 @@ device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <0x300>; - clock-frequency= <1400000000>; + clock-frequency = <1400000000>; cpu-release-addr = <0>; // Fixed by the boot loader }; @@ -177,7 +177,7 @@ device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <0x301>; - clock-frequency= <1400000000>; + clock-frequency = <1400000000>; cpu-release-addr = <0>; // Fixed by the boot loader }; @@ -185,7 +185,7 @@ device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <0x302>; - clock-frequency= <1400000000>; + clock-frequency = <1400000000>; cpu-release-addr = <0>; // Fixed by the boot loader }; @@ -193,7 +193,7 @@ device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <0x303>; - clock-frequency= <1400000000>; + clock-frequency = <1400000000>; cpu-release-addr = <0>; // Fixed by the boot loader }; }; diff --git a/arch/arm/boot/dts/bcm2711-rpi.dtsi b/arch/arm/boot/dts/bcm2711-rpi.dtsi index ca266c5d9f9b..98817a6675b9 100644 --- a/arch/arm/boot/dts/bcm2711-rpi.dtsi +++ b/arch/arm/boot/dts/bcm2711-rpi.dtsi @@ -69,6 +69,10 @@ }; }; +&v3d { + clocks = <&firmware_clocks 5>; +}; + &vchiq { interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; }; diff --git a/arch/arm/boot/dts/bcm2711.dtsi b/arch/arm/boot/dts/bcm2711.dtsi index 89af57482bc8..941c4d16791b 100644 --- a/arch/arm/boot/dts/bcm2711.dtsi +++ b/arch/arm/boot/dts/bcm2711.dtsi @@ -107,12 +107,13 @@ }; pm: watchdog@7e100000 { - compatible = "brcm,bcm2835-pm", "brcm,bcm2835-pm-wdt"; + compatible = "brcm,bcm2711-pm", "brcm,bcm2835-pm-wdt"; #power-domain-cells = <1>; #reset-cells = <1>; reg = <0x7e100000 0x114>, <0x7e00a000 0x24>, <0x7ec11000 0x20>; + reg-names = "pm", "asb", "rpivid_asb"; clocks = <&clocks BCM2835_CLOCK_V3D>, <&clocks BCM2835_CLOCK_PERI_IMAGE>, <&clocks BCM2835_CLOCK_H264>, @@ -601,6 +602,17 @@ #size-cells = <0x0>; }; }; + + v3d: gpu@7ec00000 { + compatible = "brcm,2711-v3d"; + reg = <0x0 0x7ec00000 0x4000>, + <0x0 0x7ec04000 0x4000>; + reg-names = "hub", "core0"; + + power-domains = <&pm BCM2835_POWER_DOMAIN_GRAFX_V3D>; + resets = <&pm BCM2835_RESET_V3D>; + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; + }; }; }; diff --git a/arch/arm/boot/dts/bcm28155-ap.dts b/arch/arm/boot/dts/bcm28155-ap.dts index ead6e9804dbf..78465ad37c5f 100644 --- a/arch/arm/boot/dts/bcm28155-ap.dts +++ b/arch/arm/boot/dts/bcm28155-ap.dts @@ -31,22 +31,22 @@ }; i2c@3e016000 { - status="okay"; + status = "okay"; clock-frequency = <400000>; }; i2c@3e017000 { - status="okay"; + status = "okay"; clock-frequency = <400000>; }; i2c@3e018000 { - status="okay"; + status = "okay"; clock-frequency = <400000>; }; i2c@3500d000 { - status="okay"; + status = "okay"; clock-frequency = <100000>; pmu: pmu@8 { diff --git a/arch/arm/boot/dts/bcm2835-common.dtsi b/arch/arm/boot/dts/bcm2835-common.dtsi index c25e797b9060..a037d2bc5b11 100644 --- a/arch/arm/boot/dts/bcm2835-common.dtsi +++ b/arch/arm/boot/dts/bcm2835-common.dtsi @@ -62,6 +62,7 @@ #reset-cells = <1>; reg = <0x7e100000 0x114>, <0x7e00a000 0x24>; + reg-names = "pm", "asb"; clocks = <&clocks BCM2835_CLOCK_V3D>, <&clocks BCM2835_CLOCK_PERI_IMAGE>, <&clocks BCM2835_CLOCK_H264>, diff --git a/arch/arm/boot/dts/bcm283x.dtsi b/arch/arm/boot/dts/bcm283x.dtsi index c113661a6668..d2d9c6e67f39 100644 --- a/arch/arm/boot/dts/bcm283x.dtsi +++ b/arch/arm/boot/dts/bcm283x.dtsi @@ -50,9 +50,9 @@ trips { cpu-crit { - temperature = <90000>; - hysteresis = <0>; - type = "critical"; + temperature = <90000>; + hysteresis = <0>; + type = "critical"; }; }; @@ -352,8 +352,6 @@ clocks = <&clocks BCM2835_CLOCK_VPU>, <&clocks BCM2835_CLOCK_DPI>; clock-names = "core", "pixel"; - #address-cells = <1>; - #size-cells = <0>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dts b/arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dts index 8ed403767540..09ee3e46c0cc 100644 --- a/arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dts +++ b/arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dts @@ -70,19 +70,19 @@ gpio-keys { compatible = "gpio-keys"; - rfkill { + button-rfkill { label = "WiFi"; linux,code = <KEY_RFKILL>; gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>; }; - restart { + button-restart { label = "Reset"; linux,code = <KEY_RESTART>; gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; }; - wps { + button-wps { label = "WPS"; linux,code = <KEY_WPS_BUTTON>; gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/bcm4708-asus-rt-ac68u.dts b/arch/arm/boot/dts/bcm4708-asus-rt-ac68u.dts index 667b118ba4ee..32619c6045d3 100644 --- a/arch/arm/boot/dts/bcm4708-asus-rt-ac68u.dts +++ b/arch/arm/boot/dts/bcm4708-asus-rt-ac68u.dts @@ -54,25 +54,25 @@ gpio-keys { compatible = "gpio-keys"; - brightness { + button-brightness { label = "Backlight"; linux,code = <KEY_BRIGHTNESS_ZERO>; gpios = <&chipcommon 5 GPIO_ACTIVE_LOW>; }; - wps { + button-wps { label = "WPS"; linux,code = <KEY_WPS_BUTTON>; gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>; }; - restart { + button-restart { label = "Reset"; linux,code = <KEY_RESTART>; gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; }; - rfkill { + button-rfkill { label = "WiFi"; linux,code = <KEY_RFKILL>; gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/bcm4708-buffalo-wzr-1166dhp-common.dtsi b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1166dhp-common.dtsi index d659e409a17e..a658b9b7bcec 100644 --- a/arch/arm/boot/dts/bcm4708-buffalo-wzr-1166dhp-common.dtsi +++ b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1166dhp-common.dtsi @@ -104,33 +104,33 @@ gpio-keys { compatible = "gpio-keys"; - restart { + button-restart { label = "Reset"; linux,code = <KEY_RESTART>; gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; }; - aoss { + button-aoss { label = "AOSS"; linux,code = <KEY_WPS_BUTTON>; gpios = <&chipcommon 12 GPIO_ACTIVE_LOW>; }; /* Commit mode set by switch? */ - mode { + button-mode { label = "Mode"; linux,code = <KEY_SETUP>; gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>; }; /* Switch: AP mode */ - sw_ap { + button-sw-ap { label = "AP"; linux,code = <BTN_0>; gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>; }; - eject { + button-eject { label = "USB eject"; linux,code = <KEY_EJECTCD>; gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts index ff31ce45831a..f8f53457dd43 100644 --- a/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts +++ b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts @@ -100,33 +100,33 @@ gpio-keys { compatible = "gpio-keys"; - restart { + button-restart { label = "Reset"; linux,code = <KEY_RESTART>; gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; }; - aoss { + button-aoss { label = "AOSS"; linux,code = <KEY_WPS_BUTTON>; gpios = <&chipcommon 12 GPIO_ACTIVE_LOW>; }; /* Commit mode set by switch? */ - mode { + button-mode { label = "Mode"; linux,code = <KEY_SETUP>; gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>; }; /* Switch: AP mode */ - sw_ap { + button-sw-ap { label = "AP"; linux,code = <BTN_0>; gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>; }; - eject { + button-eject { label = "USB eject"; linux,code = <KEY_EJECTCD>; gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/bcm4708-linksys-ea6300-v1.dts b/arch/arm/boot/dts/bcm4708-linksys-ea6300-v1.dts index 5bac1e15775a..0ed25bf71f0d 100644 --- a/arch/arm/boot/dts/bcm4708-linksys-ea6300-v1.dts +++ b/arch/arm/boot/dts/bcm4708-linksys-ea6300-v1.dts @@ -29,13 +29,13 @@ gpio-keys { compatible = "gpio-keys"; - wps { + button-wps { label = "WPS"; linux,code = <KEY_WPS_BUTTON>; gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>; }; - restart { + button-restart { label = "Reset"; linux,code = <KEY_RESTART>; gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/bcm4708-linksys-ea6500-v2.dts b/arch/arm/boot/dts/bcm4708-linksys-ea6500-v2.dts index cd797b4202ad..f1412ba83def 100644 --- a/arch/arm/boot/dts/bcm4708-linksys-ea6500-v2.dts +++ b/arch/arm/boot/dts/bcm4708-linksys-ea6500-v2.dts @@ -25,13 +25,13 @@ gpio-keys { compatible = "gpio-keys"; - wps { + button-wps { label = "WPS"; linux,code = <KEY_WPS_BUTTON>; gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>; }; - restart { + button-restart { label = "Reset"; linux,code = <KEY_RESTART>; gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts b/arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts index 5b4a481be4f4..14ee410183af 100644 --- a/arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts +++ b/arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts @@ -45,7 +45,7 @@ gpio-keys { compatible = "gpio-keys"; - restart { + button-restart { label = "Reset"; linux,code = <KEY_RESTART>; gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts b/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts index c81944cd6d0b..600ab087f5e5 100644 --- a/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts +++ b/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts @@ -52,7 +52,7 @@ gpio-keys { compatible = "gpio-keys"; - restart { + button-restart { label = "Reset"; linux,code = <KEY_RESTART>; gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/bcm4708-netgear-r6250.dts b/arch/arm/boot/dts/bcm4708-netgear-r6250.dts index 43a5d675dd67..fd6d8d2a4456 100644 --- a/arch/arm/boot/dts/bcm4708-netgear-r6250.dts +++ b/arch/arm/boot/dts/bcm4708-netgear-r6250.dts @@ -63,19 +63,19 @@ gpio-keys { compatible = "gpio-keys"; - wps { + button-wps { label = "WPS"; linux,code = <KEY_WPS_BUTTON>; gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>; }; - rfkill { + button-rfkill { label = "WiFi"; linux,code = <KEY_RFKILL>; gpios = <&chipcommon 5 GPIO_ACTIVE_LOW>; }; - restart { + button-restart { label = "Reset"; linux,code = <KEY_RESTART>; gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts b/arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts index 4c60eda296d9..76fc1099d47d 100644 --- a/arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts +++ b/arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts @@ -59,19 +59,19 @@ gpio-keys { compatible = "gpio-keys"; - wps { + button-wps { label = "WPS"; linux,code = <KEY_WPS_BUTTON>; gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>; }; - rfkill { + button-rfkill { label = "WiFi"; linux,code = <KEY_RFKILL>; gpios = <&chipcommon 5 GPIO_ACTIVE_LOW>; }; - restart { + button-restart { label = "Reset"; linux,code = <KEY_RESTART>; gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts b/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts index 9ca6d1b2590d..6bcdfb73cb9e 100644 --- a/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts +++ b/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts @@ -94,19 +94,19 @@ gpio-keys { compatible = "gpio-keys"; - rfkill { + button-rfkill { label = "WiFi"; linux,code = <KEY_RFKILL>; gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>; }; - wps { + button-wps { label = "WPS"; linux,code = <KEY_WPS_BUTTON>; gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>; }; - restart { + button-restart { label = "Reset"; linux,code = <KEY_RESTART>; gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts b/arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts index 0e273c598732..ca47cc4f2ba1 100644 --- a/arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts +++ b/arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts @@ -60,13 +60,13 @@ gpio-keys { compatible = "gpio-keys"; - restart { + button-restart { label = "Reset"; linux,code = <KEY_RESTART>; gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>; }; - wps { + button-wps { label = "WPS"; linux,code = <KEY_WPS_BUTTON>; gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts b/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts index d00495a8b6fc..0edc2543e568 100644 --- a/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts +++ b/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts @@ -91,26 +91,26 @@ gpio-keys { compatible = "gpio-keys"; - aoss { + button-aoss { label = "AOSS"; linux,code = <KEY_WPS_BUTTON>; gpios = <&chipcommon 9 GPIO_ACTIVE_LOW>; }; - restart { + button-restart { label = "Reset"; linux,code = <KEY_RESTART>; gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; }; /* Switch device mode? */ - mode { + button-mode { label = "Mode"; linux,code = <KEY_SETUP>; gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>; }; - eject { + button-eject { label = "USB eject"; linux,code = <KEY_EJECTCD>; gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts b/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts index 8b1a05a0f1a1..1f0998f34afd 100644 --- a/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts +++ b/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts @@ -96,7 +96,7 @@ gpio-keys { compatible = "gpio-keys"; - restart { + button-restart { label = "Reset"; linux,code = <KEY_RESTART>; gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts b/arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts index 68aaf0af3945..c8c02377543b 100644 --- a/arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts +++ b/arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts @@ -45,7 +45,7 @@ gpio-keys { compatible = "gpio-keys"; - restart { + button-restart { label = "Reset"; linux,code = <KEY_RESTART>; gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts b/arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts index 9316a36434f7..3b35a7af4b1c 100644 --- a/arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts +++ b/arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts @@ -94,7 +94,7 @@ gpio-keys { compatible = "gpio-keys"; - restart { + button-restart { label = "Reset"; linux,code = <KEY_RESTART>; gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/bcm47081-tplink-archer-c5-v2.dts b/arch/arm/boot/dts/bcm47081-tplink-archer-c5-v2.dts index 12e34a0439b4..19a7971b5a00 100644 --- a/arch/arm/boot/dts/bcm47081-tplink-archer-c5-v2.dts +++ b/arch/arm/boot/dts/bcm47081-tplink-archer-c5-v2.dts @@ -77,13 +77,13 @@ gpio-keys { compatible = "gpio-keys"; - rfkill { + button-rfkill { label = "WiFi"; linux,code = <KEY_RFKILL>; gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; }; - restart { + button-restart { label = "Reset"; linux,code = <KEY_RESTART>; gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts b/arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts index 7546c8d07bcd..f52a75c4ca09 100644 --- a/arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts +++ b/arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts @@ -47,16 +47,14 @@ gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - wps { + button-wps { label = "WPS"; linux,code = <KEY_WPS_BUTTON>; gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>; }; - restart { + button-restart { label = "Reset"; linux,code = <KEY_RESTART>; gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts b/arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts index beae9eab9cb8..5ff6c588e16e 100644 --- a/arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts +++ b/arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts @@ -77,42 +77,40 @@ gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - power { + button-power { label = "Power"; linux,code = <KEY_POWER>; gpios = <&chipcommon 1 GPIO_ACTIVE_LOW>; }; - restart { + button-restart { label = "Reset"; linux,code = <KEY_RESTART>; gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>; }; - aoss { + button-aoss { label = "AOSS"; linux,code = <KEY_WPS_BUTTON>; gpios = <&chipcommon 16 GPIO_ACTIVE_LOW>; }; /* Commit mode set by switch? */ - mode { + button-mode { label = "Mode"; linux,code = <KEY_SETUP>; gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; }; /* Switch: AP mode */ - sw_ap { + button-sw-ap { label = "AP"; linux,code = <BTN_0>; gpios = <&chipcommon 18 GPIO_ACTIVE_LOW>; }; - eject { + button-eject { label = "USB eject"; linux,code = <KEY_EJECTCD>; gpios = <&chipcommon 20 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/bcm4709-linksys-ea9200.dts b/arch/arm/boot/dts/bcm4709-linksys-ea9200.dts index 7879f7d7d9c3..99253fd7adb3 100644 --- a/arch/arm/boot/dts/bcm4709-linksys-ea9200.dts +++ b/arch/arm/boot/dts/bcm4709-linksys-ea9200.dts @@ -29,16 +29,14 @@ gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - wps { + button-wps { label = "WPS"; linux,code = <KEY_WPS_BUTTON>; gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; }; - restart { + button-restart { label = "Reset"; linux,code = <KEY_RESTART>; gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/bcm4709-netgear-r7000.dts b/arch/arm/boot/dts/bcm4709-netgear-r7000.dts index 56d309dbc6b0..de961fbb6200 100644 --- a/arch/arm/boot/dts/bcm4709-netgear-r7000.dts +++ b/arch/arm/boot/dts/bcm4709-netgear-r7000.dts @@ -72,22 +72,20 @@ gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - wps { + button-wps { label = "WPS"; linux,code = <KEY_WPS_BUTTON>; gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>; }; - rfkill { + button-rfkill { label = "WiFi"; linux,code = <KEY_RFKILL>; gpios = <&chipcommon 5 GPIO_ACTIVE_LOW>; }; - restart { + button-restart { label = "Reset"; linux,code = <KEY_RESTART>; gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/bcm4709-netgear-r8000.dts b/arch/arm/boot/dts/bcm4709-netgear-r8000.dts index 89f992af61d1..087f7f60de18 100644 --- a/arch/arm/boot/dts/bcm4709-netgear-r8000.dts +++ b/arch/arm/boot/dts/bcm4709-netgear-r8000.dts @@ -99,28 +99,26 @@ gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - rfkill { + button-rfkill { label = "WiFi"; linux,code = <KEY_RFKILL>; gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>; }; - wps { + button-wps { label = "WPS"; linux,code = <KEY_WPS_BUTTON>; gpios = <&chipcommon 5 GPIO_ACTIVE_LOW>; }; - restart { + button-restart { label = "Reset"; linux,code = <KEY_RESTART>; gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>; }; - brightness { + button-brightness { label = "Backlight"; linux,code = <KEY_BRIGHTNESS_ZERO>; gpios = <&chipcommon 19 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/bcm4709-tplink-archer-c9-v1.dts b/arch/arm/boot/dts/bcm4709-tplink-archer-c9-v1.dts index c2a266a439d0..11d1068160da 100644 --- a/arch/arm/boot/dts/bcm4709-tplink-archer-c9-v1.dts +++ b/arch/arm/boot/dts/bcm4709-tplink-archer-c9-v1.dts @@ -77,16 +77,14 @@ gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - wps { + button-wps { label = "WPS"; linux,code = <KEY_WPS_BUTTON>; gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>; }; - restart { + button-restart { label = "Reset"; linux,code = <KEY_RESTART>; gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts b/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts index d8503758342b..a5fec56d11c0 100644 --- a/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts +++ b/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts @@ -72,25 +72,25 @@ gpio-keys { compatible = "gpio-keys"; - wps { + button-wps { label = "WPS"; linux,code = <KEY_WPS_BUTTON>; gpios = <&chipcommon 20 GPIO_ACTIVE_LOW>; }; - reset { + button-reset { label = "Reset"; linux,code = <KEY_RESTART>; gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; }; - wifi { + button-wifi { label = "Wi-Fi"; linux,code = <KEY_RFKILL>; gpios = <&chipcommon 18 GPIO_ACTIVE_LOW>; }; - led { + button-led { label = "Backlight"; linux,code = <KEY_BRIGHTNESS_ZERO>; gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts b/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts index 60bfd52ee677..2c38b642a8b8 100644 --- a/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts +++ b/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts @@ -86,20 +86,20 @@ gpio-keys { compatible = "gpio-keys"; - wps { + button-wps { label = "WPS"; linux,code = <KEY_WPS_BUTTON>; gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>; }; /* Switch: router / extender */ - extender { + button-extender { label = "Extender"; linux,code = <BTN_0>; gpios = <&chipcommon 10 GPIO_ACTIVE_LOW>; }; - restart { + button-restart { label = "Reset"; linux,code = <KEY_RESTART>; gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/bcm47094-linksys-panamera.dts b/arch/arm/boot/dts/bcm47094-linksys-panamera.dts index 9bef6b9bfa8d..86c7cc0fa70e 100644 --- a/arch/arm/boot/dts/bcm47094-linksys-panamera.dts +++ b/arch/arm/boot/dts/bcm47094-linksys-panamera.dts @@ -30,19 +30,19 @@ gpio-keys { compatible = "gpio-keys"; - wps { + button-wps { label = "WPS"; linux,code = <KEY_WPS_BUTTON>; gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; }; - rfkill { + button-rfkill { label = "WiFi"; linux,code = <KEY_RFKILL>; gpios = <&chipcommon 16 GPIO_ACTIVE_LOW>; }; - reset { + button-reset { label = "Reset"; linux,code = <KEY_RESTART>; gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/bcm47094-luxul-abr-4500.dts b/arch/arm/boot/dts/bcm47094-luxul-abr-4500.dts index b51a0ee7e584..9ad15bcae1ca 100644 --- a/arch/arm/boot/dts/bcm47094-luxul-abr-4500.dts +++ b/arch/arm/boot/dts/bcm47094-luxul-abr-4500.dts @@ -49,7 +49,7 @@ gpio-keys { compatible = "gpio-keys"; - restart { + button-restart { label = "Reset"; linux,code = <KEY_RESTART>; gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/bcm47094-luxul-xap-1610.dts b/arch/arm/boot/dts/bcm47094-luxul-xap-1610.dts index 6fa101f0a90d..ee24d3768536 100644 --- a/arch/arm/boot/dts/bcm47094-luxul-xap-1610.dts +++ b/arch/arm/boot/dts/bcm47094-luxul-xap-1610.dts @@ -43,7 +43,7 @@ gpio-keys { compatible = "gpio-keys"; - restart { + button-restart { label = "Reset"; linux,code = <KEY_RESTART>; gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/bcm47094-luxul-xbr-4500.dts b/arch/arm/boot/dts/bcm47094-luxul-xbr-4500.dts index b959a9504eea..6549d07b9887 100644 --- a/arch/arm/boot/dts/bcm47094-luxul-xbr-4500.dts +++ b/arch/arm/boot/dts/bcm47094-luxul-xbr-4500.dts @@ -49,7 +49,7 @@ gpio-keys { compatible = "gpio-keys"; - restart { + button-restart { label = "Reset"; linux,code = <KEY_RESTART>; gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/bcm47094-luxul-xwc-2000.dts b/arch/arm/boot/dts/bcm47094-luxul-xwc-2000.dts index b0d8a688141d..654fcce9fded 100644 --- a/arch/arm/boot/dts/bcm47094-luxul-xwc-2000.dts +++ b/arch/arm/boot/dts/bcm47094-luxul-xwc-2000.dts @@ -34,10 +34,8 @@ gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - restart { + button-restart { label = "Reset"; linux,code = <KEY_RESTART>; gpios = <&chipcommon 19 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts b/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts index cbe8c8e4a301..bf053a2fcc7c 100644 --- a/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts +++ b/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts @@ -89,7 +89,7 @@ gpio-keys { compatible = "gpio-keys"; - restart { + button-restart { label = "Reset"; linux,code = <KEY_RESTART>; gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts b/arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts index 9efcb2424228..78a90dd57a4e 100644 --- a/arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts +++ b/arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts @@ -67,7 +67,7 @@ gpio-keys { compatible = "gpio-keys"; - restart { + button-restart { label = "Reset"; linux,code = <KEY_RESTART>; gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/bcm47094-netgear-r8500.dts b/arch/arm/boot/dts/bcm47094-netgear-r8500.dts index 42097a4c2659..f850dce37b20 100644 --- a/arch/arm/boot/dts/bcm47094-netgear-r8500.dts +++ b/arch/arm/boot/dts/bcm47094-netgear-r8500.dts @@ -65,25 +65,25 @@ gpio-keys { compatible = "gpio-keys"; - brightness { + button-brightness { label = "Backlight"; linux,code = <KEY_BRIGHTNESS_ZERO>; gpios = <&chipcommon 1 GPIO_ACTIVE_LOW>; }; - restart { + button-restart { label = "Reset"; linux,code = <KEY_RESTART>; gpios = <&chipcommon 10 GPIO_ACTIVE_LOW>; }; - wps { + button-wps { label = "WPS"; linux,code = <KEY_WPS_BUTTON>; gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>; }; - rfkill { + button-rfkill { label = "WiFi"; linux,code = <KEY_RFKILL>; gpios = <&chipcommon 20 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/bcm47094-phicomm-k3.dts b/arch/arm/boot/dts/bcm47094-phicomm-k3.dts index a2566ad4619c..3bf6e24978ac 100644 --- a/arch/arm/boot/dts/bcm47094-phicomm-k3.dts +++ b/arch/arm/boot/dts/bcm47094-phicomm-k3.dts @@ -22,7 +22,7 @@ gpio-keys { compatible = "gpio-keys"; - restart { + button-restart { label = "Reset"; linux,code = <KEY_RESTART>; gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/bcm47189-luxul-xap-1440.dts b/arch/arm/boot/dts/bcm47189-luxul-xap-1440.dts index 57ca1cfaecd8..e20b6d2eb274 100644 --- a/arch/arm/boot/dts/bcm47189-luxul-xap-1440.dts +++ b/arch/arm/boot/dts/bcm47189-luxul-xap-1440.dts @@ -39,7 +39,7 @@ gpio-keys { compatible = "gpio-keys"; - restart { + button-restart { label = "Reset"; linux,code = <KEY_RESTART>; gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/bcm47189-luxul-xap-810.dts b/arch/arm/boot/dts/bcm47189-luxul-xap-810.dts index 2e1a7e382cb7..9d863570fcf3 100644 --- a/arch/arm/boot/dts/bcm47189-luxul-xap-810.dts +++ b/arch/arm/boot/dts/bcm47189-luxul-xap-810.dts @@ -49,7 +49,7 @@ gpio-keys { compatible = "gpio-keys"; - restart { + button-restart { label = "Reset"; linux,code = <KEY_RESTART>; gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/bcm47189-tenda-ac9.dts b/arch/arm/boot/dts/bcm47189-tenda-ac9.dts index 07eb3a8287d6..55b92645b0f1 100644 --- a/arch/arm/boot/dts/bcm47189-tenda-ac9.dts +++ b/arch/arm/boot/dts/bcm47189-tenda-ac9.dts @@ -59,19 +59,19 @@ gpio-keys { compatible = "gpio-keys"; - rfkill { + button-rfkill { label = "WiFi"; linux,code = <KEY_RFKILL>; gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; }; - restart { + button-restart { label = "Reset"; linux,code = <KEY_RESTART>; gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>; }; - wps { + button-wps { label = "WPS"; linux,code = <KEY_WPS_BUTTON>; gpios = <&chipcommon 9 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/bcm47622.dtsi b/arch/arm/boot/dts/bcm47622.dtsi index c016e12b7372..2df04528af82 100644 --- a/arch/arm/boot/dts/bcm47622.dtsi +++ b/arch/arm/boot/dts/bcm47622.dtsi @@ -32,6 +32,7 @@ next-level-cache = <&L2_0>; enable-method = "psci"; }; + CA7_2: cpu@2 { device_type = "cpu"; compatible = "arm,cortex-a7"; @@ -39,6 +40,7 @@ next-level-cache = <&L2_0>; enable-method = "psci"; }; + CA7_3: cpu@3 { device_type = "cpu"; compatible = "arm,cortex-a7"; @@ -46,6 +48,7 @@ next-level-cache = <&L2_0>; enable-method = "psci"; }; + L2_0: l2-cache0 { compatible = "cache"; }; @@ -76,6 +79,7 @@ #clock-cells = <0>; clock-frequency = <200000000>; }; + uart_clk: uart-clk { compatible = "fixed-factor-clock"; #clock-cells = <0>; @@ -88,23 +92,23 @@ psci { compatible = "arm,psci-0.2"; method = "smc"; - cpu_off = <1>; - cpu_on = <2>; }; axi@81000000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; - ranges = <0 0x81000000 0x818000>; + ranges = <0 0x81000000 0x8000>; gic: interrupt-controller@1000 { compatible = "arm,cortex-a7-gic"; #interrupt-cells = <3>; - #address-cells = <0>; interrupt-controller; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; reg = <0x1000 0x1000>, - <0x2000 0x2000>; + <0x2000 0x2000>, + <0x4000 0x2000>, + <0x6000 0x2000>; }; }; diff --git a/arch/arm/boot/dts/bcm53015-meraki-mr26.dts b/arch/arm/boot/dts/bcm53015-meraki-mr26.dts new file mode 100644 index 000000000000..14f58033efeb --- /dev/null +++ b/arch/arm/boot/dts/bcm53015-meraki-mr26.dts @@ -0,0 +1,166 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Broadcom BCM470X / BCM5301X ARM platform code. + * DTS for Meraki MR26 / Codename: Venom + * + * Copyright (C) 2022 Christian Lamparter <chunkeey@gmail.com> + */ + +/dts-v1/; + +#include "bcm4708.dtsi" +#include "bcm5301x-nand-cs0-bch8.dtsi" +#include <dt-bindings/leds/common.h> + +/ { + compatible = "meraki,mr26", "brcm,bcm53015", "brcm,bcm4708"; + model = "Meraki MR26"; + + memory@0 { + reg = <0x00000000 0x08000000>; + device_type = "memory"; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + function = LED_FUNCTION_FAULT; + color = <LED_COLOR_ID_AMBER>; + gpios = <&chipcommon 13 GPIO_ACTIVE_HIGH>; + panic-indicator; + }; + led-1 { + function = LED_FUNCTION_INDICATOR; + color = <LED_COLOR_ID_WHITE>; + gpios = <&chipcommon 12 GPIO_ACTIVE_HIGH>; + }; + }; + + keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + key-restart { + label = "Reset"; + linux,code = <KEY_RESTART>; + gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&uart0 { + clock-frequency = <50000000>; + /delete-property/ clocks; +}; + +&uart1 { + status = "disabled"; +}; + +&gmac0 { + status = "okay"; +}; + +&gmac1 { + status = "disabled"; +}; +&gmac2 { + status = "disabled"; +}; +&gmac3 { + status = "disabled"; +}; + +&nandcs { + nand-ecc-algo = "hw"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <0x1>; + #size-cells = <0x1>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x200000>; + read-only; + }; + + partition@200000 { + label = "u-boot-env"; + reg = <0x200000 0x200000>; + /* empty */ + }; + + partition@400000 { + label = "u-boot-backup"; + reg = <0x400000 0x200000>; + /* empty */ + }; + + partition@600000 { + label = "u-boot-env-backup"; + reg = <0x600000 0x200000>; + /* empty */ + }; + + partition@800000 { + label = "ubi"; + reg = <0x800000 0x7780000>; + }; + }; +}; + +&srab { + status = "okay"; + + ports { + port@0 { + reg = <0>; + label = "poe"; + }; + + port@5 { + reg = <5>; + label = "cpu"; + ethernet = <&gmac0>; + + fixed-link { + speed = <1000>; + duplex-full; + }; + }; + }; +}; + +&i2c0 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinmux_i2c>; + + clock-frequency = <100000>; + + ina219@40 { + compatible = "ti,ina219"; /* PoE power */ + reg = <0x40>; + shunt-resistor = <60000>; /* = 60 mOhms */ + }; + + eeprom@56 { + compatible = "atmel,24c64"; + reg = <0x56>; + pagesize = <32>; + read-only; + #address-cells = <1>; + #size-cells = <1>; + + /* it's empty */ + }; +}; + +&thermal { + status = "disabled"; + /* does not work, reads 418 degree Celsius */ +}; diff --git a/arch/arm/boot/dts/bcm53016-meraki-mr32.dts b/arch/arm/boot/dts/bcm53016-meraki-mr32.dts index daca63f25134..e678bc03d816 100644 --- a/arch/arm/boot/dts/bcm53016-meraki-mr32.dts +++ b/arch/arm/boot/dts/bcm53016-meraki-mr32.dts @@ -47,10 +47,8 @@ keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - restart { + button-restart { label = "Reset"; linux,code = <KEY_RESTART>; gpios = <&chipcommon 21 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi index 65f8a759f1e3..5fc1b847f4aa 100644 --- a/arch/arm/boot/dts/bcm5301x.dtsi +++ b/arch/arm/boot/dts/bcm5301x.dtsi @@ -568,9 +568,9 @@ trips { cpu-crit { - temperature = <125000>; - hysteresis = <0>; - type = "critical"; + temperature = <125000>; + hysteresis = <0>; + type = "critical"; }; }; diff --git a/arch/arm/boot/dts/bcm63138.dtsi b/arch/arm/boot/dts/bcm63138.dtsi index cca49a2e2d62..b774a8d63813 100644 --- a/arch/arm/boot/dts/bcm63138.dtsi +++ b/arch/arm/boot/dts/bcm63138.dtsi @@ -9,8 +9,8 @@ / { #address-cells = <1>; #size-cells = <1>; - compatible = "brcm,bcm63138"; - model = "Broadcom BCM63138 DSL SoC"; + compatible = "brcm,bcm63138", "brcm,bcmbca"; + model = "Broadcom BCM963138 Reference Board"; interrupt-parent = <&gic>; aliases { diff --git a/arch/arm/boot/dts/bcm63148.dtsi b/arch/arm/boot/dts/bcm63148.dtsi new file mode 100644 index 000000000000..df5307b6b3af --- /dev/null +++ b/arch/arm/boot/dts/bcm63148.dtsi @@ -0,0 +1,103 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Broadcom Ltd. + */ + +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/interrupt-controller/irq.h> + +/ { + compatible = "brcm,bcm63148", "brcm,bcmbca"; + #address-cells = <1>; + #size-cells = <1>; + + interrupt-parent = <&gic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + B15_0: cpu@0 { + device_type = "cpu"; + compatible = "brcm,brahma-b15"; + reg = <0x0>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + B15_1: cpu@1 { + device_type = "cpu"; + compatible = "brcm,brahma-b15"; + reg = <0x1>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + L2_0: l2-cache0 { + compatible = "cache"; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; + }; + + pmu: pmu { + compatible = "arm,cortex-a15-pmu"; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&B15_0>, <&B15_1>; + }; + + clocks: clocks { + periph_clk: periph-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + axi@80030000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x80030000 0x8000>; + + gic: interrupt-controller@1000 { + compatible = "arm,cortex-a15-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x1000 0x1000>, + <0x2000 0x2000>, + <0x4000 0x2000>, + <0x6000 0x2000>; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | + IRQ_TYPE_LEVEL_HIGH)>; + }; + }; + + bus@ff800000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xfffe8000 0x8000>; + + uart0: serial@600 { + compatible = "brcm,bcm6345-uart"; + reg = <0x600 0x20>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&periph_clk>; + clock-names = "refclk"; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/boot/dts/bcm63178.dtsi b/arch/arm/boot/dts/bcm63178.dtsi new file mode 100644 index 000000000000..5463443f0762 --- /dev/null +++ b/arch/arm/boot/dts/bcm63178.dtsi @@ -0,0 +1,118 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Broadcom Ltd. + */ + +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/interrupt-controller/irq.h> + +/ { + compatible = "brcm,bcm63178", "brcm,bcmbca"; + #address-cells = <1>; + #size-cells = <1>; + + interrupt-parent = <&gic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + CA7_0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x0>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + CA7_1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x1>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + CA7_2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x2>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + L2_0: l2-cache0 { + compatible = "cache"; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; + arm,cpu-registers-not-fw-configured; + }; + + pmu: pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&CA7_0>, <&CA7_1>, + <&CA7_2>; + }; + + clocks: clocks { + periph_clk: periph-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; + uart_clk: uart-clk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&periph_clk>; + clock-div = <4>; + clock-mult = <1>; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + cpu_off = <1>; + cpu_on = <2>; + }; + + axi@81000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x81000000 0x4000>; + + gic: interrupt-controller@1000 { + compatible = "arm,cortex-a7-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x1000 0x1000>, + <0x2000 0x2000>; + }; + }; + + bus@ff800000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xff800000 0x800000>; + + uart0: serial@12000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x12000 0x1000>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&uart_clk>, <&uart_clk>; + clock-names = "uartclk", "apb_pclk"; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/boot/dts/bcm6756.dtsi b/arch/arm/boot/dts/bcm6756.dtsi new file mode 100644 index 000000000000..ce1b59faf800 --- /dev/null +++ b/arch/arm/boot/dts/bcm6756.dtsi @@ -0,0 +1,130 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Broadcom Ltd. + */ + +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/interrupt-controller/irq.h> + +/ { + compatible = "brcm,bcm6756", "brcm,bcmbca"; + #address-cells = <1>; + #size-cells = <1>; + + interrupt-parent = <&gic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + CA7_0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x0>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + CA7_1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x1>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + CA7_2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x2>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + CA7_3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x3>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + L2_0: l2-cache0 { + compatible = "cache"; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; + arm,cpu-registers-not-fw-configured; + }; + + pmu: pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&CA7_0>, <&CA7_1>, + <&CA7_2>, <&CA7_3>; + }; + + clocks: clocks { + periph_clk: periph-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; + + uart_clk: uart-clk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&periph_clk>; + clock-div = <4>; + clock-mult = <1>; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + axi@81000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x81000000 0x8000>; + + gic: interrupt-controller@1000 { + compatible = "arm,cortex-a7-gic"; + #interrupt-cells = <3>; + interrupt-controller; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + reg = <0x1000 0x1000>, + <0x2000 0x2000>, + <0x4000 0x2000>, + <0x6000 0x2000>; + }; + }; + + bus@ff800000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xff800000 0x800000>; + + uart0: serial@12000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x12000 0x1000>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&uart_clk>, <&uart_clk>; + clock-names = "uartclk", "apb_pclk"; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/boot/dts/bcm6846.dtsi b/arch/arm/boot/dts/bcm6846.dtsi new file mode 100644 index 000000000000..e610c102498f --- /dev/null +++ b/arch/arm/boot/dts/bcm6846.dtsi @@ -0,0 +1,103 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Broadcom Ltd. + */ + +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/interrupt-controller/irq.h> + +/ { + compatible = "brcm,bcm6846", "brcm,bcmbca"; + #address-cells = <1>; + #size-cells = <1>; + + interrupt-parent = <&gic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + CA7_0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x0>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + CA7_1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x1>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + L2_0: l2-cache0 { + compatible = "cache"; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; + arm,cpu-registers-not-fw-configured; + }; + + pmu: pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&CA7_0>, <&CA7_1>; + }; + + clocks: clocks { + periph_clk: periph-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + cpu_off = <1>; + cpu_on = <2>; + }; + + axi@81000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x81000000 0x4000>; + + gic: interrupt-controller@1000 { + compatible = "arm,cortex-a7-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x1000 0x1000>, + <0x2000 0x2000>; + }; + }; + + bus@ff800000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xff800000 0x800000>; + + uart0: serial@640 { + compatible = "brcm,bcm6345-uart"; + reg = <0x640 0x1b>; + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&periph_clk>; + clock-names = "refclk"; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/boot/dts/bcm6855.dtsi b/arch/arm/boot/dts/bcm6855.dtsi new file mode 100644 index 000000000000..620f51aee1a2 --- /dev/null +++ b/arch/arm/boot/dts/bcm6855.dtsi @@ -0,0 +1,120 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Broadcom Ltd. + */ + +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/interrupt-controller/irq.h> + +/ { + compatible = "brcm,bcm6855", "brcm,bcmbca"; + #address-cells = <1>; + #size-cells = <1>; + + interrupt-parent = <&gic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + CA7_0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x0>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + CA7_1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x1>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + CA7_2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x2>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + L2_0: l2-cache0 { + compatible = "cache"; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>; + arm,cpu-registers-not-fw-configured; + }; + + pmu: pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&CA7_0>, <&CA7_1>, <&CA7_2>; + }; + + clocks: clocks { + periph_clk: periph-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; + + uart_clk: uart-clk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&periph_clk>; + clock-div = <4>; + clock-mult = <1>; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + axi@81000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x81000000 0x8000>; + + gic: interrupt-controller@1000 { + compatible = "arm,cortex-a7-gic"; + #interrupt-cells = <3>; + interrupt-controller; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_HIGH)>; + reg = <0x1000 0x1000>, + <0x2000 0x2000>, + <0x4000 0x2000>, + <0x6000 0x2000>; + }; + }; + + bus@ff800000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xff800000 0x800000>; + + uart0: serial@12000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x12000 0x1000>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&uart_clk>, <&uart_clk>; + clock-names = "uartclk", "apb_pclk"; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/boot/dts/bcm6878.dtsi b/arch/arm/boot/dts/bcm6878.dtsi new file mode 100644 index 000000000000..a7dff596fe1e --- /dev/null +++ b/arch/arm/boot/dts/bcm6878.dtsi @@ -0,0 +1,110 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Broadcom Ltd. + */ + +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/interrupt-controller/irq.h> + +/ { + compatible = "brcm,bcm6878", "brcm,bcmbca"; + #address-cells = <1>; + #size-cells = <1>; + + interrupt-parent = <&gic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + CA7_0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x0>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + CA7_1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x1>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + L2_0: l2-cache0 { + compatible = "cache"; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; + arm,cpu-registers-not-fw-configured; + }; + + pmu: pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&CA7_0>, <&CA7_1>; + }; + + clocks: clocks { + periph_clk: periph-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; + uart_clk: uart-clk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&periph_clk>; + clock-div = <4>; + clock-mult = <1>; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + axi@81000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x81000000 0x8000>; + + gic: interrupt-controller@1000 { + compatible = "arm,cortex-a7-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x1000 0x1000>, + <0x2000 0x2000>, + <0x4000 0x2000>, + <0x6000 0x2000>; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | + IRQ_TYPE_LEVEL_HIGH)>; + }; + }; + + bus@ff800000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xff800000 0x800000>; + + uart0: serial@12000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x12000 0x1000>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&uart_clk>, <&uart_clk>; + clock-names = "uartclk", "apb_pclk"; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/boot/dts/bcm911360_entphn.dts b/arch/arm/boot/dts/bcm911360_entphn.dts index a76c74b44bba..363009e747b3 100644 --- a/arch/arm/boot/dts/bcm911360_entphn.dts +++ b/arch/arm/boot/dts/bcm911360_entphn.dts @@ -47,10 +47,10 @@ stdout-path = "serial0:115200n8"; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; - hook { + button-hook { label = "HOOK"; linux,code = <KEY_O>; gpios = <&gpio_asiu 48 0>; diff --git a/arch/arm/boot/dts/bcm947189acdbmr.dts b/arch/arm/boot/dts/bcm947189acdbmr.dts index b0b8c774a37f..16e70a264faf 100644 --- a/arch/arm/boot/dts/bcm947189acdbmr.dts +++ b/arch/arm/boot/dts/bcm947189acdbmr.dts @@ -44,13 +44,13 @@ gpio-keys { compatible = "gpio-keys"; - restart { + button-restart { label = "Reset"; linux,code = <KEY_RESTART>; gpios = <&chipcommon 7 GPIO_ACTIVE_HIGH>; }; - wps { + button-wps { label = "WPS"; linux,code = <KEY_WPS_BUTTON>; gpios = <&chipcommon 9 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/bcm953012er.dts b/arch/arm/boot/dts/bcm953012er.dts index dd63a148a16b..4fe3b3653376 100644 --- a/arch/arm/boot/dts/bcm953012er.dts +++ b/arch/arm/boot/dts/bcm953012er.dts @@ -47,13 +47,13 @@ gpio-keys { compatible = "gpio-keys"; - wps { + button-wps { label = "WPS"; linux,code = <KEY_WPS_BUTTON>; gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>; }; - restart { + button-restart { label = "Reset"; linux,code = <KEY_RESTART>; gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi b/arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi index 58b7d9fc7574..c54451dde6dd 100644 --- a/arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi +++ b/arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi @@ -13,7 +13,7 @@ autorepeat; poll-interval = <20>; - reset { + button-reset { label = "reset"; linux,code = <KEY_RESTART>; gpios = <&gpioa 8 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/bcm958625-meraki-kingpin.dtsi b/arch/arm/boot/dts/bcm958625-meraki-kingpin.dtsi index 576cfc52567b..1830844c8404 100644 --- a/arch/arm/boot/dts/bcm958625-meraki-kingpin.dtsi +++ b/arch/arm/boot/dts/bcm958625-meraki-kingpin.dtsi @@ -14,7 +14,7 @@ autorepeat; poll-interval = <20>; - reset { + button-reset { label = "reset"; linux,code = <KEY_RESTART>; gpios = <&gpioa 6 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/bcm963138.dts b/arch/arm/boot/dts/bcm963138.dts new file mode 100644 index 000000000000..d28c4f130ca2 --- /dev/null +++ b/arch/arm/boot/dts/bcm963138.dts @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Broadcom Ltd. + */ + +/dts-v1/; + +#include "bcm63138.dtsi" + +/ { + model = "Broadcom BCM963138 Reference Board"; + compatible = "brcm,bcm963138", "brcm,bcm63138", "brcm,bcmbca"; + + chosen { + bootargs = "console=ttyS0,115200"; + stdout-path = &serial0; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x08000000>; + }; +}; + +&serial0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm963138dvt.dts b/arch/arm/boot/dts/bcm963138dvt.dts index df5c8ab90627..15bec75be74c 100644 --- a/arch/arm/boot/dts/bcm963138dvt.dts +++ b/arch/arm/boot/dts/bcm963138dvt.dts @@ -8,7 +8,7 @@ #include "bcm63138.dtsi" / { - compatible = "brcm,BCM963138DVT", "brcm,bcm63138"; + compatible = "brcm,BCM963138DVT", "brcm,bcm63138", "brcm,bcmbca"; model = "Broadcom BCM963138DVT"; chosen { diff --git a/arch/arm/boot/dts/bcm963148.dts b/arch/arm/boot/dts/bcm963148.dts new file mode 100644 index 000000000000..98f6a6d09f50 --- /dev/null +++ b/arch/arm/boot/dts/bcm963148.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019 Broadcom Ltd. + */ + +/dts-v1/; + +#include "bcm63148.dtsi" + +/ { + model = "Broadcom BCM963148 Reference Board"; + compatible = "brcm,bcm963148", "brcm,bcm63148", "brcm,bcmbca"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x08000000>; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm963178.dts b/arch/arm/boot/dts/bcm963178.dts new file mode 100644 index 000000000000..fa096e9cde23 --- /dev/null +++ b/arch/arm/boot/dts/bcm963178.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019 Broadcom Ltd. + */ + +/dts-v1/; + +#include "bcm63178.dtsi" + +/ { + model = "Broadcom BCM963178 Reference Board"; + compatible = "brcm,bcm963178", "brcm,bcm63178", "brcm,bcmbca"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x08000000>; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm96756.dts b/arch/arm/boot/dts/bcm96756.dts new file mode 100644 index 000000000000..9a4a87ba9c8a --- /dev/null +++ b/arch/arm/boot/dts/bcm96756.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019 Broadcom Ltd. + */ + +/dts-v1/; + +#include "bcm6756.dtsi" + +/ { + model = "Broadcom BCM96756 Reference Board"; + compatible = "brcm,bcm96756", "brcm,bcm6756", "brcm,bcmbca"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x08000000>; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm96846.dts b/arch/arm/boot/dts/bcm96846.dts new file mode 100644 index 000000000000..c70ebccabc19 --- /dev/null +++ b/arch/arm/boot/dts/bcm96846.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Broadcom Ltd. + */ + +/dts-v1/; + +#include "bcm6846.dtsi" + +/ { + model = "Broadcom BCM96846 Reference Board"; + compatible = "brcm,bcm96846", "brcm,bcm6846", "brcm,bcmbca"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x08000000>; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm96855.dts b/arch/arm/boot/dts/bcm96855.dts new file mode 100644 index 000000000000..4438152561ac --- /dev/null +++ b/arch/arm/boot/dts/bcm96855.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019 Broadcom Ltd. + */ + +/dts-v1/; + +#include "bcm6855.dtsi" + +/ { + model = "Broadcom BCM96855 Reference Board"; + compatible = "brcm,bcm96855", "brcm,bcm6855", "brcm,bcmbca"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x08000000>; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm96878.dts b/arch/arm/boot/dts/bcm96878.dts new file mode 100644 index 000000000000..8fbc175cb452 --- /dev/null +++ b/arch/arm/boot/dts/bcm96878.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019 Broadcom Ltd. + */ + +/dts-v1/; + +#include "bcm6878.dtsi" + +/ { + model = "Broadcom BCM96878 Reference Board"; + compatible = "brcm,bcm96878", "brcm,bcm6878", "brcm,bcmbca"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x08000000>; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/da850-evm.dts b/arch/arm/boot/dts/da850-evm.dts index e9aecac4f5b5..1fdd9a249165 100644 --- a/arch/arm/boot/dts/da850-evm.dts +++ b/arch/arm/boot/dts/da850-evm.dts @@ -52,15 +52,15 @@ enable-gpios = <&gpio 40 GPIO_ACTIVE_HIGH>; /* lcd_panel_pwr */ panel-info { - ac-bias = <255>; - ac-bias-intrpt = <0>; - dma-burst-sz = <16>; - bpp = <16>; - fdd = <0x80>; - sync-edge = <0>; - sync-ctrl = <1>; - raster-order = <0>; - fifo-th = <0>; + ac-bias = <255>; + ac-bias-intrpt = <0>; + dma-burst-sz = <16>; + bpp = <16>; + fdd = <0x80>; + sync-edge = <0>; + sync-ctrl = <1>; + raster-order = <0>; + fifo-th = <0>; }; display-timings { diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi index 0386376fa486..e46e4d22db39 100644 --- a/arch/arm/boot/dts/da850.dtsi +++ b/arch/arm/boot/dts/da850.dtsi @@ -419,7 +419,7 @@ edma0: edma@0 { compatible = "ti,edma3-tpcc"; /* eDMA3 CC0: 0x01c0 0000 - 0x01c0 7fff */ - reg = <0x0 0x8000>; + reg = <0x0 0x8000>; reg-names = "edma3_cc"; interrupts = <11 12>; interrupt-names = "edma3_ccint", "edma3_ccerrint"; @@ -430,14 +430,14 @@ }; edma0_tptc0: tptc@8000 { compatible = "ti,edma3-tptc"; - reg = <0x8000 0x400>; + reg = <0x8000 0x400>; interrupts = <13>; interrupt-names = "edm3_tcerrint"; power-domains = <&psc0 1>; }; edma0_tptc1: tptc@8400 { compatible = "ti,edma3-tptc"; - reg = <0x8400 0x400>; + reg = <0x8400 0x400>; interrupts = <32>; interrupt-names = "edm3_tcerrint"; power-domains = <&psc0 2>; @@ -445,7 +445,7 @@ edma1: edma@230000 { compatible = "ti,edma3-tpcc"; /* eDMA3 CC1: 0x01e3 0000 - 0x01e3 7fff */ - reg = <0x230000 0x8000>; + reg = <0x230000 0x8000>; reg-names = "edma3_cc"; interrupts = <93 94>; interrupt-names = "edma3_ccint", "edma3_ccerrint"; @@ -456,7 +456,7 @@ }; edma1_tptc0: tptc@238000 { compatible = "ti,edma3-tptc"; - reg = <0x238000 0x400>; + reg = <0x238000 0x400>; interrupts = <95>; interrupt-names = "edm3_tcerrint"; power-domains = <&psc1 21>; @@ -672,7 +672,7 @@ cppi41dma: dma-controller@201000 { compatible = "ti,da830-cppi41"; - reg = <0x201000 0x1000 + reg = <0x201000 0x1000 0x202000 0x1000 0x204000 0x4000>; reg-names = "controller", diff --git a/arch/arm/boot/dts/dm8148-evm.dts b/arch/arm/boot/dts/dm8148-evm.dts index 8ef48c00f98d..fe3f9a970b18 100644 --- a/arch/arm/boot/dts/dm8148-evm.dts +++ b/arch/arm/boot/dts/dm8148-evm.dts @@ -51,7 +51,7 @@ interrupt-parent = <&gpmc>; interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ <1 IRQ_TYPE_NONE>; /* termcount */ - linux,mtd-name= "micron,mt29f2g16aadwp"; + linux,mtd-name = "micron,mt29f2g16aadwp"; #address-cells = <1>; #size-cells = <1>; ti,nand-ecc-opt = "bch8"; diff --git a/arch/arm/boot/dts/dm8168-evm.dts b/arch/arm/boot/dts/dm8168-evm.dts index 778796c10af8..244a957f9ba3 100644 --- a/arch/arm/boot/dts/dm8168-evm.dts +++ b/arch/arm/boot/dts/dm8168-evm.dts @@ -119,7 +119,7 @@ nand@0,0 { compatible = "ti,omap2-nand"; - linux,mtd-name= "micron,mt29f2g16aadwp"; + linux,mtd-name = "micron,mt29f2g16aadwp"; reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ interrupt-parent = <&gpmc>; interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ diff --git a/arch/arm/boot/dts/dra62x-j5eco-evm.dts b/arch/arm/boot/dts/dra62x-j5eco-evm.dts index c16e183822be..577114c4c20a 100644 --- a/arch/arm/boot/dts/dra62x-j5eco-evm.dts +++ b/arch/arm/boot/dts/dra62x-j5eco-evm.dts @@ -51,7 +51,7 @@ interrupt-parent = <&gpmc>; interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ <1 IRQ_TYPE_NONE>; /* termcount */ - linux,mtd-name= "micron,mt29f2g16aadwp"; + linux,mtd-name = "micron,mt29f2g16aadwp"; #address-cells = <1>; #size-cells = <1>; ti,nand-ecc-opt = "bch8"; diff --git a/arch/arm/boot/dts/dra76x.dtsi b/arch/arm/boot/dts/dra76x.dtsi index bc4ae91cba16..931db7932c11 100644 --- a/arch/arm/boot/dts/dra76x.dtsi +++ b/arch/arm/boot/dts/dra76x.dtsi @@ -90,8 +90,8 @@ clocks = <&dpll_gmac_x2_ck>; ti,max-div = <63>; reg = <0x03fc>; - ti,bit-shift=<20>; - ti,latch-bit=<26>; + ti,bit-shift = <20>; + ti,latch-bit = <26>; assigned-clocks = <&dpll_gmac_h14x2_ctrl_ck>; assigned-clock-rates = <80000000>; }; @@ -102,7 +102,7 @@ clocks = <&dpll_gmac_ck>, <&dpll_gmac_h14x2_ctrl_ck>; reg = <0x3fc>; ti,bit-shift = <29>; - ti,latch-bit=<26>; + ti,latch-bit = <26>; assigned-clocks = <&dpll_gmac_h14x2_ctrl_mux_ck>; assigned-clock-parents = <&dpll_gmac_h14x2_ctrl_ck>; }; diff --git a/arch/arm/boot/dts/e60k02.dtsi b/arch/arm/boot/dts/e60k02.dtsi index 1a49f15f2df2..935e2359f8df 100644 --- a/arch/arm/boot/dts/e60k02.dtsi +++ b/arch/arm/boot/dts/e60k02.dtsi @@ -22,14 +22,14 @@ gpio_keys: gpio-keys { compatible = "gpio-keys"; - power { + key-power { label = "Power"; gpios = <&gpio5 8 GPIO_ACTIVE_LOW>; linux,code = <KEY_POWER>; wakeup-source; }; - cover { + key-cover { label = "Cover"; gpios = <&gpio5 12 GPIO_ACTIVE_LOW>; linux,code = <SW_LID>; diff --git a/arch/arm/boot/dts/e70k02.dtsi b/arch/arm/boot/dts/e70k02.dtsi index 156de653f2cd..27ef9a62b23c 100644 --- a/arch/arm/boot/dts/e70k02.dtsi +++ b/arch/arm/boot/dts/e70k02.dtsi @@ -26,14 +26,14 @@ gpio_keys: gpio-keys { compatible = "gpio-keys"; - power { + key-power { label = "Power"; gpios = <&gpio4 25 GPIO_ACTIVE_LOW>; linux,code = <KEY_POWER>; wakeup-source; }; - cover { + key-cover { label = "Cover"; gpios = <&gpio4 23 GPIO_ACTIVE_LOW>; linux,code = <SW_LID>; @@ -41,13 +41,13 @@ wakeup-source; }; - pageup { + key-pageup { label = "PageUp"; gpios = <&gpio4 0 GPIO_ACTIVE_LOW>; linux,code = <KEY_PAGEUP>; }; - pagedown { + key-pagedown { label = "PageDown"; gpios = <&gpio4 2 GPIO_ACTIVE_LOW>; linux,code = <KEY_PAGEDOWN>; diff --git a/arch/arm/boot/dts/ecx-common.dtsi b/arch/arm/boot/dts/ecx-common.dtsi index 57a028a69373..ce5221c6b358 100644 --- a/arch/arm/boot/dts/ecx-common.dtsi +++ b/arch/arm/boot/dts/ecx-common.dtsi @@ -9,11 +9,11 @@ }; psci { - compatible = "arm,psci"; - method = "smc"; - cpu_suspend = <0x84000002>; - cpu_off = <0x84000004>; - cpu_on = <0x84000006>; + compatible = "arm,psci"; + method = "smc"; + cpu_suspend = <0x84000002>; + cpu_off = <0x84000004>; + cpu_on = <0x84000006>; }; soc { diff --git a/arch/arm/boot/dts/en7523-evb.dts b/arch/arm/boot/dts/en7523-evb.dts index a8d8bb0419a0..f23a25cce119 100644 --- a/arch/arm/boot/dts/en7523-evb.dts +++ b/arch/arm/boot/dts/en7523-evb.dts @@ -33,3 +33,11 @@ &gpio1 { status = "okay"; }; + +&pcie0 { + status = "okay"; +}; + +&pcie1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/en7523.dtsi b/arch/arm/boot/dts/en7523.dtsi index 36597f587f46..7f839331a777 100644 --- a/arch/arm/boot/dts/en7523.dtsi +++ b/arch/arm/boot/dts/en7523.dtsi @@ -3,6 +3,7 @@ #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/clock/en7523-clk.h> / { interrupt-parent = <&gic>; @@ -83,6 +84,13 @@ }; }; + scu: system-controller@1fa20000 { + compatible = "airoha,en7523-scu"; + reg = <0x1fa20000 0x400>, + <0x1fb00000 0x1000>; + #clock-cells = <1>; + }; + gic: interrupt-controller@9000000 { compatible = "arm,gic-v3"; interrupt-controller; @@ -135,4 +143,62 @@ gpio-controller; #gpio-cells = <2>; }; + + pcie0: pcie@1fa91000 { + compatible = "airoha,en7523-pcie", "mediatek,mt7622-pcie"; + device_type = "pci"; + reg = <0x1fa91000 0x1000>; + reg-names = "port0"; + linux,pci-domain = <0>; + #address-cells = <3>; + #size-cells = <2>; + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pcie_irq"; + clocks = <&scu EN7523_CLK_PCIE>; + clock-names = "sys_ck0"; + bus-range = <0x00 0xff>; + ranges = <0x82000000 0 0x20000000 0x20000000 0 0x8000000>; + status = "disabled"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc0 0>, + <0 0 0 2 &pcie_intc0 1>, + <0 0 0 3 &pcie_intc0 2>, + <0 0 0 4 &pcie_intc0 3>; + pcie_intc0: interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + }; + + pcie1: pcie@1fa92000 { + compatible = "airoha,en7523-pcie", "mediatek,mt7622-pcie"; + device_type = "pci"; + reg = <0x1fa92000 0x1000>; + reg-names = "port1"; + linux,pci-domain = <1>; + #address-cells = <3>; + #size-cells = <2>; + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pcie_irq"; + clocks = <&scu EN7523_CLK_PCIE>; + clock-names = "sys_ck1"; + bus-range = <0x00 0xff>; + ranges = <0x82000000 0 0x28000000 0x28000000 0 0x8000000>; + status = "disabled"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc1 0>, + <0 0 0 2 &pcie_intc1 1>, + <0 0 0 3 &pcie_intc1 2>, + <0 0 0 4 &pcie_intc1 3>; + pcie_intc1: interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + }; }; diff --git a/arch/arm/boot/dts/exynos-pinctrl.h b/arch/arm/boot/dts/exynos-pinctrl.h new file mode 100644 index 000000000000..e3a6df95281c --- /dev/null +++ b/arch/arm/boot/dts/exynos-pinctrl.h @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Samsung Exynos DTS pinctrl constants + * + * Copyright (c) 2016 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * Copyright (c) 2022 Linaro Ltd + * Author: Krzysztof Kozlowski <krzk@kernel.org> + */ + +#ifndef __DTS_ARM_SAMSUNG_EXYNOS_PINCTRL_H__ +#define __DTS_ARM_SAMSUNG_EXYNOS_PINCTRL_H__ + +#define EXYNOS_PIN_PULL_NONE 0 +#define EXYNOS_PIN_PULL_DOWN 1 +#define EXYNOS_PIN_PULL_UP 3 + +/* Pin function in power down mode */ +#define EXYNOS_PIN_PDN_OUT0 0 +#define EXYNOS_PIN_PDN_OUT1 1 +#define EXYNOS_PIN_PDN_INPUT 2 +#define EXYNOS_PIN_PDN_PREV 3 + +/* Drive strengths for Exynos3250, Exynos4 (all) and Exynos5250 */ +#define EXYNOS4_PIN_DRV_LV1 0 +#define EXYNOS4_PIN_DRV_LV2 2 +#define EXYNOS4_PIN_DRV_LV3 1 +#define EXYNOS4_PIN_DRV_LV4 3 + +/* Drive strengths for Exynos5260 */ +#define EXYNOS5260_PIN_DRV_LV1 0 +#define EXYNOS5260_PIN_DRV_LV2 1 +#define EXYNOS5260_PIN_DRV_LV4 2 +#define EXYNOS5260_PIN_DRV_LV6 3 + +/* + * Drive strengths for Exynos5410, Exynos542x, Exynos5800 and Exynos850 (except + * GPIO_HSI block) + */ +#define EXYNOS5420_PIN_DRV_LV1 0 +#define EXYNOS5420_PIN_DRV_LV2 1 +#define EXYNOS5420_PIN_DRV_LV3 2 +#define EXYNOS5420_PIN_DRV_LV4 3 + +#define EXYNOS_PIN_FUNC_INPUT 0 +#define EXYNOS_PIN_FUNC_OUTPUT 1 +#define EXYNOS_PIN_FUNC_2 2 +#define EXYNOS_PIN_FUNC_3 3 +#define EXYNOS_PIN_FUNC_4 4 +#define EXYNOS_PIN_FUNC_5 5 +#define EXYNOS_PIN_FUNC_6 6 +#define EXYNOS_PIN_FUNC_EINT 0xf +#define EXYNOS_PIN_FUNC_F EXYNOS_PIN_FUNC_EINT + +#endif /* __DTS_ARM_SAMSUNG_EXYNOS_PINCTRL_H__ */ diff --git a/arch/arm/boot/dts/exynos3250-artik5.dtsi b/arch/arm/boot/dts/exynos3250-artik5.dtsi index 7b429622a288..0ac3f284fbb8 100644 --- a/arch/arm/boot/dts/exynos3250-artik5.dtsi +++ b/arch/arm/boot/dts/exynos3250-artik5.dtsi @@ -357,7 +357,7 @@ &pinctrl_1 { bten: bten-pins { - samsung,pins ="gpx1-7"; + samsung,pins = "gpx1-7"; samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>; samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>; diff --git a/arch/arm/boot/dts/exynos3250-pinctrl.dtsi b/arch/arm/boot/dts/exynos3250-pinctrl.dtsi index cc30d154ec94..011ba2eff29e 100644 --- a/arch/arm/boot/dts/exynos3250-pinctrl.dtsi +++ b/arch/arm/boot/dts/exynos3250-pinctrl.dtsi @@ -9,7 +9,7 @@ * tree nodes are listed in this file. */ -#include <dt-bindings/pinctrl/samsung.h> +#include "exynos-pinctrl.h" #define PIN_IN(_pin, _pull, _drv) \ pin- ## _pin { \ diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi index 78dad233ff34..326b9e0ed8d3 100644 --- a/arch/arm/boot/dts/exynos3250.dtsi +++ b/arch/arm/boot/dts/exynos3250.dtsi @@ -376,7 +376,7 @@ status = "disabled"; }; - mshc_0: mshc@12510000 { + mshc_0: mmc@12510000 { compatible = "samsung,exynos5420-dw-mshc"; reg = <0x12510000 0x1000>; interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; @@ -388,7 +388,7 @@ status = "disabled"; }; - mshc_1: mshc@12520000 { + mshc_1: mmc@12520000 { compatible = "samsung,exynos5420-dw-mshc"; reg = <0x12520000 0x1000>; interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; @@ -400,7 +400,7 @@ status = "disabled"; }; - mshc_2: mshc@12530000 { + mshc_2: mmc@12530000 { compatible = "samsung,exynos5250-dw-mshc"; reg = <0x12530000 0x1000>; interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi index 6f0ca3354e39..5c4ecda27a47 100644 --- a/arch/arm/boot/dts/exynos4.dtsi +++ b/arch/arm/boot/dts/exynos4.dtsi @@ -316,7 +316,7 @@ status = "disabled"; }; - sdhci_0: sdhci@12510000 { + sdhci_0: mmc@12510000 { compatible = "samsung,exynos4210-sdhci"; reg = <0x12510000 0x100>; interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; @@ -325,7 +325,7 @@ status = "disabled"; }; - sdhci_1: sdhci@12520000 { + sdhci_1: mmc@12520000 { compatible = "samsung,exynos4210-sdhci"; reg = <0x12520000 0x100>; interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; @@ -334,7 +334,7 @@ status = "disabled"; }; - sdhci_2: sdhci@12530000 { + sdhci_2: mmc@12530000 { compatible = "samsung,exynos4210-sdhci"; reg = <0x12530000 0x100>; interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; @@ -343,7 +343,7 @@ status = "disabled"; }; - sdhci_3: sdhci@12540000 { + sdhci_3: mmc@12540000 { compatible = "samsung,exynos4210-sdhci"; reg = <0x12540000 0x100>; interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm/boot/dts/exynos4210-i9100.dts b/arch/arm/boot/dts/exynos4210-i9100.dts index 3c0a18b30837..bba85011ecc9 100644 --- a/arch/arm/boot/dts/exynos4210-i9100.dts +++ b/arch/arm/boot/dts/exynos4210-i9100.dts @@ -89,21 +89,21 @@ gpio-keys { compatible = "gpio-keys"; - vol-down { + key-vol-down { gpios = <&gpx2 1 GPIO_ACTIVE_LOW>; linux,code = <KEY_VOLUMEDOWN>; label = "volume down"; debounce-interval = <10>; }; - vol-up { + key-vol-up { gpios = <&gpx2 0 GPIO_ACTIVE_LOW>; linux,code = <KEY_VOLUMEUP>; label = "volume up"; debounce-interval = <10>; }; - power { + key-power { gpios = <&gpx2 7 GPIO_ACTIVE_LOW>; linux,code = <KEY_POWER>; label = "power"; @@ -111,7 +111,7 @@ wakeup-source; }; - ok { + key-ok { gpios = <&gpx3 5 GPIO_ACTIVE_LOW>; linux,code = <KEY_OK>; label = "ok"; diff --git a/arch/arm/boot/dts/exynos4210-origen.dts b/arch/arm/boot/dts/exynos4210-origen.dts index a08ce2f37ea2..5f37b751f700 100644 --- a/arch/arm/boot/dts/exynos4210-origen.dts +++ b/arch/arm/boot/dts/exynos4210-origen.dts @@ -15,6 +15,7 @@ #include "exynos4210.dtsi" #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> #include "exynos-mfc-reserved-memory.dtsi" / { @@ -46,35 +47,35 @@ gpio-keys { compatible = "gpio-keys"; - up { + key-up { label = "Up"; gpios = <&gpx2 0 GPIO_ACTIVE_LOW>; linux,code = <KEY_UP>; wakeup-source; }; - down { + key-down { label = "Down"; gpios = <&gpx2 1 GPIO_ACTIVE_LOW>; linux,code = <KEY_DOWN>; wakeup-source; }; - back { + key-back { label = "Back"; gpios = <&gpx1 7 GPIO_ACTIVE_LOW>; linux,code = <KEY_BACK>; wakeup-source; }; - home { + key-home { label = "Home"; gpios = <&gpx1 6 GPIO_ACTIVE_LOW>; linux,code = <KEY_HOME>; wakeup-source; }; - menu { + key-menu { label = "Menu"; gpios = <&gpx1 5 GPIO_ACTIVE_LOW>; linux,code = <KEY_MENU>; @@ -86,6 +87,7 @@ compatible = "gpio-leds"; status { gpios = <&gpx1 3 GPIO_ACTIVE_LOW>; + function = LED_FUNCTION_HEARTBEAT; linux,default-trigger = "heartbeat"; }; }; diff --git a/arch/arm/boot/dts/exynos4210-pinctrl.dtsi b/arch/arm/boot/dts/exynos4210-pinctrl.dtsi index 6373009bb727..76f44ae0de46 100644 --- a/arch/arm/boot/dts/exynos4210-pinctrl.dtsi +++ b/arch/arm/boot/dts/exynos4210-pinctrl.dtsi @@ -11,7 +11,7 @@ * tree nodes are listed in this file. */ -#include <dt-bindings/pinctrl/samsung.h> +#include "exynos-pinctrl.h" &pinctrl_0 { gpa0: gpa0-gpio-bank { diff --git a/arch/arm/boot/dts/exynos4210-trats.dts b/arch/arm/boot/dts/exynos4210-trats.dts index 01f44d95f671..b8e9dd23fc51 100644 --- a/arch/arm/boot/dts/exynos4210-trats.dts +++ b/arch/arm/boot/dts/exynos4210-trats.dts @@ -180,7 +180,7 @@ vdd3-supply = <&vcclcd_reg>; vci-supply = <&vlcd_reg>; reset-gpios = <&gpy4 5 GPIO_ACTIVE_HIGH>; - power-on-delay= <50>; + power-on-delay = <50>; reset-delay = <100>; init-delay = <100>; flip-horizontal; diff --git a/arch/arm/boot/dts/exynos4412-galaxy-s3.dtsi b/arch/arm/boot/dts/exynos4412-galaxy-s3.dtsi index 03dffc690b79..94122e9c6625 100644 --- a/arch/arm/boot/dts/exynos4412-galaxy-s3.dtsi +++ b/arch/arm/boot/dts/exynos4412-galaxy-s3.dtsi @@ -7,6 +7,7 @@ */ /dts-v1/; +#include <dt-bindings/leds/common.h> #include "exynos4412-midas.dtsi" / { @@ -25,8 +26,9 @@ pinctrl-1 = <&camera_flash_host>; pinctrl-2 = <&camera_flash_isp>; - flash-led { - label = "flash"; + led { + function = LED_FUNCTION_FLASH; + color = <LED_COLOR_ID_WHITE>; led-max-microamp = <520833>; flash-max-microamp = <1012500>; flash-max-timeout-us = <1940000>; @@ -107,7 +109,7 @@ vdd3-supply = <&lcd_vdd3_reg>; vci-supply = <&ldo25_reg>; reset-gpios = <&gpf2 1 GPIO_ACTIVE_HIGH>; - power-on-delay= <50>; + power-on-delay = <50>; reset-delay = <100>; init-delay = <100>; flip-horizontal; diff --git a/arch/arm/boot/dts/exynos4412-itop-elite.dts b/arch/arm/boot/dts/exynos4412-itop-elite.dts index a9406280b979..202ab0fee3b7 100644 --- a/arch/arm/boot/dts/exynos4412-itop-elite.dts +++ b/arch/arm/boot/dts/exynos4412-itop-elite.dts @@ -11,6 +11,7 @@ */ /dts-v1/; +#include <dt-bindings/leds/common.h> #include <dt-bindings/pwm/pwm.h> #include <dt-bindings/sound/samsung-i2s.h> #include "exynos4412-itop-scp-core.dtsi" @@ -28,7 +29,8 @@ compatible = "gpio-leds"; led2 { - label = "red:system"; + function = LED_FUNCTION_HEARTBEAT; + color = <LED_COLOR_ID_RED>; gpios = <&gpx1 0 GPIO_ACTIVE_HIGH>; default-state = "off"; linux,default-trigger = "heartbeat"; @@ -36,6 +38,7 @@ led3 { label = "red:user"; + color = <LED_COLOR_ID_RED>; gpios = <&gpk1 1 GPIO_ACTIVE_HIGH>; default-state = "off"; }; @@ -44,31 +47,31 @@ gpio-keys { compatible = "gpio-keys"; - home { + key-home { label = "GPIO Key Home"; linux,code = <KEY_HOME>; gpios = <&gpx1 1 GPIO_ACTIVE_LOW>; }; - back { + key-back { label = "GPIO Key Back"; linux,code = <KEY_BACK>; gpios = <&gpx1 2 GPIO_ACTIVE_LOW>; }; - sleep { + key-sleep { label = "GPIO Key Sleep"; linux,code = <KEY_POWER>; gpios = <&gpx3 3 GPIO_ACTIVE_LOW>; }; - vol-up { + key-vol-up { label = "GPIO Key Vol+"; linux,code = <KEY_UP>; gpios = <&gpx2 1 GPIO_ACTIVE_LOW>; }; - vol-down { + key-vol-down { label = "GPIO Key Vol-"; linux,code = <KEY_DOWN>; gpios = <&gpx2 0 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/exynos4412-midas.dtsi b/arch/arm/boot/dts/exynos4412-midas.dtsi index 23f50c9be527..b967397a46c5 100644 --- a/arch/arm/boot/dts/exynos4412-midas.dtsi +++ b/arch/arm/boot/dts/exynos4412-midas.dtsi @@ -12,11 +12,12 @@ /dts-v1/; #include "exynos4412.dtsi" #include "exynos4412-ppmu-common.dtsi" + #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/clock/maxim,max77686.h> -#include <dt-bindings/pinctrl/samsung.h> +#include "exynos-pinctrl.h" / { compatible = "samsung,midas", "samsung,exynos4412", "samsung,exynos4"; diff --git a/arch/arm/boot/dts/exynos4412-odroidu3.dts b/arch/arm/boot/dts/exynos4412-odroidu3.dts index 36c369c42b77..a5ad88b897ff 100644 --- a/arch/arm/boot/dts/exynos4412-odroidu3.dts +++ b/arch/arm/boot/dts/exynos4412-odroidu3.dts @@ -9,6 +9,7 @@ */ /dts-v1/; +#include <dt-bindings/leds/common.h> #include "exynos4412-odroid-common.dtsi" #include "exynos4412-prime.dtsi" @@ -37,7 +38,8 @@ leds { compatible = "gpio-leds"; led1 { - label = "led1:heart"; + function = LED_FUNCTION_HEARTBEAT; + color = <LED_COLOR_ID_BLUE>; gpios = <&gpc1 0 GPIO_ACTIVE_LOW>; default-state = "on"; linux,default-trigger = "heartbeat"; diff --git a/arch/arm/boot/dts/exynos4412-odroidx.dts b/arch/arm/boot/dts/exynos4412-odroidx.dts index 1f17cc30ed14..68d589e081bc 100644 --- a/arch/arm/boot/dts/exynos4412-odroidx.dts +++ b/arch/arm/boot/dts/exynos4412-odroidx.dts @@ -9,6 +9,7 @@ */ /dts-v1/; +#include <dt-bindings/leds/common.h> #include "exynos4412-odroid-common.dtsi" / { @@ -27,13 +28,15 @@ leds { compatible = "gpio-leds"; led1 { - label = "led1:heart"; + function = LED_FUNCTION_HEARTBEAT; + color = <LED_COLOR_ID_BLUE>; gpios = <&gpc1 0 GPIO_ACTIVE_LOW>; default-state = "on"; linux,default-trigger = "heartbeat"; }; led2 { label = "led2:mmc0"; + function = LED_FUNCTION_DISK_ACTIVITY; gpios = <&gpc1 2 GPIO_ACTIVE_LOW>; default-state = "on"; linux,default-trigger = "mmc0"; diff --git a/arch/arm/boot/dts/exynos4412-p4note.dtsi b/arch/arm/boot/dts/exynos4412-p4note.dtsi index 97f131b1014b..7a515b87bc7c 100644 --- a/arch/arm/boot/dts/exynos4412-p4note.dtsi +++ b/arch/arm/boot/dts/exynos4412-p4note.dtsi @@ -15,8 +15,8 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/linux-event-codes.h> #include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/pinctrl/samsung.h> #include <dt-bindings/power/summit,smb347-charger.h> +#include "exynos-pinctrl.h" / { compatible = "samsung,p4note", "samsung,exynos4412", "samsung,exynos4"; @@ -106,6 +106,16 @@ regulator-always-on; }; + panel_vdd: voltage-regulator-4 { + compatible = "regulator-fixed"; + regulator-name = "LCD_ENABLE"; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_enable>; + gpios = <&gpc0 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-boot-on; + }; + wlan_pwrseq: sdhci3-pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&gpm3 5 GPIO_ACTIVE_LOW>; @@ -216,6 +226,32 @@ monitored-battery = <&battery_cell>; }; }; + + panel { + compatible = "samsung,ltl101al01"; + pinctrl-0 = <&lvds_nshdn>; + pinctrl-names = "default"; + power-supply = <&panel_vdd>; + enable-gpios = <&gpm0 5 GPIO_ACTIVE_HIGH>; + backlight = <&backlight>; + + port { + lcd_ep: endpoint { + remote-endpoint = <&fimd_ep>; + }; + }; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pinctrl-0 = <&led_bl_reset>; + pinctrl-names = "default"; + enable-gpios = <&gpm0 1 GPIO_ACTIVE_HIGH>; + pwms = <&pwm 1 78770 0>; + brightness-levels = <0 48 128 255>; + num-interpolated-steps = <8>; + default-brightness-level = <12>; + }; }; &adc { @@ -295,22 +331,19 @@ }; &fimd { - pinctrl-0 = <&lcd_clk &lcd_data24 &pwm1_out>; + pinctrl-0 = <&lcd_clk &lcd_data24>; pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; status = "okay"; - display-timings { - timing0 { - clock-frequency = <66666666>; - hactive = <1280>; - vactive = <800>; - hfront-porch = <18>; - hback-porch = <36>; - hsync-len = <16>; - vback-porch = <16>; - vfront-porch = <4>; - vsync-len = <3>; - hsync-active = <1>; + samsung,invert-vclk; + + port@3 { + reg = <3>; + + fimd_ep: endpoint { + remote-endpoint = <&lcd_ep>; }; }; }; @@ -687,6 +720,12 @@ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; }; + lcd_enable: lcd-enable-pins { + samsung,pins = "gpc0-1"; + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + }; + sleep0: sleep-state { PIN_SLP(gpa0-0, INPUT, NONE); PIN_SLP(gpa0-1, OUT0, NONE); @@ -809,12 +848,24 @@ /* 0 = CP, 1 = AP (serial output) */ }; + led_bl_reset: led-bl-reset-pins { + samsung,pins = "gpm0-1"; + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + }; + tsp_rst: tsp-rst-pins { samsung,pins = "gpm0-4"; samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; }; + lvds_nshdn: lvds-nshdn-pins { + samsung,pins = "gpm0-5"; + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + }; + tsp_irq: tsp-irq-pins { samsung,pins = "gpm2-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_F>; @@ -1100,6 +1151,13 @@ assigned-clock-parents = <&clock CLK_XUSBXTI>; }; +&pwm { + pinctrl-0 = <&pwm1_out>; + pinctrl-names = "default"; + samsung,pwm-outputs = <1>; + status = "okay"; +}; + &rtc { clocks = <&clock CLK_RTC>, <&max77686 MAX77686_CLK_AP>; clock-names = "rtc", "rtc_src"; diff --git a/arch/arm/boot/dts/exynos4412-pinctrl.dtsi b/arch/arm/boot/dts/exynos4412-pinctrl.dtsi index 88b8afd55664..58847d4fa846 100644 --- a/arch/arm/boot/dts/exynos4412-pinctrl.dtsi +++ b/arch/arm/boot/dts/exynos4412-pinctrl.dtsi @@ -9,7 +9,7 @@ * tree nodes are listed in this file. */ -#include <dt-bindings/pinctrl/samsung.h> +#include "exynos-pinctrl.h" #define PIN_SLP(_pin, _mode, _pull) \ _pin { \ diff --git a/arch/arm/boot/dts/exynos4412-tiny4412.dts b/arch/arm/boot/dts/exynos4412-tiny4412.dts index 017b26108bb0..04388c575efe 100644 --- a/arch/arm/boot/dts/exynos4412-tiny4412.dts +++ b/arch/arm/boot/dts/exynos4412-tiny4412.dts @@ -11,6 +11,7 @@ /dts-v1/; #include "exynos4412.dtsi" #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/leds/common.h> / { model = "FriendlyARM TINY4412 board based on Exynos4412"; @@ -30,6 +31,7 @@ led1 { label = "led1"; + function = LED_FUNCTION_HEARTBEAT; gpios = <&gpm4 0 GPIO_ACTIVE_LOW>; default-state = "off"; linux,default-trigger = "heartbeat"; @@ -49,6 +51,7 @@ led4 { label = "led4"; + function = LED_FUNCTION_DISK_ACTIVITY; gpios = <&gpm4 3 GPIO_ACTIVE_LOW>; default-state = "off"; linux,default-trigger = "mmc0"; diff --git a/arch/arm/boot/dts/exynos5.dtsi b/arch/arm/boot/dts/exynos5.dtsi index 9ce9fb3fc190..c8da0d4b1b33 100644 --- a/arch/arm/boot/dts/exynos5.dtsi +++ b/arch/arm/boot/dts/exynos5.dtsi @@ -89,7 +89,7 @@ compatible = "arm,gic-400", "arm,cortex-a15-gic"; #interrupt-cells = <3>; interrupt-controller; - reg = <0x10481000 0x1000>, + reg = <0x10481000 0x1000>, <0x10482000 0x2000>, <0x10484000 0x2000>, <0x10486000 0x2000>; diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts index f7795f2d0f0e..71c0e87d3a1d 100644 --- a/arch/arm/boot/dts/exynos5250-arndale.dts +++ b/arch/arm/boot/dts/exynos5250-arndale.dts @@ -30,42 +30,42 @@ gpio-keys { compatible = "gpio-keys"; - menu { + key-menu { label = "SW-TACT2"; gpios = <&gpx1 4 GPIO_ACTIVE_LOW>; linux,code = <KEY_MENU>; wakeup-source; }; - home { + key-home { label = "SW-TACT3"; gpios = <&gpx1 5 GPIO_ACTIVE_LOW>; linux,code = <KEY_HOME>; wakeup-source; }; - up { + key-up { label = "SW-TACT4"; gpios = <&gpx1 6 GPIO_ACTIVE_LOW>; linux,code = <KEY_UP>; wakeup-source; }; - down { + key-down { label = "SW-TACT5"; gpios = <&gpx1 7 GPIO_ACTIVE_LOW>; linux,code = <KEY_DOWN>; wakeup-source; }; - back { + key-back { label = "SW-TACT6"; gpios = <&gpx2 0 GPIO_ACTIVE_LOW>; linux,code = <KEY_BACK>; wakeup-source; }; - wakeup { + key-wakeup { label = "SW-TACT7"; gpios = <&gpx2 1 GPIO_ACTIVE_LOW>; linux,code = <KEY_WAKEUP>; diff --git a/arch/arm/boot/dts/exynos5250-pinctrl.dtsi b/arch/arm/boot/dts/exynos5250-pinctrl.dtsi index 918947a3897e..48732edadff1 100644 --- a/arch/arm/boot/dts/exynos5250-pinctrl.dtsi +++ b/arch/arm/boot/dts/exynos5250-pinctrl.dtsi @@ -9,7 +9,7 @@ * tree nodes are listed in this file. */ -#include <dt-bindings/pinctrl/samsung.h> +#include "exynos-pinctrl.h" &pinctrl_0 { gpa0: gpa0-gpio-bank { diff --git a/arch/arm/boot/dts/exynos5250-snow-common.dtsi b/arch/arm/boot/dts/exynos5250-snow-common.dtsi index c15ecfc4077d..3d84b9c6dea3 100644 --- a/arch/arm/boot/dts/exynos5250-snow-common.dtsi +++ b/arch/arm/boot/dts/exynos5250-snow-common.dtsi @@ -32,7 +32,7 @@ pinctrl-names = "default"; pinctrl-0 = <&power_key_irq &lid_irq>; - power { + power-key { label = "Power"; gpios = <&gpx1 3 GPIO_ACTIVE_LOW>; linux,code = <KEY_POWER>; diff --git a/arch/arm/boot/dts/exynos5250-spring.dts b/arch/arm/boot/dts/exynos5250-spring.dts index 24609bb20158..5eca10ecd550 100644 --- a/arch/arm/boot/dts/exynos5250-spring.dts +++ b/arch/arm/boot/dts/exynos5250-spring.dts @@ -33,7 +33,7 @@ pinctrl-names = "default"; pinctrl-0 = <&power_key_irq>, <&lid_irq>; - power { + power-key { label = "Power"; gpios = <&gpx1 3 GPIO_ACTIVE_LOW>; linux,code = <KEY_POWER>; diff --git a/arch/arm/boot/dts/exynos5260-pinctrl.dtsi b/arch/arm/boot/dts/exynos5260-pinctrl.dtsi index 150607f8103d..43e4a541f479 100644 --- a/arch/arm/boot/dts/exynos5260-pinctrl.dtsi +++ b/arch/arm/boot/dts/exynos5260-pinctrl.dtsi @@ -9,7 +9,7 @@ * tree nodes are listed in this file. */ -#include <dt-bindings/pinctrl/samsung.h> +#include "exynos-pinctrl.h" &pinctrl_0 { gpa0: gpa0-gpio-bank { diff --git a/arch/arm/boot/dts/exynos5410-pinctrl.dtsi b/arch/arm/boot/dts/exynos5410-pinctrl.dtsi index 6c7814b4372e..f7b923382892 100644 --- a/arch/arm/boot/dts/exynos5410-pinctrl.dtsi +++ b/arch/arm/boot/dts/exynos5410-pinctrl.dtsi @@ -6,7 +6,7 @@ * https://www.hardkernel.com */ -#include <dt-bindings/pinctrl/samsung.h> +#include "exynos-pinctrl.h" &pinctrl_0 { gpa0: gpa0-gpio-bank { diff --git a/arch/arm/boot/dts/exynos5420-arndale-octa.dts b/arch/arm/boot/dts/exynos5420-arndale-octa.dts index 946b791faf85..55b7759682a9 100644 --- a/arch/arm/boot/dts/exynos5420-arndale-octa.dts +++ b/arch/arm/boot/dts/exynos5420-arndale-octa.dts @@ -42,7 +42,7 @@ gpio-keys { compatible = "gpio-keys"; - wakeup { + key-wakeup { label = "SW-TACT1"; gpios = <&gpx2 7 GPIO_ACTIVE_LOW>; linux,code = <KEY_WAKEUP>; diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts index d6434ec86022..9e2123470cad 100644 --- a/arch/arm/boot/dts/exynos5420-peach-pit.dts +++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts @@ -60,7 +60,7 @@ pinctrl-names = "default"; pinctrl-0 = <&power_key_irq &lid_irq>; - power { + power-key { label = "Power"; gpios = <&gpx1 2 GPIO_ACTIVE_LOW>; linux,code = <KEY_POWER>; diff --git a/arch/arm/boot/dts/exynos5420-pinctrl.dtsi b/arch/arm/boot/dts/exynos5420-pinctrl.dtsi index 546ba274f4e5..14cf9c4ca0ed 100644 --- a/arch/arm/boot/dts/exynos5420-pinctrl.dtsi +++ b/arch/arm/boot/dts/exynos5420-pinctrl.dtsi @@ -9,7 +9,7 @@ * tree nodes are listed in this file. */ -#include <dt-bindings/pinctrl/samsung.h> +#include "exynos-pinctrl.h" &pinctrl_0 { gpy7: gpy7-gpio-bank { diff --git a/arch/arm/boot/dts/exynos5422-odroidhc1.dts b/arch/arm/boot/dts/exynos5422-odroidhc1.dts index d91f7fa2cf80..3de7019572a2 100644 --- a/arch/arm/boot/dts/exynos5422-odroidhc1.dts +++ b/arch/arm/boot/dts/exynos5422-odroidhc1.dts @@ -8,6 +8,7 @@ */ /dts-v1/; +#include <dt-bindings/leds/common.h> #include "exynos5422-odroid-core.dtsi" / { @@ -19,7 +20,8 @@ compatible = "pwm-leds"; led-1 { - label = "blue:heartbeat"; + function = LED_FUNCTION_HEARTBEAT; + color = <LED_COLOR_ID_BLUE>; pwms = <&pwm 2 2000000 0>; pwm-names = "pwm2"; max-brightness = <255>; diff --git a/arch/arm/boot/dts/exynos5422-odroidxu4.dts b/arch/arm/boot/dts/exynos5422-odroidxu4.dts index 1c24f9b35973..f5fb617f46bd 100644 --- a/arch/arm/boot/dts/exynos5422-odroidxu4.dts +++ b/arch/arm/boot/dts/exynos5422-odroidxu4.dts @@ -9,6 +9,7 @@ */ /dts-v1/; +#include <dt-bindings/leds/common.h> #include <dt-bindings/sound/samsung-i2s.h> #include "exynos5422-odroidxu3-common.dtsi" @@ -21,7 +22,8 @@ compatible = "pwm-leds"; led-1 { - label = "blue:heartbeat"; + function = LED_FUNCTION_HEARTBEAT; + color = <LED_COLOR_ID_BLUE>; pwms = <&pwm 2 2000000 0>; pwm-names = "pwm2"; max-brightness = <255>; diff --git a/arch/arm/boot/dts/exynos54xx-odroidxu-leds.dtsi b/arch/arm/boot/dts/exynos54xx-odroidxu-leds.dtsi index 982752e1df24..8c0e1716c0b3 100644 --- a/arch/arm/boot/dts/exynos54xx-odroidxu-leds.dtsi +++ b/arch/arm/boot/dts/exynos54xx-odroidxu-leds.dtsi @@ -9,6 +9,7 @@ */ #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/leds/common.h> / { led-controller-1 { @@ -16,6 +17,8 @@ led-1 { label = "green:mmc0"; + function = LED_FUNCTION_DISK_ACTIVITY; + color = <LED_COLOR_ID_GREEN>; pwms = <&pwm 1 2000000 0>; pwm-names = "pwm1"; /* @@ -27,7 +30,8 @@ }; led-2 { - label = "blue:heartbeat"; + function = LED_FUNCTION_HEARTBEAT; + color = <LED_COLOR_ID_BLUE>; pwms = <&pwm 2 2000000 0>; pwm-names = "pwm2"; max-brightness = <255>; @@ -40,6 +44,8 @@ led-3 { label = "red:microSD"; + function = LED_FUNCTION_DISK_ACTIVITY; + color = <LED_COLOR_ID_RED>; gpios = <&gpx2 3 GPIO_ACTIVE_HIGH>; default-state = "off"; linux,default-trigger = "mmc1"; diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts index 4ee76281979c..0ebcb66c6319 100644 --- a/arch/arm/boot/dts/exynos5800-peach-pi.dts +++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts @@ -59,7 +59,7 @@ pinctrl-names = "default"; pinctrl-0 = <&power_key_irq &lid_irq>; - power { + power-key { label = "Power"; gpios = <&gpx1 2 GPIO_ACTIVE_LOW>; linux,code = <KEY_POWER>; diff --git a/arch/arm/boot/dts/imx25.dtsi b/arch/arm/boot/dts/imx25.dtsi index fa8044c21cb8..bc4de0c05511 100644 --- a/arch/arm/boot/dts/imx25.dtsi +++ b/arch/arm/boot/dts/imx25.dtsi @@ -68,7 +68,7 @@ }; }; - soc { + soc: soc { #address-cells = <1>; #size-cells = <1>; compatible = "simple-bus"; diff --git a/arch/arm/boot/dts/imx27.dtsi b/arch/arm/boot/dts/imx27.dtsi index b660c7d05584..e140307be2e7 100644 --- a/arch/arm/boot/dts/imx27.dtsi +++ b/arch/arm/boot/dts/imx27.dtsi @@ -74,14 +74,14 @@ }; }; - soc { + soc: soc { #address-cells = <1>; #size-cells = <1>; compatible = "simple-bus"; interrupt-parent = <&aitc>; ranges; - aipi@10000000 { /* AIPI1 */ + aipi1: aipi@10000000 { /* AIPI1 */ compatible = "fsl,aipi-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; @@ -453,7 +453,7 @@ }; }; - aipi@10020000 { /* AIPI2 */ + aipi2: aipi@10020000 { /* AIPI2 */ compatible = "fsl,aipi-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/imx31.dtsi b/arch/arm/boot/dts/imx31.dtsi index 2adb923c0b27..5c4938b0d5a1 100644 --- a/arch/arm/boot/dts/imx31.dtsi +++ b/arch/arm/boot/dts/imx31.dtsi @@ -48,7 +48,7 @@ reg = <0x68000000 0x100000>; }; - soc { + soc: soc { #address-cells = <1>; #size-cells = <1>; compatible = "simple-bus"; @@ -63,7 +63,7 @@ ranges = <0 0x1fffc000 0x4000>; }; - bus@43f00000 { /* AIPS1 */ + aips1: bus@43f00000 { /* AIPS1 */ compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/imx50.dtsi b/arch/arm/boot/dts/imx50.dtsi index be0de0fd31f9..c0c7575fbecf 100644 --- a/arch/arm/boot/dts/imx50.dtsi +++ b/arch/arm/boot/dts/imx50.dtsi @@ -94,14 +94,14 @@ status = "okay"; }; - soc { + soc: soc { #address-cells = <1>; #size-cells = <1>; compatible = "simple-bus"; interrupt-parent = <&tzic>; ranges; - bus@50000000 { /* AIPS1 */ + aips1: bus@50000000 { /* AIPS1 */ compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; @@ -385,7 +385,7 @@ }; }; - bus@60000000 { /* AIPS2 */ + aips2: bus@60000000 { /* AIPS2 */ compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/imx51-ts4800.dts b/arch/arm/boot/dts/imx51-ts4800.dts index 85654d6baf28..f7408722d68a 100644 --- a/arch/arm/boot/dts/imx51-ts4800.dts +++ b/arch/arm/boot/dts/imx51-ts4800.dts @@ -174,7 +174,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_interrupt_fpga>; interrupt-parent = <&gpio2>; - interrupts= <9 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; interrupt-controller; #interrupt-cells = <1>; }; diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi index 1e20a6639e42..592d9c23a447 100644 --- a/arch/arm/boot/dts/imx51.dtsi +++ b/arch/arm/boot/dts/imx51.dtsi @@ -114,7 +114,7 @@ ports = <&ipu_di0>, <&ipu_di1>; }; - soc { + soc: soc { #address-cells = <1>; #size-cells = <1>; compatible = "simple-bus"; @@ -171,7 +171,7 @@ }; }; - bus@70000000 { /* AIPS1 */ + aips1: bus@70000000 { /* AIPS1 */ compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; @@ -460,7 +460,7 @@ }; }; - bus@80000000 { /* AIPS2 */ + aips2: bus@80000000 { /* AIPS2 */ compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi index 67487f3caee1..b7a6469d3472 100644 --- a/arch/arm/boot/dts/imx53.dtsi +++ b/arch/arm/boot/dts/imx53.dtsi @@ -132,7 +132,7 @@ status = "okay"; }; - soc { + soc: soc { #address-cells = <1>; #size-cells = <1>; compatible = "simple-bus"; @@ -222,7 +222,7 @@ clock-names = "core_clk", "mem_iface_clk"; }; - bus@50000000 { /* AIPS1 */ + aips1: bus@50000000 { /* AIPS1 */ compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; @@ -655,7 +655,7 @@ }; }; - bus@60000000 { /* AIPS2 */ + aips2: bus@60000000 { /* AIPS2 */ compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/imx6dl-plym2m.dts b/arch/arm/boot/dts/imx6dl-plym2m.dts index c4ce23d8ac9f..522660c912a0 100644 --- a/arch/arm/boot/dts/imx6dl-plym2m.dts +++ b/arch/arm/boot/dts/imx6dl-plym2m.dts @@ -196,7 +196,7 @@ compatible = "ti,tsc2046e-adc"; reg = <0>; pinctrl-0 = <&pinctrl_tsc2046>; - pinctrl-names ="default"; + pinctrl-names = "default"; spi-max-frequency = <1000000>; interrupts-extended = <&gpio3 20 IRQ_TYPE_LEVEL_LOW>; #io-channel-cells = <1>; diff --git a/arch/arm/boot/dts/imx6dl-prtvt7.dts b/arch/arm/boot/dts/imx6dl-prtvt7.dts index b86deebef7b7..0a0b7acddfb2 100644 --- a/arch/arm/boot/dts/imx6dl-prtvt7.dts +++ b/arch/arm/boot/dts/imx6dl-prtvt7.dts @@ -344,7 +344,7 @@ compatible = "ti,tsc2046e-adc"; reg = <0>; pinctrl-0 = <&pinctrl_tsc>; - pinctrl-names ="default"; + pinctrl-names = "default"; spi-max-frequency = <1000000>; interrupts-extended = <&gpio3 20 IRQ_TYPE_LEVEL_LOW>; #io-channel-cells = <1>; diff --git a/arch/arm/boot/dts/imx6dl-victgo.dts b/arch/arm/boot/dts/imx6dl-victgo.dts index 516ec915a911..779b52858a25 100644 --- a/arch/arm/boot/dts/imx6dl-victgo.dts +++ b/arch/arm/boot/dts/imx6dl-victgo.dts @@ -144,7 +144,7 @@ compatible = "ti,tsc2046e-adc"; reg = <0>; pinctrl-0 = <&pinctrl_touchscreen>; - pinctrl-names ="default"; + pinctrl-names = "default"; spi-max-frequency = <1000000>; interrupts-extended = <&gpio5 8 IRQ_TYPE_LEVEL_LOW>; #io-channel-cells = <1>; diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi index fdd81fdc3f35..8e0ed209ede0 100644 --- a/arch/arm/boot/dts/imx6dl.dtsi +++ b/arch/arm/boot/dts/imx6dl.dtsi @@ -80,7 +80,7 @@ }; }; - soc { + soc: soc { ocram: sram@900000 { compatible = "mmio-sram"; reg = <0x00900000 0x20000>; diff --git a/arch/arm/boot/dts/imx6q-apalis-eval.dts b/arch/arm/boot/dts/imx6q-apalis-eval.dts index a0683b4aeca1..fa160a389870 100644 --- a/arch/arm/boot/dts/imx6q-apalis-eval.dts +++ b/arch/arm/boot/dts/imx6q-apalis-eval.dts @@ -1,6 +1,6 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT /* - * Copyright 2014-2020 Toradex + * Copyright 2014-2022 Toradex * Copyright 2012 Freescale Semiconductor, Inc. * Copyright 2011 Linaro Ltd. */ @@ -30,89 +30,26 @@ stdout-path = "serial0:115200n8"; }; - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_keys>; - - wakeup { - label = "Wake-Up"; - gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; - linux,code = <KEY_WAKEUP>; - debounce-interval = <10>; - wakeup-source; - }; - }; - - lcd_display: disp0 { - compatible = "fsl,imx-parallel-display"; - #address-cells = <1>; - #size-cells = <0>; - interface-pix-fmt = "rgb24"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu1_lcdif>; - status = "okay"; - - port@0 { - reg = <0>; - - lcd_display_in: endpoint { - remote-endpoint = <&ipu1_di1_disp1>; - }; - }; - - port@1 { - reg = <1>; - - lcd_display_out: endpoint { - remote-endpoint = <&lcd_panel_in>; - }; - }; - }; - - panel: panel { - /* - * edt,et057090dhu: EDT 5.7" LCD TFT - * edt,et070080dh6: EDT 7.0" LCD TFT - */ - compatible = "edt,et057090dhu"; - backlight = <&backlight>; - power-supply = <®_3v3_sw>; - - port { - lcd_panel_in: endpoint { - remote-endpoint = <&lcd_display_out>; - }; - }; - }; - reg_pcie_switch: regulator-pcie-switch { compatible = "regulator-fixed"; - regulator-name = "pcie_switch"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; + enable-active-high; gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "pcie_switch"; startup-delay-us = <100000>; - enable-active-high; status = "okay"; }; reg_3v3_sw: regulator-3v3-sw { compatible = "regulator-fixed"; - regulator-name = "3.3V_SW"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; regulator-always-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "3.3V_SW"; }; }; -&backlight { - brightness-levels = <0 127 191 223 239 247 251 255>; - default-brightness-level = <1>; - power-supply = <®_3v3_sw>; - status = "okay"; -}; - &can1 { xceiver-supply = <®_3v3_sw>; status = "okay"; @@ -123,27 +60,10 @@ status = "okay"; }; -&hdmi { - status = "okay"; -}; - /* I2C1_SDA/SCL on MXM3 209/211 (e.g. RTC on carrier board) */ &i2c1 { status = "okay"; - /* - * Touchscreen is using SODIMM 28/30, also used for PWM<B>, PWM<C>, - * aka pwm2, pwm3. so if you enable touchscreen, disable the pwms - */ - touchscreen@4a { - compatible = "atmel,maxtouch"; - reg = <0x4a>; - interrupt-parent = <&gpio6>; - interrupts = <10 IRQ_TYPE_EDGE_FALLING>; - reset-gpios = <&gpio6 9 GPIO_ACTIVE_LOW>; /* SODIMM 13 */ - status = "disabled"; - }; - pcie-switch@58 { compatible = "plx,pex8605"; reg = <0x58>; @@ -164,14 +84,6 @@ status = "okay"; }; -&ipu1_di1_disp1 { - remote-endpoint = <&lcd_display_in>; -}; - -&ldb { - status = "okay"; -}; - &pcie { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_reset_moci>; @@ -198,11 +110,11 @@ status = "okay"; }; -®_usb_otg_vbus { +®_usb_host_vbus { status = "okay"; }; -®_usb_host_vbus { +®_usb_otg_vbus { status = "okay"; }; @@ -246,28 +158,13 @@ /* MMC1 */ &usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1_4bit &pinctrl_usdhc1_8bit &pinctrl_mmc_cd>; - cd-gpios = <&gpio4 20 GPIO_ACTIVE_LOW>; status = "okay"; }; /* SD1 */ &usdhc2 { + cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc2 &pinctrl_sd_cd>; - cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; status = "okay"; }; - -&iomuxc { - /* - * Mux the Apalis GPIOs - */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_apalis_gpio1 &pinctrl_apalis_gpio2 - &pinctrl_apalis_gpio3 &pinctrl_apalis_gpio4 - &pinctrl_apalis_gpio5 &pinctrl_apalis_gpio6 - &pinctrl_apalis_gpio7 &pinctrl_apalis_gpio8 - >; -}; diff --git a/arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts b/arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts index 86e84781cf5d..44637d606e61 100644 --- a/arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts +++ b/arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts @@ -1,274 +1,37 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT /* - * Copyright 2014-2020 Toradex + * Copyright 2014-2022 Toradex * Copyright 2012 Freescale Semiconductor, Inc. * Copyright 2011 Linaro Ltd. */ -/dts-v1/; - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/input/input.h> -#include <dt-bindings/interrupt-controller/irq.h> -#include "imx6q.dtsi" -#include "imx6qdl-apalis.dtsi" +#include "imx6q-apalis-ixora-v1.2.dts" / { model = "Toradex Apalis iMX6Q/D Module on Ixora Carrier Board V1.1"; - compatible = "toradex,apalis_imx6q-ixora-v1.1", - "toradex,apalis_imx6q-ixora", "toradex,apalis_imx6q", + compatible = "toradex,apalis_imx6q-ixora-v1.1", "toradex,apalis_imx6q", "fsl,imx6q"; - aliases { - i2c0 = &i2c1; - i2c1 = &i2c3; - i2c2 = &i2c2; - rtc0 = &rtc_i2c; - rtc1 = &snvs_rtc; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_keys>; - - wakeup { - label = "Wake-Up"; - gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; - linux,code = <KEY_WAKEUP>; - debounce-interval = <10>; - wakeup-source; - }; - }; - - lcd_display: disp0 { - compatible = "fsl,imx-parallel-display"; - #address-cells = <1>; - #size-cells = <0>; - interface-pix-fmt = "rgb24"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu1_lcdif>; - status = "okay"; - - port@0 { - reg = <0>; - - lcd_display_in: endpoint { - remote-endpoint = <&ipu1_di1_disp1>; - }; - }; - - port@1 { - reg = <1>; - - lcd_display_out: endpoint { - remote-endpoint = <&lcd_panel_in>; - }; - }; - }; - panel: panel { - /* - * edt,et057090dhu: EDT 5.7" LCD TFT - * edt,et070080dh6: EDT 7.0" LCD TFT - */ - compatible = "edt,et057090dhu"; - backlight = <&backlight>; - - port { - lcd_panel_in: endpoint { - remote-endpoint = <&lcd_display_out>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_leds_ixora>; - - led4-green { - label = "LED_4_GREEN"; - gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; - }; - - led4-red { - label = "LED_4_RED"; - gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; - }; - - led5-green { - label = "LED_5_GREEN"; - gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; - }; - - led5-red { - label = "LED_5_RED"; - gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>; - }; - }; }; -&backlight { - brightness-levels = <0 127 191 223 239 247 251 255>; - default-brightness-level = <1>; - status = "okay"; -}; +/delete-node/ &eeprom; +/delete-node/ ®_3v3_vmmc; +/delete-node/ ®_can1_supply; +/delete-node/ ®_can2_supply; &can1 { - status = "okay"; + /delete-property/ xceiver-supply; }; &can2 { - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -/* I2C1_SDA/SCL on MXM3 209/211 (e.g. RTC on carrier board) */ -&i2c1 { - status = "okay"; - - /* - * Touchscreen is using SODIMM 28/30, also used for PWM<B>, PWM<C>, - * aka pwm2, pwm3. so if you enable touchscreen, disable the pwms - */ - touchscreen@4a { - compatible = "atmel,maxtouch"; - reg = <0x4a>; - interrupt-parent = <&gpio6>; - interrupts = <10 IRQ_TYPE_EDGE_FALLING>; - reset-gpios = <&gpio6 9 GPIO_ACTIVE_LOW>; /* SODIMM 13 */ - status = "disabled"; - }; - - /* M41T0M6 real time clock on carrier board */ - rtc_i2c: rtc@68 { - compatible = "st,m41t0"; - reg = <0x68>; - }; -}; - -/* - * I2C3_SDA/SCL (CAM) on MXM3 pin 201/203 (e.g. camera sensor on carrier - * board) - */ -&i2c3 { - status = "okay"; -}; - -&ipu1_di1_disp1 { - remote-endpoint = <&lcd_display_in>; -}; - -&ldb { - status = "okay"; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reset_moci>; - /* active-high meaning opposite of regular PERST# active-low polarity */ - reset-gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>; - reset-gpio-active-high; - status = "okay"; -}; - -&pwm1 { - status = "okay"; -}; - -&pwm2 { - status = "okay"; -}; - -&pwm3 { - status = "okay"; -}; - -&pwm4 { - status = "okay"; -}; - -®_usb_otg_vbus { - status = "okay"; -}; - -®_usb_host_vbus { - status = "okay"; -}; - -&sata { - status = "okay"; -}; - -&sound_spdif { - status = "okay"; -}; - -&spdif { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&uart4 { - status = "okay"; -}; - -&uart5 { - status = "okay"; -}; - -&usbh1 { - vbus-supply = <®_usb_host_vbus>; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - status = "okay"; + /delete-property/ xceiver-supply; }; /* MMC1 */ &usdhc1 { + /delete-property/ cap-power-off-card; + /delete-property/ pinctrl-1; + /delete-property/ vmmc-supply; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1_4bit &pinctrl_mmc_cd>; - cd-gpios = <&gpio4 20 GPIO_ACTIVE_LOW>; - bus-width = <4>; - status = "okay"; -}; - -&iomuxc { - /* - * Mux the Apalis GPIOs - */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_apalis_gpio1 &pinctrl_apalis_gpio2 - &pinctrl_apalis_gpio3 &pinctrl_apalis_gpio4 - &pinctrl_apalis_gpio5 &pinctrl_apalis_gpio6 - &pinctrl_apalis_gpio7 &pinctrl_apalis_gpio8 - >; - - pinctrl_leds_ixora: ledsixoragrp { - fsl,pins = < - MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x1b0b0 - MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x1b0b0 - MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 - MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 - >; - }; }; diff --git a/arch/arm/boot/dts/imx6q-apalis-ixora-v1.2.dts b/arch/arm/boot/dts/imx6q-apalis-ixora-v1.2.dts new file mode 100644 index 000000000000..f9f7d99bd4db --- /dev/null +++ b/arch/arm/boot/dts/imx6q-apalis-ixora-v1.2.dts @@ -0,0 +1,276 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2014-2022 Toradex + * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include "imx6q.dtsi" +#include "imx6qdl-apalis.dtsi" + +/ { + model = "Toradex Apalis iMX6Q/D Module on Ixora Carrier Board V1.2"; + compatible = "toradex,apalis_imx6q-ixora-v1.2", "toradex,apalis_imx6q", + "fsl,imx6q"; + + aliases { + i2c0 = &i2c1; + i2c1 = &i2c3; + i2c2 = &i2c2; + rtc0 = &rtc_i2c; + rtc1 = &snvs_rtc; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_leds_ixora>; + + led4-green { + gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; + label = "LED_4_GREEN"; + }; + + led4-red { + gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; + label = "LED_4_RED"; + }; + + led5-green { + gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; + label = "LED_5_GREEN"; + }; + + led5-red { + gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>; + label = "LED_5_RED"; + }; + }; + + reg_3v3_vmmc: regulator-3v3-vmmc { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio2 0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enable_3v3_vmmc>; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "3v3_vmmc"; + startup-delay-us = <100>; + }; + + reg_can1_supply: regulator-can1-supply { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio2 3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enable_can1_power>; + regulator-name = "can1_supply"; + }; + + reg_can2_supply: regulator-can2-supply { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio3 15 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enable_can2_power>; + regulator-name = "can2_supply"; + }; +}; + +&can1 { + xceiver-supply = <®_can1_supply>; + status = "okay"; +}; + +&can2 { + xceiver-supply = <®_can2_supply>; + status = "okay"; +}; + +&gpio1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart24_forceoff>; + + /* + * uart-2-4-on-x21-enable-hog enables the UART transceiver for Apalis + * UART2 and UART3. If one wants to disable the transceiver force + * the GPIO to output-low, if one wants to control the transceiver + * from user space delete the hog node. + */ + uart-2-4-on-x21-enable-hog { + gpio-hog; + gpios = <11 GPIO_ACTIVE_HIGH>; /* MXM3 180 */ + output-high; + }; +}; + +/* I2C1_SDA/SCL on MXM3 209/211 (e.g. RTC on carrier board) */ +&i2c1 { + status = "okay"; + + /* M41T0M6 real time clock on carrier board */ + rtc_i2c: rtc@68 { + compatible = "st,m41t0"; + reg = <0x68>; + }; + + eeprom: eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + pagesize = <16>; + }; +}; + +/* + * I2C3_SDA/SCL (CAM) on MXM3 pin 201/203 (e.g. camera sensor on carrier + * board) + */ +&i2c3 { + status = "okay"; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reset_moci>; + /* active-high meaning opposite of regular PERST# active-low polarity */ + reset-gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>; + reset-gpio-active-high; + status = "okay"; +}; + +&pwm1 { + status = "okay"; +}; + +&pwm2 { + status = "okay"; +}; + +&pwm3 { + status = "okay"; +}; + +&pwm4 { + status = "okay"; +}; + +®_usb_host_vbus { + status = "okay"; +}; + +®_usb_otg_vbus { + status = "okay"; +}; + +&sata { + status = "okay"; +}; + +&sound_spdif { + status = "okay"; +}; + +&spdif { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&uart4 { + status = "okay"; +}; + +&uart5 { + status = "okay"; +}; + +&usbh1 { + vbus-supply = <®_usb_host_vbus>; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + status = "okay"; +}; + +/* MMC1 */ +&usdhc1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_usdhc1_4bit &pinctrl_mmc_cd>; + pinctrl-1 = <&pinctrl_usdhc1_4bit_sleep &pinctrl_mmc_cd_sleep>; + bus-width = <4>; + cap-power-off-card; + vmmc-supply = <®_3v3_vmmc>; + status = "okay"; +}; + +&iomuxc { + pinctrl_enable_3v3_vmmc: enable3v3vmmcgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0 + >; + }; + + pinctrl_enable_can1_power: enablecan1powergrp { + fsl,pins = < + MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 + >; + }; + + pinctrl_enable_can2_power: enablecan2powergrp { + fsl,pins = < + MX6QDL_PAD_EIM_DA15__GPIO3_IO15 0x1b0b0 + >; + }; + + pinctrl_uart24_forceoff: uart24forceoffgrp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__GPIO1_IO11 0x1b0b0 + >; + }; + + pinctrl_leds_ixora: ledsixoragrp { + fsl,pins = < + MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x1b0b0 + MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x1b0b0 + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 + MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 + >; + }; + + pinctrl_mmc_cd_sleep: mmccdslpgrp { + fsl,pins = < + /* MMC1 CD */ + MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x0 + >; + }; + + pinctrl_usdhc1_4bit_sleep: usdhc1-4bitslpgrp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x3000 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x3000 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x3000 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x3000 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x3000 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x3000 + >; + }; +}; diff --git a/arch/arm/boot/dts/imx6q-apalis-ixora.dts b/arch/arm/boot/dts/imx6q-apalis-ixora.dts index 62e72773e53b..ce39c6a3f640 100644 --- a/arch/arm/boot/dts/imx6q-apalis-ixora.dts +++ b/arch/arm/boot/dts/imx6q-apalis-ixora.dts @@ -1,6 +1,6 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT /* - * Copyright 2014-2020 Toradex + * Copyright 2014-2022 Toradex * Copyright 2012 Freescale Semiconductor, Inc. * Copyright 2011 Linaro Ltd. */ @@ -30,95 +30,33 @@ stdout-path = "serial0:115200n8"; }; - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_keys>; - - wakeup { - label = "Wake-Up"; - gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; - linux,code = <KEY_WAKEUP>; - debounce-interval = <10>; - wakeup-source; - }; - }; - - lcd_display: disp0 { - compatible = "fsl,imx-parallel-display"; - #address-cells = <1>; - #size-cells = <0>; - interface-pix-fmt = "rgb24"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu1_lcdif>; - status = "okay"; - - port@0 { - reg = <0>; - - lcd_display_in: endpoint { - remote-endpoint = <&ipu1_di1_disp1>; - }; - }; - - port@1 { - reg = <1>; - - lcd_display_out: endpoint { - remote-endpoint = <&lcd_panel_in>; - }; - }; - }; - - panel: panel { - /* - * edt,et057090dhu: EDT 5.7" LCD TFT - * edt,et070080dh6: EDT 7.0" LCD TFT - */ - compatible = "edt,et057090dhu"; - backlight = <&backlight>; - - port { - lcd_panel_in: endpoint { - remote-endpoint = <&lcd_display_out>; - }; - }; - }; - leds { compatible = "gpio-leds"; - pinctrl-names = "default"; pinctrl-0 = <&pinctrl_leds_ixora>; led4-green { - label = "LED_4_GREEN"; gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>; + label = "LED_4_GREEN"; }; led4-red { - label = "LED_4_RED"; gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; + label = "LED_4_RED"; }; led5-green { - label = "LED_5_GREEN"; gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; + label = "LED_5_GREEN"; }; led5-red { - label = "LED_5_RED"; gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>; + label = "LED_5_RED"; }; }; }; -&backlight { - brightness-levels = <0 127 191 223 239 247 251 255>; - default-brightness-level = <1>; - status = "okay"; -}; - &can1 { status = "okay"; }; @@ -127,27 +65,10 @@ status = "okay"; }; -&hdmi { - status = "okay"; -}; - /* I2C1_SDA/SCL on MXM3 209/211 (e.g. RTC on carrier board) */ &i2c1 { status = "okay"; - /* - * Touchscreen is using SODIMM 28/30, also used for PWM<B>, PWM<C>, - * aka pwm2, pwm3. so if you enable touchscreen, disable the pwms - */ - touchscreen@4a { - compatible = "atmel,maxtouch"; - reg = <0x4a>; - interrupt-parent = <&gpio6>; - interrupts = <10 IRQ_TYPE_EDGE_FALLING>; - reset-gpios = <&gpio6 9 GPIO_ACTIVE_LOW>; /* SODIMM 13 */ - status = "disabled"; - }; - eeprom@50 { compatible = "atmel,24c02"; reg = <0x50>; @@ -168,14 +89,6 @@ status = "okay"; }; -&ipu1_di1_disp1 { - remote-endpoint = <&lcd_display_in>; -}; - -&ldb { - status = "okay"; -}; - &pcie { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_reset_moci>; @@ -201,11 +114,11 @@ status = "okay"; }; -®_usb_otg_vbus { +®_usb_host_vbus { status = "okay"; }; -®_usb_host_vbus { +®_usb_otg_vbus { status = "okay"; }; @@ -249,21 +162,13 @@ /* SD1 */ &usdhc2 { + cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc2 &pinctrl_sd_cd>; - cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; status = "okay"; }; &iomuxc { - /* Mux the Apalis GPIOs */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_apalis_gpio1 &pinctrl_apalis_gpio2 - &pinctrl_apalis_gpio3 &pinctrl_apalis_gpio4 - &pinctrl_apalis_gpio5 &pinctrl_apalis_gpio6 - &pinctrl_apalis_gpio7 &pinctrl_apalis_gpio8 - >; - pinctrl_leds_ixora: ledsixoragrp { fsl,pins = < MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x1b0b0 diff --git a/arch/arm/boot/dts/imx6q-bosch-acc.dts b/arch/arm/boot/dts/imx6q-bosch-acc.dts index 8768222e183e..8263bfef9bf8 100644 --- a/arch/arm/boot/dts/imx6q-bosch-acc.dts +++ b/arch/arm/boot/dts/imx6q-bosch-acc.dts @@ -570,7 +570,7 @@ cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; no-1-8-v; keep-power-in-suspend; - enable-sdio-wakeup; + wakeup-source; voltage-ranges = <3300 3300>; vmmc-supply = <®_sw4>; fsl,wp-controller; @@ -594,7 +594,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_wdog1>; fsl,ext-reset-output; - timeout-sec=<10>; + timeout-sec = <10>; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6q-skov-reve-mi1010ait-1cp1.dts b/arch/arm/boot/dts/imx6q-skov-reve-mi1010ait-1cp1.dts index 7f1f19b74bfa..a3f247c722b4 100644 --- a/arch/arm/boot/dts/imx6q-skov-reve-mi1010ait-1cp1.dts +++ b/arch/arm/boot/dts/imx6q-skov-reve-mi1010ait-1cp1.dts @@ -125,3 +125,9 @@ >; }; }; + +®_tft_vcom { + regulator-min-microvolt = <3160000>; + regulator-max-microvolt = <3160000>; + voltage-table = <3160000 73>; +}; diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi index 9caba4529c71..3b77eae40e39 100644 --- a/arch/arm/boot/dts/imx6q.dtsi +++ b/arch/arm/boot/dts/imx6q.dtsi @@ -159,14 +159,14 @@ }; }; - soc { + soc: soc { ocram: sram@900000 { compatible = "mmio-sram"; reg = <0x00900000 0x40000>; clocks = <&clks IMX6QDL_CLK_OCRAM>; }; - bus@2000000 { /* AIPS1 */ + aips1: bus@2000000 { /* AIPS1 */ spba-bus@2000000 { ecspi5: spi@2018000 { #address-cells = <1>; diff --git a/arch/arm/boot/dts/imx6qdl-apalis.dtsi b/arch/arm/boot/dts/imx6qdl-apalis.dtsi index bd763bae596b..7c17b91f0965 100644 --- a/arch/arm/boot/dts/imx6qdl-apalis.dtsi +++ b/arch/arm/boot/dts/imx6qdl-apalis.dtsi @@ -1,11 +1,12 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT /* - * Copyright 2014-2020 Toradex + * Copyright 2014-2022 Toradex * Copyright 2012 Freescale Semiconductor, Inc. * Copyright 2011 Linaro Ltd. */ #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pwm/pwm.h> / { model = "Toradex Apalis iMX6Q/D Module"; @@ -19,88 +20,182 @@ backlight: backlight { compatible = "pwm-backlight"; + brightness-levels = <0 45 63 88 119 158 203 255>; + default-brightness-level = <4>; + enable-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_bl_on>; - pwms = <&pwm4 0 5000000>; - enable-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>; + power-supply = <®_module_3v3>; + pwms = <&pwm4 0 5000000 PWM_POLARITY_INVERTED>; + status = "disabled"; + }; + + clk_ov5640_osc: clk-ov5640-osc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + wakeup { + debounce-interval = <10>; + gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; + label = "Wake-Up"; + linux,code = <KEY_WAKEUP>; + wakeup-source; + }; + }; + + lcd_display: disp0 { + compatible = "fsl,imx-parallel-display"; + #address-cells = <1>; + #size-cells = <0>; + interface-pix-fmt = "rgb24"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1_lcdif>; status = "disabled"; + + port@0 { + reg = <0>; + + lcd_display_in: endpoint { + remote-endpoint = <&ipu1_di1_disp1>; + }; + }; + + port@1 { + reg = <1>; + + lcd_display_out: endpoint { + remote-endpoint = <&lcd_panel_in>; + }; + }; + }; + + panel_dpi: panel-dpi { + compatible = "edt,et057090dhu"; + backlight = <&backlight>; + + status = "disabled"; + + port { + lcd_panel_in: endpoint { + remote-endpoint = <&lcd_display_out>; + }; + }; + }; + + panel_lvds: panel-lvds { + compatible = "panel-lvds"; + backlight = <&backlight>; + status = "disabled"; + + port { + lvds_panel_in: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; }; reg_module_3v3: regulator-module-3v3 { compatible = "regulator-fixed"; - regulator-name = "+V3.3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; regulator-always-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "+V3.3"; }; reg_module_3v3_audio: regulator-module-3v3-audio { compatible = "regulator-fixed"; - regulator-name = "+V3.3_AUDIO"; - regulator-min-microvolt = <3300000>; + regulator-always-on; regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "+V3.3_AUDIO"; + }; + + reg_ov5640_1v8_d_o_vdd: regulator-ov5640-1v8-d-o-vdd { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "DOVDD/DVDD_1.8V"; + /* Note: The CSI module uses on-board 3.3V_SW supply */ + vin-supply = <®_module_3v3>; + }; + + reg_ov5640_2v8_a_vdd: regulator-ov5640-2v8-a-vdd { + compatible = "regulator-fixed"; regulator-always-on; + regulator-max-microvolt = <2800000>; + regulator-min-microvolt = <2800000>; + regulator-name = "AVDD/AFVDD_2.8V"; + /* Note: The CSI module uses on-board 3.3V_SW supply */ + vin-supply = <®_module_3v3>; }; reg_usb_otg_vbus: regulator-usb-otg-vbus { compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_regulator_usbotg_pwr>; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; - gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; - enable-active-high; + regulator-min-microvolt = <5000000>; + regulator-name = "usb_otg_vbus"; status = "disabled"; }; /* on module USB hub */ reg_usb_host_vbus_hub: regulator-usb-host-vbus-hub { compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio3 28 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_regulator_usbhub_pwr>; - regulator-name = "usb_host_vbus_hub"; - regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; - gpio = <&gpio3 28 GPIO_ACTIVE_HIGH>; + regulator-min-microvolt = <5000000>; + regulator-name = "usb_host_vbus_hub"; startup-delay-us = <2000>; - enable-active-high; status = "okay"; }; reg_usb_host_vbus: regulator-usb-host-vbus { compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_regulator_usbh_pwr>; - regulator-name = "usb_host_vbus"; - regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; - gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; - enable-active-high; + regulator-min-microvolt = <5000000>; + regulator-name = "usb_host_vbus"; vin-supply = <®_usb_host_vbus_hub>; status = "disabled"; }; sound { compatible = "fsl,imx-audio-sgtl5000"; - model = "imx6q-apalis-sgtl5000"; - ssi-controller = <&ssi1>; audio-codec = <&codec>; audio-routing = "LINE_IN", "Line In Jack", "MIC_IN", "Mic Jack", "Mic Jack", "Mic Bias", "Headphone Jack", "HP_OUT"; - mux-int-port = <1>; + model = "imx6q-apalis-sgtl5000"; mux-ext-port = <4>; + mux-int-port = <1>; + ssi-controller = <&ssi1>; }; sound_spdif: sound-spdif { compatible = "fsl,imx-audio-spdif"; - model = "imx-spdif"; spdif-controller = <&spdif>; spdif-in; spdif-out; + model = "imx-spdif"; status = "disabled"; }; }; @@ -125,6 +220,10 @@ status = "disabled"; }; +&clks { + fsl,pmic-stby-poweroff; +}; + /* Apalis SPI1 */ &ecspi1 { cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>; @@ -141,6 +240,214 @@ status = "disabled"; }; +&gpio1 { + gpio-line-names = "MXM3_84", + "MXM3_4", + "MXM3_15/GPIO7", + "MXM3_96", + "MXM3_37", + "", + "MXM3_17/GPIO8", + "MXM3_14", + "MXM3_12", + "MXM3_2", + "MXM3_184", + "MXM3_180", + "MXM3_178", + "MXM3_176", + "MXM3_188", + "MXM3_186", + "MXM3_160", + "MXM3_162", + "MXM3_150", + "MXM3_144", + "MXM3_154", + "MXM3_146", + "", + "", + "MXM3_72"; +}; + +&gpio2 { + gpio-line-names = "MXM3_148", + "MXM3_152", + "MXM3_156", + "MXM3_158", + "MXM3_1/GPIO1", + "MXM3_3/GPIO2", + "MXM3_5/GPIO3", + "MXM3_7/GPIO4", + "MXM3_95", + "MXM3_6", + "MXM3_8", + "MXM3_123", + "MXM3_126", + "MXM3_128", + "MXM3_130", + "MXM3_132", + "MXM3_253", + "MXM3_251", + "MXM3_283", + "MXM3_281", + "MXM3_279", + "MXM3_277", + "MXM3_243", + "MXM3_235", + "MXM3_231", + "MXM3_229", + "MXM3_233", + "MXM3_198", + "MXM3_275", + "MXM3_273", + "MXM3_207", + "MXM3_122"; +}; + +&gpio3 { + gpio-line-names = "MXM3_271", + "MXM3_269", + "MXM3_301", + "MXM3_299", + "MXM3_297", + "MXM3_295", + "MXM3_293", + "MXM3_291", + "MXM3_289", + "MXM3_287", + "MXM3_249", + "MXM3_247", + "MXM3_245", + "MXM3_286", + "MXM3_239", + "MXM3_35", + "MXM3_205", + "MXM3_203", + "MXM3_201", + "MXM3_116", + "MXM3_114", + "MXM3_262", + "MXM3_274", + "MXM3_124", + "MXM3_110", + "MXM3_120", + "MXM3_263", + "MXM3_265", + "", + "MXM3_135", + "MXM3_261", + "MXM3_259"; +}; + +&gpio4 { + gpio-line-names = "", + "", + "", + "", + "", + "MXM3_194", + "MXM3_136", + "MXM3_134", + "MXM3_140", + "MXM3_138", + "", + "MXM3_220", + "", + "", + "MXM3_18", + "MXM3_16", + "", + "", + "MXM3_214", + "MXM3_216", + "MXM3_164"; +}; + +&gpio5 { + gpio-line-names = "MXM3_159", + "", + "", + "", + "MXM3_257", + "", + "", + "", + "", + "", + "MXM3_200", + "MXM3_196", + "MXM3_204", + "MXM3_202", + "", + "", + "", + "", + "MXM3_191", + "MXM3_197", + "MXM3_77", + "MXM3_195", + "MXM3_221", + "MXM3_225", + "MXM3_223", + "MXM3_227", + "MXM3_209", + "MXM3_211", + "MXM3_118", + "MXM3_112", + "MXM3_187", + "MXM3_185"; +}; + +&gpio6 { + gpio-line-names = "MXM3_183", + "MXM3_181", + "MXM3_179", + "MXM3_177", + "MXM3_175", + "MXM3_173", + "MXM3_255", + "MXM3_83", + "MXM3_91", + "MXM3_13/GPIO6", + "MXM3_11/GPIO5", + "MXM3_79", + "", + "", + "MXM3_190", + "MXM3_193", + "MXM3_89"; +}; + +&gpio7 { + gpio-line-names = "", + "", + "", + "", + "", + "", + "", + "", + "", + "MXM3_99", + "MXM3_85", + "MXM3_217", + "MXM3_215"; +}; + +&gpr { + ipu1_csi0_mux { + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + port@1 { + reg = <1>; + ipu1_csi0_mux_from_parallel_sensor: endpoint { + remote-endpoint = <&adv7280_to_ipu1_csi0_mux>; + }; + }; + }; +}; + &fec { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet>; @@ -177,6 +484,16 @@ scl-gpios = <&gpio5 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios = <&gpio5 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "disabled"; + + atmel_mxt_ts: touchscreen@4a { + compatible = "atmel,maxtouch"; + /* These GPIOs are muxed with the iomuxc node */ + interrupt-parent = <&gpio6>; + interrupts = <10 IRQ_TYPE_EDGE_FALLING>; /* MXM3_11 */ + reg = <0x4a>; + reset-gpios = <&gpio6 9 GPIO_ACTIVE_LOW>; /* MXM3_13 */ + status = "disabled"; + }; }; /* @@ -192,103 +509,105 @@ sda-gpios = <&gpio4 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; - pmic: pfuze100@8 { + pmic: pmic@8 { compatible = "fsl,pfuze100"; + fsl,pmic-stby-poweroff; reg = <0x08>; regulators { sw1a_reg: sw1ab { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1875000>; + regulator-min-microvolt = <300000>; regulator-ramp-delay = <6250>; }; sw1c_reg: sw1c { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1875000>; + regulator-min-microvolt = <300000>; regulator-ramp-delay = <6250>; }; sw3a_reg: sw3a { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-boot-on; regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1975000>; + regulator-min-microvolt = <400000>; }; swbst_reg: swbst { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5150000>; - regulator-boot-on; regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <5150000>; + regulator-min-microvolt = <5000000>; }; snvs_reg: vsnvs { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3000000>; + regulator-min-microvolt = <1000000>; }; vref_reg: vrefddr { - regulator-boot-on; regulator-always-on; + regulator-boot-on; }; vgen1_reg: vgen1 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - regulator-boot-on; regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1550000>; + regulator-min-microvolt = <800000>; }; vgen2_reg: vgen2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - regulator-boot-on; regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1550000>; + regulator-min-microvolt = <800000>; }; vgen3_reg: vgen3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1800000>; }; vgen4_reg: vgen4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; }; vgen5_reg: vgen5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1800000>; }; vgen6_reg: vgen6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1800000>; }; }; }; codec: sgtl5000@a { compatible = "fsl,sgtl5000"; - reg = <0x0a>; + #sound-dai-cells = <0>; + clocks = <&clks IMX6QDL_CLK_CKO>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sgtl5000>; - clocks = <&clks IMX6QDL_CLK_CKO>; + reg = <0x0a>; VDDA-supply = <®_module_3v3_audio>; VDDIO-supply = <®_module_3v3>; VDDD-supply = <&vgen4_reg>; @@ -297,15 +616,15 @@ /* STMPE811 touch screen controller */ stmpe811@41 { compatible = "st,stmpe811"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_touch_int>; - reg = <0x41>; + blocks = <0x5>; + id = <0>; interrupts = <10 IRQ_TYPE_LEVEL_LOW>; - interrupt-parent = <&gpio4>; interrupt-controller; - id = <0>; - blocks = <0x5>; + interrupt-parent = <&gpio4>; irq-trigger = <0x1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_touch_int>; + reg = <0x41>; /* 3.25 MHz ADC clock speed */ st,adc-freq = <1>; /* 12-bit ADC */ @@ -315,7 +634,7 @@ /* ADC conversion time: 80 clocks */ st,sample-time = <4>; - stmpe_touchscreen: stmpe-touchscreen { + stmpe_ts: stmpe_touchscreen { compatible = "st,stmpe-ts"; /* 8 sample average control */ st,ave-ctrl = <3>; @@ -330,13 +649,14 @@ st,settling = <3>; /* 5 ms touch detect interrupt delay */ st,touch-det-delay = <5>; + status = "disabled"; }; - stmpe_adc: stmpe-adc { + stmpe_adc: stmpe_adc { compatible = "st,stmpe-adc"; + #io-channel-cells = <1>; /* forbid to use ADC channels 3-0 (touch) */ st,norequest-mask = <0x0F>; - #io-channel-cells = <1>; }; }; }; @@ -353,6 +673,90 @@ scl-gpios = <&gpio3 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios = <&gpio3 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "disabled"; + + adv_7280: adv7280@21 { + compatible = "adi,adv7280"; + adv,force-bt656-4; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1_csi0>; + reg = <0x21>; + status = "disabled"; + + port { + adv7280_to_ipu1_csi0_mux: endpoint { + bus-width = <8>; + remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>; + }; + }; + }; + + ov5640_csi_cam: ov5640_mipi@3c { + compatible = "ovti,ov5640"; + AVDD-supply = <®_ov5640_2v8_a_vdd>; + DOVDD-supply = <®_ov5640_1v8_d_o_vdd>; + DVDD-supply = <®_ov5640_1v8_d_o_vdd>; + clock-names = "xclk"; + clocks = <&clks IMX6QDL_CLK_CKO2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_cam_mclk>; + /* These GPIOs are muxed with the iomuxc node */ + powerdown-gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; + reg = <0x3c>; + reset-gpios = <&gpio2 4 GPIO_ACTIVE_LOW>; + status = "disabled"; + + port { + ov5640_to_mipi_csi2: endpoint { + clock-lanes = <0>; + data-lanes = <1 2>; + remote-endpoint = <&mipi_csi_from_ov5640>; + }; + }; + }; +}; + +&ipu1_di1_disp1 { + remote-endpoint = <&lcd_display_in>; +}; + +&ldb { + lvds-channel@0 { + port@4 { + reg = <4>; + + lvds0_out: endpoint { + remote-endpoint = <&lvds_panel_in>; + }; + }; + }; + + lvds-channel@1 { + fsl,data-mapping = "spwg"; + fsl,data-width = <18>; + + port@4 { + reg = <4>; + + lvds1_out: endpoint { + }; + }; + }; +}; + +&mipi_csi { + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + port@0 { + reg = <0>; + + mipi_csi_from_ov5640: endpoint { + clock-lanes = <0>; + data-lanes = <1 2>; + remote-endpoint = <&ov5640_to_mipi_csi2>; + }; + }; }; &pwm1 { @@ -374,7 +778,6 @@ }; &pwm4 { - #pwm-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm4>; status = "disabled"; @@ -391,72 +794,73 @@ }; &uart1 { + fsl,dte-mode; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_dte &pinctrl_uart1_ctrl>; - fsl,dte-mode; uart-has-rtscts; status = "disabled"; }; &uart2 { + fsl,dte-mode; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2_dte>; - fsl,dte-mode; uart-has-rtscts; status = "disabled"; }; &uart4 { + fsl,dte-mode; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart4_dte>; - fsl,dte-mode; status = "disabled"; }; &uart5 { + fsl,dte-mode; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart5_dte>; - fsl,dte-mode; status = "disabled"; }; &usbotg { + disable-over-current; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; status = "disabled"; }; /* MMC1 */ &usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1_4bit &pinctrl_usdhc1_8bit>; - vqmmc-supply = <®_module_3v3>; bus-width = <8>; + cd-gpios = <&gpio4 20 GPIO_ACTIVE_LOW>; disable-wp; no-1-8-v; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1_4bit &pinctrl_usdhc1_8bit &pinctrl_mmc_cd>; + vqmmc-supply = <®_module_3v3>; status = "disabled"; }; /* SD1 */ &usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - vqmmc-supply = <®_module_3v3>; bus-width = <4>; disable-wp; no-1-8-v; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + vqmmc-supply = <®_module_3v3>; status = "disabled"; }; /* eMMC */ &usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - vqmmc-supply = <®_module_3v3>; bus-width = <8>; no-1-8-v; non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + vqmmc-supply = <®_module_3v3>; status = "okay"; }; @@ -465,49 +869,57 @@ }; &iomuxc { - pinctrl_apalis_gpio1: gpio2io04grp { + /* Mux the Apalis GPIOs */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_apalis_gpio1 &pinctrl_apalis_gpio2 + &pinctrl_apalis_gpio3 &pinctrl_apalis_gpio4 + &pinctrl_apalis_gpio5 &pinctrl_apalis_gpio6 + &pinctrl_apalis_gpio7 &pinctrl_apalis_gpio8 + >; + + pinctrl_apalis_gpio1: apalisgpio1grp { fsl,pins = < MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x130b0 >; }; - pinctrl_apalis_gpio2: gpio2io05grp { + pinctrl_apalis_gpio2: apalisgpio2grp { fsl,pins = < MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x130b0 >; }; - pinctrl_apalis_gpio3: gpio2io06grp { + pinctrl_apalis_gpio3: apalisgpio3grp { fsl,pins = < MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x130b0 >; }; - pinctrl_apalis_gpio4: gpio2io07grp { + pinctrl_apalis_gpio4: apalisgpio4grp { fsl,pins = < MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x130b0 >; }; - pinctrl_apalis_gpio5: gpio6io10grp { + pinctrl_apalis_gpio5: apalisgpio5grp { fsl,pins = < MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x130b0 >; }; - pinctrl_apalis_gpio6: gpio6io09grp { + pinctrl_apalis_gpio6: apalisgpio6grp { fsl,pins = < MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x130b0 >; }; - pinctrl_apalis_gpio7: gpio1io02grp { + pinctrl_apalis_gpio7: apalisgpio7grp { fsl,pins = < MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x130b0 >; }; - pinctrl_apalis_gpio8: gpio1io06grp { + pinctrl_apalis_gpio8: apalisgpio8grp { fsl,pins = < MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x130b0 >; @@ -600,7 +1012,7 @@ >; }; - pinctrl_gpio_bl_on: gpioblon { + pinctrl_gpio_bl_on: gpioblongrp { fsl,pins = < MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x1b0b0 >; @@ -745,7 +1157,7 @@ >; }; - pinctrl_mmc_cd: gpiommccdgrp { + pinctrl_mmc_cd: mmccdgrp { fsl,pins = < /* MMC1 CD */ MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x000b0 @@ -776,35 +1188,35 @@ >; }; - pinctrl_regulator_usbh_pwr: gpioregusbhpwrgrp { + pinctrl_regulator_usbh_pwr: regusbhpwrgrp { fsl,pins = < /* USBH_EN */ MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x0f058 >; }; - pinctrl_regulator_usbhub_pwr: gpioregusbhubpwrgrp { + pinctrl_regulator_usbhub_pwr: regusbhubpwrgrp { fsl,pins = < /* USBH_HUB_EN */ MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x0f058 >; }; - pinctrl_regulator_usbotg_pwr: gpioregusbotgpwrgrp { + pinctrl_regulator_usbotg_pwr: regusbotgpwrgrp { fsl,pins = < /* USBO1 power en */ MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x0f058 >; }; - pinctrl_reset_moci: gpioresetmocigrp { + pinctrl_reset_moci: resetmocigrp { fsl,pins = < /* RESET_MOCI control */ MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x0f058 >; }; - pinctrl_sd_cd: gpiosdcdgrp { + pinctrl_sd_cd: sdcdgrp { fsl,pins = < /* SD1 CD */ MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x000b0 @@ -824,13 +1236,22 @@ >; }; - pinctrl_touch_int: gpiotouchintgrp { + pinctrl_touch_int: touchintgrp { fsl,pins = < /* STMPE811 interrupt */ MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 >; }; + /* Additional DTR, DSR, DCD */ + pinctrl_uart1_ctrl: uart1ctrlgrp { + fsl,pins = < + MX6QDL_PAD_EIM_D23__UART1_DCD_B 0x1b0b0 + MX6QDL_PAD_EIM_D24__UART1_DTR_B 0x1b0b0 + MX6QDL_PAD_EIM_D25__UART1_DSR_B 0x1b0b0 + >; + }; + pinctrl_uart1_dce: uart1dcegrp { fsl,pins = < MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 @@ -848,15 +1269,6 @@ >; }; - /* Additional DTR, DSR, DCD */ - pinctrl_uart1_ctrl: uart1ctrlgrp { - fsl,pins = < - MX6QDL_PAD_EIM_D23__UART1_DCD_B 0x1b0b0 - MX6QDL_PAD_EIM_D24__UART1_DTR_B 0x1b0b0 - MX6QDL_PAD_EIM_D25__UART1_DSR_B 0x1b0b0 - >; - }; - pinctrl_uart2_dce: uart2dcegrp { fsl,pins = < MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 @@ -910,7 +1322,7 @@ >; }; - pinctrl_usdhc1_4bit: usdhc1grp_4bit { + pinctrl_usdhc1_4bit: usdhc1-4bitgrp { fsl,pins = < MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10071 @@ -921,7 +1333,7 @@ >; }; - pinctrl_usdhc1_8bit: usdhc1grp_8bit { + pinctrl_usdhc1_8bit: usdhc1-8bitgrp { fsl,pins = < MX6QDL_PAD_NANDF_D0__SD1_DATA4 0x17071 MX6QDL_PAD_NANDF_D1__SD1_DATA5 0x17071 diff --git a/arch/arm/boot/dts/imx6qdl-colibri.dtsi b/arch/arm/boot/dts/imx6qdl-colibri.dtsi index 7df270cea292..023e76215064 100644 --- a/arch/arm/boot/dts/imx6qdl-colibri.dtsi +++ b/arch/arm/boot/dts/imx6qdl-colibri.dtsi @@ -6,6 +6,7 @@ */ #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pwm/pwm.h> / { model = "Toradex Colibri iMX6DL/S Module"; @@ -13,13 +14,13 @@ backlight: backlight { compatible = "pwm-backlight"; - brightness-levels = <0 127 191 223 239 247 251 255>; - default-brightness-level = <1>; + brightness-levels = <0 45 63 88 119 158 203 255>; + default-brightness-level = <4>; enable-gpios = <&gpio3 26 GPIO_ACTIVE_HIGH>; /* Colibri BL_ON */ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_bl_on>; power-supply = <®_module_3v3>; - pwms = <&pwm3 0 5000000>; + pwms = <&pwm3 0 5000000 PWM_POLARITY_INVERTED>; status = "disabled"; }; @@ -520,6 +521,8 @@ compatible = "fsl,sgtl5000"; clocks = <&clks IMX6QDL_CLK_CKO>; lrclk-strength = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sgtl5000>; reg = <0x0a>; #sound-dai-cells = <0>; VDDA-supply = <®_module_3v3_audio>; @@ -618,7 +621,6 @@ /* Colibri PWM<A> */ &pwm3 { - #pwm-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm3>; status = "disabled"; @@ -739,8 +741,6 @@ pinctrl_audmux: audmuxgrp { fsl,pins = < - /* SGTL5000 sys_mclk */ - MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0 MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0 MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x130b0 MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x130b0 @@ -991,6 +991,13 @@ >; }; + pinctrl_sgtl5000: sgtl5000grp { + fsl,pins = < + /* SGTL5000 sys_mclk */ + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0 + >; + }; + pinctrl_spdif: spdifgrp { fsl,pins = < MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0 diff --git a/arch/arm/boot/dts/imx6qdl-prti6q.dtsi b/arch/arm/boot/dts/imx6qdl-prti6q.dtsi index 19578f660b09..f0db0d4471f4 100644 --- a/arch/arm/boot/dts/imx6qdl-prti6q.dtsi +++ b/arch/arm/boot/dts/imx6qdl-prti6q.dtsi @@ -94,6 +94,9 @@ pinctrl-0 = <&pinctrl_usdhc3>; bus-width = <8>; non-removable; + no-1-8-v; + no-sd; + no-sdio; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6qdl-skov-cpu-revc.dtsi b/arch/arm/boot/dts/imx6qdl-skov-cpu-revc.dtsi index 69ae430a53bd..8254bce1b8a2 100644 --- a/arch/arm/boot/dts/imx6qdl-skov-cpu-revc.dtsi +++ b/arch/arm/boot/dts/imx6qdl-skov-cpu-revc.dtsi @@ -15,13 +15,13 @@ reg = <0>; spi-max-frequency = <1000000>; interrupts-extended = <&gpio3 19 IRQ_TYPE_LEVEL_LOW>; - vcc-supply = <®_3v3>; + vcc-supply = <®_3v3>; pendown-gpio = <&gpio3 19 GPIO_ACTIVE_LOW>; ti,x-plate-ohms = /bits/ 16 <850>; ti,y-plate-ohms = /bits/ 16 <295>; ti,pressure-min = /bits/ 16 <2>; ti,pressure-max = /bits/ 16 <1500>; - ti,vref-mv = /bits/ 16 <3300>; + ti,vref-mv = /bits/ 16 <3300>; ti,settle-delay-usec = /bits/ 16 <15>; ti,vref-delay-usecs = /bits/ 16 <0>; ti,penirq-recheck-delay-usecs = /bits/ 16 <100>; diff --git a/arch/arm/boot/dts/imx6qdl-skov-cpu.dtsi b/arch/arm/boot/dts/imx6qdl-skov-cpu.dtsi index 77a91a97e6cf..3def1b621c8e 100644 --- a/arch/arm/boot/dts/imx6qdl-skov-cpu.dtsi +++ b/arch/arm/boot/dts/imx6qdl-skov-cpu.dtsi @@ -149,6 +149,16 @@ gpio = <&gpio4 11 GPIO_ACTIVE_LOW>; }; + reg_tft_vcom: regulator-tft-vcom { + compatible = "pwm-regulator"; + pwms = <&pwm3 0 20000 0>; + regulator-name = "tft_vcom"; + regulator-min-microvolt = <3600000>; + regulator-max-microvolt = <3600000>; + regulator-always-on; + voltage-table = <3600000 26>; + }; + reg_vcc_mmc: regulator-vcc-mmc { compatible = "regulator-fixed"; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index 652feff33496..4f7fefc14d0a 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@ -143,7 +143,7 @@ #phy-cells = <0>; }; - soc { + soc: soc { #address-cells = <1>; #size-cells = <1>; compatible = "simple-bus"; @@ -290,7 +290,7 @@ status = "disabled"; }; - bus@2000000 { /* AIPS1 */ + aips1: bus@2000000 { /* AIPS1 */ compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; @@ -941,7 +941,7 @@ }; }; - bus@2100000 { /* AIPS2 */ + aips2: bus@2100000 { /* AIPS2 */ compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/imx6sl-tolino-shine2hd.dts b/arch/arm/boot/dts/imx6sl-tolino-shine2hd.dts index a17b8bbbdb95..663ee9df79e6 100644 --- a/arch/arm/boot/dts/imx6sl-tolino-shine2hd.dts +++ b/arch/arm/boot/dts/imx6sl-tolino-shine2hd.dts @@ -27,7 +27,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_keys>; - cover { + key-cover { label = "Cover"; gpios = <&gpio5 12 GPIO_ACTIVE_LOW>; linux,code = <SW_LID>; @@ -35,19 +35,19 @@ wakeup-source; }; - fl { + key-fl { label = "Frontlight"; gpios = <&gpio3 26 GPIO_ACTIVE_LOW>; linux,code = <KEY_BRIGHTNESS_CYCLE>; }; - home { + key-home { label = "Home"; gpios = <&gpio3 25 GPIO_ACTIVE_LOW>; linux,code = <KEY_HOME>; }; - power { + key-power { label = "Power"; gpios = <&gpio5 8 GPIO_ACTIVE_LOW>; linux,code = <KEY_POWER>; @@ -60,7 +60,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_led>; - on { + led-0 { label = "tolinoshine2hd:white:on"; gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; linux,default-trigger = "timer"; diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi index fc6334336b3d..4d075e2bf749 100644 --- a/arch/arm/boot/dts/imx6sx.dtsi +++ b/arch/arm/boot/dts/imx6sx.dtsi @@ -154,7 +154,7 @@ #phy-cells = <0>; }; - soc { + soc: soc { #address-cells = <1>; #size-cells = <1>; compatible = "simple-bus"; diff --git a/arch/arm/boot/dts/imx6ul-kontron-n6x1x-s.dtsi b/arch/arm/boot/dts/imx6ul-kontron-n6x1x-s.dtsi index a6cf0f21c66d..43868311f48a 100644 --- a/arch/arm/boot/dts/imx6ul-kontron-n6x1x-s.dtsi +++ b/arch/arm/boot/dts/imx6ul-kontron-n6x1x-s.dtsi @@ -72,7 +72,6 @@ &adc1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_adc1>; - num-channels = <3>; vref-supply = <®_vref_adc>; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi b/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi index 0d4ba9494cf2..38ea4dcfa228 100644 --- a/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi +++ b/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi @@ -83,11 +83,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_adc1>; vref-supply = <®_adc1_vref_3v3>; - /* - * driver can not separate a specific channel so we request 4 channels - * here - we need only the fourth channel - */ - num-channels = <4>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/imx6ul-tqma6ul2l.dtsi b/arch/arm/boot/dts/imx6ul-tqma6ul2l.dtsi index caf2c5d03f7e..4b87e2dc70dc 100644 --- a/arch/arm/boot/dts/imx6ul-tqma6ul2l.dtsi +++ b/arch/arm/boot/dts/imx6ul-tqma6ul2l.dtsi @@ -14,7 +14,7 @@ }; &usdhc2 { - fsl,tuning-step= <6>; + fsl,tuning-step = <6>; }; &iomuxc { diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi index afeec01f6522..c95efd1d8c2d 100644 --- a/arch/arm/boot/dts/imx6ul.dtsi +++ b/arch/arm/boot/dts/imx6ul.dtsi @@ -64,20 +64,18 @@ clock-frequency = <696000000>; clock-latency = <61036>; /* two CLK32 periods */ #cooling-cells = <2>; - operating-points = < + operating-points = /* kHz uV */ - 696000 1275000 - 528000 1175000 - 396000 1025000 - 198000 950000 - >; - fsl,soc-operating-points = < + <696000 1275000>, + <528000 1175000>, + <396000 1025000>, + <198000 950000>; + fsl,soc-operating-points = /* KHz uV */ - 696000 1275000 - 528000 1175000 - 396000 1175000 - 198000 1175000 - >; + <696000 1275000>, + <528000 1175000>, + <396000 1175000>, + <198000 1175000>; clocks = <&clks IMX6UL_CLK_ARM>, <&clks IMX6UL_CLK_PLL2_BUS>, <&clks IMX6UL_CLK_PLL2_PFD2>, @@ -139,7 +137,7 @@ interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; }; - soc { + soc: soc { #address-cells = <1>; #size-cells = <1>; compatible = "simple-bus"; @@ -149,6 +147,9 @@ ocram: sram@900000 { compatible = "mmio-sram"; reg = <0x00900000 0x20000>; + ranges = <0 0x00900000 0x20000>; + #address-cells = <1>; + #size-cells = <1>; }; intc: interrupt-controller@a01000 { @@ -543,7 +544,7 @@ }; kpp: keypad@20b8000 { - compatible = "fsl,imx6ul-kpp", "fsl,imx6q-kpp", "fsl,imx21-kpp"; + compatible = "fsl,imx6ul-kpp", "fsl,imx21-kpp"; reg = <0x020b8000 0x4000>; interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6UL_CLK_KPP>; @@ -923,7 +924,6 @@ reg = <0x02198000 0x4000>; interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6UL_CLK_ADC1>; - num-channels = <2>; clock-names = "adc"; fsl,adck-max-frequency = <30000000>, <40000000>, <20000000>; @@ -998,7 +998,7 @@ }; csi: csi@21c4000 { - compatible = "fsl,imx6ul-csi", "fsl,imx7-csi"; + compatible = "fsl,imx6ul-csi"; reg = <0x021c4000 0x4000>; interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6UL_CLK_CSI>; @@ -1007,7 +1007,7 @@ }; lcdif: lcdif@21c8000 { - compatible = "fsl,imx6ul-lcdif", "fsl,imx28-lcdif"; + compatible = "fsl,imx6ul-lcdif", "fsl,imx6sx-lcdif"; reg = <0x021c8000 0x4000>; interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6UL_CLK_LCDIF_PIX>, @@ -1028,7 +1028,7 @@ qspi: spi@21e0000 { #address-cells = <1>; #size-cells = <0>; - compatible = "fsl,imx6ul-qspi", "fsl,imx6sx-qspi"; + compatible = "fsl,imx6ul-qspi"; reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>; reg-names = "QuadSPI", "QuadSPI-memory"; interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm/boot/dts/imx6ull-colibri.dtsi b/arch/arm/boot/dts/imx6ull-colibri.dtsi index 2c3ae715c683..577a424b0e1d 100644 --- a/arch/arm/boot/dts/imx6ull-colibri.dtsi +++ b/arch/arm/boot/dts/imx6ull-colibri.dtsi @@ -94,7 +94,6 @@ }; &adc1 { - num-channels = <10>; vref-supply = <®_module_3v3_avdd>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_adc1>; diff --git a/arch/arm/boot/dts/imx6ull-tqma6ull2.dtsi b/arch/arm/boot/dts/imx6ull-tqma6ull2.dtsi index 326e6da91ed4..8541cb3f3b3e 100644 --- a/arch/arm/boot/dts/imx6ull-tqma6ull2.dtsi +++ b/arch/arm/boot/dts/imx6ull-tqma6ull2.dtsi @@ -14,7 +14,7 @@ }; &usdhc2 { - fsl,tuning-step= <6>; + fsl,tuning-step = <6>; /* Errata ERR010450 Workaround */ max-frequency = <99000000>; assigned-clocks = <&clks IMX6UL_CLK_USDHC2_SEL>, <&clks IMX6UL_CLK_USDHC2>; diff --git a/arch/arm/boot/dts/imx6ull-tqma6ull2l.dtsi b/arch/arm/boot/dts/imx6ull-tqma6ull2l.dtsi index 8e4d5cd18614..be593d47e3b1 100644 --- a/arch/arm/boot/dts/imx6ull-tqma6ull2l.dtsi +++ b/arch/arm/boot/dts/imx6ull-tqma6ull2l.dtsi @@ -14,7 +14,7 @@ }; &usdhc2 { - fsl,tuning-step= <6>; + fsl,tuning-step = <6>; /* Errata ERR010450 Workaround */ max-frequency = <99000000>; assigned-clocks = <&clks IMX6UL_CLK_USDHC2_SEL>, <&clks IMX6UL_CLK_USDHC2>; diff --git a/arch/arm/boot/dts/imx6ull.dtsi b/arch/arm/boot/dts/imx6ull.dtsi index 9bf67490ac49..2bccd45e9fc2 100644 --- a/arch/arm/boot/dts/imx6ull.dtsi +++ b/arch/arm/boot/dts/imx6ull.dtsi @@ -50,7 +50,7 @@ }; / { - soc { + soc: soc { aips3: bus@2200000 { compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; diff --git a/arch/arm/boot/dts/imx6ulz-bsh-smm-m2.dts b/arch/arm/boot/dts/imx6ulz-bsh-smm-m2.dts index 59bcfc9a6b10..c92e4e2f6ab9 100644 --- a/arch/arm/boot/dts/imx6ulz-bsh-smm-m2.dts +++ b/arch/arm/boot/dts/imx6ulz-bsh-smm-m2.dts @@ -29,6 +29,10 @@ status = "okay"; }; +&snvs_poweroff { + status = "okay"; +}; + &uart3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3>; diff --git a/arch/arm/boot/dts/imx7-colibri-aster.dtsi b/arch/arm/boot/dts/imx7-colibri-aster.dtsi index b770fc937970..fa488a6de0d4 100644 --- a/arch/arm/boot/dts/imx7-colibri-aster.dtsi +++ b/arch/arm/boot/dts/imx7-colibri-aster.dtsi @@ -1,169 +1,79 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT /* - * Copyright 2017-2020 Toradex AG - * + * Copyright 2017-2022 Toradex */ - -#include <dt-bindings/input/input.h> -#include <dt-bindings/pwm/pwm.h> - -/ { - chosen { - stdout-path = "serial0:115200n8"; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpiokeys>; - - power { - label = "Wake-Up"; - gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; - linux,code = <KEY_WAKEUP>; - debounce-interval = <10>; - wakeup-source; - }; - }; - - panel: panel { - compatible = "edt,et057090dhu"; - backlight = <&bl>; - power-supply = <®_3v3>; - - port { - panel_in: endpoint { - remote-endpoint = <&lcdif_out>; - }; - }; - }; - - reg_3v3: regulator-3v3 { - compatible = "regulator-fixed"; - regulator-name = "3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_5v0: regulator-5v0 { - compatible = "regulator-fixed"; - regulator-name = "5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - reg_usbh_vbus: regulator-usbh-vbus { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh_reg>; - regulator-name = "VCC_USB[1-4]"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio4 7 GPIO_ACTIVE_LOW>; - vin-supply = <®_5v0>; - }; -}; - +/* Colibri AD0 to AD3 */ &adc1 { status = "okay"; }; -/* - * ADC2 is not available on the Aster board and - * conflicts with AD7879 resistive touchscreen. - */ -&adc2 { - status = "disabled"; -}; - -&bl { - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - power-supply = <®_3v3>; +/* Colibri SSP */ +&ecspi3 { + cs-gpios = < + &gpio4 11 GPIO_ACTIVE_LOW /* SODIMM 86 / regular SSPFRM as UNO_SPI_CS or */ + &gpio4 23 GPIO_ACTIVE_LOW /* SODIMM 65 / already muxed pinctrl_gpio2 as SPI_CE0_N */ + &gpio4 22 GPIO_ACTIVE_LOW /* SODIMM 85 / already muxed pinctrl_gpio2 as SPI_CE1_N */ + >; status = "okay"; }; +/* Colibri Fast Ethernet */ &fec1 { status = "okay"; }; +/* Colibri I2C: I2C3_SDA/SCL on SODIMM 194/196 */ &i2c4 { status = "okay"; - - /* Microchip/Atmel maxtouch controller */ - touchscreen@4a { - compatible = "atmel,maxtouch"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpiotouch>; - reg = <0x4a>; - interrupt-parent = <&gpio2>; - interrupts = <15 IRQ_TYPE_EDGE_FALLING>; /* SODIMM 107 */ - reset-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; /* SODIMM 106 */ - }; - - /* M41T0M6 real time clock on carrier board */ - rtc: rtc@68 { - compatible = "st,m41t0"; - reg = <0x68>; - }; -}; - -&iomuxc { - pinctrl_gpiotouch: touchgpios { - fsl,pins = < - MX7D_PAD_EPDC_DATA15__GPIO2_IO15 0x74 - MX7D_PAD_EPDC_BDR0__GPIO2_IO28 0x14 - >; - }; -}; - -&lcdif { - status = "okay"; - - port { - lcdif_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; }; +/* Colibri PWM<A> */ &pwm1 { status = "okay"; }; +/* Colibri PWM<B> */ &pwm2 { status = "okay"; }; +/* Colibri PWM<C> */ &pwm3 { status = "okay"; }; +/* Colibri PWM<D> */ &pwm4 { status = "okay"; }; +/* M41T0M6 real time clock */ +&rtc { + status = "okay"; +}; + +/* Colibri UART_A */ &uart1 { status = "okay"; }; +/* Colibri UART_B */ &uart2 { status = "okay"; }; +/* Colibri UART_C */ &uart3 { status = "okay"; }; +/* Colibri USBC */ &usbotg1 { status = "okay"; }; +/* Colibri MMC/SD */ &usdhc1 { - keep-power-in-suspend; - no-1-8-v; - wakeup-source; - vmmc-supply = <®_3v3>; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi b/arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi index 3b9df8c82ae3..826f13da5b81 100644 --- a/arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi +++ b/arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi @@ -1,194 +1,110 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT /* - * Copyright 2016-2020 Toradex + * Copyright 2016-2022 Toradex */ / { - aliases { - rtc0 = &rtc; - rtc1 = &snvs_rtc; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - /* fixed crystal dedicated to mpc258x */ + /* Fixed crystal dedicated to MCP2515. */ clk16m: clk16m { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <16000000>; }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpiokeys>; - - power { - label = "Wake-Up"; - gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; - linux,code = <KEY_WAKEUP>; - debounce-interval = <10>; - wakeup-source; - }; - }; - - panel: panel { - compatible = "edt,et057090dhu"; - backlight = <&bl>; - power-supply = <®_3v3>; - - port { - panel_in: endpoint { - remote-endpoint = <&lcdif_out>; - }; - }; - }; - - reg_3v3: regulator-3v3 { - compatible = "regulator-fixed"; - regulator-name = "3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_5v0: regulator-5v0 { - compatible = "regulator-fixed"; - regulator-name = "5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - reg_usbh_vbus: regulator-usbh-vbus { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh_reg>; - regulator-name = "VCC_USB[1-4]"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio4 7 GPIO_ACTIVE_LOW>; - vin-supply = <®_5v0>; - }; -}; - -&bl { - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - power-supply = <®_3v3>; - - status = "okay"; }; +/* Colibri AD0 to AD3 */ &adc1 { status = "okay"; }; -&adc2 { - status = "okay"; +/* + * The Atmel maxtouch controller uses SODIMM 28/30, also used for PWM<B>, PWM<C>, aka pwm2, pwm3. + * So if you enable following capacitive touch controller, disable pwm2/pwm3 first. + */ +&atmel_mxt_ts { + interrupt-parent = <&gpio1>; + interrupts = <9 IRQ_TYPE_EDGE_FALLING>; /* SODIMM 28 / INT */ + pinctrl-0 = <&pinctrl_atmel_adapter>; + reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; /* SODIMM 30 / RST */ + status = "disabled"; }; +/* Colibri SSP */ &ecspi3 { status = "okay"; mcp2515: can@0 { + clocks = <&clk16m>; compatible = "microchip,mcp2515"; + interrupt-parent = <&gpio5>; + interrupts = <2 IRQ_TYPE_EDGE_FALLING>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can_int>; reg = <0>; - clocks = <&clk16m>; - interrupt-parent = <&gpio5>; - interrupts = <2 IRQ_TYPE_EDGE_FALLING>; spi-max-frequency = <10000000>; vdd-supply = <®_3v3>; xceiver-supply = <®_5v0>; - status = "okay"; }; }; +/* Colibri Fast Ethernet */ &fec1 { status = "okay"; }; +/* Colibri I2C: I2C3_SDA/SCL on SODIMM 194/196 */ &i2c4 { status = "okay"; - - /* - * Touchscreen is using SODIMM 28/30, also used for PWM<B>, PWM<C>, - * aka pwm2, pwm3. so if you enable touchscreen, disable the pwms - */ - touchscreen@4a { - compatible = "atmel,maxtouch"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpiotouch>; - reg = <0x4a>; - interrupt-parent = <&gpio1>; - interrupts = <9 IRQ_TYPE_EDGE_FALLING>; /* SODIMM 28 */ - reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; /* SODIMM 30 */ - status = "disabled"; - }; - - /* M41T0M6 real time clock on carrier board */ - rtc: rtc@68 { - compatible = "st,m41t0"; - reg = <0x68>; - }; -}; - -&lcdif { - status = "okay"; - - port { - lcdif_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; }; +/* Colibri PWM<A> */ &pwm1 { status = "okay"; }; +/* Colibri PWM<B> */ &pwm2 { + /* The pwm2 should be disabled to enable atmel_mxt_ts touchscreen for adapter. */ status = "okay"; }; +/* Colibri PWM<C> */ &pwm3 { + /* The pwm3 should be disabled to enable atmel_mxt_ts touchscreen for adapter. */ status = "okay"; }; +/* Colibri PWM<D> */ &pwm4 { status = "okay"; }; +/* M41T0M6 real time clock */ +&rtc { + status = "okay"; +}; + +/* Colibri UART_A */ &uart1 { status = "okay"; }; +/* Colibri UART_B */ &uart2 { status = "okay"; }; +/* Colibri UART_C */ &uart3 { status = "okay"; }; +/* Colibri USBC */ &usbotg1 { status = "okay"; }; +/* Colibri MMC/SD */ &usdhc1 { - keep-power-in-suspend; - wakeup-source; - vmmc-supply = <®_3v3>; status = "okay"; }; - -&iomuxc { - pinctrl_gpiotouch: touchgpios { - fsl,pins = < - MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x74 - MX7D_PAD_GPIO1_IO10__GPIO1_IO10 0x14 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx7-colibri-iris-v2.dtsi b/arch/arm/boot/dts/imx7-colibri-iris-v2.dtsi new file mode 100644 index 000000000000..6e199613583c --- /dev/null +++ b/arch/arm/boot/dts/imx7-colibri-iris-v2.dtsi @@ -0,0 +1,112 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2022 Toradex + */ + +/ { + reg_3v3_vmmc: regulator-3v3-vmmc { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio5 16 GPIO_ACTIVE_HIGH>; /* SODIMM 100 */ + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "3v3_vmmc"; + startup-delay-us = <100>; + }; +}; + +/* Colibri AD0 to AD3 */ +&adc1 { + status = "okay"; +}; + +/* Colibri SSP */ +&ecspi3 { + status = "okay"; +}; + +/* Colibri Fast Ethernet */ +&fec1 { + status = "okay"; +}; + +&gpio2 { + /* + * uart_b_c_on_x14_enable turns the UART transceiver for UART2 and 5 on. If one wants to + * turn the transceiver off, that property has to be deleted and the gpio handled in + * userspace. + * The same applies to uart_a_on_x13_enable where the UART_A transceiver is turned on. + */ + uart-b-c-on-x14-enable-hog { + gpio-hog; + gpios = <27 GPIO_ACTIVE_HIGH>; /* SODIMM 104 */ + output-high; + }; +}; + +&gpio5 { + uart-a-on-x13-enable-hog { + gpio-hog; + gpios = <17 GPIO_ACTIVE_HIGH>; /* SODIMM 102 */ + output-high; + }; +}; + +/* Colibri I2C: I2C3_SDA/SCL on SODIMM 194/196 */ +&i2c4 { + status = "okay"; +}; + +/* Colibri PWM<A> */ +&pwm1 { + status = "okay"; +}; + +/* Colibri PWM<B> */ +&pwm2 { + status = "okay"; +}; + +/* Colibri PWM<C> */ +&pwm3 { + status = "okay"; +}; + +/* Colibri PWM<D> */ +&pwm4 { + status = "okay"; +}; + +/* M41T0M6 real time clock */ +&rtc { + status = "okay"; +}; + +/* Colibri UART_A */ +&uart1 { + status = "okay"; +}; + +/* Colibri UART_B */ +&uart2 { + status = "okay"; +}; + +/* Colibri UART_C */ +&uart3 { + status = "okay"; +}; + +/* Colibri USBC */ +&usbotg1 { + status = "okay"; +}; + +/* Colibri MMC/SD, UHS-I capable uSD slot */ +&usdhc1 { + cap-power-off-card; + /delete-property/ keep-power-in-suspend; + /delete-property/ no-1-8-v; + vmmc-supply = <®_3v3_vmmc>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx7-colibri-iris.dtsi b/arch/arm/boot/dts/imx7-colibri-iris.dtsi new file mode 100644 index 000000000000..175c5d478d2e --- /dev/null +++ b/arch/arm/boot/dts/imx7-colibri-iris.dtsi @@ -0,0 +1,108 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2022 Toradex + */ + +/* Colibri AD0 to AD3 */ +&adc1 { + status = "okay"; +}; + +/* + * The Atmel maxtouch controller uses SODIMM 28/30, also used for PWM<B>, PWM<C>, aka pwm2, pwm3. + * So if you enable following capacitive touch controller, disable pwm2/pwm3 first. + */ +&atmel_mxt_ts { + interrupt-parent = <&gpio1>; + interrupts = <9 IRQ_TYPE_EDGE_FALLING>; /* SODIMM 28 / INT */ + pinctrl-0 = <&pinctrl_atmel_adapter>; + reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; /* SODIMM 30 / RST */ +}; + +/* Colibri SSP */ +&ecspi3 { + status = "okay"; +}; + +/* Colibri Fast Ethernet */ +&fec1 { + status = "okay"; +}; + +&gpio2 { + /* + * uart25 turns the UART transceiver for UART2 and 5 on. If one wants to turn the + * transceiver off, that property has to be deleted and the gpio handled in userspace. + * The same applies to uart1_tx_on where the UART1 transceiver is turned on. + */ + uart25-tx-on-hog { + gpio-hog; + gpios = <27 GPIO_ACTIVE_HIGH>; /* SODIMM 104 */ + output-high; + }; +}; + +&gpio5 { + uart1-tx-on-hog { + gpio-hog; + gpios = <17 GPIO_ACTIVE_HIGH>; /* SODIMM 102 */ + output-high; + }; +}; + +/* Colibri I2C: I2C3_SDA/SCL on SODIMM 194/196 */ +&i2c4 { + status = "okay"; +}; + +/* Colibri PWM<A> */ +&pwm1 { + status = "okay"; +}; + +/* Colibri PWM<B> */ +&pwm2 { + /* The pwm2 should be disabled to enable atmel_mxt_ts touchscreen for adapter. */ + status = "okay"; +}; + +/* Colibri PWM<C> */ +&pwm3 { + /* The pwm3 should be disabled to enable atmel_mxt_ts touchscreen for adapter. */ + status = "okay"; +}; + +/* Colibri PWM<D> */ +&pwm4 { + status = "okay"; +}; + +/* M41T0M6 real time clock */ +&rtc { + status = "okay"; +}; + +/* Colibri UART_A */ +&uart1 { + status = "okay"; +}; + +/* Colibri UART_B */ +&uart2 { + status = "okay"; +}; + +/* Colibri UART_C */ +&uart3 { + status = "okay"; +}; + +/* Colibri USBC */ +&usbotg1 { + status = "okay"; +}; + +/* Colibri MMC/SD */ +&usdhc1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx7-colibri.dtsi b/arch/arm/boot/dts/imx7-colibri.dtsi index f1c60b0cb143..a8c31ee65623 100644 --- a/arch/arm/boot/dts/imx7-colibri.dtsi +++ b/arch/arm/boot/dts/imx7-colibri.dtsi @@ -1,96 +1,198 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT /* - * Copyright 2016-2020 Toradex + * Copyright 2016-2022 Toradex */ +#include <dt-bindings/pwm/pwm.h> + / { - bl: backlight { + aliases { + rtc0 = &rtc; + rtc1 = &snvs_rtc; + }; + + backlight: backlight { + brightness-levels = <0 45 63 88 119 158 203 255>; compatible = "pwm-backlight"; + default-brightness-level = <4>; + enable-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_bl_on>; - pwms = <&pwm1 0 5000000 0>; - enable-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; + power-supply = <®_module_3v3>; + pwms = <&pwm1 0 6666667 PWM_POLARITY_INVERTED>; + status = "disabled"; }; - reg_module_3v3: regulator-module-3v3 { + chosen { + stdout-path = "serial0:115200n8"; + }; + + extcon_usbc_det: usbc-det { + compatible = "linux,extcon-usb-gpio"; + debounce = <25>; + id-gpio = <&gpio7 14 GPIO_ACTIVE_HIGH>; /* SODIMM 137 / USBC_DET */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbc_det>; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpiokeys>; + + wakeup { + debounce-interval = <10>; + gpios = <&gpio1 1 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* SODIMM 45 */ + label = "Wake-Up"; + linux,code = <KEY_WAKEUP>; + wakeup-source; + }; + }; + + panel_dpi: panel-dpi { + backlight = <&backlight>; + compatible = "edt,et057090dhu"; + power-supply = <®_3v3>; + status = "disabled"; + + port { + lcd_panel_in: endpoint { + remote-endpoint = <&lcdif_out>; + }; + }; + }; + + reg_3v3: regulator-3v3 { compatible = "regulator-fixed"; - regulator-name = "+V3.3"; - regulator-min-microvolt = <3300000>; + regulator-always-on; regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "3.3V"; + }; + + reg_5v0: regulator-5v0 { + compatible = "regulator-fixed"; regulator-always-on; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "5V"; + }; + + reg_module_3v3: regulator-module-3v3 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "+V3.3"; }; reg_module_3v3_avdd: regulator-module-3v3-avdd { compatible = "regulator-fixed"; + regulator-always-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; regulator-name = "+V3.3_AVDD_AUDIO"; + }; + + reg_module_3v3_eth: regulator-module-3v3-eth { + compatible = "regulator-fixed"; + off-on-delay-us = <200000>; + regulator-name = "+V3.3_ETH"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - regulator-always-on; + regulator-boot-on; + startup-delay-us = <200000>; + vin-supply = <®_LDO1>; + }; + + reg_usbh_vbus: regulator-usbh-vbus { + compatible = "regulator-fixed"; + gpio = <&gpio4 7 GPIO_ACTIVE_LOW>; /* SODIMM 129 / USBH_PEN */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh_reg>; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "VCC_USB[1-4]"; + vin-supply = <®_5v0>; }; sound { compatible = "simple-audio-card"; - simple-audio-card,name = "imx7-sgtl5000"; - simple-audio-card,format = "i2s"; simple-audio-card,bitclock-master = <&dailink_master>; + simple-audio-card,format = "i2s"; simple-audio-card,frame-master = <&dailink_master>; + simple-audio-card,name = "imx7-sgtl5000"; + simple-audio-card,cpu { sound-dai = <&sai1>; }; dailink_master: simple-audio-card,codec { - sound-dai = <&codec>; clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>; + sound-dai = <&codec>; }; }; }; +/* Colibri AD0 to AD3 */ &adc1 { vref-supply = <®_DCDC3>; }; -&adc2 { - vref-supply = <®_DCDC3>; -}; +/* ADC2 is not available as it conflicts with AD7879 resistive touchscreen. */ &cpu0 { cpu-supply = <®_DCDC2>; }; +/* Colibri SSP */ &ecspi3 { + cs-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>; /* SODIMM 86 / SSPFRM */ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi3 &pinctrl_ecspi3_cs>; - cs-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>; }; +/* Colibri Fast Ethernet */ &fec1 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&pinctrl_enet1>; - pinctrl-1 = <&pinctrl_enet1_sleep>; - clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>, - <&clks IMX7D_ENET_AXI_ROOT_CLK>, - <&clks IMX7D_ENET1_TIME_ROOT_CLK>, - <&clks IMX7D_PLL_ENET_MAIN_50M_CLK>; - clock-names = "ipg", "ahb", "ptp", "enet_clk_ref"; - assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>, - <&clks IMX7D_ENET1_TIME_ROOT_CLK>; assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; assigned-clock-rates = <0>, <100000000>; - phy-mode = "rmii"; - phy-supply = <®_LDO1>; + assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>, + <&clks IMX7D_ENET1_TIME_ROOT_CLK>; + clock-names = "ipg", "ahb", "ptp", "enet_clk_ref"; + clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>, + <&clks IMX7D_ENET_AXI_ROOT_CLK>, + <&clks IMX7D_ENET1_TIME_ROOT_CLK>, + <&clks IMX7D_PLL_ENET_MAIN_50M_CLK>; fsl,magic-packet; + phy-handle = <ðphy0>; + phy-mode = "rmii"; + phy-supply = <®_module_3v3_eth>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_enet1>; + pinctrl-1 = <&pinctrl_enet1_sleep>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + /* Micrel KSZ8041RNL */ + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + max-speed = <100>; + micrel,led-mode = <0>; + reg = <0>; + }; + }; }; &flexcan1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flexcan1>; - status = "disabled"; }; &flexcan2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flexcan2>; - status = "disabled"; }; &gpio1 { @@ -271,14 +373,16 @@ "SODIMM_137"; }; +/* NAND on such SKUs */ &gpmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpmi_nand>; fsl,use-minimum-ecc; - nand-on-flash-bbt; nand-ecc-mode = "hw"; + nand-on-flash-bbt; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; }; +/* On-module Power I2C */ &i2c1 { clock-frequency = <100000>; pinctrl-names = "default", "gpio"; @@ -286,33 +390,33 @@ pinctrl-1 = <&pinctrl_i2c1_recovery &pinctrl_i2c1_int>; scl-gpios = <&gpio1 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios = <&gpio1 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; codec: sgtl5000@a { - compatible = "fsl,sgtl5000"; #sound-dai-cells = <0>; - reg = <0x0a>; clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>; + compatible = "fsl,sgtl5000"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sai1_mclk>; + reg = <0xa>; VDDA-supply = <®_module_3v3_avdd>; - VDDIO-supply = <®_module_3v3>; VDDD-supply = <®_DCDC3>; + VDDIO-supply = <®_module_3v3>; }; - ad7879@2c { + ad7879_ts: touchscreen@2c { + adi,acquisition-time = /bits/ 8 <1>; + adi,averaging = /bits/ 8 <1>; + adi,conversion-interval = /bits/ 8 <255>; + adi,first-conversion-delay = /bits/ 8 <3>; + adi,median-filter-size = /bits/ 8 <2>; + adi,resistance-plate-x = <120>; compatible = "adi,ad7879-1"; - reg = <0x2c>; interrupt-parent = <&gpio1>; interrupts = <13 IRQ_TYPE_EDGE_FALLING>; + reg = <0x2c>; touchscreen-max-pressure = <4096>; - adi,resistance-plate-x = <120>; - adi,first-conversion-delay = /bits/ 8 <3>; - adi,acquisition-time = /bits/ 8 <1>; - adi,median-filter-size = /bits/ 8 <2>; - adi,averaging = /bits/ 8 <1>; - adi,conversion-interval = /bits/ 8 <255>; + status = "disabled"; }; pmic@33 { @@ -320,71 +424,81 @@ reg = <0x33>; regulators { - reg_DCDC1: DCDC1 { /* V1.0_SOC */ - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1100000>; - regulator-boot-on; + reg_DCDC1: DCDC1 { regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1100000>; + regulator-min-microvolt = <1000000>; + regulator-name = "+V1.0_SOC"; }; - reg_DCDC2: DCDC2 { /* V1.1_ARM */ - regulator-min-microvolt = <975000>; - regulator-max-microvolt = <1100000>; - regulator-boot-on; + reg_DCDC2: DCDC2 { regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1100000>; + regulator-min-microvolt = <975000>; + regulator-name = "+V1.1_ARM"; }; - reg_DCDC3: DCDC3 { /* V1.8 */ - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; + reg_DCDC3: DCDC3 { regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "+V1.8"; }; - reg_DCDC4: DCDC4 { /* V1.35_DRAM */ - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-boot-on; + reg_DCDC4: DCDC4 { regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1350000>; + regulator-min-microvolt = <1350000>; + regulator-name = "+V1.35_DRAM"; }; - reg_LDO1: LDO1 { /* PWR_EN_+V3.3_ETH */ - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; + reg_LDO1: LDO1 { regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "PWR_EN_+V3.3_ETH"; }; - reg_LDO2: LDO2 { /* +V1.8_SD */ - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; + reg_LDO2: LDO2 { regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1800000>; + regulator-name = "+V1.8_SD"; }; - reg_LDO3: LDO3 { /* PWR_EN_+V3.3_LPSR */ - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; + reg_LDO3: LDO3 { regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "PWR_EN_+V3.3_LPSR"; }; - reg_LDO4: LDO4 { /* V1.8_LPSR */ - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; + reg_LDO4: LDO4 { regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "+V1.8_LPSR"; }; - reg_LDO5: LDO5 { /* PWR_EN_+V3.3 */ - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; + reg_LDO5: LDO5 { regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "PWR_EN_+V3.3"; }; }; }; }; +/* Colibri I2C: I2C3_SDA/SCL on SODIMM 194/196 */ &i2c4 { clock-frequency = <100000>; pinctrl-names = "default", "gpio"; @@ -392,36 +506,69 @@ pinctrl-1 = <&pinctrl_i2c4_recovery>; scl-gpios = <&gpio7 8 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios = <&gpio7 9 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "disabled"; + + /* Atmel maxtouch controller */ + atmel_mxt_ts: touchscreen@4a { + compatible = "atmel,maxtouch"; + interrupt-parent = <&gpio2>; + interrupts = <15 IRQ_TYPE_EDGE_FALLING>; /* SODIMM 107 / INT */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_atmel_connector>; + reg = <0x4a>; + reset-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; /* SODIMM 106 / RST */ + status = "disabled"; + }; + + /* M41T0M6 real time clock on carrier board */ + rtc: rtc@68 { + compatible = "st,m41t0"; + reg = <0x68>; + status = "disabled"; + }; }; &lcdif { + assigned-clocks = <&clks IMX7D_LCDIF_PIXEL_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_PLL_VIDEO_POST_DIV>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_lcdif_dat &pinctrl_lcdif_ctrl>; + status = "disabled"; + + port { + lcdif_out: endpoint { + remote-endpoint = <&lcd_panel_in>; + }; + }; }; +/* Colibri PWM<A> */ &pwm1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm1>; }; +/* Colibri PWM<B> */ &pwm2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm2>; }; +/* Colibri PWM<C> */ &pwm3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm3>; }; +/* Colibri PWM<D> */ &pwm4 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm4>; }; ®_1p0d { - vin-supply = <®_DCDC3>; + vin-supply = <®_DCDC3>; /* VDDA_1P8_IN */ }; &sai1 { @@ -430,237 +577,257 @@ status = "okay"; }; +/* Colibri UART_A */ &uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_ctrl1 &pinctrl_uart1_ctrl2>; assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>; assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; - uart-has-rtscts; fsl,dte-mode; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_ctrl1 &pinctrl_uart1_ctrl2>; + uart-has-rtscts; }; +/* Colibri UART_B */ &uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; assigned-clocks = <&clks IMX7D_UART2_ROOT_SRC>; assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; - uart-has-rtscts; fsl,dte-mode; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + uart-has-rtscts; }; +/* Colibri UART_C */ &uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>; assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; fsl,dte-mode; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; }; +/* Colibri USBC */ &usbotg1 { - dr_mode = "host"; + dr_mode = "otg"; + extcon = <0>, <&extcon_usbc_det>; }; +/* Colibri MMC/SD */ &usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_cd_usdhc1>; cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; disable-wp; + no-1-8-v; + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_cd_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz &pinctrl_cd_usdhc1>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz &pinctrl_cd_usdhc1>; + pinctrl-3 = <&pinctrl_usdhc1_sleep &pinctrl_cd_usdhc1_sleep>; + vmmc-supply = <®_3v3>; vqmmc-supply = <®_LDO2>; + wakeup-source; }; +/* eMMC on 1GB (eMMC) SKUs */ &usdhc3 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>; assigned-clock-rates = <400000000>; bus-width = <8>; fsl,tuning-step = <2>; - vmmc-supply = <®_module_3v3>; - vqmmc-supply = <®_DCDC3>; non-removable; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; sdhci-caps-mask = <0x80000000 0x0>; + vmmc-supply = <®_module_3v3>; + vqmmc-supply = <®_DCDC3>; }; &iomuxc { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio1 &pinctrl_gpio2 &pinctrl_gpio3 &pinctrl_gpio4 - &pinctrl_gpio7 &pinctrl_usbc_det>; - - pinctrl_gpio1: gpio1-grp { - fsl,pins = < - MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16 0x14 /* SODIMM 77 */ - MX7D_PAD_EPDC_DATA09__GPIO2_IO9 0x14 /* SODIMM 89 */ - MX7D_PAD_EPDC_DATA08__GPIO2_IO8 0x74 /* SODIMM 91 */ - MX7D_PAD_LCD_RESET__GPIO3_IO4 0x14 /* SODIMM 93 */ - MX7D_PAD_EPDC_DATA13__GPIO2_IO13 0x14 /* SODIMM 95 */ - MX7D_PAD_ENET1_RGMII_TXC__GPIO7_IO11 0x14 /* SODIMM 99 */ - MX7D_PAD_EPDC_DATA10__GPIO2_IO10 0x74 /* SODIMM 105 */ - MX7D_PAD_EPDC_DATA00__GPIO2_IO0 0x14 /* SODIMM 111 */ - MX7D_PAD_EPDC_DATA01__GPIO2_IO1 0x14 /* SODIMM 113 */ - MX7D_PAD_EPDC_DATA02__GPIO2_IO2 0x14 /* SODIMM 115 */ - MX7D_PAD_EPDC_DATA03__GPIO2_IO3 0x14 /* SODIMM 117 */ - MX7D_PAD_EPDC_DATA04__GPIO2_IO4 0x14 /* SODIMM 119 */ - MX7D_PAD_EPDC_DATA05__GPIO2_IO5 0x14 /* SODIMM 121 */ - MX7D_PAD_EPDC_DATA06__GPIO2_IO6 0x14 /* SODIMM 123 */ - MX7D_PAD_EPDC_DATA07__GPIO2_IO7 0x14 /* SODIMM 125 */ - MX7D_PAD_EPDC_SDCE2__GPIO2_IO22 0x14 /* SODIMM 127 */ - MX7D_PAD_UART3_RTS_B__GPIO4_IO6 0x14 /* SODIMM 131 */ - MX7D_PAD_EPDC_GDRL__GPIO2_IO26 0x14 /* SODIMM 133 */ - MX7D_PAD_SAI1_RX_DATA__GPIO6_IO12 0x14 /* SODIMM 169 */ - MX7D_PAD_SAI1_RX_BCLK__GPIO6_IO17 0x14 /* SODIMM 24 */ - MX7D_PAD_SD2_DATA2__GPIO5_IO16 0x14 /* SODIMM 100 */ - MX7D_PAD_SD2_DATA3__GPIO5_IO17 0x14 /* SODIMM 102 */ - MX7D_PAD_EPDC_GDSP__GPIO2_IO27 0x14 /* SODIMM 104 */ - MX7D_PAD_EPDC_BDR1__GPIO2_IO29 0x14 /* SODIMM 110 */ - MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 0x14 /* SODIMM 112 */ - MX7D_PAD_EPDC_SDCLK__GPIO2_IO16 0x14 /* SODIMM 114 */ - MX7D_PAD_EPDC_SDLE__GPIO2_IO17 0x14 /* SODIMM 116 */ - MX7D_PAD_EPDC_SDOE__GPIO2_IO18 0x14 /* SODIMM 118 */ - MX7D_PAD_EPDC_SDSHR__GPIO2_IO19 0x14 /* SODIMM 120 */ - MX7D_PAD_EPDC_SDCE0__GPIO2_IO20 0x14 /* SODIMM 122 */ - MX7D_PAD_EPDC_SDCE1__GPIO2_IO21 0x14 /* SODIMM 124 */ - MX7D_PAD_EPDC_DATA14__GPIO2_IO14 0x14 /* SODIMM 126 */ - MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 0x14 /* SODIMM 128 */ - MX7D_PAD_EPDC_SDCE3__GPIO2_IO23 0x14 /* SODIMM 130 */ - MX7D_PAD_EPDC_GDCLK__GPIO2_IO24 0x14 /* SODIMM 132 */ - MX7D_PAD_EPDC_GDOE__GPIO2_IO25 0x14 /* SODIMM 134 */ - MX7D_PAD_EPDC_DATA12__GPIO2_IO12 0x14 /* SODIMM 150 */ - MX7D_PAD_EPDC_DATA11__GPIO2_IO11 0x14 /* SODIMM 152 */ - MX7D_PAD_SD2_CLK__GPIO5_IO12 0x14 /* SODIMM 184 */ - MX7D_PAD_SD2_CMD__GPIO5_IO13 0x14 /* SODIMM 186 */ - >; - }; - - pinctrl_gpio2: gpio2-grp { /* On X22 Camera interface */ + pinctrl-0 = <&pinctrl_gpio1 &pinctrl_gpio2 &pinctrl_gpio3 &pinctrl_gpio4>; + + /* + * Atmel MXT touchsceen + Capacitive Touch Adapter + * NOTE: This pin group conflicts with pin groups pinctrl_pwm2/pinctrl_pwm3. + * Don't use them simultaneously. + */ + pinctrl_atmel_adapter: atmelconnectorgrp { fsl,pins = < - MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 0x14 /* SODIMM 65 */ - MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x74 /* SODIMM 69 */ - MX7D_PAD_I2C4_SDA__GPIO4_IO15 0x14 /* SODIMM 75 */ - MX7D_PAD_ECSPI1_MISO__GPIO4_IO18 0x14 /* SODIMM 79 */ - MX7D_PAD_I2C3_SCL__GPIO4_IO12 0x14 /* SODIMM 81 */ - MX7D_PAD_ECSPI2_MISO__GPIO4_IO22 0x14 /* SODIMM 85 */ - MX7D_PAD_ECSPI1_SS0__GPIO4_IO19 0x14 /* SODIMM 97 */ - MX7D_PAD_ECSPI1_SCLK__GPIO4_IO16 0x14 /* SODIMM 101 */ - MX7D_PAD_ECSPI1_MOSI__GPIO4_IO17 0x14 /* SODIMM 103 */ - MX7D_PAD_I2C3_SDA__GPIO4_IO13 0x14 /* SODIMM 94 */ - MX7D_PAD_I2C4_SCL__GPIO4_IO14 0x14 /* SODIMM 96 */ - MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x14 /* SODIMM 98 */ + MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x74 /* SODIMM 28 / INT */ + MX7D_PAD_GPIO1_IO10__GPIO1_IO10 0x14 /* SODIMM 30 / RST */ >; }; - pinctrl_gpio3: gpio3-grp { /* LCD 18-23 */ + /* Atmel MXT touchsceen + boards with built-in Capacitive Touch Connector */ + pinctrl_atmel_connector: atmeladaptergrp { fsl,pins = < - MX7D_PAD_LCD_DATA18__GPIO3_IO23 0x14 /* SODIMM 136 */ - MX7D_PAD_LCD_DATA19__GPIO3_IO24 0x14 /* SODIMM 138 */ - MX7D_PAD_LCD_DATA20__GPIO3_IO25 0x14 /* SODIMM 140 */ - MX7D_PAD_LCD_DATA21__GPIO3_IO26 0x14 /* SODIMM 142 */ - MX7D_PAD_LCD_DATA22__GPIO3_IO27 0x74 /* SODIMM 144 */ - MX7D_PAD_LCD_DATA23__GPIO3_IO28 0x74 /* SODIMM 146 */ + MX7D_PAD_EPDC_BDR0__GPIO2_IO28 0x14 /* SODIMM 106 / RST */ + MX7D_PAD_EPDC_DATA15__GPIO2_IO15 0x74 /* SODIMM 107 / INT */ >; }; - pinctrl_gpio4: gpio4-grp { /* Alternatively CAN2 */ + pinctrl_can_int: canintgrp { fsl,pins = < - MX7D_PAD_GPIO1_IO15__GPIO1_IO15 0x14 /* SODIMM 178 */ - MX7D_PAD_GPIO1_IO14__GPIO1_IO14 0x14 /* SODIMM 188 */ + MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0X14 /* SODIMM 73 */ >; }; - pinctrl_gpio7: gpio7-grp { /* Alternatively CAN1 */ + pinctrl_ecspi3: ecspi3grp { fsl,pins = < - MX7D_PAD_ENET1_RGMII_RD3__GPIO7_IO3 0x14 /* SODIMM 55 */ - MX7D_PAD_ENET1_RGMII_RD2__GPIO7_IO2 0x14 /* SODIMM 63 */ + MX7D_PAD_I2C1_SCL__ECSPI3_MISO 0x2 /* SODIMM 90 */ + MX7D_PAD_I2C1_SDA__ECSPI3_MOSI 0x2 /* SODIMM 92 */ + MX7D_PAD_I2C2_SCL__ECSPI3_SCLK 0x2 /* SODIMM 88 */ >; }; - pinctrl_i2c1_int: i2c1-int-grp { /* PMIC / TOUCH */ + pinctrl_ecspi3_cs: ecspi3csgrp { fsl,pins = < - MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x79 - >; - }; - - pinctrl_can_int: can-int-grp { - fsl,pins = < - MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0X14 /* SODIMM 73 */ + MX7D_PAD_I2C2_SDA__GPIO4_IO11 0x14 /* SODIMM 86 */ >; }; pinctrl_enet1: enet1grp { fsl,pins = < - MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x73 MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x73 MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x73 MX7D_PAD_ENET1_RGMII_RXC__ENET1_RX_ER 0x73 - - MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x73 + MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x73 MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x73 MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x73 + MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x73 MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1 0x73 MX7D_PAD_SD2_CD_B__ENET1_MDIO 0x3 MX7D_PAD_SD2_WP__ENET1_MDC 0x3 >; }; - pinctrl_enet1_sleep: enet1sleepgrp { + pinctrl_enet1_sleep: enet1-sleepgrp { fsl,pins = < - MX7D_PAD_ENET1_RGMII_RX_CTL__GPIO7_IO4 0x0 MX7D_PAD_ENET1_RGMII_RD0__GPIO7_IO0 0x0 MX7D_PAD_ENET1_RGMII_RD1__GPIO7_IO1 0x0 MX7D_PAD_ENET1_RGMII_RXC__GPIO7_IO5 0x0 - - MX7D_PAD_ENET1_RGMII_TX_CTL__GPIO7_IO10 0x0 + MX7D_PAD_ENET1_RGMII_RX_CTL__GPIO7_IO4 0x0 MX7D_PAD_ENET1_RGMII_TD0__GPIO7_IO6 0x0 MX7D_PAD_ENET1_RGMII_TD1__GPIO7_IO7 0x0 + MX7D_PAD_ENET1_RGMII_TX_CTL__GPIO7_IO10 0x0 MX7D_PAD_GPIO1_IO12__GPIO1_IO12 0x0 MX7D_PAD_SD2_CD_B__GPIO5_IO9 0x0 MX7D_PAD_SD2_WP__GPIO5_IO10 0x0 >; }; - pinctrl_ecspi3_cs: ecspi3-cs-grp { + pinctrl_flexcan1: flexcan1grp { fsl,pins = < - MX7D_PAD_I2C2_SDA__GPIO4_IO11 0x14 + MX7D_PAD_ENET1_RGMII_RD2__FLEXCAN1_RX 0x79 /* SODIMM 63 */ + MX7D_PAD_ENET1_RGMII_RD3__FLEXCAN1_TX 0x79 /* SODIMM 55 */ >; }; - pinctrl_ecspi3: ecspi3-grp { + pinctrl_flexcan2: flexcan2grp { fsl,pins = < - MX7D_PAD_I2C1_SCL__ECSPI3_MISO 0x2 - MX7D_PAD_I2C1_SDA__ECSPI3_MOSI 0x2 - MX7D_PAD_I2C2_SCL__ECSPI3_SCLK 0x2 + MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x79 /* SODIMM 188 */ + MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x79 /* SODIMM 178 */ >; }; - pinctrl_flexcan1: flexcan1-grp { + pinctrl_gpio1: gpio1grp { fsl,pins = < - MX7D_PAD_ENET1_RGMII_RD3__FLEXCAN1_TX 0x79 /* SODIMM 55 */ - MX7D_PAD_ENET1_RGMII_RD2__FLEXCAN1_RX 0x79 /* SODIMM 63 */ + MX7D_PAD_EPDC_BDR1__GPIO2_IO29 0x14 /* SODIMM 110 */ + MX7D_PAD_EPDC_DATA00__GPIO2_IO0 0x14 /* SODIMM 111 */ + MX7D_PAD_EPDC_DATA01__GPIO2_IO1 0x14 /* SODIMM 113 */ + MX7D_PAD_EPDC_DATA02__GPIO2_IO2 0x14 /* SODIMM 115 */ + MX7D_PAD_EPDC_DATA03__GPIO2_IO3 0x14 /* SODIMM 117 */ + MX7D_PAD_EPDC_DATA04__GPIO2_IO4 0x14 /* SODIMM 119 */ + MX7D_PAD_EPDC_DATA05__GPIO2_IO5 0x14 /* SODIMM 121 */ + MX7D_PAD_EPDC_DATA06__GPIO2_IO6 0x14 /* SODIMM 123 */ + MX7D_PAD_EPDC_DATA07__GPIO2_IO7 0x14 /* SODIMM 125 */ + MX7D_PAD_EPDC_DATA08__GPIO2_IO8 0x74 /* SODIMM 91 */ + MX7D_PAD_EPDC_DATA09__GPIO2_IO9 0x14 /* SODIMM 89 */ + MX7D_PAD_EPDC_DATA10__GPIO2_IO10 0x74 /* SODIMM 105 */ + MX7D_PAD_EPDC_DATA11__GPIO2_IO11 0x14 /* SODIMM 152 */ + MX7D_PAD_EPDC_DATA12__GPIO2_IO12 0x14 /* SODIMM 150 */ + MX7D_PAD_EPDC_DATA14__GPIO2_IO14 0x14 /* SODIMM 126 */ + MX7D_PAD_EPDC_GDCLK__GPIO2_IO24 0x14 /* SODIMM 132 */ + MX7D_PAD_EPDC_GDOE__GPIO2_IO25 0x14 /* SODIMM 134 */ + MX7D_PAD_EPDC_GDRL__GPIO2_IO26 0x14 /* SODIMM 133 */ + MX7D_PAD_EPDC_GDSP__GPIO2_IO27 0x14 /* SODIMM 104 */ + MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 0x14 /* SODIMM 112 */ + MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 0x14 /* SODIMM 128 */ + MX7D_PAD_EPDC_SDCE0__GPIO2_IO20 0x14 /* SODIMM 122 */ + MX7D_PAD_EPDC_SDCE1__GPIO2_IO21 0x14 /* SODIMM 124 */ + MX7D_PAD_EPDC_SDCE2__GPIO2_IO22 0x14 /* SODIMM 127 */ + MX7D_PAD_EPDC_SDCE3__GPIO2_IO23 0x14 /* SODIMM 130 */ + MX7D_PAD_EPDC_SDCLK__GPIO2_IO16 0x14 /* SODIMM 114 */ + MX7D_PAD_EPDC_SDLE__GPIO2_IO17 0x14 /* SODIMM 116 */ + MX7D_PAD_EPDC_SDOE__GPIO2_IO18 0x14 /* SODIMM 118 */ + MX7D_PAD_EPDC_SDSHR__GPIO2_IO19 0x14 /* SODIMM 120 */ + MX7D_PAD_LCD_RESET__GPIO3_IO4 0x14 /* SODIMM 93 */ + MX7D_PAD_SAI1_RX_BCLK__GPIO6_IO17 0x14 /* SODIMM 24 */ + MX7D_PAD_SAI1_RX_DATA__GPIO6_IO12 0x14 /* SODIMM 169 */ + MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16 0x14 /* SODIMM 77 */ + MX7D_PAD_SD2_CLK__GPIO5_IO12 0x14 /* SODIMM 184 */ + MX7D_PAD_SD2_CMD__GPIO5_IO13 0x14 /* SODIMM 186 */ + MX7D_PAD_SD2_DATA2__GPIO5_IO16 0x14 /* SODIMM 100 */ + MX7D_PAD_SD2_DATA3__GPIO5_IO17 0x14 /* SODIMM 102 */ + MX7D_PAD_UART3_RTS_B__GPIO4_IO6 0x14 /* SODIMM 131 */ >; }; - pinctrl_flexcan2: flexcan2-grp { + pinctrl_gpio2: gpio2grp { /* On X22 Camera interface */ fsl,pins = < - MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x79 /* SODIMM 188 */ - MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x79 /* SODIMM 178 */ + MX7D_PAD_ECSPI1_MISO__GPIO4_IO18 0x14 /* SODIMM 79 */ + MX7D_PAD_ECSPI1_MOSI__GPIO4_IO17 0x14 /* SODIMM 103 */ + MX7D_PAD_ECSPI1_SCLK__GPIO4_IO16 0x14 /* SODIMM 101 */ + MX7D_PAD_ECSPI1_SS0__GPIO4_IO19 0x14 /* SODIMM 97 */ + MX7D_PAD_ECSPI2_MISO__GPIO4_IO22 0x14 /* SODIMM 85 */ + MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 0x14 /* SODIMM 65 */ + MX7D_PAD_I2C3_SCL__GPIO4_IO12 0x14 /* SODIMM 81 */ + MX7D_PAD_I2C3_SDA__GPIO4_IO13 0x14 /* SODIMM 94 */ + MX7D_PAD_I2C4_SCL__GPIO4_IO14 0x14 /* SODIMM 96 */ + MX7D_PAD_I2C4_SDA__GPIO4_IO15 0x14 /* SODIMM 75 */ + MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x74 /* SODIMM 69 */ + MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x14 /* SODIMM 98 */ + >; + }; + + pinctrl_gpio3: gpio3grp { /* LCD 18-23 */ + fsl,pins = < + MX7D_PAD_LCD_DATA18__GPIO3_IO23 0x14 /* SODIMM 136 */ + MX7D_PAD_LCD_DATA19__GPIO3_IO24 0x14 /* SODIMM 138 */ + MX7D_PAD_LCD_DATA20__GPIO3_IO25 0x14 /* SODIMM 140 */ + MX7D_PAD_LCD_DATA21__GPIO3_IO26 0x14 /* SODIMM 142 */ + MX7D_PAD_LCD_DATA22__GPIO3_IO27 0x74 /* SODIMM 144 */ + MX7D_PAD_LCD_DATA23__GPIO3_IO28 0x74 /* SODIMM 146 */ + >; + }; + + pinctrl_gpio4: gpio4grp { /* Alternatively CAN2 */ + fsl,pins = < + MX7D_PAD_GPIO1_IO14__GPIO1_IO14 0x14 /* SODIMM 188 */ + MX7D_PAD_GPIO1_IO15__GPIO1_IO15 0x14 /* SODIMM 178 */ + >; + }; + + pinctrl_gpio7: gpio7grp { /* Alternatively CAN1 */ + fsl,pins = < + MX7D_PAD_ENET1_RGMII_RD2__GPIO7_IO2 0x14 /* SODIMM 63 */ + MX7D_PAD_ENET1_RGMII_RD3__GPIO7_IO3 0x14 /* SODIMM 55 */ >; }; - pinctrl_gpio_bl_on: gpio-bl-on { + pinctrl_gpio_bl_on: gpioblongrp { fsl,pins = < MX7D_PAD_SD1_WP__GPIO5_IO1 0x14 /* SODIMM 71 */ >; }; - pinctrl_gpmi_nand: gpmi-nand-grp { + pinctrl_gpmi_nand: gpminandgrp { fsl,pins = < - MX7D_PAD_SD3_CLK__NAND_CLE 0x71 - MX7D_PAD_SD3_CMD__NAND_ALE 0x71 MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B 0x71 MX7D_PAD_SAI1_TX_DATA__NAND_READY_B 0x74 - MX7D_PAD_SD3_STROBE__NAND_RE_B 0x71 - MX7D_PAD_SD3_RESET_B__NAND_WE_B 0x71 + MX7D_PAD_SD3_CLK__NAND_CLE 0x71 + MX7D_PAD_SD3_CMD__NAND_ALE 0x71 MX7D_PAD_SD3_DATA0__NAND_DATA00 0x71 MX7D_PAD_SD3_DATA1__NAND_DATA01 0x71 MX7D_PAD_SD3_DATA2__NAND_DATA02 0x71 @@ -669,13 +836,21 @@ MX7D_PAD_SD3_DATA5__NAND_DATA05 0x71 MX7D_PAD_SD3_DATA6__NAND_DATA06 0x71 MX7D_PAD_SD3_DATA7__NAND_DATA07 0x71 + MX7D_PAD_SD3_RESET_B__NAND_WE_B 0x71 + MX7D_PAD_SD3_STROBE__NAND_RE_B 0x71 >; }; - pinctrl_i2c4: i2c4-grp { + pinctrl_i2c1_int: i2c1intgrp { /* PMIC / TOUCH */ fsl,pins = < - MX7D_PAD_ENET1_RGMII_TD3__I2C4_SDA 0x4000007f - MX7D_PAD_ENET1_RGMII_TD2__I2C4_SCL 0x4000007f + MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x79 + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX7D_PAD_ENET1_RGMII_TD2__I2C4_SCL 0x4000007f /* SODIMM 196 */ + MX7D_PAD_ENET1_RGMII_TD3__I2C4_SDA 0x4000007f /* SODIMM 194 */ >; }; @@ -686,155 +861,176 @@ >; }; - pinctrl_lcdif_dat: lcdif-dat-grp { + pinctrl_lcdif_dat: lcdifdatgrp { + fsl,pins = < + MX7D_PAD_LCD_DATA00__LCD_DATA0 0x79 /* SODIMM 76 */ + MX7D_PAD_LCD_DATA01__LCD_DATA1 0x79 /* SODIMM 70 */ + MX7D_PAD_LCD_DATA02__LCD_DATA2 0x79 /* SODIMM 60 */ + MX7D_PAD_LCD_DATA03__LCD_DATA3 0x79 /* SODIMM 58 */ + MX7D_PAD_LCD_DATA04__LCD_DATA4 0x79 /* SODIMM 78 */ + MX7D_PAD_LCD_DATA05__LCD_DATA5 0x79 /* SODIMM 72 */ + MX7D_PAD_LCD_DATA06__LCD_DATA6 0x79 /* SODIMM 80 */ + MX7D_PAD_LCD_DATA07__LCD_DATA7 0x79 /* SODIMM 46 */ + MX7D_PAD_LCD_DATA08__LCD_DATA8 0x79 /* SODIMM 62 */ + MX7D_PAD_LCD_DATA09__LCD_DATA9 0x79 /* SODIMM 48 */ + MX7D_PAD_LCD_DATA10__LCD_DATA10 0x79 /* SODIMM 74 */ + MX7D_PAD_LCD_DATA11__LCD_DATA11 0x79 /* SODIMM 50 */ + MX7D_PAD_LCD_DATA12__LCD_DATA12 0x79 /* SODIMM 52 */ + MX7D_PAD_LCD_DATA13__LCD_DATA13 0x79 /* SODIMM 54 */ + MX7D_PAD_LCD_DATA14__LCD_DATA14 0x79 /* SODIMM 66 */ + MX7D_PAD_LCD_DATA15__LCD_DATA15 0x79 /* SODIMM 64 */ + MX7D_PAD_LCD_DATA16__LCD_DATA16 0x79 /* SODIMM 57 */ + MX7D_PAD_LCD_DATA17__LCD_DATA17 0x79 /* SODIMM 61 */ + >; + }; + + pinctrl_lcdif_dat_24: lcdifdat24grp { fsl,pins = < - MX7D_PAD_LCD_DATA00__LCD_DATA0 0x79 - MX7D_PAD_LCD_DATA01__LCD_DATA1 0x79 - MX7D_PAD_LCD_DATA02__LCD_DATA2 0x79 - MX7D_PAD_LCD_DATA03__LCD_DATA3 0x79 - MX7D_PAD_LCD_DATA04__LCD_DATA4 0x79 - MX7D_PAD_LCD_DATA05__LCD_DATA5 0x79 - MX7D_PAD_LCD_DATA06__LCD_DATA6 0x79 - MX7D_PAD_LCD_DATA07__LCD_DATA7 0x79 - MX7D_PAD_LCD_DATA08__LCD_DATA8 0x79 - MX7D_PAD_LCD_DATA09__LCD_DATA9 0x79 - MX7D_PAD_LCD_DATA10__LCD_DATA10 0x79 - MX7D_PAD_LCD_DATA11__LCD_DATA11 0x79 - MX7D_PAD_LCD_DATA12__LCD_DATA12 0x79 - MX7D_PAD_LCD_DATA13__LCD_DATA13 0x79 - MX7D_PAD_LCD_DATA14__LCD_DATA14 0x79 - MX7D_PAD_LCD_DATA15__LCD_DATA15 0x79 - MX7D_PAD_LCD_DATA16__LCD_DATA16 0x79 - MX7D_PAD_LCD_DATA17__LCD_DATA17 0x79 + MX7D_PAD_LCD_DATA18__LCD_DATA18 0x79 /* SODIMM 136 */ + MX7D_PAD_LCD_DATA19__LCD_DATA19 0x79 /* SODIMM 138 */ + MX7D_PAD_LCD_DATA20__LCD_DATA20 0x79 /* SODIMM 140 */ + MX7D_PAD_LCD_DATA21__LCD_DATA21 0x79 /* SODIMM 142 */ + MX7D_PAD_LCD_DATA22__LCD_DATA22 0x79 /* SODIMM 144 */ + MX7D_PAD_LCD_DATA23__LCD_DATA23 0x79 /* SODIMM 146 */ >; }; - pinctrl_lcdif_dat_24: lcdif-dat-24-grp { + pinctrl_lcdif_ctrl: lcdifctrlgrp { fsl,pins = < - MX7D_PAD_LCD_DATA18__LCD_DATA18 0x79 - MX7D_PAD_LCD_DATA19__LCD_DATA19 0x79 - MX7D_PAD_LCD_DATA20__LCD_DATA20 0x79 - MX7D_PAD_LCD_DATA21__LCD_DATA21 0x79 - MX7D_PAD_LCD_DATA22__LCD_DATA22 0x79 - MX7D_PAD_LCD_DATA23__LCD_DATA23 0x79 + MX7D_PAD_LCD_CLK__LCD_CLK 0x79 /* SODIMM 56 */ + MX7D_PAD_LCD_ENABLE__LCD_ENABLE 0x79 /* SODIMM 44 */ + MX7D_PAD_LCD_HSYNC__LCD_HSYNC 0x79 /* SODIMM 68 */ + MX7D_PAD_LCD_VSYNC__LCD_VSYNC 0x79 /* SODIMM 82 */ >; }; - pinctrl_lcdif_ctrl: lcdif-ctrl-grp { + pinctrl_lvds_transceiver: lvdstx { fsl,pins = < - MX7D_PAD_LCD_CLK__LCD_CLK 0x79 - MX7D_PAD_LCD_ENABLE__LCD_ENABLE 0x79 - MX7D_PAD_LCD_VSYNC__LCD_VSYNC 0x79 - MX7D_PAD_LCD_HSYNC__LCD_HSYNC 0x79 + MX7D_PAD_ENET1_RGMII_RD2__GPIO7_IO2 0x14 /* SODIMM 63 */ + MX7D_PAD_ENET1_RGMII_RD3__GPIO7_IO3 0x74 /* SODIMM 55 */ + MX7D_PAD_ENET1_RGMII_TXC__GPIO7_IO11 0x14 /* SODIMM 99 */ + MX7D_PAD_EPDC_DATA13__GPIO2_IO13 0x14 /* SODIMM 95 */ >; }; - pinctrl_pwm1: pwm1-grp { + pinctrl_pwm1: pwm1grp { fsl,pins = < - MX7D_PAD_GPIO1_IO08__PWM1_OUT 0x79 - MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 0x4 + MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 0x4 /* SODIMM 59 */ + MX7D_PAD_GPIO1_IO08__PWM1_OUT 0x79 /* SODIMM 59 */ >; }; - pinctrl_pwm2: pwm2-grp { + pinctrl_pwm2: pwm2grp { fsl,pins = < - MX7D_PAD_GPIO1_IO09__PWM2_OUT 0x79 + MX7D_PAD_GPIO1_IO09__PWM2_OUT 0x79 /* SODIMM 28 */ >; }; - pinctrl_pwm3: pwm3-grp { + pinctrl_pwm3: pwm3grp { fsl,pins = < - MX7D_PAD_GPIO1_IO10__PWM3_OUT 0x79 + MX7D_PAD_GPIO1_IO10__PWM3_OUT 0x79 /* SODIMM 30 */ >; }; - pinctrl_pwm4: pwm4-grp { + pinctrl_pwm4: pwm4grp { fsl,pins = < - MX7D_PAD_GPIO1_IO11__PWM4_OUT 0x79 - MX7D_PAD_ECSPI2_SCLK__GPIO4_IO20 0x4 + MX7D_PAD_ECSPI2_SCLK__GPIO4_IO20 0x4 /* SODIMM 67 */ + MX7D_PAD_GPIO1_IO11__PWM4_OUT 0x79 /* SODIMM 67 */ >; }; - pinctrl_uart1: uart1-grp { + pinctrl_uart1: uart1grp { fsl,pins = < - MX7D_PAD_UART1_TX_DATA__UART1_DTE_RX 0x79 - MX7D_PAD_UART1_RX_DATA__UART1_DTE_TX 0x79 - MX7D_PAD_SAI2_TX_BCLK__UART1_DTE_CTS 0x79 - MX7D_PAD_SAI2_TX_SYNC__UART1_DTE_RTS 0x79 + MX7D_PAD_SAI2_TX_BCLK__UART1_DTE_CTS 0x79 /* SODIMM 25 */ + MX7D_PAD_SAI2_TX_SYNC__UART1_DTE_RTS 0x79 /* SODIMM 27 */ + MX7D_PAD_UART1_RX_DATA__UART1_DTE_TX 0x79 /* SODIMM 35 */ + MX7D_PAD_UART1_TX_DATA__UART1_DTE_RX 0x79 /* SODIMM 33 */ >; }; - pinctrl_uart1_ctrl1: uart1-ctrl1-grp { + pinctrl_uart1_ctrl1: uart1ctrl1grp { fsl,pins = < - MX7D_PAD_SD2_DATA1__GPIO5_IO15 0x14 /* DCD */ - MX7D_PAD_SD2_DATA0__GPIO5_IO14 0x14 /* DTR */ + MX7D_PAD_SD2_DATA0__GPIO5_IO14 0x14 /* SODIMM 23 / DTR */ + MX7D_PAD_SD2_DATA1__GPIO5_IO15 0x14 /* SODIMM 31 / DCD */ >; }; - pinctrl_uart2: uart2-grp { + pinctrl_uart2: uart2grp { + fsl,pins = < + MX7D_PAD_SAI2_RX_DATA__UART2_DTE_RTS 0x79 /* SODIMM 32 / CTS */ + MX7D_PAD_SAI2_TX_DATA__UART2_DTE_CTS 0x79 /* SODIMM 34 / RTS */ + MX7D_PAD_UART2_RX_DATA__UART2_DTE_TX 0x79 /* SODIMM 38 */ + MX7D_PAD_UART2_TX_DATA__UART2_DTE_RX 0x79 /* SODIMM 36 */ + >; + }; + pinctrl_uart3: uart3grp { fsl,pins = < - MX7D_PAD_UART2_TX_DATA__UART2_DTE_RX 0x79 - MX7D_PAD_UART2_RX_DATA__UART2_DTE_TX 0x79 - MX7D_PAD_SAI2_RX_DATA__UART2_DTE_RTS 0x79 - MX7D_PAD_SAI2_TX_DATA__UART2_DTE_CTS 0x79 + MX7D_PAD_UART3_RX_DATA__UART3_DTE_TX 0x79 /* SODIMM 21 */ + MX7D_PAD_UART3_TX_DATA__UART3_DTE_RX 0x79 /* SODIMM 19 */ >; }; - pinctrl_uart3: uart3-grp { + + pinctrl_usbc_det: usbcdetgrp { fsl,pins = < - MX7D_PAD_UART3_TX_DATA__UART3_DTE_RX 0x79 - MX7D_PAD_UART3_RX_DATA__UART3_DTE_TX 0x79 + MX7D_PAD_ENET1_CRS__GPIO7_IO14 0x14 /* SODIMM 137 / USBC_DET */ >; }; - pinctrl_usbc_det: gpio-usbc-det { + pinctrl_usbh_reg: usbhreggrp { fsl,pins = < - MX7D_PAD_ENET1_CRS__GPIO7_IO14 0x14 + MX7D_PAD_UART3_CTS_B__GPIO4_IO7 0x14 /* SODIMM 129 / USBH_PEN */ >; }; - pinctrl_usbh_reg: gpio-usbh-vbus { + pinctrl_usdhc1: usdhc1grp { fsl,pins = < - MX7D_PAD_UART3_CTS_B__GPIO4_IO7 0x14 /* SODIMM 129 USBH PEN */ + MX7D_PAD_SD1_CLK__SD1_CLK 0x19 /* SODIMM 47 */ + MX7D_PAD_SD1_CMD__SD1_CMD 0x59 /* SODIMM 190 */ + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 /* SODIMM 192 */ + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 /* SODIMM 49 */ + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 /* SODIMM 51 */ + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 /* SODIMM 53 */ >; }; - pinctrl_usdhc1: usdhc1-grp { + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { fsl,pins = < - MX7D_PAD_SD1_CMD__SD1_CMD 0x59 - MX7D_PAD_SD1_CLK__SD1_CLK 0x19 - MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 - MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 - MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 - MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 + MX7D_PAD_SD1_CLK__SD1_CLK 0x1a + MX7D_PAD_SD1_CMD__SD1_CMD 0x5a + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5a + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5a + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5a + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5a >; }; - pinctrl_usdhc1_100mhz: usdhc1grp_100mhz { + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { fsl,pins = < - MX7D_PAD_SD1_CMD__SD1_CMD 0x5a - MX7D_PAD_SD1_CLK__SD1_CLK 0x1a - MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5a - MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5a - MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5a - MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5a + MX7D_PAD_SD1_CLK__SD1_CLK 0x1b + MX7D_PAD_SD1_CMD__SD1_CMD 0x5b + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5b + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5b + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5b + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5b >; }; - pinctrl_usdhc1_200mhz: usdhc1grp_200mhz { + /* Avoid backfeeding with removed card power. */ + pinctrl_usdhc1_sleep: usdhc1-slpgrp { fsl,pins = < - MX7D_PAD_SD1_CMD__SD1_CMD 0x5b - MX7D_PAD_SD1_CLK__SD1_CLK 0x1b - MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5b - MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5b - MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5b - MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5b + MX7D_PAD_SD1_CMD__SD1_CMD 0x10 + MX7D_PAD_SD1_CLK__SD1_CLK 0x10 + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x10 + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x10 + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x10 + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x10 >; }; pinctrl_usdhc3: usdhc3grp { fsl,pins = < - MX7D_PAD_SD3_CMD__SD3_CMD 0x59 MX7D_PAD_SD3_CLK__SD3_CLK 0x19 + MX7D_PAD_SD3_CMD__SD3_CMD 0x59 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59 @@ -847,10 +1043,10 @@ >; }; - pinctrl_usdhc3_100mhz: usdhc3grp_100mhz { + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { fsl,pins = < - MX7D_PAD_SD3_CMD__SD3_CMD 0x5a MX7D_PAD_SD3_CLK__SD3_CLK 0x1a + MX7D_PAD_SD3_CMD__SD3_CMD 0x5a MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a @@ -863,10 +1059,10 @@ >; }; - pinctrl_usdhc3_200mhz: usdhc3grp_200mhz { + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { fsl,pins = < - MX7D_PAD_SD3_CMD__SD3_CMD 0x5b MX7D_PAD_SD3_CLK__SD3_CLK 0x1b + MX7D_PAD_SD3_CMD__SD3_CMD 0x5b MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b @@ -879,16 +1075,16 @@ >; }; - pinctrl_sai1: sai1-grp { + pinctrl_sai1: sai1grp { fsl,pins = < - MX7D_PAD_ENET1_RX_CLK__SAI1_TX_BCLK 0x1f - MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC 0x1f MX7D_PAD_ENET1_COL__SAI1_TX_DATA0 0x30 + MX7D_PAD_ENET1_RX_CLK__SAI1_TX_BCLK 0x1f MX7D_PAD_ENET1_TX_CLK__SAI1_RX_DATA0 0x1f + MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC 0x1f >; }; - pinctrl_sai1_mclk: sai1grp_mclk { + pinctrl_sai1_mclk: sai1mclkgrp { fsl,pins = < MX7D_PAD_SAI1_MCLK__SAI1_MCLK 0x1f >; @@ -899,23 +1095,35 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_lpsr>; - pinctrl_gpio_lpsr: gpio1-grp { + pinctrl_cd_usdhc1: cdusdhc1grp { fsl,pins = < - MX7D_PAD_LPSR_GPIO1_IO02__GPIO1_IO2 0x59 - MX7D_PAD_LPSR_GPIO1_IO03__GPIO1_IO3 0x59 + MX7D_PAD_LPSR_GPIO1_IO00__GPIO1_IO0 0x59 /* SODIMM 43 / MMC_CD */ + >; + }; + + pinctrl_cd_usdhc1_sleep: cdusdhc1-slpgrp { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO00__GPIO1_IO0 0x0 + >; + }; + + pinctrl_gpio_lpsr: gpiolpsrgrp { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO02__GPIO1_IO2 0x59 /* SODIMM 135 */ + MX7D_PAD_LPSR_GPIO1_IO03__GPIO1_IO3 0x59 /* SODIMM 22 */ >; }; pinctrl_gpiokeys: gpiokeysgrp { fsl,pins = < - MX7D_PAD_LPSR_GPIO1_IO01__GPIO1_IO1 0x19 + MX7D_PAD_LPSR_GPIO1_IO01__GPIO1_IO1 0x19 /* SODIMM 45 / WAKE_UP */ >; }; - pinctrl_i2c1: i2c1-grp { + pinctrl_i2c1: i2c1grp { fsl,pins = < - MX7D_PAD_LPSR_GPIO1_IO05__I2C1_SDA 0x4000007f MX7D_PAD_LPSR_GPIO1_IO04__I2C1_SCL 0x4000007f + MX7D_PAD_LPSR_GPIO1_IO05__I2C1_SDA 0x4000007f >; }; @@ -926,16 +1134,10 @@ >; }; - pinctrl_cd_usdhc1: usdhc1-cd-grp { - fsl,pins = < - MX7D_PAD_LPSR_GPIO1_IO00__GPIO1_IO0 0x59 /* CD */ - >; - }; - - pinctrl_uart1_ctrl2: uart1-ctrl2-grp { + pinctrl_uart1_ctrl2: uart1ctrl2grp { fsl,pins = < - MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x14 /* DSR */ - MX7D_PAD_LPSR_GPIO1_IO06__GPIO1_IO6 0x14 /* RI */ + MX7D_PAD_LPSR_GPIO1_IO06__GPIO1_IO6 0x14 /* SODIMM 37 / RI */ + MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x14 /* SODIMM 29 / DSR */ >; }; }; diff --git a/arch/arm/boot/dts/imx7d-colibri-aster.dts b/arch/arm/boot/dts/imx7d-colibri-aster.dts index f3f0537d5a37..90aaeddfb4f6 100644 --- a/arch/arm/boot/dts/imx7d-colibri-aster.dts +++ b/arch/arm/boot/dts/imx7d-colibri-aster.dts @@ -1,7 +1,6 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT /* - * Copyright 2017-2020 Toradex AG - * + * Copyright 2017-2022 Toradex */ /dts-v1/; @@ -10,11 +9,32 @@ / { model = "Toradex Colibri iMX7D on Aster Carrier Board"; - compatible = "toradex,colibri-imx7d-aster", "toradex,colibri-imx7d", + compatible = "toradex,colibri-imx7d-aster", + "toradex,colibri-imx7d", "fsl,imx7d"; }; +&ad7879_ts { + status = "okay"; +}; + +&atmel_mxt_ts { + status = "okay"; +}; + +&backlight { + status = "okay"; +}; + +&lcdif { + status = "okay"; +}; + +&panel_dpi { + status = "okay"; +}; + +/* Colibri USBH */ &usbotg2 { - vbus-supply = <®_usbh_vbus>; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx7d-colibri-emmc-aster.dts b/arch/arm/boot/dts/imx7d-colibri-emmc-aster.dts index 20480276cb0e..3ec9ef6baaa4 100644 --- a/arch/arm/boot/dts/imx7d-colibri-emmc-aster.dts +++ b/arch/arm/boot/dts/imx7d-colibri-emmc-aster.dts @@ -1,6 +1,6 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT /* - * Copyright 2017-2020 Toradex AG + * Copyright 2017-2022 Toradex * */ @@ -11,10 +11,12 @@ / { model = "Toradex Colibri iMX7D 1GB (eMMC) on Aster Carrier Board"; compatible = "toradex,colibri-imx7d-emmc-aster", - "toradex,colibri-imx7d-emmc", "fsl,imx7d"; + "toradex,colibri-imx7d-emmc", + "toradex,colibri-imx7d", + "fsl,imx7d"; }; +/* Colibri USBH */ &usbotg2 { - vbus-supply = <®_usbh_vbus>; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx7d-colibri-emmc-eval-v3.dts b/arch/arm/boot/dts/imx7d-colibri-emmc-eval-v3.dts index 8ee73c870b12..6d505cb02aad 100644 --- a/arch/arm/boot/dts/imx7d-colibri-emmc-eval-v3.dts +++ b/arch/arm/boot/dts/imx7d-colibri-emmc-eval-v3.dts @@ -1,6 +1,6 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT /* - * Copyright 2017 Toradex AG + * Copyright 2017-2022 Toradex */ /dts-v1/; @@ -10,10 +10,12 @@ / { model = "Toradex Colibri iMX7D 1GB (eMMC) on Colibri Evaluation Board V3"; compatible = "toradex,colibri-imx7d-emmc-eval-v3", - "toradex,colibri-imx7d-emmc", "fsl,imx7d"; + "toradex,colibri-imx7d-emmc", + "toradex,colibri-imx7d", + "fsl,imx7d"; }; +/* Colibri USBH */ &usbotg2 { - vbus-supply = <®_usbh_vbus>; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx7d-colibri-emmc-iris-v2.dts b/arch/arm/boot/dts/imx7d-colibri-emmc-iris-v2.dts new file mode 100644 index 000000000000..7347659557f3 --- /dev/null +++ b/arch/arm/boot/dts/imx7d-colibri-emmc-iris-v2.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2022 Toradex + */ + +/dts-v1/; +#include "imx7d-colibri-emmc.dtsi" +#include "imx7-colibri-iris-v2.dtsi" + +/ { + model = "Toradex Colibri iMX7D 1GB on Iris V2 Carrier Board"; + compatible = "toradex,colibri-imx7d-emmc-iris-v2", + "toradex,colibri-imx7d-emmc", + "toradex,colibri-imx7d", + "fsl,imx7d"; +}; + +/* Colibri USBH */ +&usbotg2 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx7d-colibri-emmc-iris.dts b/arch/arm/boot/dts/imx7d-colibri-emmc-iris.dts new file mode 100644 index 000000000000..5324c92e368d --- /dev/null +++ b/arch/arm/boot/dts/imx7d-colibri-emmc-iris.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2022 Toradex + */ + +/dts-v1/; +#include "imx7d-colibri-emmc.dtsi" +#include "imx7-colibri-iris.dtsi" + +/ { + model = "Toradex Colibri iMX7D 1GB on Iris Carrier Board"; + compatible = "toradex,colibri-imx7d-emmc-iris", + "toradex,colibri-imx7d-emmc", + "toradex,colibri-imx7d", + "fsl,imx7d"; +}; + +/* Colibri USBH */ +&usbotg2 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx7d-colibri-emmc.dtsi b/arch/arm/boot/dts/imx7d-colibri-emmc.dtsi index af39e5370fa1..2fb4d2133a1b 100644 --- a/arch/arm/boot/dts/imx7d-colibri-emmc.dtsi +++ b/arch/arm/boot/dts/imx7d-colibri-emmc.dtsi @@ -1,18 +1,28 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT /* - * Copyright 2017 Toradex AG + * Copyright 2017-2022 Toradex */ #include "imx7d.dtsi" #include "imx7-colibri.dtsi" / { + aliases { + /* Required to properly pass MAC addresses from bootloader. */ + ethernet0 = &fec1; + ethernet1 = &fec2; + }; + memory@80000000 { device_type = "memory"; reg = <0x80000000 0x40000000>; }; }; +&cpu1 { + cpu-supply = <®_DCDC2>; +}; + &gpio6 { gpio-line-names = "", "", @@ -39,10 +49,13 @@ "SODIMM_34"; }; +/* Colibri USBH */ &usbotg2 { dr_mode = "host"; + vbus-supply = <®_usbh_vbus>; }; +/* eMMC */ &usdhc3 { status = "okay"; }; diff --git a/arch/arm/boot/dts/imx7d-colibri-eval-v3.dts b/arch/arm/boot/dts/imx7d-colibri-eval-v3.dts index 87b132bcd272..c7a8b5aa2408 100644 --- a/arch/arm/boot/dts/imx7d-colibri-eval-v3.dts +++ b/arch/arm/boot/dts/imx7d-colibri-eval-v3.dts @@ -1,6 +1,6 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT /* - * Copyright 2016-2020 Toradex + * Copyright 2016-2022 Toradex */ /dts-v1/; @@ -9,11 +9,48 @@ / { model = "Toradex Colibri iMX7D on Colibri Evaluation Board V3"; - compatible = "toradex,colibri-imx7d-eval-v3", "toradex,colibri-imx7d", + compatible = "toradex,colibri-imx7d-eval-v3", + "toradex,colibri-imx7d", "fsl,imx7d"; }; +&ad7879_ts { + status = "okay"; +}; + +/* + * The Atmel maxtouch controller uses SODIMM 28/30, also used for PWM<B>, PWM<C>, aka pwm2, pwm3. + * So if you enable following capacitive touch controller, disable pwm2/pwm3 first. + */ +&atmel_mxt_ts { + status = "disabled"; +}; + +&backlight { + status = "okay"; +}; + +&lcdif { + status = "okay"; +}; + +&panel_dpi { + status = "okay"; +}; + +/* Colibri PWM<B> */ +&pwm2 { + /* The pwm2 should be disabled to enable atmel_mxt_ts touchscreen for adapter. */ + status = "okay"; +}; + +/* Colibri PWM<C> */ +&pwm3 { + /* The pwm3 should be disabled to enable atmel_mxt_ts touchscreen for adapter. */ + status = "okay"; +}; + +/* Colibri USBH */ &usbotg2 { - vbus-supply = <®_usbh_vbus>; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx7d-colibri-iris-v2.dts b/arch/arm/boot/dts/imx7d-colibri-iris-v2.dts new file mode 100644 index 000000000000..5762f51d5f0f --- /dev/null +++ b/arch/arm/boot/dts/imx7d-colibri-iris-v2.dts @@ -0,0 +1,83 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2022 Toradex + */ + +/dts-v1/; +#include "imx7d-colibri.dtsi" +#include "imx7-colibri-iris-v2.dtsi" + +/ { + model = "Toradex Colibri iMX7D on Iris V2 Carrier Board"; + compatible = "toradex,colibri-imx7d-iris-v2", + "toradex,colibri-imx7d", + "fsl,imx7d"; +}; + +&ad7879_ts { + status = "okay"; +}; + +&atmel_mxt_ts { + status = "okay"; +}; + +&backlight { + status = "okay"; +}; + +&gpio2 { + /* + * This switches the LVDS transceiver to VESA color mapping mode. + */ + lvds-color-map-hog { + gpio-hog; + gpios = <13 GPIO_ACTIVE_HIGH>; /* SODIMM 95 */ + line-name = "LVDS_COLOR_MAP"; + output-low; + }; +}; + +&gpio7 { + /* + * This switches the LVDS transceiver to the 24-bit RGB mode. + */ + lvds-rgb-mode-hog { + gpio-hog; + gpios = <2 GPIO_ACTIVE_HIGH>; /* SODIMM 63 */ + line-name = "LVDS_RGB_MODE"; + output-low; + }; + + /* + * This switches the LVDS transceiver to the single-channel + * output mode. + */ + lvds-ch-mode-hog { + gpio-hog; + gpios = <3 GPIO_ACTIVE_HIGH>; /* SODIMM 55 */ + line-name = "LVDS_CH_MODE"; + output-high; + }; + + /* This turns the LVDS transceiver on */ + lvds-power-on-hog { + gpio-hog; + gpios = <11 GPIO_ACTIVE_HIGH>; /* SODIMM 99 */ + line-name = "LVDS_POWER_ON"; + output-high; + }; +}; + +&lcdif { + status = "okay"; +}; + +&panel_dpi { + status = "okay"; +}; + +/* Colibri USBH */ +&usbotg2 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx7d-colibri-iris.dts b/arch/arm/boot/dts/imx7d-colibri-iris.dts new file mode 100644 index 000000000000..9c63cb9d9a64 --- /dev/null +++ b/arch/arm/boot/dts/imx7d-colibri-iris.dts @@ -0,0 +1,56 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2022 Toradex + */ + +/dts-v1/; +#include "imx7d-colibri.dtsi" +#include "imx7-colibri-iris.dtsi" + +/ { + model = "Toradex Colibri iMX7D on Iris Carrier Board"; + compatible = "toradex,colibri-imx7d-iris", + "toradex,colibri-imx7d", + "fsl,imx7d"; +}; + +&ad7879_ts { + status = "okay"; +}; + +/* + * The Atmel maxtouch controller uses SODIMM 28/30, also used for PWM<B>, PWM<C>, aka pwm2, pwm3. + * So if you enable following capacitive touch controller, disable pwm2/pwm3 first. + */ +&atmel_mxt_ts { + status = "disabled"; +}; + +&backlight { + status = "okay"; +}; + +&lcdif { + status = "okay"; +}; + +&panel_dpi { + status = "okay"; +}; + +/* Colibri PWM<B> */ +&pwm2 { + /* The pwm2 should be disabled to enable atmel_mxt_ts touchscreen for adapter. */ + status = "okay"; +}; + +/* Colibri PWM<C> */ +&pwm3 { + /* The pwm3 should be disabled to enable atmel_mxt_ts touchscreen for adapter. */ + status = "okay"; +}; + +/* Colibri USBH */ +&usbotg2 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx7d-colibri.dtsi b/arch/arm/boot/dts/imx7d-colibri.dtsi index 219a0404a058..531a45b176a1 100644 --- a/arch/arm/boot/dts/imx7d-colibri.dtsi +++ b/arch/arm/boot/dts/imx7d-colibri.dtsi @@ -1,12 +1,18 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT /* - * Copyright 2016-2020 Toradex + * Copyright 2016-2022 Toradex */ #include "imx7d.dtsi" #include "imx7-colibri.dtsi" / { + aliases { + /* Required to properly pass MAC addresses from bootloader. */ + ethernet0 = &fec1; + ethernet1 = &fec2; + }; + memory@80000000 { device_type = "memory"; reg = <0x80000000 0x20000000>; @@ -17,10 +23,13 @@ cpu-supply = <®_DCDC2>; }; +/* NAND */ &gpmi { status = "okay"; }; +/* Colibri USBH */ &usbotg2 { dr_mode = "host"; + vbus-supply = <®_usbh_vbus>; }; diff --git a/arch/arm/boot/dts/imx7d-sdb.dts b/arch/arm/boot/dts/imx7d-sdb.dts index f053f5122741..78f4224a9bf4 100644 --- a/arch/arm/boot/dts/imx7d-sdb.dts +++ b/arch/arm/boot/dts/imx7d-sdb.dts @@ -201,7 +201,7 @@ compatible = "ti,tsc2046"; reg = <0>; spi-max-frequency = <1000000>; - pinctrl-names ="default"; + pinctrl-names = "default"; pinctrl-0 = <&pinctrl_tsc2046_pendown>; interrupt-parent = <&gpio2>; interrupts = <29 0>; diff --git a/arch/arm/boot/dts/imx7d-smegw01.dts b/arch/arm/boot/dts/imx7d-smegw01.dts index 21b509c43393..546268b8d0b1 100644 --- a/arch/arm/boot/dts/imx7d-smegw01.dts +++ b/arch/arm/boot/dts/imx7d-smegw01.dts @@ -207,7 +207,7 @@ pinctrl-0 = <&pinctrl_usdhc1>; cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; no-1-8-v; - enable-sdio-wakeup; + wakeup-source; keep-power-in-suspend; status = "okay"; }; @@ -219,7 +219,7 @@ no-1-8-v; non-removable; vmmc-supply = <®_wifi>; - enable-sdio-wakeup; + wakeup-source; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx7d.dtsi b/arch/arm/boot/dts/imx7d.dtsi index f8cba47536a0..7ceb7c09f7ad 100644 --- a/arch/arm/boot/dts/imx7d.dtsi +++ b/arch/arm/boot/dts/imx7d.dtsi @@ -78,7 +78,7 @@ #phy-cells = <0>; }; - soc { + soc: soc { etm@3007d000 { compatible = "arm,coresight-etm3x", "arm,primecell"; reg = <0x3007d000 0x1000>; diff --git a/arch/arm/boot/dts/imx7s-colibri-aster.dts b/arch/arm/boot/dts/imx7s-colibri-aster.dts index fca4e0a95c1b..58ebb02d948a 100644 --- a/arch/arm/boot/dts/imx7s-colibri-aster.dts +++ b/arch/arm/boot/dts/imx7s-colibri-aster.dts @@ -1,6 +1,6 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT /* - * Copyright 2017-2020 Toradex AG + * Copyright 2017-2022 Toradex * */ @@ -10,6 +10,27 @@ / { model = "Toradex Colibri iMX7S on Aster Carrier Board"; - compatible = "toradex,colibri-imx7s-aster", "toradex,colibri-imx7s", + compatible = "toradex,colibri-imx7s-aster", + "toradex,colibri-imx7s", "fsl,imx7s"; }; + +&ad7879_ts { + status = "okay"; +}; + +&atmel_mxt_ts { + status = "okay"; +}; + +&backlight { + status = "okay"; +}; + +&lcdif { + status = "okay"; +}; + +&panel_dpi { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx7s-colibri-eval-v3.dts b/arch/arm/boot/dts/imx7s-colibri-eval-v3.dts index aa70d3f2e2e2..38de76630d6a 100644 --- a/arch/arm/boot/dts/imx7s-colibri-eval-v3.dts +++ b/arch/arm/boot/dts/imx7s-colibri-eval-v3.dts @@ -1,6 +1,6 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT /* - * Copyright 2016-2020 Toradex + * Copyright 2016-2022 Toradex */ /dts-v1/; @@ -9,6 +9,43 @@ / { model = "Toradex Colibri iMX7S on Colibri Evaluation Board V3"; - compatible = "toradex,colibri-imx7s-eval-v3", "toradex,colibri-imx7s", + compatible = "toradex,colibri-imx7s-eval-v3", + "toradex,colibri-imx7s", "fsl,imx7s"; }; + +&ad7879_ts { + status = "okay"; +}; + +/* + * The Atmel maxtouch controller uses SODIMM 28/30, also used for PWM<B>, PWM<C>, aka pwm2, pwm3. + * So if you enable following capacitive touch controller, disable pwm2/pwm3 first. + */ +&atmel_mxt_ts { + status = "disabled"; +}; + +&backlight { + status = "okay"; +}; + +&lcdif { + status = "okay"; +}; + +&panel_dpi { + status = "okay"; +}; + +/* Colibri PWM<B> */ +&pwm2 { + /* The pwm2 should be disabled to enable atmel_mxt_ts touchscreen for adapter. */ + status = "okay"; +}; + +/* Colibri PWM<C> */ +&pwm3 { + /* The pwm3 should be disabled to enable atmel_mxt_ts touchscreen for adapter. */ + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx7s-colibri-iris-v2.dts b/arch/arm/boot/dts/imx7s-colibri-iris-v2.dts new file mode 100644 index 000000000000..72b5c17ab1ab --- /dev/null +++ b/arch/arm/boot/dts/imx7s-colibri-iris-v2.dts @@ -0,0 +1,78 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2022 Toradex + */ + +/dts-v1/; +#include "imx7s-colibri.dtsi" +#include "imx7-colibri-iris-v2.dtsi" + +/ { + model = "Toradex Colibri iMX7S on Iris V2 Carrier Board"; + compatible = "toradex,colibri-imx7s-iris-v2", + "toradex,colibri-imx7s", + "fsl,imx7s"; +}; + +&ad7879_ts { + status = "okay"; +}; + +&atmel_mxt_ts { + status = "okay"; +}; + +&backlight { + status = "okay"; +}; + +&gpio2 { + /* + * This switches the LVDS transceiver to VESA color mapping mode. + */ + lvds-color-map-hog { + gpio-hog; + gpios = <13 GPIO_ACTIVE_HIGH>; /* SODIMM 95 */ + line-name = "LVDS_COLOR_MAP"; + output-low; + }; +}; + +&gpio7 { + /* + * This switches the LVDS transceiver to the 24-bit RGB mode. + */ + lvds-rgb-mode-hog { + gpio-hog; + gpios = <2 GPIO_ACTIVE_HIGH>; /* SODIMM 63 */ + line-name = "LVDS_RGB_MODE"; + output-low; + }; + + /* + * This switches the LVDS transceiver to the single-channel + * output mode. + */ + lvds-ch-mode-hog { + gpio-hog; + gpios = <3 GPIO_ACTIVE_HIGH>; /* SODIMM 55 */ + line-name = "LVDS_CH_MODE"; + output-high; + }; + + /* This turns the LVDS transceiver on */ + lvds-power-on-hog { + gpio-hog; + gpios = <11 GPIO_ACTIVE_HIGH>; /* SODIMM 99 */ + line-name = "LVDS_POWER_ON"; + output-high; + }; +}; + +&lcdif { + status = "okay"; +}; + +&panel_dpi { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx7s-colibri-iris.dts b/arch/arm/boot/dts/imx7s-colibri-iris.dts new file mode 100644 index 000000000000..26ba72c17feb --- /dev/null +++ b/arch/arm/boot/dts/imx7s-colibri-iris.dts @@ -0,0 +1,51 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2022 Toradex + */ + +/dts-v1/; +#include "imx7s-colibri.dtsi" +#include "imx7-colibri-iris.dtsi" + +/ { + model = "Toradex Colibri iMX7S on Iris Carrier Board"; + compatible = "toradex,colibri-imx7s-iris", + "toradex,colibri-imx7s", + "fsl,imx7s"; +}; + +&ad7879_ts { + status = "okay"; +}; + +/* + * The Atmel maxtouch controller uses SODIMM 28/30, also used for PWM<B>, PWM<C>, aka pwm2, pwm3. + * So if you enable following capacitive touch controller, disable pwm2/pwm3 first. + */ +&atmel_mxt_ts { + status = "disabled"; +}; + +&backlight { + status = "okay"; +}; + +&lcdif { + status = "okay"; +}; + +&panel_dpi { + status = "okay"; +}; + +/* Colibri PWM<B> */ +&pwm2 { + /* The pwm2 should be disabled to enable atmel_mxt_ts touchscreen for adapter. */ + status = "okay"; +}; + +/* Colibri PWM<C> */ +&pwm3 { + /* The pwm3 should be disabled to enable atmel_mxt_ts touchscreen for adapter. */ + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx7s-colibri.dtsi b/arch/arm/boot/dts/imx7s-colibri.dtsi index 94de220a5965..ef51395d3537 100644 --- a/arch/arm/boot/dts/imx7s-colibri.dtsi +++ b/arch/arm/boot/dts/imx7s-colibri.dtsi @@ -1,6 +1,6 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT /* - * Copyright 2016-2020 Toradex + * Copyright 2016-2022 Toradex */ #include "imx7s.dtsi" @@ -13,6 +13,7 @@ }; }; +/* NAND */ &gpmi { status = "okay"; }; diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi index 039eed79d2e7..29148285f9fc 100644 --- a/arch/arm/boot/dts/imx7s.dtsi +++ b/arch/arm/boot/dts/imx7s.dtsi @@ -176,7 +176,7 @@ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; }; - soc { + soc: soc { #address-cells = <1>; #size-cells = <1>; compatible = "simple-bus"; diff --git a/arch/arm/boot/dts/imxrt1050.dtsi b/arch/arm/boot/dts/imxrt1050.dtsi index 77b911b06041..03e6a858a7be 100644 --- a/arch/arm/boot/dts/imxrt1050.dtsi +++ b/arch/arm/boot/dts/imxrt1050.dtsi @@ -83,7 +83,7 @@ }; usdhc1: mmc@402c0000 { - compatible ="fsl,imxrt1050-usdhc", "fsl,imx6sl-usdhc"; + compatible = "fsl,imxrt1050-usdhc", "fsl,imx6sl-usdhc"; reg = <0x402c0000 0x4000>; interrupts = <110>; clocks = <&clks IMXRT1050_CLK_IPG_PDOF>, @@ -95,7 +95,7 @@ no-1-8-v; max-frequency = <4000000>; fsl,tuning-start-tap = <20>; - fsl,tuning-step= <2>; + fsl,tuning-step = <2>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/keystone-k2e-netcp.dtsi b/arch/arm/boot/dts/keystone-k2e-netcp.dtsi index 71064483d34f..42cf74db673c 100644 --- a/arch/arm/boot/dts/keystone-k2e-netcp.dtsi +++ b/arch/arm/boot/dts/keystone-k2e-netcp.dtsi @@ -12,9 +12,9 @@ qmss: qmss@2a40000 { #size-cells = <1>; clocks = <&chipclk13>; ranges; - queue-range = <0 0x2000>; - linkram0 = <0x100000 0x4000>; - linkram1 = <0 0x10000>; + queue-range = <0 0x2000>; + linkram0 = <0x100000 0x4000>; + linkram1 = <0 0x10000>; qmgrs { #address-cells = <1>; @@ -176,40 +176,40 @@ netcp: netcp@24000000 { interfaces { gbe0: interface-0 { slave-port = <0>; - link-interface = <1>; - phy-handle = <ðphy0>; + link-interface = <1>; + phy-handle = <ðphy0>; }; gbe1: interface-1 { slave-port = <1>; - link-interface = <1>; - phy-handle = <ðphy1>; + link-interface = <1>; + phy-handle = <ðphy1>; }; }; secondary-slave-ports { port-2 { slave-port = <2>; - link-interface = <2>; + link-interface = <2>; }; port-3 { slave-port = <3>; - link-interface = <2>; + link-interface = <2>; }; port-4 { slave-port = <4>; - link-interface = <2>; + link-interface = <2>; }; port-5 { slave-port = <5>; - link-interface = <2>; + link-interface = <2>; }; port-6 { slave-port = <6>; - link-interface = <2>; + link-interface = <2>; }; port-7 { slave-port = <7>; - link-interface = <2>; + link-interface = <2>; }; }; }; diff --git a/arch/arm/boot/dts/keystone-k2e.dtsi b/arch/arm/boot/dts/keystone-k2e.dtsi index b8f152e7af7f..65c32946c522 100644 --- a/arch/arm/boot/dts/keystone-k2e.dtsi +++ b/arch/arm/boot/dts/keystone-k2e.dtsi @@ -141,7 +141,7 @@ clock-names = "pcie"; #address-cells = <3>; #size-cells = <2>; - reg = <0x21021000 0x2000>, <0x21020000 0x1000>, <0x02620128 4>; + reg = <0x21021000 0x2000>, <0x21020000 0x1000>, <0x02620128 4>; ranges = <0x82000000 0 0x60000000 0x60000000 0 0x10000000>; @@ -185,14 +185,14 @@ }; mdio: mdio@24200f00 { - compatible = "ti,keystone_mdio", "ti,davinci_mdio"; + compatible = "ti,keystone_mdio", "ti,davinci_mdio"; #address-cells = <1>; #size-cells = <0>; reg = <0x24200f00 0x100>; status = "disabled"; clocks = <&clkcpgmac>; clock-names = "fck"; - bus_freq = <2500000>; + bus_freq = <2500000>; }; /include/ "keystone-k2e-netcp.dtsi" }; diff --git a/arch/arm/boot/dts/keystone-k2g-netcp.dtsi b/arch/arm/boot/dts/keystone-k2g-netcp.dtsi index d0e6a9a43402..f6306933ff42 100644 --- a/arch/arm/boot/dts/keystone-k2g-netcp.dtsi +++ b/arch/arm/boot/dts/keystone-k2g-netcp.dtsi @@ -125,7 +125,7 @@ netcp: netcp@4000000 { interfaces { gbe0: interface-0 { slave-port = <0>; - link-interface = <5>; + link-interface = <5>; }; }; }; diff --git a/arch/arm/boot/dts/keystone-k2g.dtsi b/arch/arm/boot/dts/keystone-k2g.dtsi index 37198294f4b2..380dd9d637ee 100644 --- a/arch/arm/boot/dts/keystone-k2g.dtsi +++ b/arch/arm/boot/dts/keystone-k2g.dtsi @@ -262,7 +262,7 @@ */ ti,system-reboot-controller; mbox-names = "rx", "tx"; - mboxes= <&msgmgr 5 2>, + mboxes = <&msgmgr 5 2>, <&msgmgr 0 0>; reg-names = "debug_messages"; reg = <0x02921c00 0x400>; @@ -326,13 +326,13 @@ dss: dss@02540000 { compatible = "ti,k2g-dss"; - reg = <0x02540000 0x400>, + reg = <0x02540000 0x400>, <0x02550000 0x1000>, <0x02557000 0x1000>, <0x0255a800 0x100>, <0x0255ac00 0x100>; reg-names = "cfg", "common", "vid1", "ovr1", "vp1"; - clocks = <&k2g_clks 0x2 0>, + clocks = <&k2g_clks 0x2 0>, <&k2g_clks 0x2 1>; clock-names = "fck", "vp1"; interrupts = <GIC_SPI 247 IRQ_TYPE_EDGE_RISING>; @@ -348,7 +348,7 @@ edma0: edma@2700000 { compatible = "ti,k2g-edma3-tpcc", "ti,edma3-tpcc"; - reg = <0x02700000 0x8000>; + reg = <0x02700000 0x8000>; reg-names = "edma3_cc"; interrupts = <GIC_SPI 200 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 216 IRQ_TYPE_EDGE_RISING>, @@ -367,19 +367,19 @@ edma0_tptc0: tptc@2760000 { compatible = "ti,k2g-edma3-tptc", "ti,edma3-tptc"; - reg = <0x02760000 0x400>; + reg = <0x02760000 0x400>; power-domains = <&k2g_pds 0x3f>; }; edma0_tptc1: tptc@2768000 { compatible = "ti,k2g-edma3-tptc", "ti,edma3-tptc"; - reg = <0x02768000 0x400>; + reg = <0x02768000 0x400>; power-domains = <&k2g_pds 0x3f>; }; edma1: edma@2728000 { compatible = "ti,k2g-edma3-tpcc", "ti,edma3-tpcc"; - reg = <0x02728000 0x8000>; + reg = <0x02728000 0x8000>; reg-names = "edma3_cc"; interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 219 IRQ_TYPE_EDGE_RISING>, @@ -402,13 +402,13 @@ edma1_tptc0: tptc@27b0000 { compatible = "ti,k2g-edma3-tptc", "ti,edma3-tptc"; - reg = <0x027b0000 0x400>; + reg = <0x027b0000 0x400>; power-domains = <&k2g_pds 0x4f>; }; edma1_tptc1: tptc@27b8000 { compatible = "ti,k2g-edma3-tptc", "ti,edma3-tptc"; - reg = <0x027b8000 0x400>; + reg = <0x027b8000 0x400>; power-domains = <&k2g_pds 0x4f>; }; diff --git a/arch/arm/boot/dts/keystone-k2hk-netcp.dtsi b/arch/arm/boot/dts/keystone-k2hk-netcp.dtsi index 022d93c366c7..8a421c65f920 100644 --- a/arch/arm/boot/dts/keystone-k2hk-netcp.dtsi +++ b/arch/arm/boot/dts/keystone-k2hk-netcp.dtsi @@ -12,9 +12,9 @@ qmss: qmss@2a40000 { #size-cells = <1>; clocks = <&chipclk13>; ranges; - queue-range = <0 0x4000>; - linkram0 = <0x100000 0x8000>; - linkram1 = <0x0 0x10000>; + queue-range = <0 0x4000>; + linkram0 = <0x100000 0x8000>; + linkram1 = <0x0 0x10000>; qmgrs { #address-cells = <1>; @@ -150,7 +150,7 @@ netcp: netcp@2000000 { #size-cells = <1>; /* NetCP address range */ - ranges = <0 0x2000000 0x100000>; + ranges = <0 0x2000000 0x100000>; clocks = <&clkpa>, <&clkcpgmac>; clock-names = "pa_clk", "ethss_clk"; @@ -207,11 +207,11 @@ netcp: netcp@2000000 { secondary-slave-ports { port-2 { slave-port = <2>; - link-interface = <2>; + link-interface = <2>; }; port-3 { slave-port = <3>; - link-interface = <2>; + link-interface = <2>; }; }; }; diff --git a/arch/arm/boot/dts/keystone-k2hk.dtsi b/arch/arm/boot/dts/keystone-k2hk.dtsi index 8a9447703310..da6d3934c2e8 100644 --- a/arch/arm/boot/dts/keystone-k2hk.dtsi +++ b/arch/arm/boot/dts/keystone-k2hk.dtsi @@ -282,14 +282,14 @@ }; mdio: mdio@2090300 { - compatible = "ti,keystone_mdio", "ti,davinci_mdio"; + compatible = "ti,keystone_mdio", "ti,davinci_mdio"; #address-cells = <1>; #size-cells = <0>; reg = <0x02090300 0x100>; status = "disabled"; clocks = <&clkcpgmac>; clock-names = "fck"; - bus_freq = <2500000>; + bus_freq = <2500000>; }; /include/ "keystone-k2hk-netcp.dtsi" }; diff --git a/arch/arm/boot/dts/keystone-k2l-netcp.dtsi b/arch/arm/boot/dts/keystone-k2l-netcp.dtsi index e96ca664abc2..5ec6680a533d 100644 --- a/arch/arm/boot/dts/keystone-k2l-netcp.dtsi +++ b/arch/arm/boot/dts/keystone-k2l-netcp.dtsi @@ -12,9 +12,9 @@ qmss: qmss@2a40000 { #size-cells = <1>; clocks = <&chipclk13>; ranges; - queue-range = <0 0x2000>; - linkram0 = <0x100000 0x4000>; - linkram1 = <0x70000000 0x10000>; /* 1MB OSR mem */ + queue-range = <0 0x2000>; + linkram0 = <0x100000 0x4000>; + linkram1 = <0x70000000 0x10000>; /* 1MB OSR mem */ qmgrs { #address-cells = <1>; @@ -174,24 +174,24 @@ netcp: netcp@26000000 { interfaces { gbe0: interface-0 { slave-port = <0>; - link-interface = <1>; - phy-handle = <ðphy0>; + link-interface = <1>; + phy-handle = <ðphy0>; }; gbe1: interface-1 { slave-port = <1>; - link-interface = <1>; - phy-handle = <ðphy1>; + link-interface = <1>; + phy-handle = <ðphy1>; }; }; secondary-slave-ports { port-2 { slave-port = <2>; - link-interface = <2>; + link-interface = <2>; }; port-3 { slave-port = <3>; - link-interface = <2>; + link-interface = <2>; }; }; }; diff --git a/arch/arm/boot/dts/keystone-k2l.dtsi b/arch/arm/boot/dts/keystone-k2l.dtsi index dff5fea72b2f..421a02bbc9d3 100644 --- a/arch/arm/boot/dts/keystone-k2l.dtsi +++ b/arch/arm/boot/dts/keystone-k2l.dtsi @@ -47,7 +47,7 @@ reg-shift = <2>; reg-io-width = <4>; reg = <0x02348400 0x100>; - clocks = <&clkuart2>; + clocks = <&clkuart2>; interrupts = <GIC_SPI 432 IRQ_TYPE_EDGE_RISING>; }; @@ -57,7 +57,7 @@ reg-shift = <2>; reg-io-width = <4>; reg = <0x02348800 0x100>; - clocks = <&clkuart3>; + clocks = <&clkuart3>; interrupts = <GIC_SPI 435 IRQ_TYPE_EDGE_RISING>; }; @@ -388,14 +388,14 @@ }; mdio: mdio@26200f00 { - compatible = "ti,keystone_mdio", "ti,davinci_mdio"; + compatible = "ti,keystone_mdio", "ti,davinci_mdio"; #address-cells = <1>; #size-cells = <0>; reg = <0x26200f00 0x100>; status = "disabled"; clocks = <&clkcpgmac>; clock-names = "fck"; - bus_freq = <2500000>; + bus_freq = <2500000>; }; /include/ "keystone-k2l-netcp.dtsi" }; diff --git a/arch/arm/boot/dts/keystone.dtsi b/arch/arm/boot/dts/keystone.dtsi index fc9fdc857ae8..50789f9e2215 100644 --- a/arch/arm/boot/dts/keystone.dtsi +++ b/arch/arm/boot/dts/keystone.dtsi @@ -14,7 +14,7 @@ interrupt-parent = <&gic>; aliases { - serial0 = &uart0; + serial0 = &uart0; spi0 = &spi0; spi1 = &spi1; spi2 = &spi2; @@ -61,11 +61,11 @@ }; psci { - compatible = "arm,psci"; - method = "smc"; - cpu_suspend = <0x84000001>; - cpu_off = <0x84000002>; - cpu_on = <0x84000003>; + compatible = "arm,psci"; + method = "smc"; + cpu_suspend = <0x84000001>; + cpu_off = <0x84000002>; + cpu_on = <0x84000003>; }; soc0: soc@0 { @@ -119,7 +119,7 @@ reg-shift = <2>; reg-io-width = <4>; reg = <0x02530c00 0x100>; - clocks = <&clkuart0>; + clocks = <&clkuart0>; interrupts = <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>; }; @@ -129,7 +129,7 @@ reg-shift = <2>; reg-io-width = <4>; reg = <0x02531000 0x100>; - clocks = <&clkuart1>; + clocks = <&clkuart1>; interrupts = <GIC_SPI 280 IRQ_TYPE_EDGE_RISING>; }; @@ -301,7 +301,7 @@ clock-names = "pcie"; #address-cells = <3>; #size-cells = <2>; - reg = <0x21801000 0x2000>, <0x21800000 0x1000>, <0x02620128 4>; + reg = <0x21801000 0x2000>, <0x21800000 0x1000>, <0x02620128 4>; ranges = <0x82000000 0 0x50000000 0x50000000 0 0x10000000>; diff --git a/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt.dtsi b/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt.dtsi index 725dcf707b31..0097e72e3fb2 100644 --- a/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt.dtsi +++ b/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt.dtsi @@ -76,6 +76,12 @@ pins = "GPIO_25", "GPIO_26"; function = "fc0_b"; }; + + usbs_a_pins: usbs-a-pins { + /* VBUS_DET */ + pins = "GPIO_66"; + function = "gpio"; + }; }; &mdio0 { @@ -185,6 +191,13 @@ status = "okay"; }; +&udc { + pinctrl-0 = <&usbs_a_pins>; + pinctrl-names = "default"; + atmel,vbus-gpio = <&gpio 66 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + &watchdog { status = "okay"; }; diff --git a/arch/arm/boot/dts/lan966x-pcb8291.dts b/arch/arm/boot/dts/lan966x-pcb8291.dts index 3c7e3a7d6f14..24d9055c4a08 100644 --- a/arch/arm/boot/dts/lan966x-pcb8291.dts +++ b/arch/arm/boot/dts/lan966x-pcb8291.dts @@ -4,6 +4,7 @@ */ /dts-v1/; #include "lan966x.dtsi" +#include "dt-bindings/phy/phy-lan966x-serdes.h" / { model = "Microchip EVB - LAN9662"; @@ -16,22 +17,18 @@ aliases { serial0 = &usart3; }; -}; - -&gpio { - fc_shrd7_pins: fc_shrd7-pins { - pins = "GPIO_49"; - function = "fc_shrd7"; - }; - fc_shrd8_pins: fc_shrd8-pins { - pins = "GPIO_54"; - function = "fc_shrd8"; + gpio-restart { + compatible = "gpio-restart"; + gpios = <&gpio 56 GPIO_ACTIVE_LOW>; + priority = <200>; }; +}; - fc3_b_pins: fcb3-spi-pins { - /* SCK, RXD, TXD */ - pins = "GPIO_51", "GPIO_52", "GPIO_53"; +&gpio { + fc3_b_pins: fc3-b-pins { + /* RX, TX */ + pins = "GPIO_52", "GPIO_53"; function = "fc3_b"; }; @@ -45,7 +42,7 @@ &can0 { pinctrl-0 = <&can0_b_pins>; pinctrl-names = "default"; - status = "okay"; + status = "disabled"; /* Conflict with switch */ }; &flx3 { @@ -53,12 +50,46 @@ status = "okay"; usart3: serial@200 { - pinctrl-0 = <&fc3_b_pins>, <&fc_shrd7_pins>, <&fc_shrd8_pins>; + pinctrl-0 = <&fc3_b_pins>; pinctrl-names = "default"; status = "okay"; }; }; +&mdio1 { + status = "okay"; +}; + +&phy0 { + status = "okay"; +}; + +&phy1 { + status = "okay"; +}; + +&port0 { + phy-handle = <&phy0>; + phy-mode = "gmii"; + phys = <&serdes 0 CU(0)>; + status = "okay"; +}; + +&port1 { + phy-handle = <&phy1>; + phy-mode = "gmii"; + phys = <&serdes 1 CU(1)>; + status = "okay"; +}; + +&serdes { + status = "okay"; +}; + +&switch { + status = "okay"; +}; + &watchdog { status = "okay"; }; diff --git a/arch/arm/boot/dts/lan966x-pcb8309.dts b/arch/arm/boot/dts/lan966x-pcb8309.dts new file mode 100644 index 000000000000..05ce27ed5648 --- /dev/null +++ b/arch/arm/boot/dts/lan966x-pcb8309.dts @@ -0,0 +1,184 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * lan966x_pcb8309.dts - Device Tree file for PCB8309 + */ +/dts-v1/; +#include "lan966x.dtsi" +#include "dt-bindings/phy/phy-lan966x-serdes.h" + +/ { + model = "Microchip EVB - LAN9662"; + compatible = "microchip,lan9662-pcb8309", "microchip,lan9662", "microchip,lan966"; + + aliases { + serial0 = &usart3; + i2c102 = &i2c102; + i2c103 = &i2c103; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-restart { + compatible = "gpio-restart"; + gpios = <&gpio 56 GPIO_ACTIVE_LOW>; + priority = <200>; + }; + + i2c-mux { + compatible = "i2c-mux"; + #address-cells = <1>; + #size-cells = <0>; + mux-controls = <&mux>; + i2c-parent = <&i2c4>; + + i2c102: i2c-sfp@1 { + reg = <1>; + }; + + i2c103: i2c-sfp@2 { + reg = <2>; + }; + }; + + mux: mux-controller { + compatible = "gpio-mux"; + #mux-control-cells = <0>; + + mux-gpios = <&sgpio_out 11 0 GPIO_ACTIVE_HIGH>, /* p11b0 */ + <&sgpio_out 11 1 GPIO_ACTIVE_HIGH>; /* p11b1 */ + }; + + sfp2: sfp2 { + compatible = "sff,sfp"; + i2c-bus = <&i2c102>; + tx-disable-gpios = <&sgpio_out 10 0 GPIO_ACTIVE_LOW>; + los-gpios = <&sgpio_in 2 0 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&sgpio_in 2 1 GPIO_ACTIVE_LOW>; + tx-fault-gpios = <&sgpio_in 1 0 GPIO_ACTIVE_HIGH>; + }; + + sfp3: sfp3 { + compatible = "sff,sfp"; + i2c-bus = <&i2c103>; + tx-disable-gpios = <&sgpio_out 10 1 GPIO_ACTIVE_LOW>; + los-gpios = <&sgpio_in 3 0 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&sgpio_in 3 1 GPIO_ACTIVE_LOW>; + tx-fault-gpios = <&sgpio_in 1 1 GPIO_ACTIVE_HIGH>; + }; +}; + +&flx3 { + atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_USART>; + status = "okay"; + + usart3: serial@200 { + pinctrl-0 = <&fc3_b_pins>; + pinctrl-names = "default"; + status = "okay"; + }; +}; + +&flx4 { + atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>; + status = "okay"; + + i2c4: i2c@600 { + compatible = "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&nic_clk>; + pinctrl-0 = <&fc4_b_pins>; + pinctrl-names = "default"; + i2c-analog-filter; + i2c-digital-filter; + i2c-digital-filter-width-ns = <35>; + i2c-sda-hold-time-ns = <1500>; + status = "okay"; + }; +}; + +&gpio { + fc3_b_pins: fc3-b-pins { + /* RXD, TXD */ + pins = "GPIO_52", "GPIO_53"; + function = "fc3_b"; + }; + + fc4_b_pins: fc4-b-pins { + /* SCL, SDA */ + pins = "GPIO_57", "GPIO_58"; + function = "fc4_b"; + }; + + sgpio_a_pins: sgpio-a-pins { + /* SCK, D0, D1, LD */ + pins = "GPIO_32", "GPIO_33", "GPIO_34", "GPIO_35"; + function = "sgpio_a"; + }; +}; + +&mdio1 { + status = "okay"; +}; + +&phy0 { + status = "okay"; +}; + +&phy1 { + status = "okay"; +}; + +&port0 { + phy-handle = <&phy0>; + phy-mode = "gmii"; + phys = <&serdes 0 CU(0)>; + status = "okay"; +}; + +&port1 { + phy-handle = <&phy1>; + phy-mode = "gmii"; + phys = <&serdes 1 CU(1)>; + status = "okay"; +}; + +&port2 { + sfp = <&sfp2>; + managed = "in-band-status"; + phy-mode = "sgmii"; + phys = <&serdes 2 SERDES6G(0)>; + status = "okay"; +}; + +&port3 { + sfp = <&sfp3>; + managed = "in-band-status"; + phy-mode = "sgmii"; + phys = <&serdes 3 SERDES6G(1)>; + status = "okay"; +}; + +&serdes { + status = "okay"; +}; + +&sgpio { + pinctrl-0 = <&sgpio_a_pins>; + pinctrl-names = "default"; + microchip,sgpio-port-ranges = <0 3>, <8 11>; + status = "okay"; + + gpio@0 { + ngpios = <64>; + }; + gpio@1 { + ngpios = <64>; + }; +}; + +&switch { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/lan966x.dtsi b/arch/arm/boot/dts/lan966x.dtsi index 38e90a31d2dd..894bf9da19a4 100644 --- a/arch/arm/boot/dts/lan966x.dtsi +++ b/arch/arm/boot/dts/lan966x.dtsi @@ -65,7 +65,7 @@ #clock-cells = <1>; clocks = <&cpu_clk>, <&ddr_clk>, <&sys_clk>; clock-names = "cpu", "ddr", "sys"; - reg = <0xe00c00a8 0x38>; + reg = <0xe00c00a8 0x38>, <0xe00c02cc 0x4>; }; timer { @@ -84,6 +84,17 @@ #size-cells = <1>; ranges; + udc: usb@200000 { + compatible = "microchip,lan9662-udc", + "atmel,sama5d3-udc"; + reg = <0x00200000 0x80000>, + <0xe0808000 0x400>; + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks GCK_GATE_UDPHS>, <&nic_clk>; + clock-names = "pclk", "hclk"; + status = "disabled"; + }; + switch: switch@e0000000 { compatible = "microchip,lan966x-switch"; reg = <0xe0000000 0x0100000>, @@ -473,6 +484,21 @@ status = "disabled"; }; + can1: can@e0820000 { + compatible = "bosch,m_can"; + reg = <0xe0820000 0xfc>, <0x00100000 0x8000>; + reg-names = "m_can", "message_ram"; + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "int0", "int1"; + clocks = <&clks GCK_ID_MCAN1>, <&clks GCK_ID_MCAN1>; + clock-names = "hclk", "cclk"; + assigned-clocks = <&clks GCK_ID_MCAN1>; + assigned-clock-rates = <40000000>; + bosch,mram-cfg = <0x4000 0 0 64 0 0 32 32>; + status = "disabled"; + }; + reset: reset-controller@e200400c { compatible = "microchip,lan966x-switch-reset"; reg = <0xe200400c 0x4>; diff --git a/arch/arm/boot/dts/lpc18xx.dtsi b/arch/arm/boot/dts/lpc18xx.dtsi index 10b8249b8ab6..1bb686a7b3ec 100644 --- a/arch/arm/boot/dts/lpc18xx.dtsi +++ b/arch/arm/boot/dts/lpc18xx.dtsi @@ -121,7 +121,7 @@ status = "disabled"; }; - usb0: ehci@40006100 { + usb0: usb@40006100 { compatible = "nxp,lpc1850-ehci", "generic-ehci"; reg = <0x40006100 0x100>; interrupts = <8>; @@ -133,7 +133,7 @@ status = "disabled"; }; - usb1: ehci@40007100 { + usb1: usb@40007100 { compatible = "nxp,lpc1850-ehci", "generic-ehci"; reg = <0x40007100 0x100>; interrupts = <9>; @@ -183,7 +183,7 @@ compatible = "nxp,lpc1850-dwmac", "snps,dwmac-3.611", "snps,dwmac"; reg = <0x40010000 0x2000>; interrupts = <5>; - interrupt-names = "macirq"; + interrupt-names = "macirq"; clocks = <&ccu1 CLK_CPU_ETHERNET>; clock-names = "stmmaceth"; resets = <&rgu 22>; diff --git a/arch/arm/boot/dts/ls1021a-iot.dts b/arch/arm/boot/dts/ls1021a-iot.dts index 66bcdaf4b6f9..ce8e26d7791f 100644 --- a/arch/arm/boot/dts/ls1021a-iot.dts +++ b/arch/arm/boot/dts/ls1021a-iot.dts @@ -142,7 +142,7 @@ }; sgtl5000: audio-codec@2a { - #sound-dai-cells=<0x0>; + #sound-dai-cells = <0x0>; compatible = "fsl,sgtl5000"; reg = <0x2a>; VDDA-supply = <®_3p3v>; diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi index 6c88be2a7e8e..fa761620f073 100644 --- a/arch/arm/boot/dts/ls1021a.dtsi +++ b/arch/arm/boot/dts/ls1021a.dtsi @@ -129,6 +129,13 @@ status = "disabled"; }; + sfp: efuse@1e80000 { + compatible = "fsl,ls1021a-sfp"; + reg = <0x0 0x1e80000 0x0 0x10000>; + clocks = <&clockgen 4 3>; + clock-names = "sfp"; + }; + dcfg: dcfg@1ee0000 { compatible = "fsl,ls1021a-dcfg", "syscon"; reg = <0x0 0x1ee0000 0x0 0x1000>; diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi index 26eaba3fa96f..8e3860d5d916 100644 --- a/arch/arm/boot/dts/meson.dtsi +++ b/arch/arm/boot/dts/meson.dtsi @@ -214,14 +214,14 @@ ranges = <0x0 0xc8100000 0x100000>; ao_arc_rproc: remoteproc@1c { - compatible= "amlogic,meson-mx-ao-arc"; + compatible = "amlogic,meson-mx-ao-arc"; reg = <0x1c 0x8>, <0x38 0x8>; reg-names = "remap", "cpu"; status = "disabled"; }; ir_receiver: ir-receiver@480 { - compatible= "amlogic,meson6-ir"; + compatible = "amlogic,meson6-ir"; reg = <0x480 0x20>; interrupts = <GIC_SPI 15 IRQ_TYPE_EDGE_RISING>; status = "disabled"; diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi index 9997a5d0333a..0f8bac8bac8b 100644 --- a/arch/arm/boot/dts/meson8.dtsi +++ b/arch/arm/boot/dts/meson8.dtsi @@ -430,7 +430,7 @@ }; &ao_arc_rproc { - compatible= "amlogic,meson8-ao-arc", "amlogic,meson-mx-ao-arc"; + compatible = "amlogic,meson8-ao-arc", "amlogic,meson-mx-ao-arc"; amlogic,secbus2 = <&secbus2>; sram = <&ao_arc_sram>; resets = <&reset RESET_MEDIA_CPU>; diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi index 94f1c03decce..cf9c04a61ba3 100644 --- a/arch/arm/boot/dts/meson8b.dtsi +++ b/arch/arm/boot/dts/meson8b.dtsi @@ -384,7 +384,7 @@ }; &ao_arc_rproc { - compatible= "amlogic,meson8b-ao-arc", "amlogic,meson-mx-ao-arc"; + compatible = "amlogic,meson8b-ao-arc", "amlogic,meson-mx-ao-arc"; amlogic,secbus2 = <&secbus2>; sram = <&ao_arc_sram>; resets = <&reset RESET_MEDIA_CPU>; diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi index ef583cfd3baf..b8eba3ba153c 100644 --- a/arch/arm/boot/dts/mt2701.dtsi +++ b/arch/arm/boot/dts/mt2701.dtsi @@ -427,9 +427,9 @@ afe: audio-controller { compatible = "mediatek,mt2701-audio"; - interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>, + interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>, <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>; - interrupt-names = "afe", "asys"; + interrupt-names = "afe", "asys"; power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>; clocks = <&infracfg CLK_INFRA_AUDIO>, @@ -559,7 +559,7 @@ compatible = "mediatek,mt2701-jpgdec"; reg = <0 0x15004000 0 0x1000>; interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_LOW>; - clocks = <&imgsys CLK_IMG_JPGDEC_SMI>, + clocks = <&imgsys CLK_IMG_JPGDEC_SMI>, <&imgsys CLK_IMG_JPGDEC>; clock-names = "jpgdec-smi", "jpgdec"; @@ -573,7 +573,7 @@ "mediatek,mtk-jpgenc"; reg = <0 0x1500a000 0 0x1000>; interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_LOW>; - clocks = <&imgsys CLK_IMG_VENC>; + clocks = <&imgsys CLK_IMG_VENC>; clock-names = "jpgenc"; power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>; iommus = <&iommu MT2701_M4U_PORT_JPGENC_RDMA>, diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi index f4848362b3be..25d31e40a553 100644 --- a/arch/arm/boot/dts/mt7623.dtsi +++ b/arch/arm/boot/dts/mt7623.dtsi @@ -241,7 +241,7 @@ }; pericfg: syscon@10003000 { - compatible = "mediatek,mt7623-pericfg", + compatible = "mediatek,mt7623-pericfg", "mediatek,mt2701-pericfg", "syscon"; reg = <0 0x10003000 0 0x1000>; @@ -628,9 +628,9 @@ afe: audio-controller { compatible = "mediatek,mt7623-audio", "mediatek,mt2701-audio"; - interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>, + interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>, <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>; - interrupt-names = "afe", "asys"; + interrupt-names = "afe", "asys"; power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>; clocks = <&infracfg CLK_INFRA_AUDIO>, diff --git a/arch/arm/boot/dts/mt7623a-rfb-emmc.dts b/arch/arm/boot/dts/mt7623a-rfb-emmc.dts index 13c86936d1c8..e8b4b6d30d19 100644 --- a/arch/arm/boot/dts/mt7623a-rfb-emmc.dts +++ b/arch/arm/boot/dts/mt7623a-rfb-emmc.dts @@ -45,13 +45,13 @@ pinctrl-names = "default"; pinctrl-0 = <&key_pins_a>; - factory { + button-factory { label = "factory"; linux,code = <BTN_0>; gpios = <&pio 256 GPIO_ACTIVE_LOW>; }; - wps { + button-wps { label = "wps"; linux,code = <KEY_WPS_BUTTON>; gpios = <&pio 257 GPIO_ACTIVE_HIGH>; diff --git a/arch/arm/boot/dts/mt7623a-rfb-nand.dts b/arch/arm/boot/dts/mt7623a-rfb-nand.dts index 88d8f0b2f4c2..61f5da68d4b0 100644 --- a/arch/arm/boot/dts/mt7623a-rfb-nand.dts +++ b/arch/arm/boot/dts/mt7623a-rfb-nand.dts @@ -45,13 +45,13 @@ pinctrl-names = "default"; pinctrl-0 = <&key_pins_a>; - factory { + button-factory { label = "factory"; linux,code = <BTN_0>; gpios = <&pio 256 GPIO_ACTIVE_LOW>; }; - wps { + button-wps { label = "wps"; linux,code = <KEY_WPS_BUTTON>; gpios = <&pio 257 GPIO_ACTIVE_HIGH>; diff --git a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts index 027c1b0c6a98..5008115d2494 100644 --- a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts +++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts @@ -91,13 +91,13 @@ pinctrl-names = "default"; pinctrl-0 = <&key_pins_a>; - factory { + button-factory { label = "factory"; linux,code = <BTN_0>; gpios = <&pio 256 GPIO_ACTIVE_LOW>; }; - wps { + button-wps { label = "wps"; linux,code = <KEY_WPS_BUTTON>; gpios = <&pio 257 GPIO_ACTIVE_HIGH>; diff --git a/arch/arm/boot/dts/mt7623n-rfb-emmc.dts b/arch/arm/boot/dts/mt7623n-rfb-emmc.dts index 1b9b9a8145a7..bf67a8e9be59 100644 --- a/arch/arm/boot/dts/mt7623n-rfb-emmc.dts +++ b/arch/arm/boot/dts/mt7623n-rfb-emmc.dts @@ -60,13 +60,13 @@ pinctrl-names = "default"; pinctrl-0 = <&key_pins_a>; - factory { + button-factory { label = "factory"; linux,code = <BTN_0>; gpios = <&pio 256 GPIO_ACTIVE_LOW>; }; - wps { + button-wps { label = "wps"; linux,code = <KEY_WPS_BUTTON>; gpios = <&pio 257 GPIO_ACTIVE_HIGH>; diff --git a/arch/arm/boot/dts/mt7629-rfb.dts b/arch/arm/boot/dts/mt7629-rfb.dts index eb536cbebd9b..84e14bee7235 100644 --- a/arch/arm/boot/dts/mt7629-rfb.dts +++ b/arch/arm/boot/dts/mt7629-rfb.dts @@ -23,13 +23,13 @@ gpio-keys { compatible = "gpio-keys"; - reset { + button-reset { label = "factory"; linux,code = <KEY_RESTART>; gpios = <&pio 60 GPIO_ACTIVE_LOW>; }; - wps { + button-wps { label = "wps"; linux,code = <KEY_WPS_BUTTON>; gpios = <&pio 58 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi b/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi index 3696980a3da1..9633b50a9c6d 100644 --- a/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi +++ b/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi @@ -128,7 +128,7 @@ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "macirq"; ethernet = <0>; - clocks = <&clk_rg1refck>, <&clk NPCM7XX_CLK_AHB>; + clocks = <&clk_rg1refck>, <&clk NPCM7XX_CLK_AHB>; clock-names = "stmmaceth", "clk_gmac"; pinctrl-names = "default"; pinctrl-0 = <&rg1_pins diff --git a/arch/arm/boot/dts/nuvoton-npcm750.dtsi b/arch/arm/boot/dts/nuvoton-npcm750.dtsi index 13eee0fe5642..30eed40b89b5 100644 --- a/arch/arm/boot/dts/nuvoton-npcm750.dtsi +++ b/arch/arm/boot/dts/nuvoton-npcm750.dtsi @@ -51,7 +51,7 @@ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "macirq"; ethernet = <1>; - clocks = <&clk_rg2refck>, <&clk NPCM7XX_CLK_AHB>; + clocks = <&clk_rg2refck>, <&clk NPCM7XX_CLK_AHB>; clock-names = "stmmaceth", "clk_gmac"; pinctrl-names = "default"; pinctrl-0 = <&rg2_pins diff --git a/arch/arm/boot/dts/omap2420-h4.dts b/arch/arm/boot/dts/omap2420-h4.dts index af964f139abf..5acf5dd87c59 100644 --- a/arch/arm/boot/dts/omap2420-h4.dts +++ b/arch/arm/boot/dts/omap2420-h4.dts @@ -21,7 +21,7 @@ nor@0,0 { compatible = "cfi-flash"; - linux,mtd-name= "intel,ge28f256l18b85"; + linux,mtd-name = "intel,ge28f256l18b85"; #address-cells = <1>; #size-cells = <1>; reg = <0 0 0x04000000>; diff --git a/arch/arm/boot/dts/omap3-evm-37xx.dts b/arch/arm/boot/dts/omap3-evm-37xx.dts index c9332195d096..abd403c228c7 100644 --- a/arch/arm/boot/dts/omap3-evm-37xx.dts +++ b/arch/arm/boot/dts/omap3-evm-37xx.dts @@ -60,7 +60,7 @@ interrupt-parent = <&gpmc>; interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ <1 IRQ_TYPE_NONE>; /* termcount */ - linux,mtd-name= "hynix,h8kds0un0mer-4em"; + linux,mtd-name = "hynix,h8kds0un0mer-4em"; nand-bus-width = <16>; gpmc,device-width = <2>; ti,nand-ecc-opt = "bch8"; diff --git a/arch/arm/boot/dts/omap3-evm.dts b/arch/arm/boot/dts/omap3-evm.dts index 5cc0cf7cd16c..f95eea63b355 100644 --- a/arch/arm/boot/dts/omap3-evm.dts +++ b/arch/arm/boot/dts/omap3-evm.dts @@ -60,7 +60,7 @@ interrupt-parent = <&gpmc>; interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ <1 IRQ_TYPE_NONE>; /* termcount */ - linux,mtd-name= "micron,mt29f2g16abdhc"; + linux,mtd-name = "micron,mt29f2g16abdhc"; nand-bus-width = <16>; gpmc,device-width = <2>; ti,nand-ecc-opt = "bch8"; diff --git a/arch/arm/boot/dts/omap3-gta04.dtsi b/arch/arm/boot/dts/omap3-gta04.dtsi index 0365f06165e9..28a6a9345be5 100644 --- a/arch/arm/boot/dts/omap3-gta04.dtsi +++ b/arch/arm/boot/dts/omap3-gta04.dtsi @@ -127,7 +127,7 @@ spi-cpol; spi-cpha; - backlight= <&backlight>; + backlight = <&backlight>; label = "lcd"; port { lcd_in: endpoint { diff --git a/arch/arm/boot/dts/omap3-igep.dtsi b/arch/arm/boot/dts/omap3-igep.dtsi index 99f5585097a1..219202610463 100644 --- a/arch/arm/boot/dts/omap3-igep.dtsi +++ b/arch/arm/boot/dts/omap3-igep.dtsi @@ -111,7 +111,7 @@ interrupt-parent = <&gpmc>; interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ <1 IRQ_TYPE_NONE>; /* termcount */ - linux,mtd-name= "micron,mt29c4g96maz"; + linux,mtd-name = "micron,mt29c4g96maz"; nand-bus-width = <16>; gpmc,device-width = <2>; ti,nand-ecc-opt = "bch8"; diff --git a/arch/arm/boot/dts/omap3-ldp.dts b/arch/arm/boot/dts/omap3-ldp.dts index 9c6a92724590..36fc8805e0c1 100644 --- a/arch/arm/boot/dts/omap3-ldp.dts +++ b/arch/arm/boot/dts/omap3-ldp.dts @@ -103,7 +103,7 @@ interrupt-parent = <&gpmc>; interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ <1 IRQ_TYPE_NONE>; /* termcount */ - linux,mtd-name= "micron,nand"; + linux,mtd-name = "micron,nand"; nand-bus-width = <16>; gpmc,device-width = <2>; ti,nand-ecc-opt = "bch8"; @@ -215,11 +215,11 @@ }; &mmc2 { - status="disabled"; + status = "disabled"; }; &mmc3 { - status="disabled"; + status = "disabled"; }; &omap3_pmx_core { diff --git a/arch/arm/boot/dts/omap3-lilly-a83x.dtsi b/arch/arm/boot/dts/omap3-lilly-a83x.dtsi index 73d477898ec2..c595afe4181d 100644 --- a/arch/arm/boot/dts/omap3-lilly-a83x.dtsi +++ b/arch/arm/boot/dts/omap3-lilly-a83x.dtsi @@ -372,7 +372,7 @@ gpmc,device-width = <2>; gpmc,wait-pin = <0>; gpmc,wait-monitoring-ns = <0>; - gpmc,burst-length= <4>; + gpmc,burst-length = <4>; gpmc,cs-on-ns = <0>; gpmc,cs-rd-off-ns = <100>; gpmc,cs-wr-off-ns = <100>; diff --git a/arch/arm/boot/dts/omap3-n900.dts b/arch/arm/boot/dts/omap3-n900.dts index d40c3d2c4914..dd7971556449 100644 --- a/arch/arm/boot/dts/omap3-n900.dts +++ b/arch/arm/boot/dts/omap3-n900.dts @@ -568,8 +568,8 @@ }; &twl_gpio { - ti,pullups = <0x0>; - ti,pulldowns = <0x03ff3f>; /* BIT(0..5) | BIT(8..17) */ + ti,pullups = <0x0>; + ti,pulldowns = <0x03ff3f>; /* BIT(0..5) | BIT(8..17) */ }; &i2c2 { diff --git a/arch/arm/boot/dts/omap3-n950-n9.dtsi b/arch/arm/boot/dts/omap3-n950-n9.dtsi index 7dde9fbb06d3..f68da828b050 100644 --- a/arch/arm/boot/dts/omap3-n950-n9.dtsi +++ b/arch/arm/boot/dts/omap3-n950-n9.dtsi @@ -162,8 +162,8 @@ }; &twl_gpio { - ti,pullups = <0x000001>; /* BIT(0) */ - ti,pulldowns = <0x008106>; /* BIT(1) | BIT(2) | BIT(8) | BIT(15) */ + ti,pullups = <0x000001>; /* BIT(0) */ + ti,pulldowns = <0x008106>; /* BIT(1) | BIT(2) | BIT(8) | BIT(15) */ }; &vdac { diff --git a/arch/arm/boot/dts/omap3-overo-base.dtsi b/arch/arm/boot/dts/omap3-overo-base.dtsi index 006a6d97231c..adc714c39825 100644 --- a/arch/arm/boot/dts/omap3-overo-base.dtsi +++ b/arch/arm/boot/dts/omap3-overo-base.dtsi @@ -222,7 +222,7 @@ nand@0,0 { compatible = "ti,omap2-nand"; - linux,mtd-name= "micron,mt29c4g96maz"; + linux,mtd-name = "micron,mt29c4g96maz"; reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ interrupt-parent = <&gpmc>; interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ diff --git a/arch/arm/boot/dts/omap3-pandora-common.dtsi b/arch/arm/boot/dts/omap3-pandora-common.dtsi index 37608af6c07f..559853764487 100644 --- a/arch/arm/boot/dts/omap3-pandora-common.dtsi +++ b/arch/arm/boot/dts/omap3-pandora-common.dtsi @@ -666,7 +666,7 @@ lcd: lcd@1 { reg = <1>; /* CS1 */ - compatible = "tpo,td043mtea1"; + compatible = "tpo,td043mtea1"; spi-max-frequency = <100000>; spi-cpol; spi-cpha; diff --git a/arch/arm/boot/dts/omap3430-sdp.dts b/arch/arm/boot/dts/omap3430-sdp.dts index 7d530ae3483b..258ecd9e4519 100644 --- a/arch/arm/boot/dts/omap3430-sdp.dts +++ b/arch/arm/boot/dts/omap3430-sdp.dts @@ -53,7 +53,7 @@ nor@0,0 { compatible = "cfi-flash"; - linux,mtd-name= "intel,pf48f6000m0y1be"; + linux,mtd-name = "intel,pf48f6000m0y1be"; #address-cells = <1>; #size-cells = <1>; reg = <0 0 0x08000000>; @@ -105,7 +105,7 @@ interrupt-parent = <&gpmc>; interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ <1 IRQ_TYPE_NONE>; /* termcount */ - linux,mtd-name= "micron,mt29f1g08abb"; + linux,mtd-name = "micron,mt29f1g08abb"; #address-cells = <1>; #size-cells = <1>; ti,nand-ecc-opt = "sw"; @@ -148,7 +148,7 @@ }; onenand@2,0 { - linux,mtd-name= "samsung,kfm2g16q2m-deb8"; + linux,mtd-name = "samsung,kfm2g16q2m-deb8"; #address-cells = <1>; #size-cells = <1>; compatible = "ti,omap2-onenand"; diff --git a/arch/arm/boot/dts/omap5-l4.dtsi b/arch/arm/boot/dts/omap5-l4.dtsi index 06cc3a19ddaa..3b505fe415ed 100644 --- a/arch/arm/boot/dts/omap5-l4.dtsi +++ b/arch/arm/boot/dts/omap5-l4.dtsi @@ -482,7 +482,7 @@ clocks = <&usb_phy_cm_clk32k>, <&sys_clkin>, <&l3init_clkctrl OMAP5_USB_OTG_SS_CLKCTRL 8>; - clock-names = "wkupclk", + clock-names = "wkupclk", "sysclk", "refclk"; #phy-cells = <0>; diff --git a/arch/arm/boot/dts/pxa300-raumfeld-common.dtsi b/arch/arm/boot/dts/pxa300-raumfeld-common.dtsi index 8a6721d436bd..147c99191dc2 100644 --- a/arch/arm/boot/dts/pxa300-raumfeld-common.dtsi +++ b/arch/arm/boot/dts/pxa300-raumfeld-common.dtsi @@ -189,31 +189,31 @@ regulators { regulator-v3 { - regulator-compatible= "V3(DCDC)"; + regulator-compatible = "V3(DCDC)"; regulator-min-microvolt = <725000>; regulator-max-microvolt = <1800000>; }; regulator-v4 { - regulator-compatible= "V4(DCDC)"; + regulator-compatible = "V4(DCDC)"; regulator-min-microvolt = <725000>; regulator-max-microvolt = <1800000>; }; regulator-v5 { - regulator-compatible= "V5(LDO)"; + regulator-compatible = "V5(LDO)"; regulator-min-microvolt = <1700000>; regulator-max-microvolt = <2000000>; }; reg_vcc_sdio: regulator-v6 { - regulator-compatible= "V6(LDO)"; + regulator-compatible = "V6(LDO)"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; regulator-v7 { - regulator-compatible= "V7(LDO)"; + regulator-compatible = "V7(LDO)"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; }; diff --git a/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts b/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts index 138d6478ac84..70a1dd629c7a 100644 --- a/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts +++ b/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts @@ -1,6 +1,7 @@ // SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) #include <dt-bindings/input/input.h> #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/leds/common.h> #include <dt-bindings/pinctrl/qcom,pmic-gpio.h> #include <dt-bindings/pinctrl/qcom,pmic-mpp.h> #include "qcom-msm8660.dtsi" @@ -273,7 +274,7 @@ }; gpio@150 { - dragon_ethernet_gpios: ethernet-gpios { + dragon_ethernet_gpios: ethernet-state { pinconf { pins = "gpio7"; function = "normal"; @@ -282,7 +283,7 @@ power-source = <PM8058_GPIO_S3>; }; }; - dragon_bmp085_gpios: bmp085-gpios { + dragon_bmp085_gpios: bmp085-state { pinconf { pins = "gpio16"; function = "normal"; @@ -291,7 +292,7 @@ power-source = <PM8058_GPIO_S3>; }; }; - dragon_mpu3050_gpios: mpu3050-gpios { + dragon_mpu3050_gpios: mpu3050-state { pinconf { pins = "gpio17"; function = "normal"; @@ -300,7 +301,7 @@ power-source = <PM8058_GPIO_S3>; }; }; - dragon_sdcc3_gpios: sdcc3-gpios { + dragon_sdcc3_gpios: sdcc3-state { pinconf { pins = "gpio22"; function = "normal"; @@ -309,7 +310,7 @@ power-source = <PM8058_GPIO_S3>; }; }; - dragon_sdcc5_gpios: sdcc5-gpios { + dragon_sdcc5_gpios: sdcc5-state { pinconf { pins = "gpio26"; function = "normal"; @@ -319,7 +320,7 @@ power-source = <PM8058_GPIO_S3>; }; }; - dragon_ak8975_gpios: ak8975-gpios { + dragon_ak8975_gpios: ak8975-state { pinconf { pins = "gpio33"; function = "normal"; @@ -328,9 +329,9 @@ power-source = <PM8058_GPIO_S3>; }; }; - dragon_cm3605_gpios: cm3605-gpios { + dragon_cm3605_gpios: cm3605-state { /* Pin 34 connected to the proxy IRQ */ - pinconf_gpio34 { + gpio34-pins { pins = "gpio34"; function = "normal"; input-enable; @@ -338,7 +339,7 @@ power-source = <PM8058_GPIO_S3>; }; /* Pin 35 connected to ASET */ - pinconf_gpio35 { + gpio35-pins { pins = "gpio35"; function = "normal"; output-high; @@ -346,7 +347,7 @@ power-source = <PM8058_GPIO_S3>; }; }; - dragon_veth_gpios: veth-gpios { + dragon_veth_gpios: veth-state { pinconf { pins = "gpio40"; function = "normal"; @@ -416,6 +417,7 @@ compatible = "qcom,pm8058-led"; reg = <0x131>; label = "pm8058:red"; + color = <LED_COLOR_ID_RED>; default-state = "off"; }; led@132 { @@ -426,6 +428,7 @@ compatible = "qcom,pm8058-led"; reg = <0x132>; label = "pm8058:yellow"; + color = <LED_COLOR_ID_YELLOW>; default-state = "off"; linux,default-trigger = "mmc0"; }; @@ -433,6 +436,8 @@ compatible = "qcom,pm8058-led"; reg = <0x133>; label = "pm8058:green"; + function = LED_FUNCTION_HEARTBEAT; + color = <LED_COLOR_ID_GREEN>; default-state = "on"; linux,default-trigger = "heartbeat"; }; diff --git a/arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts b/arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts index ca9f73528196..fee278e32cb6 100644 --- a/arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts +++ b/arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts @@ -24,9 +24,9 @@ ramoops@88d00000{ compatible = "ramoops"; reg = <0x88d00000 0x100000>; - record-size = <0x00020000>; - console-size = <0x00020000>; - ftrace-size = <0x00020000>; + record-size = <0x00020000>; + console-size = <0x00020000>; + ftrace-size = <0x00020000>; }; }; @@ -44,12 +44,12 @@ gpio-keys { compatible = "gpio-keys"; - volume_up { + key-volume-up { label = "Volume Up"; gpios = <&pm8921_gpio 4 GPIO_ACTIVE_HIGH>; linux,code = <KEY_VOLUMEUP>; }; - volume_down { + key-volume-down { label = "Volume Down"; gpios = <&pm8921_gpio 38 GPIO_ACTIVE_HIGH>; linux,code = <KEY_VOLUMEDOWN>; @@ -98,8 +98,8 @@ * tabla2x-slim-VDDIO_CDC */ s4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; qcom,switch-mode-frequency = <3200000>; regulator-always-on; }; @@ -341,17 +341,17 @@ }; }; - imem@2a03f000 { - compatible = "syscon", "simple-mfd"; + sram@2a03f000 { + compatible = "qcom,apq8064-imem", "syscon", "simple-mfd"; reg = <0x2a03f000 0x1000>; reboot-mode { compatible = "syscon-reboot-mode"; offset = <0x65c>; - mode-normal = <0x77665501>; - mode-bootloader = <0x77665500>; - mode-recovery = <0x77665502>; + mode-normal = <0x77665501>; + mode-bootloader = <0x77665500>; + mode-recovery = <0x77665502>; }; }; }; diff --git a/arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts b/arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts index e068a8d0adf0..e3bf57cd7423 100644 --- a/arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts +++ b/arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts @@ -82,8 +82,8 @@ }; s4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; qcom,switch-mode-frequency = <3200000>; }; @@ -196,8 +196,8 @@ qcom,ssbi@500000 { pmic@0 { gpio@150 { - wlan_default_gpios: wlan-gpios { - pios { + wlan_default_gpios: wlan-gpios-state { + pinconf { pins = "gpio43"; function = "normal"; bias-disable; @@ -230,9 +230,9 @@ sdcc3: mmc@12180000 { status = "okay"; vmmc-supply = <&v3p3_fixed>; - pinctrl-names = "default"; - pinctrl-0 = <&card_detect>; - cd-gpios = <&tlmm_pinmux 26 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&card_detect>; + cd-gpios = <&tlmm_pinmux 26 GPIO_ACTIVE_LOW>; }; /* WLAN */ sdcc4: mmc@121c0000 { diff --git a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts index 2638b380be20..0322cb88d448 100644 --- a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts +++ b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 #include "qcom-apq8064-v2.0.dtsi" #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/leds/common.h> #include <dt-bindings/pinctrl/qcom,pmic-gpio.h> / { @@ -39,6 +40,7 @@ led@1 { label = "apq8064:green:user1"; + color = <LED_COLOR_ID_GREEN>; gpios = <&pm8921_gpio 18 GPIO_ACTIVE_HIGH>; default-state = "on"; }; @@ -108,8 +110,8 @@ }; s4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; qcom,switch-mode-frequency = <3200000>; }; @@ -240,8 +242,8 @@ }; sata0: sata@29000000 { - status = "okay"; - target-supply = <&pm8921_s4>; + status = "okay"; + target-supply = <&pm8921_s4>; }; /* OTG */ @@ -291,8 +293,8 @@ qcom,ssbi@500000 { pmic@0 { gpio@150 { - wlan_default_gpios: wlan-gpios { - pios { + wlan_default_gpios: wlan-gpios-state { + pinconf { pins = "gpio43"; function = "normal"; bias-disable; @@ -300,8 +302,8 @@ }; }; - notify_led: nled { - pios { + notify_led: nled-state { + pinconf { pins = "gpio18"; function = "normal"; bias-disable; @@ -324,9 +326,9 @@ sdcc3: mmc@12180000 { status = "okay"; vmmc-supply = <&pm8921_l6>; - pinctrl-names = "default"; - pinctrl-0 = <&card_detect>; - cd-gpios = <&tlmm_pinmux 26 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&card_detect>; + cd-gpios = <&tlmm_pinmux 26 GPIO_ACTIVE_LOW>; }; /* WLAN */ sdcc4: mmc@121c0000 { @@ -341,7 +343,6 @@ status = "okay"; core-vdda-supply = <&pm8921_hdmi_switch>; - hdmi-mux-supply = <&ext_3p3v>; hpd-gpios = <&tlmm_pinmux 72 GPIO_ACTIVE_HIGH>; diff --git a/arch/arm/boot/dts/qcom-apq8064-sony-xperia-lagan-yuga.dts b/arch/arm/boot/dts/qcom-apq8064-sony-xperia-lagan-yuga.dts index 0cee62c7b8b0..c07c5474750d 100644 --- a/arch/arm/boot/dts/qcom-apq8064-sony-xperia-lagan-yuga.dts +++ b/arch/arm/boot/dts/qcom-apq8064-sony-xperia-lagan-yuga.dts @@ -23,28 +23,28 @@ pinctrl-names = "default"; pinctrl-0 = <&gpio_keys_pin_a>; - camera-focus { + key-camera-focus { label = "camera_focus"; gpios = <&pm8921_gpio 3 GPIO_ACTIVE_LOW>; linux,input-type = <1>; linux,code = <KEY_CAMERA_FOCUS>; }; - camera-snapshot { + key-camera-snapshot { label = "camera_snapshot"; gpios = <&pm8921_gpio 4 GPIO_ACTIVE_LOW>; linux,input-type = <1>; linux,code = <KEY_CAMERA>; }; - volume-down { + key-volume-down { label = "volume_down"; gpios = <&pm8921_gpio 29 GPIO_ACTIVE_LOW>; linux,input-type = <1>; linux,code = <KEY_VOLUMEDOWN>; }; - volume-up { + key-volume-up { label = "volume_up"; gpios = <&pm8921_gpio 35 GPIO_ACTIVE_LOW>; linux,input-type = <1>; @@ -334,7 +334,7 @@ qcom,ssbi@500000 { pmic@0 { gpio@150 { - gpio_keys_pin_a: gpio-keys-pin-active { + gpio_keys_pin_a: gpio-keys-active-state { pins = "gpio3", "gpio4", "gpio29", "gpio35"; function = "normal"; diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index 34c0ba7fa358..ada4c828bf2f 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -105,7 +105,7 @@ polling-delay-passive = <250>; polling-delay = <1000>; - thermal-sensors = <&gcc 7>; + thermal-sensors = <&tsens 7>; coefficients = <1199 0>; trips { @@ -126,7 +126,7 @@ polling-delay-passive = <250>; polling-delay = <1000>; - thermal-sensors = <&gcc 8>; + thermal-sensors = <&tsens 8>; coefficients = <1132 0>; trips { @@ -147,7 +147,7 @@ polling-delay-passive = <250>; polling-delay = <1000>; - thermal-sensors = <&gcc 9>; + thermal-sensors = <&tsens 9>; coefficients = <1199 0>; trips { @@ -168,7 +168,7 @@ polling-delay-passive = <250>; polling-delay = <1000>; - thermal-sensors = <&gcc 10>; + thermal-sensors = <&tsens 10>; coefficients = <1132 0>; trips { @@ -315,7 +315,7 @@ firmware { scm { - compatible = "qcom,scm-apq8064"; + compatible = "qcom,scm-apq8064", "qcom,scm"; clocks = <&rpmcc RPM_DAYTONA_FABRIC_CLK>; clock-names = "core"; @@ -430,8 +430,8 @@ }; sps_sic_non_secure: sps-sic-non-secure@12100000 { - compatible = "syscon"; - reg = <0x12100000 0x10000>; + compatible = "syscon"; + reg = <0x12100000 0x10000>; }; gsbi1: gsbi@12440000 { @@ -796,28 +796,37 @@ }; qfprom: qfprom@700000 { - compatible = "qcom,qfprom"; - reg = <0x00700000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; + compatible = "qcom,apq8064-qfprom", "qcom,qfprom"; + reg = <0x00700000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; ranges; - tsens_calib: calib { + tsens_calib: calib@404 { reg = <0x404 0x10>; }; - tsens_backup: backup_calib { + tsens_backup: backup_calib@414 { reg = <0x414 0x10>; }; }; gcc: clock-controller@900000 { - compatible = "qcom,gcc-apq8064"; + compatible = "qcom,gcc-apq8064", "syscon"; reg = <0x00900000 0x4000>; - nvmem-cells = <&tsens_calib>, <&tsens_backup>; - nvmem-cell-names = "calib", "calib_backup"; #clock-cells = <1>; #power-domain-cells = <1>; #reset-cells = <1>; - #thermal-sensor-cells = <1>; + + tsens: thermal-sensor { + compatible = "qcom,msm8960-tsens"; + + nvmem-cells = <&tsens_calib>, <&tsens_backup>; + nvmem-cell-names = "calib", "calib_backup"; + interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "uplow"; + + #qcom,sensors = <11>; + #thermal-sensor-cells = <1>; + }; }; lcc: clock-controller@28000000 { @@ -836,23 +845,25 @@ }; l2cc: clock-controller@2011000 { - compatible = "qcom,kpss-gcc", "syscon"; - reg = <0x2011000 0x1000>; + compatible = "qcom,kpss-gcc", "syscon"; + reg = <0x2011000 0x1000>; }; rpm@108000 { - compatible = "qcom,rpm-apq8064"; - reg = <0x108000 0x1000>; - qcom,ipc = <&l2cc 0x8 2>; + compatible = "qcom,rpm-apq8064"; + reg = <0x108000 0x1000>; + qcom,ipc = <&l2cc 0x8 2>; - interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "ack", "err", "wakeup"; + interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "ack", "err", "wakeup"; rpmcc: clock-controller { - compatible = "qcom,rpmcc-apq8064", "qcom,rpmcc"; + compatible = "qcom,rpmcc-apq8064", "qcom,rpmcc"; #clock-cells = <1>; + clocks = <&pxo_board>, <&cxo_board>; + clock-names = "pxo", "cxo"; }; regulators { @@ -1004,39 +1015,39 @@ }; sata_phy0: phy@1b400000 { - compatible = "qcom,apq8064-sata-phy"; - status = "disabled"; - reg = <0x1b400000 0x200>; - reg-names = "phy_mem"; - clocks = <&gcc SATA_PHY_CFG_CLK>; - clock-names = "cfg"; - #phy-cells = <0>; + compatible = "qcom,apq8064-sata-phy"; + status = "disabled"; + reg = <0x1b400000 0x200>; + reg-names = "phy_mem"; + clocks = <&gcc SATA_PHY_CFG_CLK>; + clock-names = "cfg"; + #phy-cells = <0>; }; sata0: sata@29000000 { - compatible = "qcom,apq8064-ahci", "generic-ahci"; - status = "disabled"; - reg = <0x29000000 0x180>; - interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; - - clocks = <&gcc SFAB_SATA_S_H_CLK>, - <&gcc SATA_H_CLK>, - <&gcc SATA_A_CLK>, - <&gcc SATA_RXOOB_CLK>, - <&gcc SATA_PMALIVE_CLK>; - clock-names = "slave_iface", - "iface", - "bus", - "rxoob", - "core_pmalive"; - - assigned-clocks = <&gcc SATA_RXOOB_CLK>, - <&gcc SATA_PMALIVE_CLK>; - assigned-clock-rates = <100000000>, <100000000>; - - phys = <&sata_phy0>; - phy-names = "sata-phy"; - ports-implemented = <0x1>; + compatible = "qcom,apq8064-ahci", "generic-ahci"; + status = "disabled"; + reg = <0x29000000 0x180>; + interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc SFAB_SATA_S_H_CLK>, + <&gcc SATA_H_CLK>, + <&gcc SATA_A_CLK>, + <&gcc SATA_RXOOB_CLK>, + <&gcc SATA_PMALIVE_CLK>; + clock-names = "slave_iface", + "iface", + "bus", + "rxoob", + "core_pmalive"; + + assigned-clocks = <&gcc SATA_RXOOB_CLK>, + <&gcc SATA_PMALIVE_CLK>; + assigned-clock-rates = <100000000>, <100000000>; + + phys = <&sata_phy0>; + phy-names = "sata-phy"; + ports-implemented = <0x1>; }; /* Temporary fixed regulator */ @@ -1076,18 +1087,18 @@ #size-cells = <1>; ranges; sdcc1: mmc@12400000 { - status = "disabled"; - compatible = "arm,pl18x", "arm,primecell"; - pinctrl-names = "default"; - pinctrl-0 = <&sdcc1_pins>; + status = "disabled"; + compatible = "arm,pl18x", "arm,primecell"; + pinctrl-names = "default"; + pinctrl-0 = <&sdcc1_pins>; arm,primecell-periphid = <0x00051180>; - reg = <0x12400000 0x2000>; - interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "cmd_irq"; - clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; - clock-names = "mclk", "apb_pclk"; - bus-width = <8>; - max-frequency = <96000000>; + reg = <0x12400000 0x2000>; + interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "cmd_irq"; + clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; + clock-names = "mclk", "apb_pclk"; + bus-width = <8>; + max-frequency = <96000000>; non-removable; cap-sd-highspeed; cap-mmc-highspeed; @@ -1096,36 +1107,36 @@ }; sdcc3: mmc@12180000 { - compatible = "arm,pl18x", "arm,primecell"; + compatible = "arm,pl18x", "arm,primecell"; arm,primecell-periphid = <0x00051180>; - status = "disabled"; - reg = <0x12180000 0x2000>; - interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "cmd_irq"; - clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>; - clock-names = "mclk", "apb_pclk"; - bus-width = <4>; + status = "disabled"; + reg = <0x12180000 0x2000>; + interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "cmd_irq"; + clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>; + clock-names = "mclk", "apb_pclk"; + bus-width = <4>; cap-sd-highspeed; cap-mmc-highspeed; - max-frequency = <192000000>; + max-frequency = <192000000>; no-1-8-v; dmas = <&sdcc3bam 2>, <&sdcc3bam 1>; dma-names = "tx", "rx"; }; sdcc4: mmc@121c0000 { - compatible = "arm,pl18x", "arm,primecell"; + compatible = "arm,pl18x", "arm,primecell"; arm,primecell-periphid = <0x00051180>; - status = "disabled"; - reg = <0x121c0000 0x2000>; - interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "cmd_irq"; - clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>; - clock-names = "mclk", "apb_pclk"; - bus-width = <4>; + status = "disabled"; + reg = <0x121c0000 0x2000>; + interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "cmd_irq"; + clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>; + clock-names = "mclk", "apb_pclk"; + bus-width = <4>; cap-sd-highspeed; cap-mmc-highspeed; - max-frequency = <48000000>; + max-frequency = <48000000>; dmas = <&sdcc4bam 2>, <&sdcc4bam 1>; dma-names = "tx", "rx"; pinctrl-names = "default"; @@ -1271,6 +1282,8 @@ syscon-sfpb = <&mmss_sfpb>; phys = <&dsi0_phy>; phy-names = "dsi"; + status = "disabled"; + ports { #address-cells = <1>; #size-cells = <0>; @@ -1299,9 +1312,10 @@ <0x04700300 0x200>, <0x04700500 0x5c>; reg-names = "dsi_pll", "dsi_phy", "dsi_phy_regulator"; - clock-names = "iface_clk", "ref"; + clock-names = "iface", "ref"; clocks = <&mmcc DSI_M_AHB_CLK>, <&pxo_board>; + status = "disabled"; }; @@ -1420,7 +1434,6 @@ "slave_iface"; phys = <&hdmi_phy>; - phy-names = "hdmi-phy"; ports { #address-cells = <1>; diff --git a/arch/arm/boot/dts/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom-apq8084.dtsi index da50a1a0197f..72f9255855a1 100644 --- a/arch/arm/boot/dts/qcom-apq8084.dtsi +++ b/arch/arm/boot/dts/qcom-apq8084.dtsi @@ -95,7 +95,7 @@ firmware { scm { - compatible = "qcom,scm"; + compatible = "qcom,scm-apq8084", "qcom,scm"; clocks = <&gcc GCC_CE1_CLK> , <&gcc GCC_CE1_AXI_CLK>, <&gcc GCC_CE1_AHB_CLK>; clock-names = "core", "bus", "iface"; }; @@ -240,10 +240,10 @@ }; qfprom: qfprom@fc4bc000 { + compatible = "qcom,apq8084-qfprom", "qcom,qfprom"; + reg = <0xfc4bc000 0x1000>; #address-cells = <1>; #size-cells = <1>; - compatible = "qcom,qfprom"; - reg = <0xfc4bc000 0x1000>; tsens_calib: calib@d0 { reg = <0xd0 0x18>; }; @@ -419,7 +419,7 @@ status = "disabled"; }; - sdhci@f9824900 { + mmc@f9824900 { compatible = "qcom,apq8084-sdhci", "qcom,sdhci-msm-v4"; reg = <0xf9824900 0x11c>, <0xf9824000 0x800>; reg-names = "hc_mem", "core_mem"; @@ -432,7 +432,7 @@ status = "disabled"; }; - sdhci@f98a4900 { + mmc@f98a4900 { compatible = "qcom,apq8084-sdhci", "qcom,sdhci-msm-v4"; reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; reg-names = "hc_mem", "core_mem"; diff --git a/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac-bit.dts b/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac-bit.dts index 028ac8e24797..cf7da1ab177c 100644 --- a/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac-bit.dts +++ b/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac-bit.dts @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-or-later OR MIT +#include <dt-bindings/leds/common.h> #include "qcom-ipq4018-ap120c-ac.dtsi" / { @@ -10,17 +11,22 @@ power { label = "ap120c-ac:green:power"; + function = LED_FUNCTION_POWER; + color = <LED_COLOR_ID_GREEN>; gpios = <&tlmm 5 GPIO_ACTIVE_LOW>; default-state = "on"; }; wlan { label = "ap120c-ac:green:wlan"; + function = LED_FUNCTION_WLAN; + color = <LED_COLOR_ID_GREEN>; gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>; }; support { label = "ap120c-ac:green:support"; + color = <LED_COLOR_ID_GREEN>; gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>; panic-indicator; }; diff --git a/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dts b/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dts index b7916fc26d68..c4f89b712fd9 100644 --- a/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dts +++ b/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dts @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-or-later OR MIT +#include <dt-bindings/leds/common.h> #include "qcom-ipq4018-ap120c-ac.dtsi" / { @@ -8,18 +9,24 @@ status: status { label = "ap120c-ac:blue:status"; + function = LED_FUNCTION_STATUS; + color = <LED_COLOR_ID_BLUE>; gpios = <&tlmm 5 GPIO_ACTIVE_LOW>; default-state = "keep"; }; wlan2g { label = "ap120c-ac:green:wlan2g"; + function = LED_FUNCTION_WLAN; + color = <LED_COLOR_ID_GREEN>; gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>; linux,default-trigger = "phy0tpt"; }; wlan5g { label = "ap120c-ac:red:wlan5g"; + function = LED_FUNCTION_WLAN; + color = <LED_COLOR_ID_RED>; gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>; linux,default-trigger = "phy1tpt"; }; diff --git a/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dtsi b/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dtsi index 1f3b1ce82108..af9a26fb5d4a 100644 --- a/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dtsi +++ b/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dtsi @@ -11,7 +11,7 @@ keys { compatible = "gpio-keys"; - reset { + key-reset { label = "reset"; gpios = <&tlmm 63 GPIO_ACTIVE_LOW>; linux,code = <KEY_RESTART>; diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi index faeaa6bf0def..44a9597d8bfd 100644 --- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi +++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi @@ -93,7 +93,7 @@ #address-cells = <1>; #size-cells = <1>; reg = <0>; - compatible = "n25q128a11"; + compatible = "micron,n25q128a11", "jedec,spi-nor"; spi-max-frequency = <24000000>; }; }; diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts index d596dd1180ae..c7a6e77da272 100644 --- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts +++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts @@ -56,7 +56,7 @@ #address-cells = <1>; #size-cells = <1>; reg = <0>; - compatible = "n25q128a11"; + compatible = "micron,n25q128a11", "jedec,spi-nor"; spi-max-frequency = <24000000>; }; }; diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi index c5da723f7674..bb307b8f678c 100644 --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi @@ -156,7 +156,7 @@ firmware { scm { - compatible = "qcom,scm-ipq4019"; + compatible = "qcom,scm-ipq4019", "qcom,scm"; }; }; @@ -221,7 +221,7 @@ status = "disabled"; }; - sdhci: sdhci@7824900 { + sdhci: mmc@7824900 { compatible = "qcom,sdhci-msm-v4"; reg = <0x7824900 0x11c>, <0x7824000 0x800>; interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts index b63d01d10189..a654d3c22c4f 100644 --- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts +++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts @@ -7,12 +7,6 @@ soc { pinmux@800000 { - i2c4_pins: i2c4_pinmux { - pins = "gpio12", "gpio13"; - function = "gsbi4"; - bias-disable; - }; - buttons_pins: buttons_pins { mux { pins = "gpio54", "gpio65"; diff --git a/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts b/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts index 596d129d4a95..5a65cce2500c 100644 --- a/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts +++ b/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 #include "qcom-ipq8064.dtsi" #include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> / { model = "MikroTik RB3011UiAS-RM"; @@ -187,12 +188,12 @@ }; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; pinctrl-0 = <&buttons_pins>; pinctrl-names = "default"; - button@1 { + button { label = "reset"; linux,code = <KEY_RESTART>; gpios = <&qcom_pinmux 66 GPIO_ACTIVE_LOW>; @@ -208,6 +209,7 @@ led@7 { label = "rb3011:green:user"; + color = <LED_COLOR_ID_GREEN>; gpios = <&qcom_pinmux 33 GPIO_ACTIVE_HIGH>; default-state = "off"; }; @@ -305,15 +307,6 @@ }; }; - mdio0_pins: mdio0_pins { - mux { - pins = "gpio0", "gpio1"; - function = "gpio"; - drive-strength = <8>; - bias-disable; - }; - }; - mdio1_pins: mdio1_pins { mux { pins = "gpio10", "gpio11"; diff --git a/arch/arm/boot/dts/qcom-ipq8064-smb208.dtsi b/arch/arm/boot/dts/qcom-ipq8064-smb208.dtsi new file mode 100644 index 000000000000..ac9c44f0c164 --- /dev/null +++ b/arch/arm/boot/dts/qcom-ipq8064-smb208.dtsi @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include "qcom-ipq8064.dtsi" + +&rpm { + smb208_regulators: regulators { + compatible = "qcom,rpm-smb208-regulators"; + + smb208_s1a: s1a { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1150000>; + + qcom,switch-mode-frequency = <1200000>; + }; + + smb208_s1b: s1b { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1150000>; + + qcom,switch-mode-frequency = <1200000>; + }; + + smb208_s2a: s2a { + regulator-min-microvolt = < 800000>; + regulator-max-microvolt = <1250000>; + + qcom,switch-mode-frequency = <1200000>; + }; + + smb208_s2b: s2b { + regulator-min-microvolt = < 800000>; + regulator-max-microvolt = <1250000>; + + qcom,switch-mode-frequency = <1200000>; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi b/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi index 5c802b99e15f..411c8d63c38e 100644 --- a/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi +++ b/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 #include "qcom-ipq8064.dtsi" #include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> / { model = "Qualcomm Technologies, Inc. IPQ8064-v1.0"; @@ -65,19 +66,19 @@ status = "okay"; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; pinctrl-0 = <&buttons_pins>; pinctrl-names = "default"; - button@1 { + button-1 { label = "reset"; linux,code = <KEY_RESTART>; gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>; linux,input-type = <1>; debounce-interval = <60>; }; - button@2 { + button-2 { label = "wps"; linux,code = <KEY_WPS_BUTTON>; gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>; @@ -107,6 +108,7 @@ led@9 { label = "status_led_fail"; + function = LED_FUNCTION_STATUS; gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>; default-state = "off"; }; @@ -119,6 +121,7 @@ led@53 { label = "status_led_pass"; + function = LED_FUNCTION_STATUS; gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>; default-state = "off"; }; diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi index 808ea1862283..c8337c870bdb 100644 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi @@ -292,8 +292,11 @@ }; smem: smem@41000000 { + compatible = "qcom,smem"; reg = <0x41000000 0x200000>; no-map; + + hwlocks = <&sfpb_mutex 3>; }; }; @@ -382,6 +385,13 @@ }; }; + i2c4_pins: i2c4-default { + pins = "gpio12", "gpio13"; + function = "gsbi4"; + drive-strength = <12>; + bias-disable; + }; + spi_pins: spi_pins { mux { pins = "gpio18", "gpio19", "gpio21"; @@ -424,6 +434,8 @@ pullups { pins = "gpio39"; + function = "nand"; + drive-strength = <10>; bias-pull-up; }; @@ -431,9 +443,32 @@ pins = "gpio40", "gpio41", "gpio42", "gpio43", "gpio44", "gpio45", "gpio46", "gpio47"; + function = "nand"; + drive-strength = <10>; bias-bus-hold; }; }; + + mdio0_pins: mdio0-pins { + mux { + pins = "gpio0", "gpio1"; + function = "mdio"; + drive-strength = <8>; + bias-disable; + }; + }; + + rgmii2_pins: rgmii2-pins { + mux { + pins = "gpio27", "gpio28", "gpio29", + "gpio30", "gpio31", "gpio32", + "gpio51", "gpio52", "gpio59", + "gpio60", "gpio61", "gpio62"; + function = "rgmii2"; + drive-strength = <8>; + bias-disable; + }; + }; }; intc: interrupt-controller@2000000 { @@ -507,6 +542,44 @@ regulator; }; + gsbi1: gsbi@12440000 { + compatible = "qcom,gsbi-v1.0.0"; + reg = <0x12440000 0x100>; + cell-index = <1>; + clocks = <&gcc GSBI1_H_CLK>; + clock-names = "iface"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + syscon-tcsr = <&tcsr>; + + status = "disabled"; + + gsbi1_serial: serial@12450000 { + compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; + reg = <0x12450000 0x100>, + <0x12400000 0x03>; + interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>; + clock-names = "core", "iface"; + + status = "disabled"; + }; + + gsbi1_i2c: i2c@12460000 { + compatible = "qcom,i2c-qup-v1.1.1"; + reg = <0x12460000 0x1000>; + interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>; + clock-names = "core", "iface"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + }; + gsbi2: gsbi@12480000 { compatible = "qcom,gsbi-v1.0.0"; cell-index = <2>; @@ -530,7 +603,7 @@ status = "disabled"; }; - i2c@124a0000 { + gsbi2_i2c: i2c@124a0000 { compatible = "qcom,i2c-qup-v1.1.1"; reg = <0x124a0000 0x1000>; interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; @@ -631,6 +704,49 @@ }; }; + gsbi6: gsbi@16500000 { + compatible = "qcom,gsbi-v1.0.0"; + reg = <0x16500000 0x100>; + cell-index = <6>; + clocks = <&gcc GSBI6_H_CLK>; + clock-names = "iface"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + syscon-tcsr = <&tcsr>; + + status = "disabled"; + + gsbi6_i2c: i2c@16580000 { + compatible = "qcom,i2c-qup-v1.1.1"; + reg = <0x16580000 0x1000>; + interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>; + clock-names = "core", "iface"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + gsbi6_spi: spi@16580000 { + compatible = "qcom,spi-qup-v1.1.1"; + reg = <0x16580000 0x1000>; + interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>; + clock-names = "core", "iface"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + }; + gsbi7: gsbi@16600000 { status = "disabled"; compatible = "qcom,gsbi-v1.0.0"; @@ -652,6 +768,20 @@ clock-names = "core", "iface"; status = "disabled"; }; + + gsbi7_i2c: i2c@16680000 { + compatible = "qcom,i2c-qup-v1.1.1"; + reg = <0x16680000 0x1000>; + interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GSBI7_QUP_CLK>, <&gcc GSBI7_H_CLK>; + clock-names = "core", "iface"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; }; rng@1a500000 { @@ -723,10 +853,13 @@ }; qfprom: qfprom@700000 { - compatible = "qcom,qfprom"; + compatible = "qcom,ipq8064-qfprom", "qcom,qfprom"; reg = <0x00700000 0x1000>; #address-cells = <1>; #size-cells = <1>; + speedbin_efuse: speedbin@c0 { + reg = <0xc0 0x4>; + }; tsens_calib: calib@400 { reg = <0x400 0xb>; }; @@ -773,6 +906,8 @@ rpmcc: clock-controller { compatible = "qcom,rpmcc-ipq806x", "qcom,rpmcc"; #clock-cells = <1>; + clocks = <&pxo_board>; + clock-names = "pxo"; }; }; @@ -784,7 +919,7 @@ l2cc: clock-controller@2011000 { compatible = "qcom,kpss-gcc", "syscon"; reg = <0x2011000 0x1000>; - clocks = <&gcc PLL8_VOTE>, <&gcc PXO_SRC>; + clocks = <&gcc PLL8_VOTE>, <&pxo_board>; clock-names = "pll8_vote", "pxo"; clock-output-names = "acpu_l2_aux"; }; @@ -810,7 +945,7 @@ #address-cells = <3>; #size-cells = <2>; - ranges = <0x81000000 0 0x0fe00000 0x0fe00000 0 0x00100000 /* downstream I/O */ + ranges = <0x81000000 0 0x0fe00000 0x0fe00000 0 0x00010000 /* downstream I/O */ 0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* non-prefetchable memory */ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; @@ -861,7 +996,7 @@ #address-cells = <3>; #size-cells = <2>; - ranges = <0x81000000 0 0x31e00000 0x31e00000 0 0x00100000 /* downstream I/O */ + ranges = <0x81000000 0 0x31e00000 0x31e00000 0 0x00010000 /* downstream I/O */ 0x82000000 0 0x2e000000 0x2e000000 0 0x03e00000>; /* non-prefetchable memory */ interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; @@ -912,7 +1047,7 @@ #address-cells = <3>; #size-cells = <2>; - ranges = <0x81000000 0 0x35e00000 0x35e00000 0 0x00100000 /* downstream I/O */ + ranges = <0x81000000 0 0x35e00000 0x35e00000 0 0x00010000 /* downstream I/O */ 0x82000000 0 0x32000000 0x32000000 0 0x03e00000>; /* non-prefetchable memory */ interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; @@ -967,7 +1102,7 @@ gmac0: ethernet@37000000 { device_type = "network"; - compatible = "qcom,ipq806x-gmac"; + compatible = "qcom,ipq806x-gmac", "snps,dwmac"; reg = <0x37000000 0x200000>; interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "macirq"; @@ -991,7 +1126,7 @@ gmac1: ethernet@37200000 { device_type = "network"; - compatible = "qcom,ipq806x-gmac"; + compatible = "qcom,ipq806x-gmac", "snps,dwmac"; reg = <0x37200000 0x200000>; interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "macirq"; @@ -1015,7 +1150,7 @@ gmac2: ethernet@37400000 { device_type = "network"; - compatible = "qcom,ipq806x-gmac"; + compatible = "qcom,ipq806x-gmac", "snps,dwmac"; reg = <0x37400000 0x200000>; interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "macirq"; @@ -1039,7 +1174,7 @@ gmac3: ethernet@37600000 { device_type = "network"; - compatible = "qcom,ipq806x-gmac"; + compatible = "qcom,ipq806x-gmac", "snps,dwmac"; reg = <0x37600000 0x200000>; interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "macirq"; @@ -1113,6 +1248,8 @@ clocks = <&gcc USB30_1_UTMI_CLK>; clock-names = "ref"; #phy-cells = <0>; + + status = "disabled"; }; ss_phy_1: phy@110f8830 { @@ -1121,6 +1258,8 @@ clocks = <&gcc USB30_1_MASTER_CLK>; clock-names = "ref"; #phy-cells = <0>; + + status = "disabled"; }; usb3_1: usb3@110f8800 { @@ -1184,16 +1323,16 @@ ranges; sdcc1: mmc@12400000 { - status = "disabled"; - compatible = "arm,pl18x", "arm,primecell"; + status = "disabled"; + compatible = "arm,pl18x", "arm,primecell"; arm,primecell-periphid = <0x00051180>; - reg = <0x12400000 0x2000>; - interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x12400000 0x2000>; + interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "cmd_irq"; - clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; - clock-names = "mclk", "apb_pclk"; - bus-width = <8>; - max-frequency = <96000000>; + clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; + clock-names = "mclk", "apb_pclk"; + bus-width = <8>; + max-frequency = <96000000>; non-removable; cap-sd-highspeed; cap-mmc-highspeed; @@ -1204,18 +1343,18 @@ }; sdcc3: mmc@12180000 { - compatible = "arm,pl18x", "arm,primecell"; + compatible = "arm,pl18x", "arm,primecell"; arm,primecell-periphid = <0x00051180>; - status = "disabled"; - reg = <0x12180000 0x2000>; - interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + reg = <0x12180000 0x2000>; + interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "cmd_irq"; - clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>; - clock-names = "mclk", "apb_pclk"; - bus-width = <8>; + clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>; + clock-names = "mclk", "apb_pclk"; + bus-width = <8>; cap-sd-highspeed; cap-mmc-highspeed; - max-frequency = <192000000>; + max-frequency = <192000000>; sd-uhs-sdr104; sd-uhs-ddr50; vqmmc-supply = <&vsdcc_fixed>; @@ -1223,5 +1362,12 @@ dma-names = "tx", "rx"; }; }; + + sfpb_mutex: hwlock@1200600 { + compatible = "qcom,sfpb-mutex"; + reg = <0x01200600 0x100>; + + #hwlock-cells = <1>; + }; }; }; diff --git a/arch/arm/boot/dts/qcom-mdm9615-wp8548.dtsi b/arch/arm/boot/dts/qcom-mdm9615-wp8548.dtsi index 10ad929759ed..49de1821ac3a 100644 --- a/arch/arm/boot/dts/qcom-mdm9615-wp8548.dtsi +++ b/arch/arm/boot/dts/qcom-mdm9615-wp8548.dtsi @@ -114,7 +114,7 @@ }; &pmicgpio { - usb_vbus_5v_pins: usb_vbus_5v_pins { + usb_vbus_5v_pins: usb-vbus-5v-state { pins = "gpio4"; function = "normal"; output-high; diff --git a/arch/arm/boot/dts/qcom-mdm9615.dtsi b/arch/arm/boot/dts/qcom-mdm9615.dtsi index 8f0752ce1c7b..b47c86412de2 100644 --- a/arch/arm/boot/dts/qcom-mdm9615.dtsi +++ b/arch/arm/boot/dts/qcom-mdm9615.dtsi @@ -321,6 +321,7 @@ pmicgpio: gpio@150 { compatible = "qcom,pm8018-gpio", "qcom,ssbi-gpio"; + reg = <0x150>; interrupt-controller; #interrupt-cells = <2>; gpio-controller; @@ -361,7 +362,7 @@ arm,primecell-periphid = <0x00051180>; reg = <0x12180000 0x2000>; interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "cmd_irq"; + interrupt-names = "cmd_irq"; clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; clock-names = "mclk", "apb_pclk"; bus-width = <8>; @@ -381,7 +382,7 @@ status = "disabled"; reg = <0x12140000 0x2000>; interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "cmd_irq"; + interrupt-names = "cmd_irq"; clocks = <&gcc SDC2_CLK>, <&gcc SDC2_H_CLK>; clock-names = "mclk", "apb_pclk"; bus-width = <4>; @@ -411,7 +412,7 @@ interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "ack", "err", "wakeup"; + interrupt-names = "ack", "err", "wakeup"; regulators { compatible = "qcom,rpm-pm8018-regulators"; diff --git a/arch/arm/boot/dts/qcom-msm8226.dtsi b/arch/arm/boot/dts/qcom-msm8226.dtsi index 28eca15b5712..0b5effdb269a 100644 --- a/arch/arm/boot/dts/qcom-msm8226.dtsi +++ b/arch/arm/boot/dts/qcom-msm8226.dtsi @@ -134,7 +134,7 @@ reg = <0xf9011000 0x1000>; }; - sdhc_1: sdhci@f9824900 { + sdhc_1: mmc@f9824900 { compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4"; reg = <0xf9824900 0x11c>, <0xf9824000 0x800>; reg-names = "hc_mem", "core_mem"; @@ -150,7 +150,7 @@ status = "disabled"; }; - sdhc_2: sdhci@f98a4900 { + sdhc_2: mmc@f98a4900 { compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4"; reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; reg-names = "hc_mem", "core_mem"; @@ -166,7 +166,7 @@ status = "disabled"; }; - sdhc_3: sdhci@f9864900 { + sdhc_3: mmc@f9864900 { compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4"; reg = <0xf9864900 0x11c>, <0xf9864000 0x800>; reg-names = "hc_mem", "core_mem"; diff --git a/arch/arm/boot/dts/qcom-msm8660.dtsi b/arch/arm/boot/dts/qcom-msm8660.dtsi index 47b97daecef1..63a501c63cf8 100644 --- a/arch/arm/boot/dts/qcom-msm8660.dtsi +++ b/arch/arm/boot/dts/qcom-msm8660.dtsi @@ -56,7 +56,7 @@ clock-frequency = <19200000>; }; - pxo_board { + pxo_board: pxo_board { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; @@ -392,25 +392,27 @@ }; l2cc: clock-controller@2082000 { - compatible = "qcom,kpss-gcc", "syscon"; - reg = <0x02082000 0x1000>; + compatible = "qcom,kpss-gcc", "syscon"; + reg = <0x02082000 0x1000>; }; rpm: rpm@104000 { - compatible = "qcom,rpm-msm8660"; - reg = <0x00104000 0x1000>; - qcom,ipc = <&l2cc 0x8 2>; - - interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "ack", "err", "wakeup"; + compatible = "qcom,rpm-msm8660"; + reg = <0x00104000 0x1000>; + qcom,ipc = <&l2cc 0x8 2>; + + interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "ack", "err", "wakeup"; clocks = <&gcc RPM_MSG_RAM_H_CLK>; clock-names = "ram"; rpmcc: clock-controller { - compatible = "qcom,rpmcc-msm8660", "qcom,rpmcc"; + compatible = "qcom,rpmcc-msm8660", "qcom,rpmcc"; #clock-cells = <1>; + clocks = <&pxo_board>; + clock-names = "pxo"; }; pm8901-regulators { @@ -486,80 +488,80 @@ #size-cells = <1>; ranges; sdcc1: mmc@12400000 { - status = "disabled"; - compatible = "arm,pl18x", "arm,primecell"; + status = "disabled"; + compatible = "arm,pl18x", "arm,primecell"; arm,primecell-periphid = <0x00051180>; - reg = <0x12400000 0x8000>; - interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "cmd_irq"; - clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; - clock-names = "mclk", "apb_pclk"; - bus-width = <8>; - max-frequency = <48000000>; + reg = <0x12400000 0x8000>; + interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "cmd_irq"; + clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; + clock-names = "mclk", "apb_pclk"; + bus-width = <8>; + max-frequency = <48000000>; non-removable; cap-sd-highspeed; cap-mmc-highspeed; }; sdcc2: mmc@12140000 { - status = "disabled"; - compatible = "arm,pl18x", "arm,primecell"; + status = "disabled"; + compatible = "arm,pl18x", "arm,primecell"; arm,primecell-periphid = <0x00051180>; - reg = <0x12140000 0x8000>; - interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "cmd_irq"; - clocks = <&gcc SDC2_CLK>, <&gcc SDC2_H_CLK>; - clock-names = "mclk", "apb_pclk"; - bus-width = <8>; - max-frequency = <48000000>; + reg = <0x12140000 0x8000>; + interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "cmd_irq"; + clocks = <&gcc SDC2_CLK>, <&gcc SDC2_H_CLK>; + clock-names = "mclk", "apb_pclk"; + bus-width = <8>; + max-frequency = <48000000>; cap-sd-highspeed; cap-mmc-highspeed; }; sdcc3: mmc@12180000 { - compatible = "arm,pl18x", "arm,primecell"; + compatible = "arm,pl18x", "arm,primecell"; arm,primecell-periphid = <0x00051180>; - status = "disabled"; - reg = <0x12180000 0x8000>; - interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "cmd_irq"; - clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>; - clock-names = "mclk", "apb_pclk"; - bus-width = <4>; + status = "disabled"; + reg = <0x12180000 0x8000>; + interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "cmd_irq"; + clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>; + clock-names = "mclk", "apb_pclk"; + bus-width = <4>; cap-sd-highspeed; cap-mmc-highspeed; - max-frequency = <48000000>; + max-frequency = <48000000>; no-1-8-v; }; sdcc4: mmc@121c0000 { - compatible = "arm,pl18x", "arm,primecell"; + compatible = "arm,pl18x", "arm,primecell"; arm,primecell-periphid = <0x00051180>; - status = "disabled"; - reg = <0x121c0000 0x8000>; - interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "cmd_irq"; - clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>; - clock-names = "mclk", "apb_pclk"; - bus-width = <4>; - max-frequency = <48000000>; + status = "disabled"; + reg = <0x121c0000 0x8000>; + interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "cmd_irq"; + clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>; + clock-names = "mclk", "apb_pclk"; + bus-width = <4>; + max-frequency = <48000000>; cap-sd-highspeed; cap-mmc-highspeed; }; sdcc5: mmc@12200000 { - compatible = "arm,pl18x", "arm,primecell"; + compatible = "arm,pl18x", "arm,primecell"; arm,primecell-periphid = <0x00051180>; - status = "disabled"; - reg = <0x12200000 0x8000>; - interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "cmd_irq"; - clocks = <&gcc SDC5_CLK>, <&gcc SDC5_H_CLK>; - clock-names = "mclk", "apb_pclk"; - bus-width = <4>; + status = "disabled"; + reg = <0x12200000 0x8000>; + interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "cmd_irq"; + clocks = <&gcc SDC5_CLK>, <&gcc SDC5_H_CLK>; + clock-names = "mclk", "apb_pclk"; + bus-width = <4>; cap-sd-highspeed; cap-mmc-highspeed; - max-frequency = <48000000>; + max-frequency = <48000000>; }; }; diff --git a/arch/arm/boot/dts/qcom-msm8960.dtsi b/arch/arm/boot/dts/qcom-msm8960.dtsi index 4a2d74cf01d2..19554f3b5196 100644 --- a/arch/arm/boot/dts/qcom-msm8960.dtsi +++ b/arch/arm/boot/dts/qcom-msm8960.dtsi @@ -148,19 +148,19 @@ }; l2cc: clock-controller@2011000 { - compatible = "qcom,kpss-gcc", "syscon"; - reg = <0x2011000 0x1000>; + compatible = "qcom,kpss-gcc", "syscon"; + reg = <0x2011000 0x1000>; }; rpm@108000 { - compatible = "qcom,rpm-msm8960"; - reg = <0x108000 0x1000>; - qcom,ipc = <&l2cc 0x8 2>; + compatible = "qcom,rpm-msm8960"; + reg = <0x108000 0x1000>; + qcom,ipc = <&l2cc 0x8 2>; - interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "ack", "err", "wakeup"; + interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "ack", "err", "wakeup"; regulators { compatible = "qcom,rpm-pm8921-regulators"; @@ -268,16 +268,16 @@ #size-cells = <1>; ranges; sdcc1: mmc@12400000 { - status = "disabled"; - compatible = "arm,pl18x", "arm,primecell"; + status = "disabled"; + compatible = "arm,pl18x", "arm,primecell"; arm,primecell-periphid = <0x00051180>; - reg = <0x12400000 0x8000>; - interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "cmd_irq"; - clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; - clock-names = "mclk", "apb_pclk"; - bus-width = <8>; - max-frequency = <96000000>; + reg = <0x12400000 0x8000>; + interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "cmd_irq"; + clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; + clock-names = "mclk", "apb_pclk"; + bus-width = <8>; + max-frequency = <96000000>; non-removable; cap-sd-highspeed; cap-mmc-highspeed; @@ -285,18 +285,18 @@ }; sdcc3: mmc@12180000 { - compatible = "arm,pl18x", "arm,primecell"; + compatible = "arm,pl18x", "arm,primecell"; arm,primecell-periphid = <0x00051180>; - status = "disabled"; - reg = <0x12180000 0x8000>; - interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "cmd_irq"; - clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>; - clock-names = "mclk", "apb_pclk"; - bus-width = <4>; + status = "disabled"; + reg = <0x12180000 0x8000>; + interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "cmd_irq"; + clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>; + clock-names = "mclk", "apb_pclk"; + bus-width = <4>; cap-sd-highspeed; cap-mmc-highspeed; - max-frequency = <192000000>; + max-frequency = <192000000>; no-1-8-v; vmmc-supply = <&vsdcc_fixed>; }; diff --git a/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts b/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts index 9493886a5c0d..ec5d340562b6 100644 --- a/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts +++ b/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts @@ -3,6 +3,7 @@ #include "qcom-pm8841.dtsi" #include "qcom-pm8941.dtsi" #include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> #include <dt-bindings/pinctrl/qcom,pmic-gpio.h> / { @@ -24,14 +25,14 @@ pinctrl-names = "default"; pinctrl-0 = <&gpio_keys_pin_a>; - volume-up { + key-volume-up { label = "volume_up"; gpios = <&pm8941_gpios 2 GPIO_ACTIVE_LOW>; linux,input-type = <1>; linux,code = <KEY_VOLUMEUP>; }; - volume-down { + key-volume-down { label = "volume_down"; gpios = <&pm8941_gpios 3 GPIO_ACTIVE_LOW>; linux,input-type = <1>; @@ -272,7 +273,7 @@ }; &pm8941_gpios { - gpio_keys_pin_a: gpio-keys-active { + gpio_keys_pin_a: gpio-keys-active-state { pins = "gpio2", "gpio3"; function = "normal"; @@ -280,7 +281,7 @@ power-source = <PM8941_GPIO_S3>; }; - fuelgauge_pin: fuelgauge-int { + fuelgauge_pin: fuelgauge-int-state { pins = "gpio9"; function = "normal"; @@ -289,7 +290,7 @@ power-source = <PM8941_GPIO_S3>; }; - wlan_sleep_clk_pin: wl-sleep-clk { + wlan_sleep_clk_pin: wl-sleep-clk-state { pins = "gpio16"; function = "func2"; @@ -297,7 +298,7 @@ power-source = <PM8941_GPIO_S3>; }; - wlan_regulator_pin: wl-reg-active { + wlan_regulator_pin: wl-reg-active-state { pins = "gpio17"; function = "normal"; @@ -313,6 +314,35 @@ }; }; +&pm8941_lpg { + status = "okay"; + + qcom,power-source = <1>; + + multi-led { + color = <LED_COLOR_ID_RGB>; + function = LED_FUNCTION_STATUS; + + #address-cells = <1>; + #size-cells = <0>; + + led@7 { + reg = <7>; + color = <LED_COLOR_ID_RED>; + }; + + led@6 { + reg = <6>; + color = <LED_COLOR_ID_GREEN>; + }; + + led@5 { + reg = <5>; + color = <LED_COLOR_ID_BLUE>; + }; + }; +}; + &rpm_requests { pm8841-regulators { compatible = "qcom,rpm-pm8841-regulators"; diff --git a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-rhine.dtsi b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-rhine.dtsi index 1d21de46f85c..5a70683d9103 100644 --- a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-rhine.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-rhine.dtsi @@ -3,6 +3,7 @@ #include "qcom-pm8841.dtsi" #include "qcom-pm8941.dtsi" #include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> #include <dt-bindings/pinctrl/qcom,pmic-gpio.h> / { @@ -20,28 +21,28 @@ pinctrl-names = "default"; pinctrl-0 = <&gpio_keys_pin_a>; - volume-down { + key-volume-down { label = "volume_down"; gpios = <&pm8941_gpios 2 GPIO_ACTIVE_LOW>; linux,input-type = <1>; linux,code = <KEY_VOLUMEDOWN>; }; - camera-snapshot { + key-camera-snapshot { label = "camera_snapshot"; gpios = <&pm8941_gpios 3 GPIO_ACTIVE_LOW>; linux,input-type = <1>; linux,code = <KEY_CAMERA>; }; - camera-focus { + key-camera-focus { label = "camera_focus"; gpios = <&pm8941_gpios 4 GPIO_ACTIVE_LOW>; linux,input-type = <1>; linux,code = <KEY_CAMERA_FOCUS>; }; - volume-up { + key-volume-up { label = "volume_up"; gpios = <&pm8941_gpios 5 GPIO_ACTIVE_LOW>; linux,input-type = <1>; @@ -163,7 +164,7 @@ }; &pm8941_gpios { - gpio_keys_pin_a: gpio-keys-active { + gpio_keys_pin_a: gpio-keys-active-state { pins = "gpio2", "gpio3", "gpio4", "gpio5"; function = "normal"; @@ -172,6 +173,35 @@ }; }; +&pm8941_lpg { + status = "okay"; + + qcom,power-source = <1>; + + rgb-led { + color = <LED_COLOR_ID_RGB>; + function = LED_FUNCTION_STATUS; + + #address-cells = <1>; + #size-cells = <0>; + + led@5 { + reg = <5>; + color = <LED_COLOR_ID_BLUE>; + }; + + led@6 { + reg = <6>; + color = <LED_COLOR_ID_GREEN>; + }; + + led@7 { + reg = <7>; + color = <LED_COLOR_ID_RED>; + }; + }; +}; + &pm8941_wled { status = "okay"; diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index c3b8a6d63027..8baca2a77717 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -96,7 +96,7 @@ firmware { scm { - compatible = "qcom,scm"; + compatible = "qcom,scm-msm8974", "qcom,scm"; clocks = <&gcc GCC_CE1_CLK>, <&gcc GCC_CE1_AXI_CLK>, <&gcc GCC_CE1_AHB_CLK>; clock-names = "core", "bus", "iface"; }; @@ -436,7 +436,7 @@ reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>; }; - sdhc_1: sdhci@f9824900 { + sdhc_1: mmc@f9824900 { compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"; reg = <0xf9824900 0x11c>, <0xf9824000 0x800>; reg-names = "hc_mem", "core_mem"; @@ -453,7 +453,7 @@ status = "disabled"; }; - sdhc_3: sdhci@f9864900 { + sdhc_3: mmc@f9864900 { compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"; reg = <0xf9864900 0x11c>, <0xf9864000 0x800>; reg-names = "hc_mem", "core_mem"; @@ -472,7 +472,7 @@ status = "disabled"; }; - sdhc_2: sdhci@f98a4900 { + sdhc_2: mmc@f98a4900 { compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"; reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; reg-names = "hc_mem", "core_mem"; @@ -580,7 +580,7 @@ blsp2_uart1: serial@f995d000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; reg = <0xf995d000 0x1000>; - interrupts = <GIC_SPI 113 IRQ_TYPE_NONE>; + interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_BLSP2_UART1_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; clock-names = "core", "iface"; pinctrl-names = "default", "sleep"; @@ -1128,10 +1128,10 @@ }; qfprom: qfprom@fc4bc000 { + compatible = "qcom,msm8974-qfprom", "qcom,qfprom"; + reg = <0xfc4bc000 0x1000>; #address-cells = <1>; #size-cells = <1>; - compatible = "qcom,qfprom"; - reg = <0xfc4bc000 0x1000>; tsens_calib: calib@d0 { reg = <0xd0 0x18>; }; @@ -1156,6 +1156,18 @@ #interrupt-cells = <4>; }; + bam_dmux_dma: dma-controller@fc834000 { + compatible = "qcom,bam-v1.4.0"; + reg = <0xfc834000 0x7000>; + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; + qcom,ee = <0>; + + num-channels = <6>; + qcom,num-ees = <1>; + qcom,powered-remotely; + }; + remoteproc_mss: remoteproc@fc880000 { compatible = "qcom,msm8974-mss-pil"; reg = <0xfc880000 0x100>, <0xfc820000 0x020>; @@ -1182,6 +1194,8 @@ qcom,smem-states = <&modem_smp2p_out 0>; qcom,smem-state-names = "stop"; + status = "disabled"; + mba { memory-region = <&mba_region>; }; @@ -1190,6 +1204,20 @@ memory-region = <&mpss_region>; }; + bam_dmux: bam-dmux { + compatible = "qcom,bam-dmux"; + + interrupt-parent = <&modem_smsm>; + interrupts = <1 IRQ_TYPE_EDGE_BOTH>, <11 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "pc", "pc-ack"; + + qcom,smem-states = <&apps_smsm 1>, <&apps_smsm 11>; + qcom,smem-state-names = "pc", "pc-ack"; + + dmas = <&bam_dmux_dma 4>, <&bam_dmux_dma 5>; + dma-names = "tx", "rx"; + }; + smd-edge { interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>; @@ -1608,7 +1636,7 @@ status = "disabled"; - gpu_opp_table: opp_table { + gpu_opp_table: opp-table { compatible = "operating-points-v2"; opp-320000000 { @@ -1625,11 +1653,12 @@ }; }; - ocmem@fdd00000 { + sram@fdd00000 { compatible = "qcom,msm8974-ocmem"; reg = <0xfdd00000 0x2000>, <0xfec00000 0x180000>; reg-names = "ctrl", "mem"; + ranges = <0 0xfec00000 0x180000>; clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>, <&mmcc OCMEMCX_OCMEMNOC_CLK>; clock-names = "core", "iface"; @@ -1661,6 +1690,8 @@ qcom,smem-states = <&adsp_smp2p_out 0>; qcom,smem-state-names = "stop"; + status = "disabled"; + smd-edge { interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; @@ -1672,8 +1703,8 @@ }; }; - imem: imem@fe805000 { - compatible = "syscon", "simple-mfd"; + imem: sram@fe805000 { + compatible = "qcom,msm8974-imem", "syscon", "simple-mfd"; reg = <0xfe805000 0x1000>; reboot-mode { diff --git a/arch/arm/boot/dts/qcom-msm8974pro-fairphone-fp2.dts b/arch/arm/boot/dts/qcom-msm8974pro-fairphone-fp2.dts index 58cb2ce1e4df..ff6e0066768b 100644 --- a/arch/arm/boot/dts/qcom-msm8974pro-fairphone-fp2.dts +++ b/arch/arm/boot/dts/qcom-msm8974pro-fairphone-fp2.dts @@ -3,6 +3,7 @@ #include "qcom-pm8841.dtsi" #include "qcom-pm8941.dtsi" #include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> #include <dt-bindings/pinctrl/qcom,pmic-gpio.h> / { @@ -25,7 +26,7 @@ pinctrl-names = "default"; pinctrl-0 = <&gpio_keys_pin_a>; - camera-snapshot { + key-camera-snapshot { label = "camera_snapshot"; gpios = <&pm8941_gpios 1 GPIO_ACTIVE_LOW>; linux,code = <KEY_CAMERA>; @@ -33,7 +34,7 @@ debounce-interval = <15>; }; - volume-down { + key-volume-down { label = "volume_down"; gpios = <&pm8941_gpios 2 GPIO_ACTIVE_LOW>; linux,code = <KEY_VOLUMEDOWN>; @@ -41,7 +42,7 @@ debounce-interval = <15>; }; - volume-up { + key-volume-up { label = "volume_up"; gpios = <&pm8941_gpios 5 GPIO_ACTIVE_LOW>; linux,code = <KEY_VOLUMEUP>; @@ -78,9 +79,9 @@ &imem { reboot-mode { - mode-normal = <0x77665501>; - mode-bootloader = <0x77665500>; - mode-recovery = <0x77665502>; + mode-normal = <0x77665501>; + mode-bootloader = <0x77665500>; + mode-recovery = <0x77665502>; }; }; @@ -110,7 +111,7 @@ }; &pm8941_gpios { - gpio_keys_pin_a: gpio-keys-active { + gpio_keys_pin_a: gpio-keys-active-state { pins = "gpio1", "gpio2", "gpio5"; function = "normal"; @@ -119,6 +120,35 @@ }; }; +&pm8941_lpg { + status = "okay"; + + qcom,power-source = <1>; + + multi-led { + color = <LED_COLOR_ID_RGB>; + function = LED_FUNCTION_STATUS; + + #address-cells = <1>; + #size-cells = <0>; + + led@7 { + reg = <7>; + color = <LED_COLOR_ID_RED>; + }; + + led@6 { + reg = <6>; + color = <LED_COLOR_ID_GREEN>; + }; + + led@5 { + reg = <5>; + color = <LED_COLOR_ID_BLUE>; + }; + }; +}; + &pronto { status = "okay"; @@ -147,10 +177,12 @@ }; &remoteproc_adsp { + status = "okay"; cx-supply = <&pm8841_s2>; }; &remoteproc_mss { + status = "okay"; cx-supply = <&pm8841_s2>; mss-supply = <&pm8841_s3>; mx-supply = <&pm8841_s1>; diff --git a/arch/arm/boot/dts/qcom-msm8974pro-samsung-klte.dts b/arch/arm/boot/dts/qcom-msm8974pro-samsung-klte.dts index d6b2300a8223..983e10c3d863 100644 --- a/arch/arm/boot/dts/qcom-msm8974pro-samsung-klte.dts +++ b/arch/arm/boot/dts/qcom-msm8974pro-samsung-klte.dts @@ -25,7 +25,7 @@ pinctrl-names = "default"; pinctrl-0 = <&gpio_keys_pin_a>; - volume-down { + key-volume-down { label = "volume_down"; gpios = <&pma8084_gpios 2 GPIO_ACTIVE_LOW>; linux,input-type = <1>; @@ -33,7 +33,7 @@ debounce-interval = <15>; }; - home-key { + key-home { label = "home_key"; gpios = <&pma8084_gpios 3 GPIO_ACTIVE_LOW>; linux,input-type = <1>; @@ -42,7 +42,7 @@ debounce-interval = <15>; }; - volume-up { + key-volume-up { label = "volume_up"; gpios = <&pma8084_gpios 5 GPIO_ACTIVE_LOW>; linux,input-type = <1>; @@ -398,7 +398,7 @@ }; &pma8084_gpios { - gpio_keys_pin_a: gpio-keys-active { + gpio_keys_pin_a: gpio-keys-active-state { pins = "gpio2", "gpio3", "gpio5"; function = "normal"; @@ -406,7 +406,7 @@ power-source = <PMA8084_GPIO_S4>; }; - touchkey_pin: touchkey-int-pin { + touchkey_pin: touchkey-int-state { pins = "gpio6"; function = "normal"; bias-disable; @@ -414,7 +414,7 @@ power-source = <PMA8084_GPIO_S4>; }; - touch_pin: touchscreen-int-pin { + touch_pin: touchscreen-int-state { pins = "gpio8"; function = "normal"; bias-disable; @@ -422,7 +422,7 @@ power-source = <PMA8084_GPIO_S4>; }; - panel_en_pin: panel-en-pin { + panel_en_pin: panel-en-state { pins = "gpio14"; function = "normal"; bias-pull-up; @@ -430,7 +430,7 @@ qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>; }; - wlan_sleep_clk_pin: wlan-sleep-clk-pin { + wlan_sleep_clk_pin: wlan-sleep-clk-state { pins = "gpio16"; function = "func2"; @@ -439,7 +439,7 @@ qcom,drive-strength = <PMIC_GPIO_STRENGTH_HIGH>; }; - panel_rst_pin: panel-rst-pin { + panel_rst_pin: panel-rst-state { pins = "gpio17"; function = "normal"; bias-disable; @@ -447,7 +447,7 @@ qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>; }; - fuelgauge_pin: fuelgauge-int-pin { + fuelgauge_pin: fuelgauge-int-state { pins = "gpio21"; function = "normal"; bias-disable; @@ -457,10 +457,12 @@ }; &remoteproc_adsp { + status = "okay"; cx-supply = <&pma8084_s2>; }; &remoteproc_mss { + status = "okay"; cx-supply = <&pma8084_s2>; mss-supply = <&pma8084_s6>; mx-supply = <&pma8084_s1>; diff --git a/arch/arm/boot/dts/qcom-msm8974pro-sony-xperia-shinano-castor.dts b/arch/arm/boot/dts/qcom-msm8974pro-sony-xperia-shinano-castor.dts index 9bd8faea61a5..3f45f5c5d37b 100644 --- a/arch/arm/boot/dts/qcom-msm8974pro-sony-xperia-shinano-castor.dts +++ b/arch/arm/boot/dts/qcom-msm8974pro-sony-xperia-shinano-castor.dts @@ -3,6 +3,7 @@ #include "qcom-pm8841.dtsi" #include "qcom-pm8941.dtsi" #include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> #include <dt-bindings/pinctrl/qcom,pmic-gpio.h> / { @@ -24,28 +25,28 @@ pinctrl-names = "default"; pinctrl-0 = <&gpio_keys_pin_a>; - volume-down { + key-volume-down { label = "volume_down"; gpios = <&pm8941_gpios 2 GPIO_ACTIVE_LOW>; linux,input-type = <1>; linux,code = <KEY_VOLUMEDOWN>; }; - camera-snapshot { + key-camera-snapshot { label = "camera_snapshot"; gpios = <&pm8941_gpios 3 GPIO_ACTIVE_LOW>; linux,input-type = <1>; linux,code = <KEY_CAMERA>; }; - camera-focus { + key-camera-focus { label = "camera_focus"; gpios = <&pm8941_gpios 4 GPIO_ACTIVE_LOW>; linux,input-type = <1>; linux,code = <KEY_CAMERA_FOCUS>; }; - volume-up { + key-volume-up { label = "volume_up"; gpios = <&pm8941_gpios 5 GPIO_ACTIVE_LOW>; linux,input-type = <1>; @@ -244,7 +245,7 @@ }; &pm8941_gpios { - gpio_keys_pin_a: gpio-keys-active { + gpio_keys_pin_a: gpio-keys-active-state { pins = "gpio2", "gpio5"; function = "normal"; @@ -252,7 +253,7 @@ power-source = <PM8941_GPIO_S3>; }; - bt_reg_on_pin: bt-reg-on { + bt_reg_on_pin: bt-reg-on-state { pins = "gpio16"; function = "normal"; @@ -260,7 +261,7 @@ power-source = <PM8941_GPIO_S3>; }; - wlan_sleep_clk_pin: wl-sleep-clk { + wlan_sleep_clk_pin: wl-sleep-clk-state { pins = "gpio17"; function = "func2"; @@ -268,7 +269,7 @@ power-source = <PM8941_GPIO_S3>; }; - wlan_regulator_pin: wl-reg-active { + wlan_regulator_pin: wl-reg-active-state { pins = "gpio18"; function = "normal"; @@ -276,7 +277,7 @@ power-source = <PM8941_GPIO_S3>; }; - lcd_dcdc_en_pin_a: lcd-dcdc-en-active { + lcd_dcdc_en_pin_a: lcd-dcdc-en-active-state { pins = "gpio20"; function = "normal"; @@ -288,6 +289,35 @@ }; +&pm8941_lpg { + status = "okay"; + + qcom,power-source = <1>; + + rgb-led { + color = <LED_COLOR_ID_RGB>; + function = LED_FUNCTION_STATUS; + + #address-cells = <1>; + #size-cells = <0>; + + led@5 { + reg = <5>; + color = <LED_COLOR_ID_BLUE>; + }; + + led@6 { + reg = <6>; + color = <LED_COLOR_ID_GREEN>; + }; + + led@7 { + reg = <7>; + color = <LED_COLOR_ID_RED>; + }; + }; +}; + &rpm_requests { pm8941-regulators { compatible = "qcom,rpm-pm8941-regulators"; diff --git a/arch/arm/boot/dts/qcom-pm8841.dtsi b/arch/arm/boot/dts/qcom-pm8841.dtsi index 2caf71eacb52..b5cdde034d18 100644 --- a/arch/arm/boot/dts/qcom-pm8841.dtsi +++ b/arch/arm/boot/dts/qcom-pm8841.dtsi @@ -24,6 +24,7 @@ compatible = "qcom,spmi-temp-alarm"; reg = <0x2400>; interrupts = <4 0x24 0 IRQ_TYPE_EDGE_RISING>; + #thermal-sensor-cells = <0>; }; }; diff --git a/arch/arm/boot/dts/qcom-pm8941.dtsi b/arch/arm/boot/dts/qcom-pm8941.dtsi index cdd2bdb77b32..59d0cde63251 100644 --- a/arch/arm/boot/dts/qcom-pm8941.dtsi +++ b/arch/arm/boot/dts/qcom-pm8941.dtsi @@ -68,7 +68,7 @@ interrupt-controller; #interrupt-cells = <2>; - boost_bypass_n_pin: boost-bypass { + boost_bypass_n_pin: boost-bypass-state { pins = "gpio21"; function = "normal"; }; @@ -144,6 +144,16 @@ #address-cells = <1>; #size-cells = <0>; + pm8941_lpg: lpg { + compatible = "qcom,pm8941-lpg"; + + #address-cells = <1>; + #size-cells = <0>; + #pwm-cells = <2>; + + status = "disabled"; + }; + pm8941_wled: wled@d800 { compatible = "qcom,pm8941-wled"; reg = <0xd800>; diff --git a/arch/arm/boot/dts/qcom-pmx55.dtsi b/arch/arm/boot/dts/qcom-pmx55.dtsi index 6571b88d018a..9de7578a4c5f 100644 --- a/arch/arm/boot/dts/qcom-pmx55.dtsi +++ b/arch/arm/boot/dts/qcom-pmx55.dtsi @@ -69,6 +69,7 @@ compatible = "qcom,pmx55-gpio", "qcom,spmi-gpio"; reg = <0xc000>; gpio-controller; + gpio-ranges = <&pmx55_gpios 0 0 11>; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; diff --git a/arch/arm/boot/dts/qcom-pmx65.dtsi b/arch/arm/boot/dts/qcom-pmx65.dtsi index 5411b833d26e..abf229a8b75a 100644 --- a/arch/arm/boot/dts/qcom-pmx65.dtsi +++ b/arch/arm/boot/dts/qcom-pmx65.dtsi @@ -21,9 +21,10 @@ }; pmx65_gpios: pinctrl@8800 { - compatible = "qcom,pmx65-gpio"; + compatible = "qcom,pmx65-gpio", "qcom,spmi-gpio"; reg = <0x8800>; gpio-controller; + gpio-ranges = <&pmx65_gpios 0 0 16>; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom-sdx55.dtsi index 1c2b208a5670..c72540223fa9 100644 --- a/arch/arm/boot/dts/qcom-sdx55.dtsi +++ b/arch/arm/boot/dts/qcom-sdx55.dtsi @@ -206,7 +206,7 @@ blsp1_uart3: serial@831000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; reg = <0x00831000 0x200>; - interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_LOW>; + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc 30>, <&gcc 9>; clock-names = "core", "iface"; @@ -388,7 +388,7 @@ reg = <0x01fc0000 0x1000>; }; - sdhc_1: sdhci@8804000 { + sdhc_1: mmc@8804000 { compatible = "qcom,sdx55-sdhci", "qcom,sdhci-msm-v5"; reg = <0x08804000 0x1000>; interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, @@ -561,8 +561,8 @@ #interrupt-cells = <2>; }; - imem@1468f000 { - compatible = "simple-mfd"; + sram@1468f000 { + compatible = "qcom,sdx55-imem", "syscon", "simple-mfd"; reg = <0x1468f000 0x1000>; #address-cells = <1>; diff --git a/arch/arm/boot/dts/qcom-sdx65-mtp.dts b/arch/arm/boot/dts/qcom-sdx65-mtp.dts index 79dc31aa7cd1..85ea02d8362d 100644 --- a/arch/arm/boot/dts/qcom-sdx65-mtp.dts +++ b/arch/arm/boot/dts/qcom-sdx65-mtp.dts @@ -64,10 +64,6 @@ }; }; -&blsp1_uart3 { - status = "ok"; -}; - &apps_rsc { pmx65-rpmh-regulators { compatible = "qcom,pmx65-rpmh-regulators"; @@ -123,7 +119,7 @@ regulator-max-microvolt = <1300000>; }; - ldo1 { + vreg_l1b_1p2: ldo1 { regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; @@ -141,13 +137,13 @@ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; - ldo4 { + vreg_l4b_0p88: ldo4 { regulator-min-microvolt = <880000>; regulator-max-microvolt = <912000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; - ldo5 { + vreg_l5b_1p8: ldo5 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; @@ -177,7 +173,7 @@ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; - ldo10 { + vreg_l10b_3p08: ldo10 { regulator-min-microvolt = <3088000>; regulator-max-microvolt = <3088000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; @@ -244,3 +240,52 @@ }; }; }; + +&blsp1_uart3 { + status = "okay"; +}; + +&qpic_bam { + status = "okay"; +}; + +&qpic_nand { + status = "okay"; + + nand@0 { + reg = <0>; + + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + nand-bus-width = <8>; + /* ico and efs2 partitions are secured */ + secure-regions = /bits/ 64 <0x500000 0x500000 + 0xa00000 0xb00000>; + }; +}; + +&remoteproc_mpss { + status = "okay"; + memory-region = <&mpss_adsp_mem>; +}; + +&usb { + status = "okay"; +}; + +&usb_dwc3 { + dr_mode = "peripheral"; +}; + +&usb_hsphy { + status = "okay"; + vdda-pll-supply = <&vreg_l4b_0p88>; + vdda33-supply = <&vreg_l10b_3p08>; + vdda18-supply = <&vreg_l5b_1p8>; +}; + +&usb_qmpphy { + status = "okay"; + vdda-phy-supply = <&vreg_l4b_0p88>; + vdda-pll-supply = <&vreg_l1b_1p2>; +}; diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi index df6f9d6288fe..8daefd50217a 100644 --- a/arch/arm/boot/dts/qcom-sdx65.dtsi +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi @@ -37,6 +37,12 @@ clock-output-names = "sleep_clk"; #clock-cells = <0>; }; + + nand_clk_dummy: nand-clk-dummy { + compatible = "fixed-clock"; + clock-frequency = <32764>; + #clock-cells = <0>; + }; }; cpus { @@ -48,9 +54,50 @@ compatible = "arm,cortex-a7"; reg = <0x0>; enable-method = "psci"; + clocks = <&apcs>; + power-domains = <&rpmhpd SDX65_CX_AO>; + power-domain-names = "rpmhpd"; + operating-points-v2 = <&cpu_opp_table>; }; }; + cpu_opp_table: cpu-opp-table { + compatible = "operating-points-v2"; + opp-shared; + + opp-345600000 { + opp-hz = /bits/ 64 <345600000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-576000000 { + opp-hz = /bits/ 64 <576000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-1094400000 { + opp-hz = /bits/ 64 <1094400000>; + required-opps = <&rpmhpd_opp_nom>; + }; + + opp-1497600000 { + opp-hz = /bits/ 64 <1497600000>; + required-opps = <&rpmhpd_opp_turbo>; + }; + }; + + firmware { + scm { + compatible = "qcom,scm-sdx65", "qcom,scm"; + }; + }; + + mc_virt: interconnect-mc-virt { + compatible = "qcom,sdx65-mc-virt"; + #interconnect-cells = <1>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + psci { compatible = "arm,psci-1.0"; method = "smc"; @@ -87,8 +134,10 @@ }; smem_mem: memory@8fe20000 { - no-map; + compatible = "qcom,smem"; reg = <0x8fe20000 0xc0000>; + hwlocks = <&tcsr_mutex 3>; + no-map; }; cmd_db: reserved-memory@8fee0000 { @@ -113,6 +162,37 @@ }; }; + smp2p-mpss { + compatible = "qcom,smp2p"; + qcom,smem = <435>, <428>; + interrupts = <GIC_SPI 113 IRQ_TYPE_EDGE_RISING>; + mboxes = <&apcs 14>; + qcom,local-pid = <0>; + qcom,remote-pid = <1>; + + modem_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + modem_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + ipa_smp2p_out: ipa-ap-to-modem { + qcom,entry-name = "ipa"; + #qcom,smem-state-cells = <1>; + }; + + ipa_smp2p_in: ipa-modem-to-ap { + qcom,entry-name = "ipa"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + soc: soc { #address-cells = <1>; #size-cells = <1>; @@ -124,6 +204,7 @@ reg = <0x00100000 0x001f7400>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>; clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; + #power-domain-cells = <1>; #clock-cells = <1>; #reset-cells = <1>; }; @@ -137,13 +218,120 @@ status = "disabled"; }; + usb_hsphy: phy@ff4000 { + compatible = "qcom,usb-snps-hs-7nm-phy"; + reg = <0xff4000 0x120>; + #phy-cells = <0>; + status = "disabled"; + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "ref"; + resets = <&gcc GCC_QUSB2PHY_BCR>; + }; + + usb_qmpphy: phy@ff6000 { + compatible = "qcom,sdx65-qmp-usb3-uni-phy"; + reg = <0x00ff6000 0x1c8>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + clocks = <&gcc GCC_USB3_PHY_AUX_CLK>, + <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, + <&gcc GCC_USB3_PRIM_CLKREF_EN>; + clock-names = "aux", "cfg_ahb", "ref"; + + resets = <&gcc GCC_USB3PHY_PHY_BCR>, + <&gcc GCC_USB3_PHY_BCR>; + reset-names = "phy", "common"; + + usb_ssphy: phy@ff6200 { + reg = <0x00ff6e00 0x160>, + <0x00ff7000 0x1ec>, + <0x00ff6200 0x1e00>; + #phy-cells = <0>; + #clock-cells = <0>; + clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>; + clock-names = "pipe0"; + clock-output-names = "usb3_uni_phy_pipe_clk_src"; + }; + }; + + system_noc: interconnect@1620000 { + compatible = "qcom,sdx65-system-noc"; + reg = <0x01620000 0x31200>; + #interconnect-cells = <1>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + qpic_bam: dma-controller@1b04000 { + compatible = "qcom,bam-v1.7.0"; + reg = <0x01b04000 0x1c000>; + interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rpmhcc RPMH_QPIC_CLK>; + clock-names = "bam_clk"; + #dma-cells = <1>; + qcom,ee = <0>; + qcom,controlled-remotely; + status = "disabled"; + }; + + qpic_nand: nand-controller@1b30000 { + compatible = "qcom,sdx55-nand"; + reg = <0x01b30000 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&rpmhcc RPMH_QPIC_CLK>, + <&nand_clk_dummy>; + clock-names = "core", "aon"; + + dmas = <&qpic_bam 0>, + <&qpic_bam 1>, + <&qpic_bam 2>; + dma-names = "tx", "rx", "cmd"; + status = "disabled"; + }; + tcsr_mutex: hwlock@1f40000 { compatible = "qcom,tcsr-mutex"; reg = <0x01f40000 0x40000>; #hwlock-cells = <1>; }; - sdhc_1: sdhci@8804000 { + remoteproc_mpss: remoteproc@4080000 { + compatible = "qcom,sdx55-mpss-pas"; + reg = <0x04080000 0x4040>; + + interrupts-extended = <&intc GIC_SPI 250 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", "handover", + "stop-ack", "shutdown-ack"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + power-domains = <&rpmhpd SDX65_CX>, + <&rpmhpd SDX65_MSS>; + power-domain-names = "cx", "mss"; + + qcom,smem-states = <&modem_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + glink-edge { + interrupts = <GIC_SPI 114 IRQ_TYPE_EDGE_RISING>; + label = "mpss"; + qcom,remote-pid = <1>; + mboxes = <&apcs 15>; + }; + }; + + sdhc_1: mmc@8804000 { compatible = "qcom,sdx65-sdhci", "qcom,sdhci-msm-v5"; reg = <0x08804000 0x1000>; reg-names = "hc_mem"; @@ -156,6 +344,63 @@ status = "disabled"; }; + mem_noc: interconnect@9680000 { + compatible = "qcom,sdx65-mem-noc"; + reg = <0x09680000 0x27200>; + #interconnect-cells = <1>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + usb: usb@a6f8800 { + compatible = "qcom,sdx65-dwc3", "qcom,dwc3"; + reg = <0x0a6f8800 0x400>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + clocks = <&gcc GCC_USB30_SLV_AHB_CLK>, + <&gcc GCC_USB30_MASTER_CLK>, + <&gcc GCC_USB30_MSTR_AXI_CLK>, + <&gcc GCC_USB30_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_SLEEP_CLK>; + clock-names = "cfg_noc", "core", "iface", "mock_utmi", + "sleep"; + + assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_MASTER_CLK>; + assigned-clock-rates = <19200000>, <200000000>; + + interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 76 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 18 IRQ_TYPE_EDGE_BOTH>, + <&pdc 19 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "hs_phy_irq", + "ss_phy_irq", + "dm_hs_phy_irq", + "dp_hs_phy_irq"; + + power-domains = <&gcc USB30_GDSC>; + + resets = <&gcc GCC_USB30_BCR>; + + usb_dwc3: usb@a600000 { + compatible = "snps,dwc3"; + reg = <0x0a600000 0xcd00>; + interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; + iommus = <&apps_smmu 0x1a0 0x0>; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + phys = <&usb_hsphy>, <&usb_ssphy>; + phy-names = "usb2-phy", "usb3-phy"; + }; + }; + + restart@c264000 { + compatible = "qcom,pshold"; + reg = <0x0c264000 0x1000>; + }; + spmi_bus: qcom,spmi@c440000 { compatible = "qcom,spmi-pmic-arb"; reg = <0xc440000 0xd00>, @@ -196,6 +441,19 @@ interrupt-controller; }; + imem@1468f000 { + compatible = "simple-mfd"; + reg = <0x1468f000 0x1000>; + ranges = <0x0 0x1468f000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + pil-reloc@94c { + compatible = "qcom,pil-reloc-info"; + reg = <0x94c 0xc8>; + }; + }; + apps_smmu: iommu@15000000 { compatible = "qcom,sdx65-smmu-500", "arm,mmu-500"; reg = <0x15000000 0x40000>; @@ -262,6 +520,12 @@ #clock-cells = <0>; }; + watchdog@17817000 { + compatible = "qcom,apss-wdt-sdx65", "qcom,kpss-wdt"; + reg = <0x17817000 0x1000>; + clocks = <&sleep_clk>; + }; + timer@17820000 { #address-cells = <1>; #size-cells = <1>; @@ -399,6 +663,11 @@ }; }; }; + + apps_bcm_voter: bcm-voter { + compatible = "qcom,bcm-voter"; + }; + }; }; diff --git a/arch/arm/boot/dts/r7s9210-rza2mevb.dts b/arch/arm/boot/dts/r7s9210-rza2mevb.dts index 9c0d9686fe01..69a5a44b8a2f 100644 --- a/arch/arm/boot/dts/r7s9210-rza2mevb.dts +++ b/arch/arm/boot/dts/r7s9210-rza2mevb.dts @@ -71,10 +71,10 @@ leds { compatible = "gpio-leds"; - red { + led-red { gpios = <&pinctrl RZA2_PIN(PORT6, 0) GPIO_ACTIVE_HIGH>; }; - green { + led-green { gpios = <&pinctrl RZA2_PIN(PORTC, 1) GPIO_ACTIVE_HIGH>; }; }; diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts index 57cd2fa72249..5ad5349a50dc 100644 --- a/arch/arm/boot/dts/r8a7790-lager.dts +++ b/arch/arm/boot/dts/r8a7790-lager.dts @@ -442,7 +442,7 @@ compatible = "dlg,da9063-rtc"; }; - wdt { + watchdog { compatible = "dlg,da9063-watchdog"; }; }; diff --git a/arch/arm/boot/dts/r8a7790-stout.dts b/arch/arm/boot/dts/r8a7790-stout.dts index c802f9f13c18..fe14727eefe1 100644 --- a/arch/arm/boot/dts/r8a7790-stout.dts +++ b/arch/arm/boot/dts/r8a7790-stout.dts @@ -341,7 +341,7 @@ compatible = "dlg,da9063-rtc"; }; - wdt { + watchdog { compatible = "dlg,da9063-watchdog"; }; }; diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts index 6e691b6cac05..26a40782cc89 100644 --- a/arch/arm/boot/dts/r8a7791-koelsch.dts +++ b/arch/arm/boot/dts/r8a7791-koelsch.dts @@ -805,7 +805,7 @@ compatible = "dlg,da9063-rtc"; }; - wdt { + watchdog { compatible = "dlg,da9063-watchdog"; }; }; diff --git a/arch/arm/boot/dts/r8a7791-porter.dts b/arch/arm/boot/dts/r8a7791-porter.dts index 38e2ab928707..ec0a20d5130d 100644 --- a/arch/arm/boot/dts/r8a7791-porter.dts +++ b/arch/arm/boot/dts/r8a7791-porter.dts @@ -390,7 +390,7 @@ interrupts = <2 IRQ_TYPE_LEVEL_LOW>; interrupt-controller; - wdt { + watchdog { compatible = "dlg,da9063-watchdog"; }; }; diff --git a/arch/arm/boot/dts/r8a7792-blanche.dts b/arch/arm/boot/dts/r8a7792-blanche.dts index 62aa9f61321b..c66de9dd12df 100644 --- a/arch/arm/boot/dts/r8a7792-blanche.dts +++ b/arch/arm/boot/dts/r8a7792-blanche.dts @@ -335,7 +335,7 @@ compatible = "dlg,da9063-rtc"; }; - wdt { + watchdog { compatible = "dlg,da9063-watchdog"; }; }; diff --git a/arch/arm/boot/dts/r8a7793-gose.dts b/arch/arm/boot/dts/r8a7793-gose.dts index c8978f4f62e9..79b537b24642 100644 --- a/arch/arm/boot/dts/r8a7793-gose.dts +++ b/arch/arm/boot/dts/r8a7793-gose.dts @@ -740,7 +740,7 @@ compatible = "dlg,da9063-rtc"; }; - wdt { + watchdog { compatible = "dlg,da9063-watchdog"; }; }; diff --git a/arch/arm/boot/dts/r8a7794-alt.dts b/arch/arm/boot/dts/r8a7794-alt.dts index 99d554fe3329..4d93319674c6 100644 --- a/arch/arm/boot/dts/r8a7794-alt.dts +++ b/arch/arm/boot/dts/r8a7794-alt.dts @@ -463,7 +463,7 @@ compatible = "dlg,da9063-rtc"; }; - wdt { + watchdog { compatible = "dlg,da9063-watchdog"; }; }; diff --git a/arch/arm/boot/dts/r8a7794-silk.dts b/arch/arm/boot/dts/r8a7794-silk.dts index 92a76164432a..b7af1befa126 100644 --- a/arch/arm/boot/dts/r8a7794-silk.dts +++ b/arch/arm/boot/dts/r8a7794-silk.dts @@ -433,7 +433,7 @@ compatible = "dlg,da9063-rtc"; }; - wdt { + watchdog { compatible = "dlg,da9063-watchdog"; }; }; diff --git a/arch/arm/boot/dts/r8a77xx-aa104xd12-panel.dtsi b/arch/arm/boot/dts/r8a77xx-aa104xd12-panel.dtsi deleted file mode 100644 index 79fce67ebb1c..000000000000 --- a/arch/arm/boot/dts/r8a77xx-aa104xd12-panel.dtsi +++ /dev/null @@ -1,39 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Common file for the AA104XD12 panel connected to Renesas R-Car boards - * - * Copyright (C) 2014 Renesas Electronics Corp. - */ - -/ { - panel { - compatible = "mitsubishi,aa104xd12", "panel-lvds"; - - width-mm = <210>; - height-mm = <158>; - data-mapping = "jeida-18"; - - panel-timing { - /* 1024x768 @65Hz */ - clock-frequency = <65000000>; - hactive = <1024>; - vactive = <768>; - hsync-len = <136>; - hfront-porch = <20>; - hback-porch = <160>; - vfront-porch = <3>; - vback-porch = <29>; - vsync-len = <6>; - }; - - port { - panel_in: endpoint { - remote-endpoint = <&lvds_connector>; - }; - }; - }; -}; - -&lvds_connector { - remote-endpoint = <&panel_in>; -}; diff --git a/arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts b/arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts index 3f8f3ce87e12..4bf813335e21 100644 --- a/arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts +++ b/arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts @@ -8,6 +8,9 @@ /dts-v1/; +#include <dt-bindings/pinctrl/rzn1-pinctrl.h> +#include <dt-bindings/net/pcs-rzn1-miic.h> + #include "r9a06g032.dtsi" / { @@ -23,6 +26,122 @@ }; }; +ð_miic { + status = "okay"; + renesas,miic-switch-portin = <MIIC_GMAC2_PORT>; +}; + +&gmac2 { + status = "okay"; + phy-mode = "gmii"; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&mii_conv4 { + renesas,miic-input = <MIIC_SWITCH_PORTB>; + status = "okay"; +}; + +&mii_conv5 { + renesas,miic-input = <MIIC_SWITCH_PORTA>; + status = "okay"; +}; + +&pinctrl{ + pins_eth3: pins_eth3 { + pinmux = <RZN1_PINMUX(36, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>, + <RZN1_PINMUX(37, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>, + <RZN1_PINMUX(38, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>, + <RZN1_PINMUX(39, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>, + <RZN1_PINMUX(40, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>, + <RZN1_PINMUX(41, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>, + <RZN1_PINMUX(42, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>, + <RZN1_PINMUX(43, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>, + <RZN1_PINMUX(44, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>, + <RZN1_PINMUX(45, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>, + <RZN1_PINMUX(46, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>, + <RZN1_PINMUX(47, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>; + drive-strength = <6>; + bias-disable; + }; + + pins_eth4: pins_eth4 { + pinmux = <RZN1_PINMUX(48, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>, + <RZN1_PINMUX(49, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>, + <RZN1_PINMUX(50, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>, + <RZN1_PINMUX(51, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>, + <RZN1_PINMUX(52, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>, + <RZN1_PINMUX(53, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>, + <RZN1_PINMUX(54, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>, + <RZN1_PINMUX(55, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>, + <RZN1_PINMUX(56, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>, + <RZN1_PINMUX(57, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>, + <RZN1_PINMUX(58, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>, + <RZN1_PINMUX(59, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>; + drive-strength = <6>; + bias-disable; + }; + + pins_mdio1: pins_mdio1 { + pinmux = <RZN1_PINMUX(152, RZN1_FUNC_MDIO1_SWITCH)>, + <RZN1_PINMUX(153, RZN1_FUNC_MDIO1_SWITCH)>; + }; +}; + +&rtc0 { + status = "okay"; +}; + +&switch { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + pinctrl-names = "default"; + pinctrl-0 = <&pins_eth3>, <&pins_eth4>, <&pins_mdio1>; + + dsa,member = <0 0>; + + mdio { + clock-frequency = <2500000>; + + #address-cells = <1>; + #size-cells = <0>; + + switch0phy4: ethernet-phy@4 { + reg = <4>; + micrel,led-mode = <1>; + }; + + switch0phy5: ethernet-phy@5 { + reg = <5>; + micrel,led-mode = <1>; + }; + }; +}; + +&switch_port0 { + label = "lan0"; + phy-mode = "mii"; + phy-handle = <&switch0phy5>; + status = "okay"; +}; + +&switch_port1 { + label = "lan1"; + phy-mode = "mii"; + phy-handle = <&switch0phy4>; + status = "okay"; +}; + +&switch_port4 { + status = "okay"; +}; + &uart0 { status = "okay"; }; diff --git a/arch/arm/boot/dts/r9a06g032.dtsi b/arch/arm/boot/dts/r9a06g032.dtsi index d3665910958b..5b97fa85474f 100644 --- a/arch/arm/boot/dts/r9a06g032.dtsi +++ b/arch/arm/boot/dts/r9a06g032.dtsi @@ -304,6 +304,114 @@ data-width = <8>; }; + gmac2: ethernet@44002000 { + compatible = "renesas,r9a06g032-gmac", "renesas,rzn1-gmac", "snps,dwmac"; + reg = <0x44002000 0x2000>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq", "eth_wake_irq", "eth_lpi"; + clocks = <&sysctrl R9A06G032_HCLK_GMAC1>; + clock-names = "stmmaceth"; + power-domains = <&sysctrl>; + snps,multicast-filter-bins = <256>; + snps,perfect-filter-entries = <128>; + tx-fifo-depth = <2048>; + rx-fifo-depth = <4096>; + status = "disabled"; + }; + + eth_miic: eth-miic@44030000 { + compatible = "renesas,r9a06g032-miic", "renesas,rzn1-miic"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x44030000 0x10000>; + clocks = <&sysctrl R9A06G032_CLK_MII_REF>, + <&sysctrl R9A06G032_CLK_RGMII_REF>, + <&sysctrl R9A06G032_CLK_RMII_REF>, + <&sysctrl R9A06G032_HCLK_SWITCH_RG>; + clock-names = "mii_ref", "rgmii_ref", "rmii_ref", "hclk"; + power-domains = <&sysctrl>; + status = "disabled"; + + mii_conv1: mii-conv@1 { + reg = <1>; + status = "disabled"; + }; + + mii_conv2: mii-conv@2 { + reg = <2>; + status = "disabled"; + }; + + mii_conv3: mii-conv@3 { + reg = <3>; + status = "disabled"; + }; + + mii_conv4: mii-conv@4 { + reg = <4>; + status = "disabled"; + }; + + mii_conv5: mii-conv@5 { + reg = <5>; + status = "disabled"; + }; + }; + + switch: switch@44050000 { + compatible = "renesas,r9a06g032-a5psw", "renesas,rzn1-a5psw"; + reg = <0x44050000 0x10000>; + clocks = <&sysctrl R9A06G032_HCLK_SWITCH>, + <&sysctrl R9A06G032_CLK_SWITCH>; + clock-names = "hclk", "clk"; + power-domains = <&sysctrl>; + status = "disabled"; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + + switch_port0: port@0 { + reg = <0>; + pcs-handle = <&mii_conv5>; + status = "disabled"; + }; + + switch_port1: port@1 { + reg = <1>; + pcs-handle = <&mii_conv4>; + status = "disabled"; + }; + + switch_port2: port@2 { + reg = <2>; + pcs-handle = <&mii_conv3>; + status = "disabled"; + }; + + switch_port3: port@3 { + reg = <3>; + pcs-handle = <&mii_conv2>; + status = "disabled"; + }; + + switch_port4: port@4 { + reg = <4>; + ethernet = <&gmac2>; + label = "cpu"; + phy-mode = "internal"; + status = "disabled"; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; + }; + gic: interrupt-controller@44101000 { compatible = "arm,gic-400", "arm,cortex-a7-gic"; interrupt-controller; diff --git a/arch/arm/boot/dts/rk3066a-bqcurie2.dts b/arch/arm/boot/dts/rk3066a-bqcurie2.dts index 390aa33cd55a..962b4d1291db 100644 --- a/arch/arm/boot/dts/rk3066a-bqcurie2.dts +++ b/arch/arm/boot/dts/rk3066a-bqcurie2.dts @@ -48,7 +48,7 @@ compatible = "gpio-keys"; autorepeat; - power { + key-power { gpios = <&gpio6 RK_PA2 GPIO_ACTIVE_LOW>; /* GPIO6_A2 */ linux,code = <KEY_POWER>; label = "GPIO Key Power"; @@ -56,7 +56,7 @@ wakeup-source; debounce-interval = <100>; }; - volume-down { + key-volume-down { gpios = <&gpio4 RK_PC5 GPIO_ACTIVE_LOW>; /* GPIO4_C5 */ linux,code = <KEY_VOLUMEDOWN>; label = "GPIO Key Vol-"; diff --git a/arch/arm/boot/dts/rk3066a-mk808.dts b/arch/arm/boot/dts/rk3066a-mk808.dts index 667d57a4ff45..cfa318a506eb 100644 --- a/arch/arm/boot/dts/rk3066a-mk808.dts +++ b/arch/arm/boot/dts/rk3066a-mk808.dts @@ -160,6 +160,24 @@ status = "okay"; }; +&nfc { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + nand@0 { + reg = <0>; + label = "rk-nand"; + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + nand-ecc-step-size = <1024>; + nand-ecc-strength = <40>; + nand-is-boot-medium; + rockchip,boot-blks = <8>; + rockchip,boot-ecc-strength = <24>; + }; +}; + &pinctrl { usb-host { host_drv: host-drv { diff --git a/arch/arm/boot/dts/rk3066a-rayeager.dts b/arch/arm/boot/dts/rk3066a-rayeager.dts index 12b2e59aebc4..dbbc5170094e 100644 --- a/arch/arm/boot/dts/rk3066a-rayeager.dts +++ b/arch/arm/boot/dts/rk3066a-rayeager.dts @@ -32,7 +32,7 @@ keys: gpio-keys { compatible = "gpio-keys"; - power { + key-power { wakeup-source; gpios = <&gpio6 RK_PA2 GPIO_ACTIVE_LOW>; label = "GPIO Power"; diff --git a/arch/arm/boot/dts/rk3188-bqedison2qc.dts b/arch/arm/boot/dts/rk3188-bqedison2qc.dts index 35b7a5798eee..9312be362a7a 100644 --- a/arch/arm/boot/dts/rk3188-bqedison2qc.dts +++ b/arch/arm/boot/dts/rk3188-bqedison2qc.dts @@ -37,7 +37,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pwr_key &usb_int>; - power { + key-power { gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; linux,code = <KEY_POWER>; label = "GPIO Key Power"; @@ -46,7 +46,7 @@ wakeup-source; }; - wake_on_usb: wake-on-usb { + wake_on_usb: key-wake-on-usb { label = "Wake-on-USB"; gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; linux,code = <KEY_WAKEUP>; diff --git a/arch/arm/boot/dts/rk3188-px3-evb.dts b/arch/arm/boot/dts/rk3188-px3-evb.dts index fc478ac4e781..0a1ae689b162 100644 --- a/arch/arm/boot/dts/rk3188-px3-evb.dts +++ b/arch/arm/boot/dts/rk3188-px3-evb.dts @@ -29,7 +29,7 @@ compatible = "gpio-keys"; autorepeat; - power { + key-power { gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; linux,code = <KEY_POWER>; label = "GPIO Key Power"; diff --git a/arch/arm/boot/dts/rk3188-radxarock.dts b/arch/arm/boot/dts/rk3188-radxarock.dts index 36c0945f43b2..a9ed3cd2c2da 100644 --- a/arch/arm/boot/dts/rk3188-radxarock.dts +++ b/arch/arm/boot/dts/rk3188-radxarock.dts @@ -24,7 +24,7 @@ compatible = "gpio-keys"; autorepeat; - power { + key-power { gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; linux,code = <KEY_POWER>; label = "GPIO Key Power"; diff --git a/arch/arm/boot/dts/rk3229-evb.dts b/arch/arm/boot/dts/rk3229-evb.dts index 797476e8bef1..5c3d08e3eea3 100644 --- a/arch/arm/boot/dts/rk3229-evb.dts +++ b/arch/arm/boot/dts/rk3229-evb.dts @@ -107,7 +107,7 @@ regulator-boot-on; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; autorepeat; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/rk3288-evb.dtsi b/arch/arm/boot/dts/rk3288-evb.dtsi index c4ca73b40d4a..399d6b9c5fd4 100644 --- a/arch/arm/boot/dts/rk3288-evb.dtsi +++ b/arch/arm/boot/dts/rk3288-evb.dtsi @@ -118,7 +118,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pwrbtn>; - power { + key-power { gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; linux,code = <KEY_POWER>; label = "GPIO Key Power"; diff --git a/arch/arm/boot/dts/rk3288-firefly-reload.dts b/arch/arm/boot/dts/rk3288-firefly-reload.dts index 9a4a9749c405..a5a0826341e6 100644 --- a/arch/arm/boot/dts/rk3288-firefly-reload.dts +++ b/arch/arm/boot/dts/rk3288-firefly-reload.dts @@ -27,7 +27,7 @@ gpio-keys { compatible = "gpio-keys"; - power { + key-power { wakeup-source; gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; label = "GPIO Power"; diff --git a/arch/arm/boot/dts/rk3288-firefly.dtsi b/arch/arm/boot/dts/rk3288-firefly.dtsi index 7fb582302b32..052afe5543e2 100644 --- a/arch/arm/boot/dts/rk3288-firefly.dtsi +++ b/arch/arm/boot/dts/rk3288-firefly.dtsi @@ -49,7 +49,7 @@ keys: gpio-keys { compatible = "gpio-keys"; - power { + key-power { wakeup-source; gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; label = "GPIO Power"; diff --git a/arch/arm/boot/dts/rk3288-phycore-rdk.dts b/arch/arm/boot/dts/rk3288-phycore-rdk.dts index 1e33859de484..1a5156951492 100644 --- a/arch/arm/boot/dts/rk3288-phycore-rdk.dts +++ b/arch/arm/boot/dts/rk3288-phycore-rdk.dts @@ -20,14 +20,14 @@ pinctrl-names = "default"; pinctrl-0 = <&user_button_pins>; - button@0 { + button-0 { label = "home"; linux,code = <KEY_HOME>; gpios = <&gpio8 0 GPIO_ACTIVE_HIGH>; wakeup-source; }; - button@1 { + button-1 { label = "menu"; linux,code = <KEY_MENU>; gpios = <&gpio8 3 GPIO_ACTIVE_HIGH>; diff --git a/arch/arm/boot/dts/rk3288-popmetal.dts b/arch/arm/boot/dts/rk3288-popmetal.dts index 8c7376d64bc4..fd90f3b8fc32 100644 --- a/arch/arm/boot/dts/rk3288-popmetal.dts +++ b/arch/arm/boot/dts/rk3288-popmetal.dts @@ -30,7 +30,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pwrbtn>; - power { + key-power { gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; linux,code = <KEY_POWER>; label = "GPIO Key Power"; diff --git a/arch/arm/boot/dts/rk3288-r89.dts b/arch/arm/boot/dts/rk3288-r89.dts index 55467bc30fa6..633e5a032463 100644 --- a/arch/arm/boot/dts/rk3288-r89.dts +++ b/arch/arm/boot/dts/rk3288-r89.dts @@ -31,7 +31,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pwrbtn>; - power { + key-power { gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; linux,code = <KEY_POWER>; label = "GPIO Key Power"; diff --git a/arch/arm/boot/dts/rk3288-rock2-square.dts b/arch/arm/boot/dts/rk3288-rock2-square.dts index c4d1d142d8c6..80e0f07c8e87 100644 --- a/arch/arm/boot/dts/rk3288-rock2-square.dts +++ b/arch/arm/boot/dts/rk3288-rock2-square.dts @@ -28,7 +28,7 @@ gpio-keys { compatible = "gpio-keys"; - power { + key-power { gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; label = "GPIO Power"; linux,code = <KEY_POWER>; diff --git a/arch/arm/boot/dts/rk3288-tinker.dtsi b/arch/arm/boot/dts/rk3288-tinker.dtsi index 9c1e38c54eae..09618bb7d872 100644 --- a/arch/arm/boot/dts/rk3288-tinker.dtsi +++ b/arch/arm/boot/dts/rk3288-tinker.dtsi @@ -26,14 +26,12 @@ gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; autorepeat; pinctrl-names = "default"; pinctrl-0 = <&pwrbtn>; - button@0 { + button { gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; linux,code = <KEY_POWER>; label = "GPIO Key Power"; diff --git a/arch/arm/boot/dts/rk3288-veyron-broadcom-bluetooth.dtsi b/arch/arm/boot/dts/rk3288-veyron-broadcom-bluetooth.dtsi index a10d25ac8f7b..f9dde0eef527 100644 --- a/arch/arm/boot/dts/rk3288-veyron-broadcom-bluetooth.dtsi +++ b/arch/arm/boot/dts/rk3288-veyron-broadcom-bluetooth.dtsi @@ -13,10 +13,10 @@ <&bt_dev_wake>; compatible = "brcm,bcm43540-bt"; - host-wakeup-gpios = <&gpio4 RK_PD7 GPIO_ACTIVE_HIGH>; - shutdown-gpios = <&gpio4 RK_PD5 GPIO_ACTIVE_HIGH>; - device-wakeup-gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>; - max-speed = <3000000>; - brcm,bt-pcm-int-params = [01 02 00 01 01]; + host-wakeup-gpios = <&gpio4 RK_PD7 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio4 RK_PD5 GPIO_ACTIVE_HIGH>; + device-wakeup-gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>; + max-speed = <3000000>; + brcm,bt-pcm-int-params = [01 02 00 01 01]; }; }; diff --git a/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi b/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi index 05112c25176d..700bb548d6b2 100644 --- a/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi +++ b/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi @@ -32,7 +32,7 @@ pinctrl-names = "default"; pinctrl-0 = <&ap_lid_int_l>; - lid { + switch-lid { label = "Lid"; gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>; wakeup-source; diff --git a/arch/arm/boot/dts/rk3288-veyron-minnie.dts b/arch/arm/boot/dts/rk3288-veyron-minnie.dts index 82fc6fba9999..dcdcc55c4098 100644 --- a/arch/arm/boot/dts/rk3288-veyron-minnie.dts +++ b/arch/arm/boot/dts/rk3288-veyron-minnie.dts @@ -21,14 +21,14 @@ pinctrl-names = "default"; pinctrl-0 = <&volum_down_l &volum_up_l>; - volum_down { + key-volum-down { label = "Volum_down"; gpios = <&gpio5 RK_PB3 GPIO_ACTIVE_LOW>; linux,code = <KEY_VOLUMEDOWN>; debounce-interval = <100>; }; - volum_up { + key-volum-up { label = "Volum_up"; gpios = <&gpio5 RK_PB2 GPIO_ACTIVE_LOW>; linux,code = <KEY_VOLUMEUP>; diff --git a/arch/arm/boot/dts/rk3288-veyron-pinky.dts b/arch/arm/boot/dts/rk3288-veyron-pinky.dts index 4e9fdb0f722d..e2a4e6232eb5 100644 --- a/arch/arm/boot/dts/rk3288-veyron-pinky.dts +++ b/arch/arm/boot/dts/rk3288-veyron-pinky.dts @@ -45,7 +45,7 @@ &lid_switch { pinctrl-0 = <&pwr_key_h &ap_lid_int_l>; - power { + key-power { gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; }; }; diff --git a/arch/arm/boot/dts/rk3288-veyron.dtsi b/arch/arm/boot/dts/rk3288-veyron.dtsi index 54a6838d73f5..e406c8c7c7e5 100644 --- a/arch/arm/boot/dts/rk3288-veyron.dtsi +++ b/arch/arm/boot/dts/rk3288-veyron.dtsi @@ -29,7 +29,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pwr_key_l>; - power { + key-power { label = "Power"; gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; linux,code = <KEY_POWER>; diff --git a/arch/arm/boot/dts/rv1108-elgin-r1.dts b/arch/arm/boot/dts/rv1108-elgin-r1.dts index 0c99a5934ebf..2d9994379eb2 100644 --- a/arch/arm/boot/dts/rv1108-elgin-r1.dts +++ b/arch/arm/boot/dts/rv1108-elgin-r1.dts @@ -83,7 +83,7 @@ regulators { vdd_core: DCDC_REG1 { - regulator-name= "vdd_core"; + regulator-name = "vdd_core"; regulator-min-microvolt = <700000>; regulator-max-microvolt = <1500000>; regulator-always-on; @@ -95,7 +95,7 @@ }; vdd_buck2: DCDC_REG2 { - regulator-name= "vdd_buck2"; + regulator-name = "vdd_buck2"; regulator-min-microvolt = <2200000>; regulator-max-microvolt = <2200000>; regulator-always-on; @@ -106,7 +106,7 @@ }; vcc_ddr: DCDC_REG3 { - regulator-name= "vcc_ddr"; + regulator-name = "vcc_ddr"; regulator-always-on; regulator-boot-on; regulator-state-mem { @@ -115,7 +115,7 @@ }; vcc_io: DCDC_REG4 { - regulator-name= "vcc_io"; + regulator-name = "vcc_io"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; @@ -127,7 +127,7 @@ }; vdd_10: LDO_REG1 { - regulator-name= "vdd_10"; + regulator-name = "vdd_10"; regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; regulator-always-on; @@ -138,7 +138,7 @@ }; vcc_18: LDO_REG2 { - regulator-name= "vcc_18"; + regulator-name = "vcc_18"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-always-on; @@ -149,7 +149,7 @@ }; vdd10_pmu: LDO_REG3 { - regulator-name= "vdd10_pmu"; + regulator-name = "vdd10_pmu"; regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; regulator-always-on; diff --git a/arch/arm/boot/dts/rv1108-evb.dts b/arch/arm/boot/dts/rv1108-evb.dts index 46cad7cb94bf..ef150f4ee99d 100644 --- a/arch/arm/boot/dts/rv1108-evb.dts +++ b/arch/arm/boot/dts/rv1108-evb.dts @@ -96,7 +96,7 @@ regulators { vdd_core: DCDC_REG1 { - regulator-name= "vdd_core"; + regulator-name = "vdd_core"; regulator-min-microvolt = <700000>; regulator-max-microvolt = <1500000>; regulator-always-on; @@ -108,7 +108,7 @@ }; vdd_cam: DCDC_REG2 { - regulator-name= "vdd_cam"; + regulator-name = "vdd_cam"; regulator-min-microvolt = <700000>; regulator-max-microvolt = <2000000>; regulator-state-mem { @@ -117,7 +117,7 @@ }; vcc_ddr: DCDC_REG3 { - regulator-name= "vcc_ddr"; + regulator-name = "vcc_ddr"; regulator-always-on; regulator-boot-on; regulator-state-mem { @@ -126,7 +126,7 @@ }; vcc_io: DCDC_REG4 { - regulator-name= "vcc_io"; + regulator-name = "vcc_io"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; @@ -138,7 +138,7 @@ }; vdd_10: LDO_REG1 { - regulator-name= "vdd_10"; + regulator-name = "vdd_10"; regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; regulator-always-on; @@ -149,7 +149,7 @@ }; vcc_18: LDO_REG2 { - regulator-name= "vcc_18"; + regulator-name = "vcc_18"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-always-on; @@ -160,7 +160,7 @@ }; vdd10_pmu: LDO_REG3 { - regulator-name= "vdd10_pmu"; + regulator-name = "vdd10_pmu"; regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; regulator-always-on; diff --git a/arch/arm/boot/dts/rv1108.dtsi b/arch/arm/boot/dts/rv1108.dtsi index c158a7ea86ec..abf3006f0a84 100644 --- a/arch/arm/boot/dts/rv1108.dtsi +++ b/arch/arm/boot/dts/rv1108.dtsi @@ -748,7 +748,7 @@ gmac { rmii_pins: rmii-pins { - rockchip,pins = <1 RK_PC5 2 &pcfg_pull_none>, + rockchip,pins = <1 RK_PC5 2 &pcfg_pull_none>, <1 RK_PC3 2 &pcfg_pull_none>, <1 RK_PC4 2 &pcfg_pull_none>, <1 RK_PB2 3 &pcfg_pull_none_drv_12ma>, diff --git a/arch/arm/boot/dts/s3c2410-pinctrl.h b/arch/arm/boot/dts/s3c2410-pinctrl.h new file mode 100644 index 000000000000..76b6171ae149 --- /dev/null +++ b/arch/arm/boot/dts/s3c2410-pinctrl.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Samsung S3C2410 DTS pinctrl constants + * + * Copyright (c) 2016 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * Copyright (c) 2022 Linaro Ltd + * Author: Krzysztof Kozlowski <krzk@kernel.org> + */ + +#ifndef __DTS_ARM_SAMSUNG_S3C2410_PINCTRL_H__ +#define __DTS_ARM_SAMSUNG_S3C2410_PINCTRL_H__ + +#define S3C2410_PIN_FUNC_INPUT 0 +#define S3C2410_PIN_FUNC_OUTPUT 1 +#define S3C2410_PIN_FUNC_2 2 +#define S3C2410_PIN_FUNC_3 3 + +#endif /* __DTS_ARM_SAMSUNG_S3C2410_PINCTRL_H__ */ diff --git a/arch/arm/boot/dts/s3c2416-pinctrl.dtsi b/arch/arm/boot/dts/s3c2416-pinctrl.dtsi index 20a7d72827c2..3268366bd8bc 100644 --- a/arch/arm/boot/dts/s3c2416-pinctrl.dtsi +++ b/arch/arm/boot/dts/s3c2416-pinctrl.dtsi @@ -5,7 +5,7 @@ * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de> */ -#include <dt-bindings/pinctrl/samsung.h> +#include "s3c2410-pinctrl.h" &pinctrl_0 { /* @@ -82,91 +82,91 @@ uart0_data: uart0-data-pins { samsung,pins = "gph-0", "gph-1"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-function = <S3C2410_PIN_FUNC_2>; }; uart0_fctl: uart0-fctl-pins { samsung,pins = "gph-8", "gph-9"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-function = <S3C2410_PIN_FUNC_2>; }; uart1_data: uart1-data-pins { samsung,pins = "gph-2", "gph-3"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-function = <S3C2410_PIN_FUNC_2>; }; uart1_fctl: uart1-fctl-pins { samsung,pins = "gph-10", "gph-11"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-function = <S3C2410_PIN_FUNC_2>; }; uart2_data: uart2-data-pins { samsung,pins = "gph-4", "gph-5"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-function = <S3C2410_PIN_FUNC_2>; }; uart2_fctl: uart2-fctl-pins { samsung,pins = "gph-6", "gph-7"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-function = <S3C2410_PIN_FUNC_2>; }; uart3_data: uart3-data-pins { samsung,pins = "gph-6", "gph-7"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-function = <S3C2410_PIN_FUNC_2>; }; extuart_clk: extuart-clk-pins { samsung,pins = "gph-12"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-function = <S3C2410_PIN_FUNC_2>; }; i2c0_bus: i2c0-bus-pins { samsung,pins = "gpe-14", "gpe-15"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-function = <S3C2410_PIN_FUNC_2>; }; spi0_bus: spi0-bus-pins { samsung,pins = "gpe-11", "gpe-12", "gpe-13"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-function = <S3C2410_PIN_FUNC_2>; }; sd0_clk: sd0-clk-pins { samsung,pins = "gpe-5"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-function = <S3C2410_PIN_FUNC_2>; }; sd0_cmd: sd0-cmd-pins { samsung,pins = "gpe-6"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-function = <S3C2410_PIN_FUNC_2>; }; sd0_bus1: sd0-bus1-pins { samsung,pins = "gpe-7"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-function = <S3C2410_PIN_FUNC_2>; }; sd0_bus4: sd0-bus4-pins { samsung,pins = "gpe-8", "gpe-9", "gpe-10"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-function = <S3C2410_PIN_FUNC_2>; }; sd1_cmd: sd1-cmd-pins { samsung,pins = "gpl-8"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-function = <S3C2410_PIN_FUNC_2>; }; sd1_clk: sd1-clk-pins { samsung,pins = "gpl-9"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-function = <S3C2410_PIN_FUNC_2>; }; sd1_bus1: sd1-bus1-pins { samsung,pins = "gpl-0"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-function = <S3C2410_PIN_FUNC_2>; }; sd1_bus4: sd1-bus4-pins { samsung,pins = "gpl-1", "gpl-2", "gpl-3"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-function = <S3C2410_PIN_FUNC_2>; }; }; diff --git a/arch/arm/boot/dts/s3c2416.dtsi b/arch/arm/boot/dts/s3c2416.dtsi index 4f084f4fe44f..4660751cb207 100644 --- a/arch/arm/boot/dts/s3c2416.dtsi +++ b/arch/arm/boot/dts/s3c2416.dtsi @@ -45,7 +45,7 @@ status = "disabled"; }; - sdhci_1: sdhci@4ac00000 { + sdhci_1: mmc@4ac00000 { compatible = "samsung,s3c6410-sdhci"; reg = <0x4AC00000 0x100>; interrupts = <0 0 21 3>; @@ -56,7 +56,7 @@ status = "disabled"; }; - sdhci_0: sdhci@4a800000 { + sdhci_0: mmc@4a800000 { compatible = "samsung,s3c6410-sdhci"; reg = <0x4A800000 0x100>; interrupts = <0 0 20 3>; diff --git a/arch/arm/boot/dts/s3c64xx-pinctrl.dtsi b/arch/arm/boot/dts/s3c64xx-pinctrl.dtsi index 0a3186d57cb5..f53959b7d031 100644 --- a/arch/arm/boot/dts/s3c64xx-pinctrl.dtsi +++ b/arch/arm/boot/dts/s3c64xx-pinctrl.dtsi @@ -9,7 +9,7 @@ * listed as device tree nodes in this file. */ -#include <dt-bindings/pinctrl/samsung.h> +#include "s3c64xx-pinctrl.h" &pinctrl0 { /* @@ -133,219 +133,219 @@ uart0_data: uart0-data-pins { samsung,pins = "gpa-0", "gpa-1"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-function = <S3C64XX_PIN_FUNC_2>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; uart0_fctl: uart0-fctl-pins { samsung,pins = "gpa-2", "gpa-3"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-function = <S3C64XX_PIN_FUNC_2>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; uart1_data: uart1-data-pins { samsung,pins = "gpa-4", "gpa-5"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-function = <S3C64XX_PIN_FUNC_2>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; uart1_fctl: uart1-fctl-pins { samsung,pins = "gpa-6", "gpa-7"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-function = <S3C64XX_PIN_FUNC_2>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; uart2_data: uart2-data-pins { samsung,pins = "gpb-0", "gpb-1"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-function = <S3C64XX_PIN_FUNC_2>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; uart3_data: uart3-data-pins { samsung,pins = "gpb-2", "gpb-3"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-function = <S3C64XX_PIN_FUNC_2>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; ext_dma_0: ext-dma-0-pins { samsung,pins = "gpb-0", "gpb-1"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-function = <S3C64XX_PIN_FUNC_3>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; ext_dma_1: ext-dma-1-pins { samsung,pins = "gpb-2", "gpb-3"; - samsung,pin-function = <EXYNOS_PIN_FUNC_4>; + samsung,pin-function = <S3C64XX_PIN_FUNC_4>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; irda_data_0: irda-data-0-pins { samsung,pins = "gpb-0", "gpb-1"; - samsung,pin-function = <EXYNOS_PIN_FUNC_4>; + samsung,pin-function = <S3C64XX_PIN_FUNC_4>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; irda_data_1: irda-data-1-pins { samsung,pins = "gpb-2", "gpb-3"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-function = <S3C64XX_PIN_FUNC_3>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; irda_sdbw: irda-sdbw-pins { samsung,pins = "gpb-4"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-function = <S3C64XX_PIN_FUNC_2>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; i2c0_bus: i2c0-bus-pins { samsung,pins = "gpb-5", "gpb-6"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-function = <S3C64XX_PIN_FUNC_2>; samsung,pin-pud = <S3C64XX_PIN_PULL_UP>; }; i2c1_bus: i2c1-bus-pins { /* S3C6410-only */ samsung,pins = "gpb-2", "gpb-3"; - samsung,pin-function = <EXYNOS_PIN_FUNC_6>; + samsung,pin-function = <S3C64XX_PIN_FUNC_6>; samsung,pin-pud = <S3C64XX_PIN_PULL_UP>; }; spi0_bus: spi0-bus-pins { samsung,pins = "gpc-0", "gpc-1", "gpc-2"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-function = <S3C64XX_PIN_FUNC_2>; samsung,pin-pud = <S3C64XX_PIN_PULL_UP>; }; spi0_cs: spi0-cs-pins { samsung,pins = "gpc-3"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-function = <S3C64XX_PIN_FUNC_2>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; spi1_bus: spi1-bus-pins { samsung,pins = "gpc-4", "gpc-5", "gpc-6"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-function = <S3C64XX_PIN_FUNC_2>; samsung,pin-pud = <S3C64XX_PIN_PULL_UP>; }; spi1_cs: spi1-cs-pins { samsung,pins = "gpc-7"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-function = <S3C64XX_PIN_FUNC_2>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; sd0_cmd: sd0-cmd-pins { samsung,pins = "gpg-1"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-function = <S3C64XX_PIN_FUNC_2>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; sd0_clk: sd0-clk-pins { samsung,pins = "gpg-0"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-function = <S3C64XX_PIN_FUNC_2>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; sd0_bus1: sd0-bus1-pins { samsung,pins = "gpg-2"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-function = <S3C64XX_PIN_FUNC_2>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; sd0_bus4: sd0-bus4-pins { samsung,pins = "gpg-2", "gpg-3", "gpg-4", "gpg-5"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-function = <S3C64XX_PIN_FUNC_2>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; sd0_cd: sd0-cd-pins { samsung,pins = "gpg-6"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-function = <S3C64XX_PIN_FUNC_2>; samsung,pin-pud = <S3C64XX_PIN_PULL_UP>; }; sd1_cmd: sd1-cmd-pins { samsung,pins = "gph-1"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-function = <S3C64XX_PIN_FUNC_2>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; sd1_clk: sd1-clk-pins { samsung,pins = "gph-0"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-function = <S3C64XX_PIN_FUNC_2>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; sd1_bus1: sd1-bus1-pins { samsung,pins = "gph-2"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-function = <S3C64XX_PIN_FUNC_2>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; sd1_bus4: sd1-bus4-pins { samsung,pins = "gph-2", "gph-3", "gph-4", "gph-5"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-function = <S3C64XX_PIN_FUNC_2>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; sd1_bus8: sd1-bus8-pins { samsung,pins = "gph-2", "gph-3", "gph-4", "gph-5", "gph-6", "gph-7", "gph-8", "gph-9"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-function = <S3C64XX_PIN_FUNC_2>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; sd1_cd: sd1-cd-pins { samsung,pins = "gpg-6"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-function = <S3C64XX_PIN_FUNC_3>; samsung,pin-pud = <S3C64XX_PIN_PULL_UP>; }; sd2_cmd: sd2-cmd-pins { samsung,pins = "gpc-4"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-function = <S3C64XX_PIN_FUNC_3>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; sd2_clk: sd2-clk-pins { samsung,pins = "gpc-5"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-function = <S3C64XX_PIN_FUNC_3>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; sd2_bus1: sd2-bus1-pins { samsung,pins = "gph-6"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-function = <S3C64XX_PIN_FUNC_3>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; sd2_bus4: sd2-bus4-pins { samsung,pins = "gph-6", "gph-7", "gph-8", "gph-9"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-function = <S3C64XX_PIN_FUNC_3>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; i2s0_bus: i2s0-bus-pins { samsung,pins = "gpd-0", "gpd-2", "gpd-3", "gpd-4"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-function = <S3C64XX_PIN_FUNC_3>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; i2s0_cdclk: i2s0-cdclk-pins { samsung,pins = "gpd-1"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-function = <S3C64XX_PIN_FUNC_3>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; i2s1_bus: i2s1-bus-pins { samsung,pins = "gpe-0", "gpe-2", "gpe-3", "gpe-4"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-function = <S3C64XX_PIN_FUNC_3>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; i2s1_cdclk: i2s1-cdclk-pins { samsung,pins = "gpe-1"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-function = <S3C64XX_PIN_FUNC_3>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; @@ -353,50 +353,50 @@ /* S3C6410-only */ samsung,pins = "gpc-4", "gpc-5", "gpc-6", "gph-6", "gph-8", "gph-9"; - samsung,pin-function = <EXYNOS_PIN_FUNC_5>; + samsung,pin-function = <S3C64XX_PIN_FUNC_5>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; i2s2_cdclk: i2s2-cdclk-pins { /* S3C6410-only */ samsung,pins = "gph-7"; - samsung,pin-function = <EXYNOS_PIN_FUNC_5>; + samsung,pin-function = <S3C64XX_PIN_FUNC_5>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; pcm0_bus: pcm0-bus-pins { samsung,pins = "gpd-0", "gpd-2", "gpd-3", "gpd-4"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-function = <S3C64XX_PIN_FUNC_2>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; pcm0_extclk: pcm0-extclk-pins { samsung,pins = "gpd-1"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-function = <S3C64XX_PIN_FUNC_2>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; pcm1_bus: pcm1-bus-pins { samsung,pins = "gpe-0", "gpe-2", "gpe-3", "gpe-4"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-function = <S3C64XX_PIN_FUNC_2>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; pcm1_extclk: pcm1-extclk-pins { samsung,pins = "gpe-1"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-function = <S3C64XX_PIN_FUNC_2>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; ac97_bus_0: ac97-bus-0-pins { samsung,pins = "gpd-0", "gpd-1", "gpd-2", "gpd-3", "gpd-4"; - samsung,pin-function = <EXYNOS_PIN_FUNC_4>; + samsung,pin-function = <S3C64XX_PIN_FUNC_4>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; ac97_bus_1: ac97-bus-1-pins { samsung,pins = "gpe-0", "gpe-1", "gpe-2", "gpe-3", "gpe-4"; - samsung,pin-function = <EXYNOS_PIN_FUNC_4>; + samsung,pin-function = <S3C64XX_PIN_FUNC_4>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; @@ -404,242 +404,242 @@ samsung,pins = "gpf-0", "gpf-1", "gpf-2", "gpf-4", "gpf-5", "gpf-6", "gpf-7", "gpf-8", "gpf-9", "gpf-10", "gpf-11", "gpf-12"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-function = <S3C64XX_PIN_FUNC_2>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; cam_rst: cam-rst-pins { samsung,pins = "gpf-3"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-function = <S3C64XX_PIN_FUNC_2>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; cam_field: cam-field-pins { /* S3C6410-only */ samsung,pins = "gpb-4"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-function = <S3C64XX_PIN_FUNC_3>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; pwm_extclk: pwm-extclk-pins { samsung,pins = "gpf-13"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-function = <S3C64XX_PIN_FUNC_2>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; pwm0_out: pwm0-out-pins { samsung,pins = "gpf-14"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-function = <S3C64XX_PIN_FUNC_2>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; pwm1_out: pwm1-out-pins { samsung,pins = "gpf-15"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-function = <S3C64XX_PIN_FUNC_2>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; clkout0: clkout-0-pins { samsung,pins = "gpf-14"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-function = <S3C64XX_PIN_FUNC_3>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; keypad_col0_0: keypad-col0-0-pins { samsung,pins = "gph-0"; - samsung,pin-function = <EXYNOS_PIN_FUNC_4>; + samsung,pin-function = <S3C64XX_PIN_FUNC_4>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; keypad_col1_0: keypad-col1-0-pins { samsung,pins = "gph-1"; - samsung,pin-function = <EXYNOS_PIN_FUNC_4>; + samsung,pin-function = <S3C64XX_PIN_FUNC_4>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; keypad_col2_0: keypad-col2-0-pins { samsung,pins = "gph-2"; - samsung,pin-function = <EXYNOS_PIN_FUNC_4>; + samsung,pin-function = <S3C64XX_PIN_FUNC_4>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; keypad_col3_0: keypad-col3-0-pins { samsung,pins = "gph-3"; - samsung,pin-function = <EXYNOS_PIN_FUNC_4>; + samsung,pin-function = <S3C64XX_PIN_FUNC_4>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; keypad_col4_0: keypad-col4-0-pins { samsung,pins = "gph-4"; - samsung,pin-function = <EXYNOS_PIN_FUNC_4>; + samsung,pin-function = <S3C64XX_PIN_FUNC_4>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; keypad_col5_0: keypad-col5-0-pins { samsung,pins = "gph-5"; - samsung,pin-function = <EXYNOS_PIN_FUNC_4>; + samsung,pin-function = <S3C64XX_PIN_FUNC_4>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; keypad_col6_0: keypad-col6-0-pins { samsung,pins = "gph-6"; - samsung,pin-function = <EXYNOS_PIN_FUNC_4>; + samsung,pin-function = <S3C64XX_PIN_FUNC_4>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; keypad_col7_0: keypad-col7-0-pins { samsung,pins = "gph-7"; - samsung,pin-function = <EXYNOS_PIN_FUNC_4>; + samsung,pin-function = <S3C64XX_PIN_FUNC_4>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; keypad_col0_1: keypad-col0-1-pins { samsung,pins = "gpl-0"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-function = <S3C64XX_PIN_FUNC_3>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; keypad_col1_1: keypad-col1-1-pins { samsung,pins = "gpl-1"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-function = <S3C64XX_PIN_FUNC_3>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; keypad_col2_1: keypad-col2-1-pins { samsung,pins = "gpl-2"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-function = <S3C64XX_PIN_FUNC_3>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; keypad_col3_1: keypad-col3-1-pins { samsung,pins = "gpl-3"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-function = <S3C64XX_PIN_FUNC_3>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; keypad_col4_1: keypad-col4-1-pins { samsung,pins = "gpl-4"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-function = <S3C64XX_PIN_FUNC_3>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; keypad_col5_1: keypad-col5-1-pins { samsung,pins = "gpl-5"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-function = <S3C64XX_PIN_FUNC_3>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; keypad_col6_1: keypad-col6-1-pins { samsung,pins = "gpl-6"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-function = <S3C64XX_PIN_FUNC_3>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; keypad_col7_1: keypad-col7-1-pins { samsung,pins = "gpl-7"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-function = <S3C64XX_PIN_FUNC_3>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; keypad_row0_0: keypad-row0-0-pins { samsung,pins = "gpk-8"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-function = <S3C64XX_PIN_FUNC_3>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; keypad_row1_0: keypad-row1-0-pins { samsung,pins = "gpk-9"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-function = <S3C64XX_PIN_FUNC_3>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; keypad_row2_0: keypad-row2-0-pins { samsung,pins = "gpk-10"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-function = <S3C64XX_PIN_FUNC_3>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; keypad_row3_0: keypad-row3-0-pins { samsung,pins = "gpk-11"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-function = <S3C64XX_PIN_FUNC_3>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; keypad_row4_0: keypad-row4-0-pins { samsung,pins = "gpk-12"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-function = <S3C64XX_PIN_FUNC_3>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; keypad_row5_0: keypad-row5-0-pins { samsung,pins = "gpk-13"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-function = <S3C64XX_PIN_FUNC_3>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; keypad_row6_0: keypad-row6-0-pins { samsung,pins = "gpk-14"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-function = <S3C64XX_PIN_FUNC_3>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; keypad_row7_0: keypad-row7-0-pins { samsung,pins = "gpk-15"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-function = <S3C64XX_PIN_FUNC_3>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; keypad_row0_1: keypad-row0-1-pins { samsung,pins = "gpn-0"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-function = <S3C64XX_PIN_FUNC_3>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; keypad_row1_1: keypad-row1-1-pins { samsung,pins = "gpn-1"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-function = <S3C64XX_PIN_FUNC_3>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; keypad_row2_1: keypad-row2-1-pins { samsung,pins = "gpn-2"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-function = <S3C64XX_PIN_FUNC_3>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; keypad_row3_1: keypad-row3-1-pins { samsung,pins = "gpn-3"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-function = <S3C64XX_PIN_FUNC_3>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; keypad_row4_1: keypad-row4-1-pins { samsung,pins = "gpn-4"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-function = <S3C64XX_PIN_FUNC_3>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; keypad_row5_1: keypad-row5-1-pins { samsung,pins = "gpn-5"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-function = <S3C64XX_PIN_FUNC_3>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; keypad_row6_1: keypad-row6-1-pins { samsung,pins = "gpn-6"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-function = <S3C64XX_PIN_FUNC_3>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; keypad_row7_1: keypad-row7-1-pins { samsung,pins = "gpn-7"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-function = <S3C64XX_PIN_FUNC_3>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; lcd_ctrl: lcd-ctrl-pins { samsung,pins = "gpj-8", "gpj-9", "gpj-10", "gpj-11"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-function = <S3C64XX_PIN_FUNC_2>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; @@ -648,7 +648,7 @@ "gpi-7", "gpi-10", "gpi-11", "gpi-12", "gpi-13", "gpi-14", "gpi-15", "gpj-3", "gpj-4", "gpj-5", "gpj-6", "gpj-7"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-function = <S3C64XX_PIN_FUNC_2>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; @@ -658,7 +658,7 @@ "gpi-12", "gpi-13", "gpi-14", "gpi-15", "gpj-2", "gpj-3", "gpj-4", "gpj-5", "gpj-6", "gpj-7"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-function = <S3C64XX_PIN_FUNC_2>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; @@ -669,14 +669,14 @@ "gpi-12", "gpi-13", "gpi-14", "gpi-15", "gpj-0", "gpj-1", "gpj-2", "gpj-3", "gpj-4", "gpj-5", "gpj-6", "gpj-7"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-function = <S3C64XX_PIN_FUNC_2>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; hsi_bus: hsi-bus-pins { samsung,pins = "gpk-0", "gpk-1", "gpk-2", "gpk-3", "gpk-4", "gpk-5", "gpk-6", "gpk-7"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-function = <S3C64XX_PIN_FUNC_3>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; }; diff --git a/arch/arm/boot/dts/s3c64xx-pinctrl.h b/arch/arm/boot/dts/s3c64xx-pinctrl.h new file mode 100644 index 000000000000..645c591db357 --- /dev/null +++ b/arch/arm/boot/dts/s3c64xx-pinctrl.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Samsung S3C64xx DTS pinctrl constants + * + * Copyright (c) 2016 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * Copyright (c) 2022 Linaro Ltd + * Author: Krzysztof Kozlowski <krzk@kernel.org> + */ + +#ifndef __DTS_ARM_SAMSUNG_S3C64XX_PINCTRL_H__ +#define __DTS_ARM_SAMSUNG_S3C64XX_PINCTRL_H__ + +#define S3C64XX_PIN_PULL_NONE 0 +#define S3C64XX_PIN_PULL_DOWN 1 +#define S3C64XX_PIN_PULL_UP 2 + +#define S3C64XX_PIN_FUNC_INPUT 0 +#define S3C64XX_PIN_FUNC_OUTPUT 1 +#define S3C64XX_PIN_FUNC_2 2 +#define S3C64XX_PIN_FUNC_3 3 +#define S3C64XX_PIN_FUNC_4 4 +#define S3C64XX_PIN_FUNC_5 5 +#define S3C64XX_PIN_FUNC_6 6 +#define S3C64XX_PIN_FUNC_EINT 7 + +#endif /* __DTS_ARM_SAMSUNG_S3C64XX_PINCTRL_H__ */ diff --git a/arch/arm/boot/dts/s3c64xx.dtsi b/arch/arm/boot/dts/s3c64xx.dtsi index 67a7a66e11d5..c03df6355500 100644 --- a/arch/arm/boot/dts/s3c64xx.dtsi +++ b/arch/arm/boot/dts/s3c64xx.dtsi @@ -59,7 +59,7 @@ #interrupt-cells = <1>; }; - sdhci0: sdhci@7c200000 { + sdhci0: mmc@7c200000 { compatible = "samsung,s3c6410-sdhci"; reg = <0x7c200000 0x100>; interrupt-parent = <&vic1>; @@ -70,7 +70,7 @@ status = "disabled"; }; - sdhci1: sdhci@7c300000 { + sdhci1: mmc@7c300000 { compatible = "samsung,s3c6410-sdhci"; reg = <0x7c300000 0x100>; interrupt-parent = <&vic1>; @@ -81,7 +81,7 @@ status = "disabled"; }; - sdhci2: sdhci@7c400000 { + sdhci2: mmc@7c400000 { compatible = "samsung,s3c6410-sdhci"; reg = <0x7c400000 0x100>; interrupt-parent = <&vic1>; diff --git a/arch/arm/boot/dts/s5pv210-aquila.dts b/arch/arm/boot/dts/s5pv210-aquila.dts index bc0b7354b6c0..0f5c6cd0f3a1 100644 --- a/arch/arm/boot/dts/s5pv210-aquila.dts +++ b/arch/arm/boot/dts/s5pv210-aquila.dts @@ -392,7 +392,7 @@ &pinctrl0 { t_flash_detect: t-flash-detect-pins { samsung,pins = "gph3-4"; - samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; + samsung,pin-function = <S5PV210_PIN_FUNC_INPUT>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; }; }; diff --git a/arch/arm/boot/dts/s5pv210-aries.dtsi b/arch/arm/boot/dts/s5pv210-aries.dtsi index daa1067055c8..5541df4df628 100644 --- a/arch/arm/boot/dts/s5pv210-aries.dtsi +++ b/arch/arm/boot/dts/s5pv210-aries.dtsi @@ -646,183 +646,183 @@ &pinctrl0 { bt_reset: bt-reset-pins { samsung,pins = "gpb-3"; - samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_OUTPUT>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; wlan_bt_en: wlan-bt-en-pins { samsung,pins = "gpb-5"; - samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; + samsung,pin-function = <S5PV210_PIN_FUNC_OUTPUT>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; samsung,pin-val = <1>; }; codec_ldo: codec-ldo-pins { samsung,pins = "gpf3-4"; - samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; + samsung,pin-function = <S5PV210_PIN_FUNC_OUTPUT>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; }; prox_i2c_pins: gp2a-i2c-pins { samsung,pins = "gpg0-2", "gpg2-2"; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; wlan_gpio_rst: wlan-gpio-rst-pins { samsung,pins = "gpg1-2"; - samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; + samsung,pin-function = <S5PV210_PIN_FUNC_OUTPUT>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; }; bt_wake: bt-wake-pins { samsung,pins = "gpg3-4"; - samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; + samsung,pin-function = <S5PV210_PIN_FUNC_OUTPUT>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; }; gp2a_irq: gp2a-irq-pins { samsung,pins = "gph0-2"; - samsung,pin-function = <EXYNOS_PIN_FUNC_F>; - samsung,pin-pud = <S3C64XX_PIN_PULL_DOWN>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_F>; + samsung,pin-pud = <S5PV210_PIN_PULL_DOWN>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; pmic_dvs_pins: pmic-dvs-pins { samsung,pins = "gph0-3", "gph0-4", "gph0-5"; - samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_OUTPUT>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; samsung,pin-val = <0>; }; pmic_irq: pmic-irq-pins { samsung,pins = "gph0-7"; - samsung,pin-function = <EXYNOS_PIN_FUNC_F>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_F>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; wifi_host_wake: wifi-host-wake-pins { samsung,pins = "gph2-4"; - samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; - samsung,pin-pud = <S3C64XX_PIN_PULL_DOWN>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_INPUT>; + samsung,pin-pud = <S5PV210_PIN_PULL_DOWN>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; bt_host_wake: bt-host-wake-pins { samsung,pins = "gph2-5"; - samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; - samsung,pin-pud = <S3C64XX_PIN_PULL_DOWN>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_INPUT>; + samsung,pin-pud = <S5PV210_PIN_PULL_DOWN>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; musb_irq: musq-irq-pins { samsung,pins = "gph2-7"; - samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_INPUT>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; tf_detect: tf-detect-pins { samsung,pins = "gph3-4"; - samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; - samsung,pin-pud = <S3C64XX_PIN_PULL_DOWN>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_INPUT>; + samsung,pin-pud = <S5PV210_PIN_PULL_DOWN>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; wifi_wake: wifi-wake-pins { samsung,pins = "gph3-5"; - samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; + samsung,pin-function = <S5PV210_PIN_FUNC_OUTPUT>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; }; magnetometer_i2c_pins: yas529-i2c-pins-pins { samsung,pins = "gpj0-0", "gpj0-1"; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; ts_irq: ts-irq-pins { samsung,pins = "gpj0-5"; - samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_INPUT>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; vibrator_ena: vibrator-ena-pins { samsung,pins = "gpj1-1"; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; gp2a_power: gp2a-power-pins { samsung,pins = "gpj1-4"; - samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_OUTPUT>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; touchkey_i2c_pins: touchkey-i2c-pins { samsung,pins = "gpj3-0", "gpj3-1"; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; touchkey_vdd_ena: touchkey-vdd-ena-pins { samsung,pins = "gpj3-2"; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; musb_i2c_pins: musb-i2c-pins { samsung,pins = "gpj3-4", "gpj3-5"; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; accel_i2c_pins: accel-i2c-pins { samsung,pins = "gpj3-6", "gpj3-7"; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; pmic_i2c_pins: pmic-i2c-pins-pins { samsung,pins = "gpj4-0", "gpj4-3"; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; touchkey_irq: touchkey-irq-pins { samsung,pins = "gpj4-1"; - samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; - samsung,pin-pud = <S3C64XX_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_INPUT>; + samsung,pin-pud = <S5PV210_PIN_PULL_UP>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; lcd_spi_pins: spi-lcd-pins { samsung,pins = "mp01-1", "mp04-1", "mp04-3"; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; fg_i2c_pins: fg-i2c-pins { samsung,pins = "mp05-0", "mp05-1"; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; sound_i2c_pins: sound-i2c-pins { samsung,pins = "mp05-2", "mp05-3"; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; panel_rst: panel-rst-pins { samsung,pins = "mp05-5"; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; }; diff --git a/arch/arm/boot/dts/s5pv210-fascinate4g.dts b/arch/arm/boot/dts/s5pv210-fascinate4g.dts index dfb2ee65e4a8..eaa7c4f0e257 100644 --- a/arch/arm/boot/dts/s5pv210-fascinate4g.dts +++ b/arch/arm/boot/dts/s5pv210-fascinate4g.dts @@ -17,20 +17,20 @@ gpio-keys { compatible = "gpio-keys"; - power { + key-power { label = "power"; gpios = <&gph2 6 GPIO_ACTIVE_LOW>; linux,code = <KEY_POWER>; wakeup-source; }; - vol-down { + key-vol-down { label = "volume_down"; gpios = <&gph3 2 GPIO_ACTIVE_LOW>; linux,code = <KEY_VOLUMEDOWN>; }; - vol-up { + key-vol-up { label = "volume_up"; gpios = <&gph3 1 GPIO_ACTIVE_LOW>; linux,code = <KEY_VOLUMEUP>; @@ -128,33 +128,33 @@ headset_det: headset-det-pins { samsung,pins = "gph0-6", "gph3-6"; - samsung,pin-function = <EXYNOS_PIN_FUNC_F>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; + samsung,pin-function = <S5PV210_PIN_FUNC_F>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; }; fg_irq: fg-irq-pins { samsung,pins = "gph3-3"; - samsung,pin-function = <EXYNOS_PIN_FUNC_F>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_F>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; headset_micbias_ena: headset-micbias-ena-pins { samsung,pins = "gpj2-5"; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; earpath_sel: earpath-sel-pins { samsung,pins = "gpj2-6"; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; main_micbias_ena: main-micbias-ena-pins { samsung,pins = "gpj4-2"; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; /* Based on vendor kernel v2.6.35.7 */ diff --git a/arch/arm/boot/dts/s5pv210-galaxys.dts b/arch/arm/boot/dts/s5pv210-galaxys.dts index a78caaa1f3c5..cdd3653d487f 100644 --- a/arch/arm/boot/dts/s5pv210-galaxys.dts +++ b/arch/arm/boot/dts/s5pv210-galaxys.dts @@ -24,26 +24,26 @@ gpio-keys { compatible = "gpio-keys"; - power { + key-power { label = "power"; gpios = <&gph2 6 GPIO_ACTIVE_LOW>; linux,code = <KEY_POWER>; wakeup-source; }; - vol-down { + key-vol-down { label = "volume_down"; gpios = <&gph3 1 GPIO_ACTIVE_LOW>; linux,code = <KEY_VOLUMEDOWN>; }; - vol-up { + key-vol-up { label = "volume_up"; gpios = <&gph3 2 GPIO_ACTIVE_LOW>; linux,code = <KEY_VOLUMEUP>; }; - home { + key-home { label = "home"; gpios = <&gph3 5 GPIO_ACTIVE_LOW>; linux,code = <KEY_HOME>; @@ -152,47 +152,47 @@ fm_i2c_pins: fm-i2c-pins-pins { samsung,pins = "gpd1-2", "gpd1-3"; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; headset_det: headset-det-pins { samsung,pins = "gph0-6", "gph3-6"; - samsung,pin-function = <EXYNOS_PIN_FUNC_F>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; + samsung,pin-function = <S5PV210_PIN_FUNC_F>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; }; fm_irq: fm-irq-pins { samsung,pins = "gpj2-4"; - samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; - samsung,pin-pud = <S3C64XX_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_INPUT>; + samsung,pin-pud = <S5PV210_PIN_PULL_UP>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; fm_rst: fm-rst-pins { samsung,pins = "gpj2-5"; - samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_OUTPUT>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; earpath_sel: earpath-sel-pins { samsung,pins = "gpj2-6"; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; massmemory_en: massmemory-en-pins { samsung,pins = "gpj2-7"; - samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_OUTPUT>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; micbias_reg_ena: micbias-reg-ena-pins { samsung,pins = "gpj4-2"; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; /* Based on CyanogenMod 3.0.101 kernel */ diff --git a/arch/arm/boot/dts/s5pv210-pinctrl.dtsi b/arch/arm/boot/dts/s5pv210-pinctrl.dtsi index ae34e7e57892..6d6daef9fb7a 100644 --- a/arch/arm/boot/dts/s5pv210-pinctrl.dtsi +++ b/arch/arm/boot/dts/s5pv210-pinctrl.dtsi @@ -16,13 +16,13 @@ * nodes can be added to this file. */ -#include <dt-bindings/pinctrl/samsung.h> +#include "s5pv210-pinctrl.h" #define PIN_SLP(_pin, _mode, _pull) \ _pin { \ samsung,pins = #_pin; \ - samsung,pin-con-pdn = <EXYNOS_PIN_PDN_ ##_mode>; \ - samsung,pin-pud-pdn = <S3C64XX_PIN_PULL_ ##_pull>; \ + samsung,pin-con-pdn = <S5PV210_PIN_PDN_ ##_mode>; \ + samsung,pin-pud-pdn = <S5PV210_PIN_PULL_ ##_pull>; \ } &pinctrl0 { @@ -280,559 +280,559 @@ uart0_data: uart0-data-pins { samsung,pins = "gpa0-0", "gpa0-1"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_2>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; uart0_fctl: uart0-fctl-pins { samsung,pins = "gpa0-2", "gpa0-3"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_2>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; uart1_data: uart1-data-pins { samsung,pins = "gpa0-4", "gpa0-5"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_2>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; uart1_fctl: uart1-fctl-pins { samsung,pins = "gpa0-6", "gpa0-7"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_2>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; uart2_data: uart2-data-pins { samsung,pins = "gpa1-0", "gpa1-1"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_2>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; uart2_fctl: uart2-fctl-pins { samsung,pins = "gpa1-2", "gpa1-3"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_3>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; uart3_data: uart3-data-pins { samsung,pins = "gpa1-2", "gpa1-3"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_2>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; uart_audio: uart-audio-pins { samsung,pins = "gpa1-2", "gpa1-3"; - samsung,pin-function = <EXYNOS_PIN_FUNC_4>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_4>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; spi0_bus: spi0-bus-pins { samsung,pins = "gpb-0", "gpb-2", "gpb-3"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <S3C64XX_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_2>; + samsung,pin-pud = <S5PV210_PIN_PULL_UP>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; spi1_bus: spi1-bus-pins { samsung,pins = "gpb-4", "gpb-6", "gpb-7"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <S3C64XX_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_2>; + samsung,pin-pud = <S5PV210_PIN_PULL_UP>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; i2s0_bus: i2s0-bus-pins { samsung,pins = "gpi-0", "gpi-1", "gpi-2", "gpi-3", "gpi-4", "gpi-5", "gpi-6"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_2>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; i2s1_bus: i2s1-bus-pins { samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", "gpc0-4"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_2>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; i2s2_bus: i2s2-bus-pins { samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", "gpc1-4"; - samsung,pin-function = <EXYNOS_PIN_FUNC_4>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_4>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; pcm1_bus: pcm1-bus-pins { samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", "gpc0-4"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_3>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; ac97_bus: ac97-bus-pins { samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", "gpc0-4"; - samsung,pin-function = <EXYNOS_PIN_FUNC_4>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_4>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; i2s2_bus: i2s2-bus-pins { samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", "gpc1-4"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_2>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; pcm2_bus: pcm2-bus-pins { samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", "gpc1-4"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_3>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; spdif_bus: spdif-bus-pins { samsung,pins = "gpc1-0", "gpc1-1"; - samsung,pin-function = <EXYNOS_PIN_FUNC_4>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_4>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; spi2_bus: spi2-bus-pins { samsung,pins = "gpc1-1", "gpc1-2", "gpc1-3", "gpc1-4"; - samsung,pin-function = <EXYNOS_PIN_FUNC_5>; - samsung,pin-pud = <S3C64XX_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_5>; + samsung,pin-pud = <S5PV210_PIN_PULL_UP>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; i2c0_bus: i2c0-bus-pins { samsung,pins = "gpd1-0", "gpd1-1"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <S3C64XX_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_2>; + samsung,pin-pud = <S5PV210_PIN_PULL_UP>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; i2c1_bus: i2c1-bus-pins { samsung,pins = "gpd1-2", "gpd1-3"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <S3C64XX_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_2>; + samsung,pin-pud = <S5PV210_PIN_PULL_UP>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; i2c2_bus: i2c2-bus-pins { samsung,pins = "gpd1-4", "gpd1-5"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <S3C64XX_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_2>; + samsung,pin-pud = <S5PV210_PIN_PULL_UP>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; pwm0_out: pwm0-out-pins { samsung,pins = "gpd0-0"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_2>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; pwm1_out: pwm1-out-pins { samsung,pins = "gpd0-1"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_2>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; pwm2_out: pwm2-out-pins { samsung,pins = "gpd0-2"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_2>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; pwm3_out: pwm3-out-pins { samsung,pins = "gpd0-3"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_2>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; keypad_row0: keypad-row-0-pins { samsung,pins = "gph3-0"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_3>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; keypad_row1: keypad-row-1-pins { samsung,pins = "gph3-1"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_3>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; keypad_row2: keypad-row-2-pins { samsung,pins = "gph3-2"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_3>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; keypad_row3: keypad-row-3-pins { samsung,pins = "gph3-3"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_3>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; keypad_row4: keypad-row-4-pins { samsung,pins = "gph3-4"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_3>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; keypad_row5: keypad-row-5-pins { samsung,pins = "gph3-5"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_3>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; keypad_row6: keypad-row-6-pins { samsung,pins = "gph3-6"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_3>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; keypad_row7: keypad-row-7-pins { samsung,pins = "gph3-7"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_3>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; keypad_col0: keypad-col-0-pins { samsung,pins = "gph2-0"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_3>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; keypad_col1: keypad-col-1-pins { samsung,pins = "gph2-1"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_3>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; keypad_col2: keypad-col-2-pins { samsung,pins = "gph2-2"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_3>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; keypad_col3: keypad-col-3-pins { samsung,pins = "gph2-3"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_3>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; keypad_col4: keypad-col-4-pins { samsung,pins = "gph2-4"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_3>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; keypad_col5: keypad-col-5-pins { samsung,pins = "gph2-5"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_3>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; keypad_col6: keypad-col-6-pins { samsung,pins = "gph2-6"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_3>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; keypad_col7: keypad-col-7-pins { samsung,pins = "gph2-7"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_3>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; sd0_clk: sd0-clk-pins { samsung,pins = "gpg0-0"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; + samsung,pin-function = <S5PV210_PIN_FUNC_2>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV4>; }; sd0_cmd: sd0-cmd-pins { samsung,pins = "gpg0-1"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; + samsung,pin-function = <S5PV210_PIN_FUNC_2>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV4>; }; sd0_cd: sd0-cd-pins { samsung,pins = "gpg0-2"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <S3C64XX_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; + samsung,pin-function = <S5PV210_PIN_FUNC_2>; + samsung,pin-pud = <S5PV210_PIN_PULL_UP>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV4>; }; sd0_bus1: sd0-bus-width1-pins { samsung,pins = "gpg0-3"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <S3C64XX_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; + samsung,pin-function = <S5PV210_PIN_FUNC_2>; + samsung,pin-pud = <S5PV210_PIN_PULL_UP>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV4>; }; sd0_bus4: sd0-bus-width4-pins { samsung,pins = "gpg0-3", "gpg0-4", "gpg0-5", "gpg0-6"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <S3C64XX_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; + samsung,pin-function = <S5PV210_PIN_FUNC_2>; + samsung,pin-pud = <S5PV210_PIN_PULL_UP>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV4>; }; sd0_bus8: sd0-bus-width8-pins { samsung,pins = "gpg1-3", "gpg1-4", "gpg1-5", "gpg1-6"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; - samsung,pin-pud = <S3C64XX_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; + samsung,pin-function = <S5PV210_PIN_FUNC_3>; + samsung,pin-pud = <S5PV210_PIN_PULL_UP>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV4>; }; sd1_clk: sd1-clk-pins { samsung,pins = "gpg1-0"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; + samsung,pin-function = <S5PV210_PIN_FUNC_2>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV4>; }; sd1_cmd: sd1-cmd-pins { samsung,pins = "gpg1-1"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; + samsung,pin-function = <S5PV210_PIN_FUNC_2>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV4>; }; sd1_cd: sd1-cd-pins { samsung,pins = "gpg1-2"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <S3C64XX_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; + samsung,pin-function = <S5PV210_PIN_FUNC_2>; + samsung,pin-pud = <S5PV210_PIN_PULL_UP>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV4>; }; sd1_bus1: sd1-bus-width1-pins { samsung,pins = "gpg1-3"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <S3C64XX_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; + samsung,pin-function = <S5PV210_PIN_FUNC_2>; + samsung,pin-pud = <S5PV210_PIN_PULL_UP>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV4>; }; sd1_bus4: sd1-bus-width4-pins { samsung,pins = "gpg1-3", "gpg1-4", "gpg1-5", "gpg1-6"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <S3C64XX_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; + samsung,pin-function = <S5PV210_PIN_FUNC_2>; + samsung,pin-pud = <S5PV210_PIN_PULL_UP>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV4>; }; sd2_clk: sd2-clk-pins { samsung,pins = "gpg2-0"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; + samsung,pin-function = <S5PV210_PIN_FUNC_2>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV4>; }; sd2_cmd: sd2-cmd-pins { samsung,pins = "gpg2-1"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; + samsung,pin-function = <S5PV210_PIN_FUNC_2>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV4>; }; sd2_cd: sd2-cd-pins { samsung,pins = "gpg2-2"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <S3C64XX_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; + samsung,pin-function = <S5PV210_PIN_FUNC_2>; + samsung,pin-pud = <S5PV210_PIN_PULL_UP>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV4>; }; sd2_bus1: sd2-bus-width1-pins { samsung,pins = "gpg2-3"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <S3C64XX_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; + samsung,pin-function = <S5PV210_PIN_FUNC_2>; + samsung,pin-pud = <S5PV210_PIN_PULL_UP>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV4>; }; sd2_bus4: sd2-bus-width4-pins { samsung,pins = "gpg2-3", "gpg2-4", "gpg2-5", "gpg2-6"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <S3C64XX_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; + samsung,pin-function = <S5PV210_PIN_FUNC_2>; + samsung,pin-pud = <S5PV210_PIN_PULL_UP>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV4>; }; sd2_bus8: sd2-bus-width8-pins { samsung,pins = "gpg3-3", "gpg3-4", "gpg3-5", "gpg3-6"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; - samsung,pin-pud = <S3C64XX_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; + samsung,pin-function = <S5PV210_PIN_FUNC_3>; + samsung,pin-pud = <S5PV210_PIN_PULL_UP>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV4>; }; sd3_clk: sd3-clk-pins { samsung,pins = "gpg3-0"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; + samsung,pin-function = <S5PV210_PIN_FUNC_2>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV4>; }; sd3_cmd: sd3-cmd-pins { samsung,pins = "gpg3-1"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; + samsung,pin-function = <S5PV210_PIN_FUNC_2>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV4>; }; sd3_cd: sd3-cd-pins { samsung,pins = "gpg3-2"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <S3C64XX_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; + samsung,pin-function = <S5PV210_PIN_FUNC_2>; + samsung,pin-pud = <S5PV210_PIN_PULL_UP>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV4>; }; sd3_bus1: sd3-bus-width1-pins { samsung,pins = "gpg3-3"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <S3C64XX_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; + samsung,pin-function = <S5PV210_PIN_FUNC_2>; + samsung,pin-pud = <S5PV210_PIN_PULL_UP>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV4>; }; sd3_bus4: sd3-bus-width4-pins { samsung,pins = "gpg3-3", "gpg3-4", "gpg3-5", "gpg3-6"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <S3C64XX_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; + samsung,pin-function = <S5PV210_PIN_FUNC_2>; + samsung,pin-pud = <S5PV210_PIN_PULL_UP>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV4>; }; eint0: ext-int0-pins { samsung,pins = "gph0-0"; - samsung,pin-function = <EXYNOS_PIN_FUNC_F>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_F>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; eint8: ext-int8-pins { samsung,pins = "gph1-0"; - samsung,pin-function = <EXYNOS_PIN_FUNC_F>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_F>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; eint15: ext-int15-pins { samsung,pins = "gph1-7"; - samsung,pin-function = <EXYNOS_PIN_FUNC_F>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_F>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; eint16: ext-int16-pins { samsung,pins = "gph2-0"; - samsung,pin-function = <EXYNOS_PIN_FUNC_F>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_F>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; eint31: ext-int31-pins { samsung,pins = "gph3-7"; - samsung,pin-function = <EXYNOS_PIN_FUNC_F>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_F>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; cam_port_a_io: cam-port-a-io-pins { samsung,pins = "gpe0-0", "gpe0-1", "gpe0-2", "gpe0-3", "gpe0-4", "gpe0-5", "gpe0-6", "gpe0-7", "gpe1-0", "gpe1-1", "gpe1-2", "gpe1-4"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_2>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; cam_port_a_clk_active: cam-port-a-clk-active-pins { samsung,pins = "gpe1-3"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; + samsung,pin-function = <S5PV210_PIN_FUNC_2>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV4>; }; cam_port_a_clk_idle: cam-port-a-clk-idle-pins { samsung,pins = "gpe1-3"; - samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; - samsung,pin-pud = <S3C64XX_PIN_PULL_DOWN>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_INPUT>; + samsung,pin-pud = <S5PV210_PIN_PULL_DOWN>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; cam_port_b_io: cam-port-b-io-pins { samsung,pins = "gpj0-0", "gpj0-1", "gpj0-2", "gpj0-3", "gpj0-4", "gpj0-5", "gpj0-6", "gpj0-7", "gpj1-0", "gpj1-1", "gpj1-2", "gpj1-4"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_3>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; cam_port_b_clk_active: cam-port-b-clk-active-pins { samsung,pins = "gpj1-3"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; + samsung,pin-function = <S5PV210_PIN_FUNC_3>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV4>; }; cam_port_b_clk_idle: cam-port-b-clk-idle-pins { samsung,pins = "gpj1-3"; - samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; - samsung,pin-pud = <S3C64XX_PIN_PULL_DOWN>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_INPUT>; + samsung,pin-pud = <S5PV210_PIN_PULL_DOWN>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; lcd_ctrl: lcd-ctrl-pins { samsung,pins = "gpd0-0", "gpd0-1"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_3>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; lcd_sync: lcd-sync-pins { samsung,pins = "gpf0-0", "gpf0-1"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_2>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; lcd_clk: lcd-clk-pins { samsung,pins = "gpf0-0", "gpf0-1", "gpf0-2", "gpf0-3"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_2>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; lcd_data24: lcd-data-width24-pins { @@ -842,8 +842,8 @@ "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3", "gpf2-4", "gpf2-5", "gpf2-6", "gpf2-7", "gpf3-0", "gpf3-1", "gpf3-2", "gpf3-3"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <S5PV210_PIN_FUNC_2>; + samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; + samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; }; }; diff --git a/arch/arm/boot/dts/s5pv210-pinctrl.h b/arch/arm/boot/dts/s5pv210-pinctrl.h new file mode 100644 index 000000000000..29bdf376d8f1 --- /dev/null +++ b/arch/arm/boot/dts/s5pv210-pinctrl.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Samsung S5PV210 DTS pinctrl constants + * + * Copyright (c) 2016 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * Copyright (c) 2022 Linaro Ltd + * Author: Krzysztof Kozlowski <krzk@kernel.org> + */ + +#ifndef __DTS_ARM_SAMSUNG_S5PV210_PINCTRL_H__ +#define __DTS_ARM_SAMSUNG_S5PV210_PINCTRL_H__ + +#define S5PV210_PIN_PULL_NONE 0 +#define S5PV210_PIN_PULL_DOWN 1 +#define S5PV210_PIN_PULL_UP 2 + +/* Pin function in power down mode */ +#define S5PV210_PIN_PDN_OUT0 0 +#define S5PV210_PIN_PDN_OUT1 1 +#define S5PV210_PIN_PDN_INPUT 2 +#define S5PV210_PIN_PDN_PREV 3 + +#define S5PV210_PIN_DRV_LV1 0 +#define S5PV210_PIN_DRV_LV2 2 +#define S5PV210_PIN_DRV_LV3 1 +#define S5PV210_PIN_DRV_LV4 3 + +#define S5PV210_PIN_FUNC_INPUT 0 +#define S5PV210_PIN_FUNC_OUTPUT 1 +#define S5PV210_PIN_FUNC_2 2 +#define S5PV210_PIN_FUNC_3 3 +#define S5PV210_PIN_FUNC_4 4 +#define S5PV210_PIN_FUNC_5 5 +#define S5PV210_PIN_FUNC_6 6 +#define S5PV210_PIN_FUNC_EINT 0xf +#define S5PV210_PIN_FUNC_F S5PV210_PIN_FUNC_EINT + +#endif /* __DTS_ARM_SAMSUNG_S5PV210_PINCTRL_H__ */ diff --git a/arch/arm/boot/dts/s5pv210.dtsi b/arch/arm/boot/dts/s5pv210.dtsi index f1b85aae8842..12e90a1cc6a1 100644 --- a/arch/arm/boot/dts/s5pv210.dtsi +++ b/arch/arm/boot/dts/s5pv210.dtsi @@ -357,7 +357,7 @@ status = "disabled"; }; - sdhci0: sdhci@eb000000 { + sdhci0: mmc@eb000000 { compatible = "samsung,s3c6410-sdhci"; reg = <0xeb000000 0x100000>; interrupt-parent = <&vic1>; @@ -368,7 +368,7 @@ status = "disabled"; }; - sdhci1: sdhci@eb100000 { + sdhci1: mmc@eb100000 { compatible = "samsung,s3c6410-sdhci"; reg = <0xeb100000 0x100000>; interrupt-parent = <&vic1>; @@ -379,7 +379,7 @@ status = "disabled"; }; - sdhci2: sdhci@eb200000 { + sdhci2: mmc@eb200000 { compatible = "samsung,s3c6410-sdhci"; reg = <0xeb200000 0x100000>; interrupt-parent = <&vic1>; @@ -390,7 +390,7 @@ status = "disabled"; }; - sdhci3: sdhci@eb300000 { + sdhci3: mmc@eb300000 { compatible = "samsung,s3c6410-sdhci"; reg = <0xeb300000 0x100000>; interrupt-parent = <&vic3>; diff --git a/arch/arm/boot/dts/sam9x60.dtsi b/arch/arm/boot/dts/sam9x60.dtsi index c328b67bea0c..d3f60f6a456d 100644 --- a/arch/arm/boot/dts/sam9x60.dtsi +++ b/arch/arm/boot/dts/sam9x60.dtsi @@ -464,7 +464,7 @@ interrupts = <18 IRQ_TYPE_LEVEL_HIGH 4>; clocks = <&pmc PMC_TYPE_PERIPHERAL 18>; #pwm-cells = <3>; - status="disabled"; + status = "disabled"; }; hlcdc: hlcdc@f8038000 { @@ -667,7 +667,7 @@ clock-names = "td_slck", "md_slck", "main_xtal"; }; - reset_controller: rstc@fffffe00 { + reset_controller: reset-controller@fffffe00 { compatible = "microchip,sam9x60-rstc"; reg = <0xfffffe00 0x10>; clocks = <&clk32k 0>; diff --git a/arch/arm/boot/dts/sama5d2.dtsi b/arch/arm/boot/dts/sama5d2.dtsi index 659a17fc755c..2c50a021aa76 100644 --- a/arch/arm/boot/dts/sama5d2.dtsi +++ b/arch/arm/boot/dts/sama5d2.dtsi @@ -99,6 +99,16 @@ ranges = <0 0x00200000 0x20000>; }; + resistive_touch: resistive-touch { + compatible = "resistive-adc-touch"; + io-channels = <&adc AT91_SAMA5D2_ADC_X_CHANNEL>, + <&adc AT91_SAMA5D2_ADC_Y_CHANNEL>, + <&adc AT91_SAMA5D2_ADC_P_CHANNEL>; + io-channel-names = "x", "y", "pressure"; + touchscreen-min-pressure = <50000>; + status = "disabled"; + }; + ahb { compatible = "simple-bus"; #address-cells = <1>; @@ -374,8 +384,6 @@ interrupts = <5 IRQ_TYPE_LEVEL_HIGH 3 /* Queue 0 */ 66 IRQ_TYPE_LEVEL_HIGH 3 /* Queue 1 */ 67 IRQ_TYPE_LEVEL_HIGH 3>; /* Queue 2 */ - #address-cells = <1>; - #size-cells = <0>; clocks = <&pmc PMC_TYPE_PERIPHERAL 5>, <&pmc PMC_TYPE_PERIPHERAL 5>; clock-names = "hclk", "pclk"; status = "disabled"; @@ -660,7 +668,7 @@ ranges = <0 0xf8044000 0x1420>; }; - reset_controller: rstc@f8048000 { + reset_controller: reset-controller@f8048000 { compatible = "atmel,sama5d3-rstc"; reg = <0xf8048000 0x10>; clocks = <&clk32k>; @@ -1050,16 +1058,6 @@ status = "disabled"; }; - resistive_touch: resistive-touch { - compatible = "resistive-adc-touch"; - io-channels = <&adc AT91_SAMA5D2_ADC_X_CHANNEL>, - <&adc AT91_SAMA5D2_ADC_Y_CHANNEL>, - <&adc AT91_SAMA5D2_ADC_P_CHANNEL>; - io-channel-names = "x", "y", "pressure"; - touchscreen-min-pressure = <50000>; - status = "disabled"; - }; - pioA: pinctrl@fc038000 { compatible = "atmel,sama5d2-pinctrl"; reg = <0xfc038000 0x600>; diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi index 8fa423c52592..2d0935ad2225 100644 --- a/arch/arm/boot/dts/sama5d3.dtsi +++ b/arch/arm/boot/dts/sama5d3.dtsi @@ -1003,7 +1003,7 @@ clock-names = "slow_clk", "main_xtal"; }; - reset_controller: rstc@fffffe00 { + reset_controller: reset-controller@fffffe00 { compatible = "atmel,sama5d3-rstc", "atmel,at91sam9g45-rstc"; reg = <0xfffffe00 0x10>; clocks = <&clk32k>; diff --git a/arch/arm/boot/dts/sama5d4.dtsi b/arch/arm/boot/dts/sama5d4.dtsi index 7b9242664875..1e5c01898ccf 100644 --- a/arch/arm/boot/dts/sama5d4.dtsi +++ b/arch/arm/boot/dts/sama5d4.dtsi @@ -726,7 +726,7 @@ }; }; - reset_controller: rstc@fc068600 { + reset_controller: reset-controller@fc068600 { compatible = "atmel,sama5d3-rstc", "atmel,at91sam9g45-rstc"; reg = <0xfc068600 0x10>; clocks = <&clk32k>; diff --git a/arch/arm/boot/dts/sama7g5.dtsi b/arch/arm/boot/dts/sama7g5.dtsi index a37e3a80392d..bb6d71e6dfeb 100644 --- a/arch/arm/boot/dts/sama7g5.dtsi +++ b/arch/arm/boot/dts/sama7g5.dtsi @@ -198,6 +198,13 @@ clock-names = "td_slck", "md_slck", "main_xtal"; }; + reset_controller: reset-controller@e001d000 { + compatible = "microchip,sama7g5-rstc"; + reg = <0xe001d000 0xc>, <0xe001d0e4 0x4>; + #reset-cells = <1>; + clocks = <&clk32k 0>; + }; + shdwc: shdwc@e001d010 { compatible = "microchip,sama7g5-shdwc", "syscon"; reg = <0xe001d010 0x10>; diff --git a/arch/arm/boot/dts/sd5203.dts b/arch/arm/boot/dts/sd5203.dts index a61a078ea042..69381819e07b 100644 --- a/arch/arm/boot/dts/sd5203.dts +++ b/arch/arm/boot/dts/sd5203.dts @@ -15,7 +15,7 @@ #size-cells = <1>; chosen { - bootargs="console=ttyS0,9600 earlycon=uart8250,mmio32,0x1600d000"; + bootargs = "console=ttyS0,9600 earlycon=uart8250,mmio32,0x1600d000"; }; aliases { diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi index 26bda2557fe8..4370e3cbbb4b 100644 --- a/arch/arm/boot/dts/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/socfpga_arria10.dtsi @@ -736,6 +736,16 @@ <37 IRQ_TYPE_LEVEL_HIGH>; }; + sdmmca-ecc@ff8c2c00 { + compatible = "altr,socfpga-sdmmc-ecc"; + reg = <0xff8c2c00 0x400>; + altr,ecc-parent = <&mmc>; + interrupts = <15 IRQ_TYPE_LEVEL_HIGH>, + <47 IRQ_TYPE_LEVEL_HIGH>, + <16 IRQ_TYPE_LEVEL_HIGH>, + <48 IRQ_TYPE_LEVEL_HIGH>; + }; + dma-ecc@ff8c8000 { compatible = "altr,socfpga-dma-ecc"; reg = <0xff8c8000 0x400>; diff --git a/arch/arm/boot/dts/socfpga_arria10_chameleonv3.dts b/arch/arm/boot/dts/socfpga_arria10_chameleonv3.dts new file mode 100644 index 000000000000..422d00cd4c74 --- /dev/null +++ b/arch/arm/boot/dts/socfpga_arria10_chameleonv3.dts @@ -0,0 +1,90 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2022 Google LLC + */ +/dts-v1/; +#include "socfpga_arria10_mercury_aa1.dtsi" + +/ { + model = "Google Chameleon V3"; + compatible = "google,chameleon-v3", "enclustra,mercury-aa1", + "altr,socfpga-arria10", "altr,socfpga"; + + aliases { + serial0 = &uart0; + i2c0 = &i2c0; + i2c1 = &i2c1; + }; +}; + +&gmac0 { + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + ssm2603: audio-codec@1a { + compatible = "adi,ssm2603"; + reg = <0x1a>; + }; +}; + +&i2c1 { + status = "okay"; + + u80: gpio@21 { + compatible = "nxp,pca9535"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + "SOM_AUD_MUTE", + "DP1_OUT_CEC_EN", + "DP2_OUT_CEC_EN", + "DP1_SOM_PS8469_CAD", + "DPD_SOM_PS8469_CAD", + "DP_OUT_PWR_EN", + "STM32_RST_L", + "STM32_BOOT0", + + "FPGA_PROT", + "STM32_FPGA_COMM0", + "TP119", + "TP120", + "TP121", + "TP122", + "TP123", + "TP124"; + }; +}; + +&mmc { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&usb0 { + status = "okay"; + dr_mode = "host"; +}; diff --git a/arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dts b/arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dtsi index a75c059b6727..ad7cd14de6b6 100644 --- a/arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dts +++ b/arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dtsi @@ -1,5 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 -/dts-v1/; +/* + * Copyright 2022 Google LLC + */ #include "socfpga_arria10.dtsi" @@ -11,8 +13,6 @@ aliases { ethernet0 = &gmac0; serial1 = &uart1; - i2c0 = &i2c0; - i2c1 = &i2c1; }; memory@0 { @@ -26,24 +26,11 @@ }; }; -&eccmgr { - sdmmca-ecc@ff8c2c00 { - compatible = "altr,socfpga-sdmmc-ecc"; - reg = <0xff8c2c00 0x400>; - altr,ecc-parent = <&mmc>; - interrupts = <15 IRQ_TYPE_LEVEL_HIGH>, - <47 IRQ_TYPE_LEVEL_HIGH>, - <16 IRQ_TYPE_LEVEL_HIGH>, - <48 IRQ_TYPE_LEVEL_HIGH>; - }; -}; - &gmac0 { phy-mode = "rgmii"; phy-addr = <0xffffffff>; /* probe for phy addr */ max-frame-size = <3800>; - status = "okay"; phy-handle = <&phy3>; @@ -69,22 +56,13 @@ }; }; -&gpio0 { - status = "okay"; -}; - -&gpio1 { - status = "okay"; -}; - -&gpio2 { - status = "okay"; -}; - &i2c1 { - status = "okay"; + atsha204a: crypto@64 { + compatible = "atmel,atsha204a"; + reg = <0x64>; + }; + isl12022: isl12022@6f { - status = "okay"; compatible = "isil,isl12022"; reg = <0x6f>; }; @@ -92,7 +70,6 @@ /* Following mappings are taken from arria10 socdk dts */ &mmc { - status = "okay"; cap-sd-highspeed; broken-cd; bus-width = <4>; @@ -101,12 +78,3 @@ &osc1 { clock-frequency = <33330000>; }; - -&uart1 { - status = "okay"; -}; - -&usb0 { - status = "okay"; - dr_mode = "host"; -}; diff --git a/arch/arm/boot/dts/spear1310-evb.dts b/arch/arm/boot/dts/spear1310-evb.dts index ddd1cf4d0554..05408df38203 100644 --- a/arch/arm/boot/dts/spear1310-evb.dts +++ b/arch/arm/boot/dts/spear1310-evb.dts @@ -170,7 +170,7 @@ smi: flash@ea000000 { status = "okay"; - clock-rate=<50000000>; + clock-rate = <50000000>; flash@e6000000 { #address-cells = <1>; diff --git a/arch/arm/boot/dts/spear1340-evb.dts b/arch/arm/boot/dts/spear1340-evb.dts index 3a51a41eb5e4..7700f2afc128 100644 --- a/arch/arm/boot/dts/spear1340-evb.dts +++ b/arch/arm/boot/dts/spear1340-evb.dts @@ -168,7 +168,7 @@ smi: flash@ea000000 { status = "okay"; - clock-rate=<50000000>; + clock-rate = <50000000>; flash@e6000000 { #address-cells = <1>; diff --git a/arch/arm/boot/dts/spear1340.dtsi b/arch/arm/boot/dts/spear1340.dtsi index 13e1bdb3ddbf..818886e11713 100644 --- a/arch/arm/boot/dts/spear1340.dtsi +++ b/arch/arm/boot/dts/spear1340.dtsi @@ -88,7 +88,7 @@ }; pwm: pwm@e0180000 { - compatible ="st,spear13xx-pwm"; + compatible = "st,spear13xx-pwm"; reg = <0xe0180000 0x1000>; #pwm-cells = <2>; status = "disabled"; diff --git a/arch/arm/boot/dts/spear300-evb.dts b/arch/arm/boot/dts/spear300-evb.dts index 2beb30ca2cba..303ef29fb805 100644 --- a/arch/arm/boot/dts/spear300-evb.dts +++ b/arch/arm/boot/dts/spear300-evb.dts @@ -80,7 +80,7 @@ smi: flash@fc000000 { status = "okay"; - clock-rate=<50000000>; + clock-rate = <50000000>; flash@f8000000 { #address-cells = <1>; diff --git a/arch/arm/boot/dts/spear310-evb.dts b/arch/arm/boot/dts/spear310-evb.dts index 1c41e4a40334..ea0b53036f7b 100644 --- a/arch/arm/boot/dts/spear310-evb.dts +++ b/arch/arm/boot/dts/spear310-evb.dts @@ -94,7 +94,7 @@ smi: flash@fc000000 { status = "okay"; - clock-rate=<50000000>; + clock-rate = <50000000>; flash@f8000000 { #address-cells = <1>; diff --git a/arch/arm/boot/dts/spear320-evb.dts b/arch/arm/boot/dts/spear320-evb.dts index c322407a0ade..3c026d021c92 100644 --- a/arch/arm/boot/dts/spear320-evb.dts +++ b/arch/arm/boot/dts/spear320-evb.dts @@ -95,7 +95,7 @@ smi: flash@fc000000 { status = "okay"; - clock-rate=<50000000>; + clock-rate = <50000000>; flash@f8000000 { #address-cells = <1>; diff --git a/arch/arm/boot/dts/spear320-hmi.dts b/arch/arm/boot/dts/spear320-hmi.dts index b587e4ec11e5..34503ac9c51c 100644 --- a/arch/arm/boot/dts/spear320-hmi.dts +++ b/arch/arm/boot/dts/spear320-hmi.dts @@ -167,7 +167,7 @@ smi: flash@fc000000 { status = "okay"; - clock-rate=<50000000>; + clock-rate = <50000000>; flash@f8000000 { #address-cells = <1>; diff --git a/arch/arm/boot/dts/spear320.dtsi b/arch/arm/boot/dts/spear320.dtsi index 47ac4474ed96..b12474446a48 100644 --- a/arch/arm/boot/dts/spear320.dtsi +++ b/arch/arm/boot/dts/spear320.dtsi @@ -78,7 +78,7 @@ }; pwm: pwm@a8000000 { - compatible ="st,spear-pwm"; + compatible = "st,spear-pwm"; reg = <0xa8000000 0x1000>; #pwm-cells = <2>; status = "disabled"; diff --git a/arch/arm/boot/dts/ste-ab8500.dtsi b/arch/arm/boot/dts/ste-ab8500.dtsi index 35137c6e52ee..dd30d08ccb9b 100644 --- a/arch/arm/boot/dts/ste-ab8500.dtsi +++ b/arch/arm/boot/dts/ste-ab8500.dtsi @@ -195,7 +195,7 @@ "CH_WD_EXP", "VBUS_CH_DROP_END"; monitored-battery = <&battery>; - vddadc-supply = <&ab8500_ldo_tvout_reg>; + vddadc-supply = <&ab8500_ldo_tvout_reg>; io-channels = <&gpadc 0x03>, <&gpadc 0x0a>, <&gpadc 0x09>, @@ -207,8 +207,8 @@ }; ab8500_chargalg { - compatible = "stericsson,ab8500-chargalg"; - monitored-battery = <&battery>; + compatible = "stericsson,ab8500-chargalg"; + monitored-battery = <&battery>; }; ab8500_usb: phy { diff --git a/arch/arm/boot/dts/ste-dbx5x0.dtsi b/arch/arm/boot/dts/ste-dbx5x0.dtsi index c28b32640254..9afe8301bd47 100644 --- a/arch/arm/boot/dts/ste-dbx5x0.dtsi +++ b/arch/arm/boot/dts/ste-dbx5x0.dtsi @@ -661,7 +661,6 @@ #address-cells = <1>; #size-cells = <0>; - v-i2c-supply = <&db8500_vape_reg>; clock-frequency = <400000>; clocks = <&prcc_kclk 3 3>, <&prcc_pclk 3 3>; @@ -679,7 +678,6 @@ #address-cells = <1>; #size-cells = <0>; - v-i2c-supply = <&db8500_vape_reg>; clock-frequency = <400000>; @@ -698,7 +696,6 @@ #address-cells = <1>; #size-cells = <0>; - v-i2c-supply = <&db8500_vape_reg>; clock-frequency = <400000>; @@ -717,7 +714,6 @@ #address-cells = <1>; #size-cells = <0>; - v-i2c-supply = <&db8500_vape_reg>; clock-frequency = <400000>; @@ -736,7 +732,6 @@ #address-cells = <1>; #size-cells = <0>; - v-i2c-supply = <&db8500_vape_reg>; clock-frequency = <400000>; diff --git a/arch/arm/boot/dts/ste-hrefv60plus.dtsi b/arch/arm/boot/dts/ste-hrefv60plus.dtsi index 8f504edefd3f..e66fa59c2de6 100644 --- a/arch/arm/boot/dts/ste-hrefv60plus.dtsi +++ b/arch/arm/boot/dts/ste-hrefv60plus.dtsi @@ -353,11 +353,11 @@ * Drive DISP1 reset high (not reset), driver DISP2 reset low (reset) */ hrefv60_cfg1 { - pins ="GPIO65_F1"; + pins = "GPIO65_F1"; ste,config = <&gpio_out_hi>; }; hrefv60_cfg2 { - pins ="GPIO66_G3"; + pins = "GPIO66_G3"; ste,config = <&gpio_out_lo>; }; }; diff --git a/arch/arm/boot/dts/ste-ux500-samsung-codina.dts b/arch/arm/boot/dts/ste-ux500-samsung-codina.dts index b6746ac167bc..5f41256d7f4b 100644 --- a/arch/arm/boot/dts/ste-ux500-samsung-codina.dts +++ b/arch/arm/boot/dts/ste-ux500-samsung-codina.dts @@ -598,8 +598,8 @@ reg = <0x19>; vdd-supply = <&ab8500_ldo_aux1_reg>; // 3V vddio-supply = <&ab8500_ldo_aux2_reg>; // 1.8V - mount-matrix = "0", "-1", "0", - "1", "0", "0", + mount-matrix = "0", "1", "0", + "-1", "0", "0", "0", "0", "1"; }; }; diff --git a/arch/arm/boot/dts/ste-ux500-samsung-gavini.dts b/arch/arm/boot/dts/ste-ux500-samsung-gavini.dts index 53062d50e455..806da3fc33cd 100644 --- a/arch/arm/boot/dts/ste-ux500-samsung-gavini.dts +++ b/arch/arm/boot/dts/ste-ux500-samsung-gavini.dts @@ -527,8 +527,8 @@ accelerometer@18 { compatible = "bosch,bma222e"; reg = <0x18>; - mount-matrix = "0", "1", "0", - "-1", "0", "0", + mount-matrix = "0", "-1", "0", + "1", "0", "0", "0", "0", "1"; vddio-supply = <&ab8500_ldo_aux2_reg>; // 1.8V vdd-supply = <&ab8500_ldo_aux1_reg>; // 3V diff --git a/arch/arm/boot/dts/ste-ux500-samsung-janice.dts b/arch/arm/boot/dts/ste-ux500-samsung-janice.dts index e6d4fd0eb5f4..ed5c79c3d04b 100644 --- a/arch/arm/boot/dts/ste-ux500-samsung-janice.dts +++ b/arch/arm/boot/dts/ste-ux500-samsung-janice.dts @@ -633,8 +633,8 @@ accelerometer@8 { compatible = "bosch,bma222"; reg = <0x08>; - mount-matrix = "0", "1", "0", - "-1", "0", "0", + mount-matrix = "0", "-1", "0", + "1", "0", "0", "0", "0", "1"; vddio-supply = <&ab8500_ldo_aux2_reg>; // 1.8V vdd-supply = <&ab8500_ldo_aux1_reg>; // 3V diff --git a/arch/arm/boot/dts/stih407-family.dtsi b/arch/arm/boot/dts/stih407-family.dtsi index 1713f7878117..5ebb77947fd9 100644 --- a/arch/arm/boot/dts/stih407-family.dtsi +++ b/arch/arm/boot/dts/stih407-family.dtsi @@ -137,8 +137,8 @@ }; irq-syscfg { - compatible = "st,stih407-irq-syscfg"; - st,syscfg = <&syscfg_core>; + compatible = "st,stih407-irq-syscfg"; + st,syscfg = <&syscfg_core>; st,irq-device = <ST_IRQ_SYSCFG_PMU_0>, <ST_IRQ_SYSCFG_PMU_1>; st,fiq-device = <ST_IRQ_SYSCFG_DISABLED>, @@ -157,8 +157,8 @@ miphy28lp_phy: miphy28lp { compatible = "st,miphy28lp-phy"; st,syscfg = <&syscfg_core>; - #address-cells = <1>; - #size-cells = <1>; + #address-cells = <1>; + #size-cells = <1>; ranges; phy_port0: port@9b22000 { @@ -208,26 +208,26 @@ }; st231_gp0: st231-gp0 { - compatible = "st,st231-rproc"; - memory-region = <&gp0_reserved>; - resets = <&softreset STIH407_ST231_GP0_SOFTRESET>; - reset-names = "sw_reset"; - clocks = <&clk_s_c0_flexgen CLK_ST231_GP_0>; - clock-frequency = <600000000>; - st,syscfg = <&syscfg_core 0x22c>; + compatible = "st,st231-rproc"; + memory-region = <&gp0_reserved>; + resets = <&softreset STIH407_ST231_GP0_SOFTRESET>; + reset-names = "sw_reset"; + clocks = <&clk_s_c0_flexgen CLK_ST231_GP_0>; + clock-frequency = <600000000>; + st,syscfg = <&syscfg_core 0x22c>; #mbox-cells = <1>; mbox-names = "vq0_rx", "vq0_tx", "vq1_rx", "vq1_tx"; mboxes = <&mailbox0 0 2>, <&mailbox2 0 1>, <&mailbox0 0 3>, <&mailbox2 0 0>; }; st231_delta: st231-delta { - compatible = "st,st231-rproc"; - memory-region = <&delta_reserved>; - resets = <&softreset STIH407_ST231_DMU_SOFTRESET>; - reset-names = "sw_reset"; - clocks = <&clk_s_c0_flexgen CLK_ST231_DMU>; - clock-frequency = <600000000>; - st,syscfg = <&syscfg_core 0x224>; + compatible = "st,st231-rproc"; + memory-region = <&delta_reserved>; + resets = <&softreset STIH407_ST231_DMU_SOFTRESET>; + reset-names = "sw_reset"; + clocks = <&clk_s_c0_flexgen CLK_ST231_DMU>; + clock-frequency = <600000000>; + st,syscfg = <&syscfg_core 0x224>; #mbox-cells = <1>; mbox-names = "vq0_rx", "vq0_tx", "vq1_rx", "vq1_tx"; mboxes = <&mailbox0 0 0>, <&mailbox3 0 1>, <&mailbox0 0 1>, <&mailbox3 0 0>; @@ -710,78 +710,78 @@ st_dwc3: dwc3@8f94000 { - compatible = "st,stih407-dwc3"; - reg = <0x08f94000 0x1000>, <0x110 0x4>; - reg-names = "reg-glue", "syscfg-reg"; - st,syscfg = <&syscfg_core>; - resets = <&powerdown STIH407_USB3_POWERDOWN>, - <&softreset STIH407_MIPHY2_SOFTRESET>; - reset-names = "powerdown", "softreset"; - #address-cells = <1>; - #size-cells = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb3>; + compatible = "st,stih407-dwc3"; + reg = <0x08f94000 0x1000>, <0x110 0x4>; + reg-names = "reg-glue", "syscfg-reg"; + st,syscfg = <&syscfg_core>; + resets = <&powerdown STIH407_USB3_POWERDOWN>, + <&softreset STIH407_MIPHY2_SOFTRESET>; + reset-names = "powerdown", "softreset"; + #address-cells = <1>; + #size-cells = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb3>; ranges; status = "disabled"; - dwc3: dwc3@9900000 { - compatible = "snps,dwc3"; - reg = <0x09900000 0x100000>; - interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; - dr_mode = "host"; - phy-names = "usb2-phy", "usb3-phy"; - phys = <&usb2_picophy0>, - <&phy_port2 PHY_TYPE_USB3>; + dwc3: usb@9900000 { + compatible = "snps,dwc3"; + reg = <0x09900000 0x100000>; + interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; + dr_mode = "host"; + phy-names = "usb2-phy", "usb3-phy"; + phys = <&usb2_picophy0>, + <&phy_port2 PHY_TYPE_USB3>; snps,dis_u3_susphy_quirk; }; }; /* COMMS PWM Module */ pwm0: pwm@9810000 { - compatible = "st,sti-pwm"; - #pwm-cells = <2>; - reg = <0x9810000 0x68>; - interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm0_chan0_default>; - clock-names = "pwm"; - clocks = <&clk_sysin>; + compatible = "st,sti-pwm"; + #pwm-cells = <2>; + reg = <0x9810000 0x68>; + interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm0_chan0_default>; + clock-names = "pwm"; + clocks = <&clk_sysin>; st,pwm-num-chan = <1>; - status = "disabled"; + status = "disabled"; }; /* SBC PWM Module */ pwm1: pwm@9510000 { - compatible = "st,sti-pwm"; - #pwm-cells = <2>; - reg = <0x9510000 0x68>; - interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1_chan0_default - &pinctrl_pwm1_chan1_default - &pinctrl_pwm1_chan2_default - &pinctrl_pwm1_chan3_default>; - clock-names = "pwm"; - clocks = <&clk_sysin>; + compatible = "st,sti-pwm"; + #pwm-cells = <2>; + reg = <0x9510000 0x68>; + interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1_chan0_default + &pinctrl_pwm1_chan1_default + &pinctrl_pwm1_chan2_default + &pinctrl_pwm1_chan3_default>; + clock-names = "pwm"; + clocks = <&clk_sysin>; st,pwm-num-chan = <4>; - status = "disabled"; + status = "disabled"; }; rng10: rng@8a89000 { - compatible = "st,rng"; - reg = <0x08a89000 0x1000>; - clocks = <&clk_sysin>; - status = "okay"; + compatible = "st,rng"; + reg = <0x08a89000 0x1000>; + clocks = <&clk_sysin>; + status = "okay"; }; rng11: rng@8a8a000 { - compatible = "st,rng"; - reg = <0x08a8a000 0x1000>; - clocks = <&clk_sysin>; - status = "okay"; + compatible = "st,rng"; + reg = <0x08a8a000 0x1000>; + clocks = <&clk_sysin>; + status = "okay"; }; ethernet0: dwmac@9630000 { @@ -812,36 +812,36 @@ }; mailbox0: mailbox@8f00000 { - compatible = "st,stih407-mailbox"; - reg = <0x8f00000 0x1000>; - interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; - #mbox-cells = <2>; - mbox-name = "a9"; - status = "okay"; + compatible = "st,stih407-mailbox"; + reg = <0x8f00000 0x1000>; + interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; + #mbox-cells = <2>; + mbox-name = "a9"; + status = "okay"; }; mailbox1: mailbox@8f01000 { - compatible = "st,stih407-mailbox"; - reg = <0x8f01000 0x1000>; - #mbox-cells = <2>; - mbox-name = "st231_gp_1"; - status = "okay"; + compatible = "st,stih407-mailbox"; + reg = <0x8f01000 0x1000>; + #mbox-cells = <2>; + mbox-name = "st231_gp_1"; + status = "okay"; }; mailbox2: mailbox@8f02000 { - compatible = "st,stih407-mailbox"; - reg = <0x8f02000 0x1000>; - #mbox-cells = <2>; - mbox-name = "st231_gp_0"; - status = "okay"; + compatible = "st,stih407-mailbox"; + reg = <0x8f02000 0x1000>; + #mbox-cells = <2>; + mbox-name = "st231_gp_0"; + status = "okay"; }; mailbox3: mailbox@8f03000 { - compatible = "st,stih407-mailbox"; - reg = <0x8f03000 0x1000>; - #mbox-cells = <2>; - mbox-name = "st231_audio_video"; - status = "okay"; + compatible = "st,stih407-mailbox"; + reg = <0x8f03000 0x1000>; + #mbox-cells = <2>; + mbox-name = "st231_audio_video"; + status = "okay"; }; /* fdma audio */ @@ -913,7 +913,7 @@ dmas = <&fdma0 2 0 1>; dma-names = "tx"; - status = "disabled"; + status = "disabled"; }; sti_uni_player1: sti-uni-player@8d81000 { diff --git a/arch/arm/boot/dts/stih407.dtsi b/arch/arm/boot/dts/stih407.dtsi index 9e212b0af89d..aca43d2bdaad 100644 --- a/arch/arm/boot/dts/stih407.dtsi +++ b/arch/arm/boot/dts/stih407.dtsi @@ -13,7 +13,7 @@ #address-cells = <1>; #size-cells = <1>; reg = <0 0>; - assigned-clocks = <&clk_s_d2_quadfs 0>, + assigned-clocks = <&clk_s_d2_quadfs 0>, <&clk_s_d2_quadfs 1>, <&clk_s_c0_pll1 0>, <&clk_s_c0_flexgen CLK_COMPO_DVP>, @@ -106,7 +106,7 @@ reg-names = "hdmi-reg"; #sound-dai-cells = <0>; interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "irq"; + interrupt-names = "irq"; clock-names = "pix", "tmds", "phy", diff --git a/arch/arm/boot/dts/stih410.dtsi b/arch/arm/boot/dts/stih410.dtsi index ce2f62cf129b..a39dd5f7bcae 100644 --- a/arch/arm/boot/dts/stih410.dtsi +++ b/arch/arm/boot/dts/stih410.dtsi @@ -105,7 +105,7 @@ #size-cells = <1>; reg = <0 0>; - assigned-clocks = <&clk_s_d2_quadfs 0>, + assigned-clocks = <&clk_s_d2_quadfs 0>, <&clk_s_d2_quadfs 1>, <&clk_s_c0_pll1 0>, <&clk_s_c0_flexgen CLK_COMPO_DVP>, @@ -198,7 +198,7 @@ reg-names = "hdmi-reg"; #sound-dai-cells = <0>; interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "irq"; + interrupt-names = "irq"; clock-names = "pix", "tmds", "phy", diff --git a/arch/arm/boot/dts/stihxxx-b2120.dtsi b/arch/arm/boot/dts/stihxxx-b2120.dtsi index 4c72dedcd1be..2aa94605d3d4 100644 --- a/arch/arm/boot/dts/stihxxx-b2120.dtsi +++ b/arch/arm/boot/dts/stihxxx-b2120.dtsi @@ -175,11 +175,11 @@ /* tsin0 is TSA on NIMA */ tsin0: port { - tsin-num = <0>; + tsin-num = <0>; serial-not-parallel; - i2c-bus = <&ssc2>; - reset-gpios = <&pio15 4 GPIO_ACTIVE_HIGH>; - dvb-card = <STV0367_TDA18212_NIMA_1>; + i2c-bus = <&ssc2>; + reset-gpios = <&pio15 4 GPIO_ACTIVE_HIGH>; + dvb-card = <STV0367_TDA18212_NIMA_1>; }; }; diff --git a/arch/arm/boot/dts/stm32429i-eval.dts b/arch/arm/boot/dts/stm32429i-eval.dts index 0d98aca01736..3de0e9dbe030 100644 --- a/arch/arm/boot/dts/stm32429i-eval.dts +++ b/arch/arm/boot/dts/stm32429i-eval.dts @@ -251,10 +251,10 @@ &mac { status = "okay"; - pinctrl-0 = <ðernet_mii>; - pinctrl-names = "default"; - phy-mode = "mii"; - phy-handle = <&phy1>; + pinctrl-0 = <ðernet_mii>; + pinctrl-names = "default"; + phy-mode = "mii"; + phy-handle = <&phy1>; mdio0 { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/stm32h743.dtsi b/arch/arm/boot/dts/stm32h743.dtsi index 91dde07a38ba..2059593da21d 100644 --- a/arch/arm/boot/dts/stm32h743.dtsi +++ b/arch/arm/boot/dts/stm32h743.dtsi @@ -375,7 +375,7 @@ arm,primecell-periphid = <0x10153180>; reg = <0x52007000 0x1000>; interrupts = <49>; - interrupt-names = "cmd_irq"; + interrupt-names = "cmd_irq"; clocks = <&rcc SDMMC1_CK>; clock-names = "apb_pclk"; resets = <&rcc STM32H7_AHB3_RESET(SDMMC1)>; @@ -389,7 +389,7 @@ arm,primecell-periphid = <0x10153180>; reg = <0x48022400 0x400>; interrupts = <124>; - interrupt-names = "cmd_irq"; + interrupt-names = "cmd_irq"; clocks = <&rcc SDMMC2_CK>; clock-names = "apb_pclk"; resets = <&rcc STM32H7_AHB2_RESET(SDMMC2)>; diff --git a/arch/arm/boot/dts/stm32h743i-disco.dts b/arch/arm/boot/dts/stm32h743i-disco.dts index 59e01ce10318..2b452883a708 100644 --- a/arch/arm/boot/dts/stm32h743i-disco.dts +++ b/arch/arm/boot/dts/stm32h743i-disco.dts @@ -77,10 +77,10 @@ &mac { status = "disabled"; - pinctrl-0 = <ðernet_rmii>; - pinctrl-names = "default"; - phy-mode = "rmii"; - phy-handle = <&phy0>; + pinctrl-0 = <ðernet_rmii>; + pinctrl-names = "default"; + phy-mode = "rmii"; + phy-handle = <&phy0>; mdio0 { #address-cells = <1>; diff --git a/arch/arm/boot/dts/stm32h743i-eval.dts b/arch/arm/boot/dts/stm32h743i-eval.dts index 38cc7faf6884..5c5d8059bdc7 100644 --- a/arch/arm/boot/dts/stm32h743i-eval.dts +++ b/arch/arm/boot/dts/stm32h743i-eval.dts @@ -115,10 +115,10 @@ &mac { status = "disabled"; - pinctrl-0 = <ðernet_rmii>; - pinctrl-names = "default"; - phy-mode = "rmii"; - phy-handle = <&phy0>; + pinctrl-0 = <ðernet_rmii>; + pinctrl-names = "default"; + phy-mode = "rmii"; + phy-handle = <&phy0>; mdio0 { #address-cells = <1>; diff --git a/arch/arm/boot/dts/stm32h750i-art-pi.dts b/arch/arm/boot/dts/stm32h750i-art-pi.dts index 9bb73bb61901..f3e70d3b65ac 100644 --- a/arch/arm/boot/dts/stm32h750i-art-pi.dts +++ b/arch/arm/boot/dts/stm32h750i-art-pi.dts @@ -126,10 +126,10 @@ &mac { status = "disabled"; - pinctrl-0 = <ðernet_rmii>; - pinctrl-names = "default"; - phy-mode = "rmii"; - phy-handle = <&phy0>; + pinctrl-0 = <ðernet_rmii>; + pinctrl-names = "default"; + phy-mode = "rmii"; + phy-handle = <&phy0>; mdio0 { #address-cells = <1>; diff --git a/arch/arm/boot/dts/stm32mp131.dtsi b/arch/arm/boot/dts/stm32mp131.dtsi index f9ebc47e6421..3a921db23e9f 100644 --- a/arch/arm/boot/dts/stm32mp131.dtsi +++ b/arch/arm/boot/dts/stm32mp131.dtsi @@ -4,6 +4,8 @@ * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. */ #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/stm32mp13-clks.h> +#include <dt-bindings/reset/stm32mp13-resets.h> / { #address-cells = <1>; @@ -27,59 +29,28 @@ interrupt-parent = <&intc>; }; - clocks { - clk_axi: clk-axi { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <266500000>; + firmware { + optee { + method = "smc"; + compatible = "linaro,optee-tz"; }; - clk_hse: clk-hse { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24000000>; - }; - - clk_hsi: clk-hsi { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <64000000>; - }; - - clk_lsi: clk-lsi { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32000>; - }; - - clk_pclk3: clk-pclk3 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <104438965>; - }; - - clk_pclk4: clk-pclk4 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <133250000>; - }; - - clk_pll4_p: clk-pll4_p { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <50000000>; - }; + scmi: scmi { + compatible = "linaro,scmi-optee"; + #address-cells = <1>; + #size-cells = <0>; + linaro,optee-channel-id = <0>; + shmem = <&scmi_shm>; - clk_pll4_r: clk-pll4_r { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <99000000>; - }; + scmi_clk: protocol@14 { + reg = <0x14>; + #clock-cells = <1>; + }; - clk_rtc_k: clk-rtc-k { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; + scmi_reset: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; }; }; @@ -113,11 +84,25 @@ interrupt-parent = <&intc>; ranges; + scmi_sram: sram@2ffff000 { + compatible = "mmio-sram"; + reg = <0x2ffff000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x2ffff000 0x1000>; + + scmi_shm: scmi-sram@0 { + compatible = "arm,scmi-shmem"; + reg = <0 0x80>; + }; + }; + uart4: serial@40010000 { compatible = "st,stm32h7-uart"; reg = <0x40010000 0x400>; interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk_hsi>; + clocks = <&rcc UART4_K>; + resets = <&rcc UART4_R>; status = "disabled"; }; @@ -132,7 +117,8 @@ <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk_pclk4>; + clocks = <&rcc DMA1>; + resets = <&rcc DMA1_R>; #dma-cells = <4>; st,mem2mem; dma-requests = <8>; @@ -149,7 +135,8 @@ <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk_pclk4>; + clocks = <&rcc DMA2>; + resets = <&rcc DMA2_R>; #dma-cells = <4>; st,mem2mem; dma-requests = <8>; @@ -158,13 +145,27 @@ dmamux1: dma-router@48002000 { compatible = "st,stm32h7-dmamux"; reg = <0x48002000 0x40>; - clocks = <&clk_pclk4>; + clocks = <&rcc DMAMUX1>; + resets = <&rcc DMAMUX1_R>; #dma-cells = <3>; dma-masters = <&dma1 &dma2>; dma-requests = <128>; dma-channels = <16>; }; + rcc: rcc@50000000 { + compatible = "st,stm32mp13-rcc", "syscon"; + reg = <0x50000000 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + clock-names = "hse", "hsi", "csi", "lse", "lsi"; + clocks = <&scmi_clk CK_SCMI_HSE>, + <&scmi_clk CK_SCMI_HSI>, + <&scmi_clk CK_SCMI_CSI>, + <&scmi_clk CK_SCMI_LSE>, + <&scmi_clk CK_SCMI_LSI>; + }; + exti: interrupt-controller@5000d000 { compatible = "st,stm32mp13-exti", "syscon"; interrupt-controller; @@ -175,14 +176,14 @@ syscfg: syscon@50020000 { compatible = "st,stm32mp157-syscfg", "syscon"; reg = <0x50020000 0x400>; - clocks = <&clk_pclk3>; + clocks = <&rcc SYSCFG>; }; mdma: dma-controller@58000000 { compatible = "st,stm32h7-mdma"; reg = <0x58000000 0x1000>; interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk_pclk4>; + clocks = <&rcc MDMA>; #dma-cells = <5>; dma-channels = <32>; dma-requests = <48>; @@ -194,8 +195,9 @@ reg = <0x58005000 0x1000>, <0x58006000 0x1000>; interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "cmd_irq"; - clocks = <&clk_pll4_p>; + clocks = <&rcc SDMMC1_K>; clock-names = "apb_pclk"; + resets = <&rcc SDMMC1_R>; cap-sd-highspeed; cap-mmc-highspeed; max-frequency = <130000000>; @@ -208,8 +210,9 @@ reg = <0x58007000 0x1000>, <0x58008000 0x1000>; interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "cmd_irq"; - clocks = <&clk_pll4_p>; + clocks = <&rcc SDMMC2_K>; clock-names = "apb_pclk"; + resets = <&rcc SDMMC2_R>; cap-sd-highspeed; cap-mmc-highspeed; max-frequency = <130000000>; @@ -219,7 +222,7 @@ iwdg2: watchdog@5a002000 { compatible = "st,stm32mp1-iwdg"; reg = <0x5a002000 0x400>; - clocks = <&clk_pclk4>, <&clk_lsi>; + clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>; clock-names = "pclk", "lsi"; status = "disabled"; }; @@ -228,7 +231,8 @@ compatible = "st,stm32mp1-rtc"; reg = <0x5c004000 0x400>; interrupts-extended = <&exti 19 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk_pclk4>, <&clk_rtc_k>; + clocks = <&scmi_clk CK_SCMI_RTCAPB>, + <&scmi_clk CK_SCMI_RTC>; clock-names = "pclk", "rtc_ck"; status = "disabled"; }; @@ -269,7 +273,7 @@ interrupt-controller; #interrupt-cells = <2>; reg = <0x0 0x400>; - clocks = <&clk_pclk4>; + clocks = <&rcc GPIOA>; st,bank-name = "GPIOA"; ngpios = <16>; gpio-ranges = <&pinctrl 0 0 16>; @@ -281,7 +285,7 @@ interrupt-controller; #interrupt-cells = <2>; reg = <0x1000 0x400>; - clocks = <&clk_pclk4>; + clocks = <&rcc GPIOB>; st,bank-name = "GPIOB"; ngpios = <16>; gpio-ranges = <&pinctrl 0 16 16>; @@ -293,7 +297,7 @@ interrupt-controller; #interrupt-cells = <2>; reg = <0x2000 0x400>; - clocks = <&clk_pclk4>; + clocks = <&rcc GPIOC>; st,bank-name = "GPIOC"; ngpios = <16>; gpio-ranges = <&pinctrl 0 32 16>; @@ -305,7 +309,7 @@ interrupt-controller; #interrupt-cells = <2>; reg = <0x3000 0x400>; - clocks = <&clk_pclk4>; + clocks = <&rcc GPIOD>; st,bank-name = "GPIOD"; ngpios = <16>; gpio-ranges = <&pinctrl 0 48 16>; @@ -317,7 +321,7 @@ interrupt-controller; #interrupt-cells = <2>; reg = <0x4000 0x400>; - clocks = <&clk_pclk4>; + clocks = <&rcc GPIOE>; st,bank-name = "GPIOE"; ngpios = <16>; gpio-ranges = <&pinctrl 0 64 16>; @@ -329,7 +333,7 @@ interrupt-controller; #interrupt-cells = <2>; reg = <0x5000 0x400>; - clocks = <&clk_pclk4>; + clocks = <&rcc GPIOF>; st,bank-name = "GPIOF"; ngpios = <16>; gpio-ranges = <&pinctrl 0 80 16>; @@ -341,7 +345,7 @@ interrupt-controller; #interrupt-cells = <2>; reg = <0x6000 0x400>; - clocks = <&clk_pclk4>; + clocks = <&rcc GPIOG>; st,bank-name = "GPIOG"; ngpios = <16>; gpio-ranges = <&pinctrl 0 96 16>; @@ -353,7 +357,7 @@ interrupt-controller; #interrupt-cells = <2>; reg = <0x7000 0x400>; - clocks = <&clk_pclk4>; + clocks = <&rcc GPIOH>; st,bank-name = "GPIOH"; ngpios = <15>; gpio-ranges = <&pinctrl 0 112 15>; @@ -365,7 +369,7 @@ interrupt-controller; #interrupt-cells = <2>; reg = <0x8000 0x400>; - clocks = <&clk_pclk4>; + clocks = <&rcc GPIOI>; st,bank-name = "GPIOI"; ngpios = <8>; gpio-ranges = <&pinctrl 0 128 8>; diff --git a/arch/arm/boot/dts/stm32mp133.dtsi b/arch/arm/boot/dts/stm32mp133.dtsi index 0fb1386257cf..531c263c9f46 100644 --- a/arch/arm/boot/dts/stm32mp133.dtsi +++ b/arch/arm/boot/dts/stm32mp133.dtsi @@ -15,7 +15,7 @@ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "int0", "int1"; - clocks = <&clk_hse>, <&clk_pll4_r>; + clocks = <&scmi_clk CK_SCMI_HSE>, <&rcc FDCAN_K>; clock-names = "hclk", "cclk"; bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>; status = "disabled"; @@ -28,7 +28,7 @@ interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "int0", "int1"; - clocks = <&clk_hse>, <&clk_pll4_r>; + clocks = <&scmi_clk CK_SCMI_HSE>, <&rcc FDCAN_K>; clock-names = "hclk", "cclk"; bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>; status = "disabled"; diff --git a/arch/arm/boot/dts/stm32mp135f-dk.dts b/arch/arm/boot/dts/stm32mp135f-dk.dts index 09d6226d598f..e6b8ffd332c7 100644 --- a/arch/arm/boot/dts/stm32mp135f-dk.dts +++ b/arch/arm/boot/dts/stm32mp135f-dk.dts @@ -26,6 +26,17 @@ reg = <0xc0000000 0x20000000>; }; + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + optee@dd000000 { + reg = <0xdd000000 0x3000000>; + no-map; + }; + }; + gpio-keys { compatible = "gpio-keys"; diff --git a/arch/arm/boot/dts/stm32mp13xc.dtsi b/arch/arm/boot/dts/stm32mp13xc.dtsi index fa6889e30591..4d00e7592882 100644 --- a/arch/arm/boot/dts/stm32mp13xc.dtsi +++ b/arch/arm/boot/dts/stm32mp13xc.dtsi @@ -10,7 +10,8 @@ compatible = "st,stm32mp1-cryp"; reg = <0x54002000 0x400>; interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk_axi>; + clocks = <&rcc CRYP1>; + resets = <&rcc CRYP1_R>; status = "disabled"; }; }; diff --git a/arch/arm/boot/dts/stm32mp13xf.dtsi b/arch/arm/boot/dts/stm32mp13xf.dtsi index fa6889e30591..4d00e7592882 100644 --- a/arch/arm/boot/dts/stm32mp13xf.dtsi +++ b/arch/arm/boot/dts/stm32mp13xf.dtsi @@ -10,7 +10,8 @@ compatible = "st,stm32mp1-cryp"; reg = <0x54002000 0x400>; interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk_axi>; + clocks = <&rcc CRYP1>; + resets = <&rcc CRYP1_R>; status = "disabled"; }; }; diff --git a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi index 6052243ad81c..2cc9341d43d2 100644 --- a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi @@ -151,6 +151,43 @@ }; }; + dcmi_pins_c: dcmi-2 { + pins { + pinmux = <STM32_PINMUX('A', 4, AF13)>,/* DCMI_HSYNC */ + <STM32_PINMUX('B', 7, AF13)>,/* DCMI_VSYNC */ + <STM32_PINMUX('A', 6, AF13)>,/* DCMI_PIXCLK */ + <STM32_PINMUX('A', 9, AF13)>,/* DCMI_D0 */ + <STM32_PINMUX('H', 10, AF13)>,/* DCMI_D1 */ + <STM32_PINMUX('E', 0, AF13)>,/* DCMI_D2 */ + <STM32_PINMUX('E', 1, AF13)>,/* DCMI_D3 */ + <STM32_PINMUX('H', 14, AF13)>,/* DCMI_D4 */ + <STM32_PINMUX('I', 4, AF13)>,/* DCMI_D5 */ + <STM32_PINMUX('I', 6, AF13)>,/* DCMI_D6 */ + <STM32_PINMUX('E', 6, AF13)>,/* DCMI_D7 */ + <STM32_PINMUX('I', 1, AF13)>,/* DCMI_D8 */ + <STM32_PINMUX('H', 7, AF13)>;/* DCMI_D9 */ + bias-pull-up; + }; + }; + + dcmi_sleep_pins_c: dcmi-sleep-2 { + pins { + pinmux = <STM32_PINMUX('A', 4, ANALOG)>,/* DCMI_HSYNC */ + <STM32_PINMUX('B', 7, ANALOG)>,/* DCMI_VSYNC */ + <STM32_PINMUX('A', 6, ANALOG)>,/* DCMI_PIXCLK */ + <STM32_PINMUX('A', 9, ANALOG)>,/* DCMI_D0 */ + <STM32_PINMUX('H', 10, ANALOG)>,/* DCMI_D1 */ + <STM32_PINMUX('E', 0, ANALOG)>,/* DCMI_D2 */ + <STM32_PINMUX('E', 1, ANALOG)>,/* DCMI_D3 */ + <STM32_PINMUX('H', 14, ANALOG)>,/* DCMI_D4 */ + <STM32_PINMUX('I', 4, ANALOG)>,/* DCMI_D5 */ + <STM32_PINMUX('I', 6, ANALOG)>,/* DCMI_D6 */ + <STM32_PINMUX('E', 6, ANALOG)>,/* DCMI_D7 */ + <STM32_PINMUX('I', 1, ANALOG)>,/* DCMI_D8 */ + <STM32_PINMUX('H', 7, ANALOG)>;/* DCMI_D9 */ + }; + }; + ethernet0_rgmii_pins_a: rgmii-0 { pins1 { pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */ @@ -923,6 +960,21 @@ }; }; + mco1_pins_a: mco1-0 { + pins { + pinmux = <STM32_PINMUX('A', 13, AF2)>; /* MCO1 */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + }; + + mco1_sleep_pins_a: mco1-sleep-0 { + pins { + pinmux = <STM32_PINMUX('A', 13, ANALOG)>; /* MCO1 */ + }; + }; + mco2_pins_a: mco2-0 { pins { pinmux = <STM32_PINMUX('G', 2, AF1)>; /* MCO2 */ @@ -978,6 +1030,26 @@ }; }; + m_can1_pins_c: m-can1-2 { + pins1 { + pinmux = <STM32_PINMUX('H', 13, AF9)>; /* CAN1_TX */ + slew-rate = <1>; + drive-push-pull; + bias-disable; + }; + pins2 { + pinmux = <STM32_PINMUX('H', 14, AF9)>; /* CAN1_RX */ + bias-disable; + }; + }; + + m_can1_sleep_pins_c: m_can1-sleep-2 { + pins { + pinmux = <STM32_PINMUX('H', 13, ANALOG)>, /* CAN1_TX */ + <STM32_PINMUX('H', 14, ANALOG)>; /* CAN1_RX */ + }; + }; + m_can2_pins_a: m-can2-0 { pins1 { pinmux = <STM32_PINMUX('B', 13, AF9)>; /* CAN2_TX */ @@ -1794,15 +1866,30 @@ spi2_pins_a: spi2-0 { pins1 { - pinmux = <STM32_PINMUX('B', 10, AF5)>, /* SPI1_SCK */ - <STM32_PINMUX('I', 3, AF5)>; /* SPI1_MOSI */ + pinmux = <STM32_PINMUX('B', 10, AF5)>, /* SPI2_SCK */ + <STM32_PINMUX('I', 3, AF5)>; /* SPI2_MOSI */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + + pins2 { + pinmux = <STM32_PINMUX('I', 2, AF5)>; /* SPI2_MISO */ + bias-disable; + }; + }; + + spi2_pins_b: spi2-1 { + pins1 { + pinmux = <STM32_PINMUX('I', 1, AF5)>, /* SPI2_SCK */ + <STM32_PINMUX('I', 3, AF5)>; /* SPI2_MOSI */ bias-disable; drive-push-pull; slew-rate = <1>; }; pins2 { - pinmux = <STM32_PINMUX('I', 2, AF5)>; /* SPI1_MISO */ + pinmux = <STM32_PINMUX('I', 2, AF5)>; /* SPI2_MISO */ bias-disable; }; }; @@ -1884,6 +1971,49 @@ }; }; + uart4_pins_d: uart4-3 { + pins1 { + pinmux = <STM32_PINMUX('A', 13, AF8)>; /* UART4_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */ + bias-disable; + }; + }; + + uart4_idle_pins_d: uart4-idle-3 { + pins1 { + pinmux = <STM32_PINMUX('A', 13, ANALOG)>; /* UART4_TX */ + }; + pins2 { + pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */ + bias-disable; + }; + }; + + uart4_sleep_pins_d: uart4-sleep-3 { + pins { + pinmux = <STM32_PINMUX('A', 13, ANALOG)>, /* UART4_TX */ + <STM32_PINMUX('B', 2, ANALOG)>; /* UART4_RX */ + }; + }; + + uart5_pins_a: uart5-0 { + pins1 { + pinmux = <STM32_PINMUX('B', 13, AF14)>; /* UART5_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = <STM32_PINMUX('B', 5, AF12)>; /* UART5_RX */ + bias-disable; + }; + }; + uart7_pins_a: uart7-0 { pins1 { pinmux = <STM32_PINMUX('E', 8, AF7)>; /* UART7_TX */ @@ -2183,6 +2313,47 @@ }; }; + usart3_pins_e: usart3-4 { + pins1 { + pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */ + <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = <STM32_PINMUX('B', 11, AF7)>, /* USART3_RX */ + <STM32_PINMUX('D', 11, AF7)>; /* USART3_CTS_NSS */ + bias-pull-up; + }; + }; + + usart3_idle_pins_e: usart3-idle-4 { + pins1 { + pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */ + <STM32_PINMUX('D', 11, ANALOG)>; /* USART3_CTS_NSS */ + }; + pins2 { + pinmux = <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins3 { + pinmux = <STM32_PINMUX('B', 11, AF7)>; /* USART3_RX */ + bias-pull-up; + }; + }; + + usart3_sleep_pins_e: usart3-sleep-4 { + pins { + pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */ + <STM32_PINMUX('G', 8, ANALOG)>, /* USART3_RTS */ + <STM32_PINMUX('D', 11, ANALOG)>, /* USART3_CTS_NSS */ + <STM32_PINMUX('B', 11, ANALOG)>; /* USART3_RX */ + }; + }; + usbotg_hs_pins_a: usbotg-hs-0 { pins { pinmux = <STM32_PINMUX('A', 10, ANALOG)>; /* OTG_ID */ diff --git a/arch/arm/boot/dts/stm32mp151.dtsi b/arch/arm/boot/dts/stm32mp151.dtsi index e04dda5ddd95..742fdeeff4b6 100644 --- a/arch/arm/boot/dts/stm32mp151.dtsi +++ b/arch/arm/boot/dts/stm32mp151.dtsi @@ -1117,10 +1117,9 @@ reg = <0x4c001000 0x400>; st,proc-id = <0>; interrupts-extended = - <&intc GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, - <&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, - <&exti 61 1>; - interrupt-names = "rx", "tx", "wakeup"; + <&exti 61 1>, + <&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "rx", "tx"; clocks = <&rcc IPCC>; wakeup-source; status = "disabled"; diff --git a/arch/arm/boot/dts/stm32mp153c-dhcor-drc-compact.dts b/arch/arm/boot/dts/stm32mp153c-dhcor-drc-compact.dts new file mode 100644 index 000000000000..c8b9818499ea --- /dev/null +++ b/arch/arm/boot/dts/stm32mp153c-dhcor-drc-compact.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) +/* + * Copyright (C) 2022 Marek Vasut <marex@denx.de> + * + * DHCOR STM32MP1 variant: + * DHCR-STM32MP153C-C065-R051-V33-SPI-I-01LG + * DHCOR PCB number: 586-100 or newer + * DRC Compact PCB number: 627-100 or newer + */ + +/dts-v1/; + +#include "stm32mp153.dtsi" +#include "stm32mp15xc.dtsi" +#include "stm32mp15xx-dhcor-som.dtsi" +#include "stm32mp15xx-dhcor-drc-compact.dtsi" + +/ { + model = "DH electronics STM32MP153C DHCOR DRC Compact"; + compatible = "dh,stm32mp153c-dhcor-drc-compact", + "dh,stm32mp153c-dhcor-som", + "st,stm32mp153"; +}; + +&m_can1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&m_can1_pins_c>; + pinctrl-1 = <&m_can1_sleep_pins_c>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi index 76c54b006d87..90933077d66d 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi @@ -126,6 +126,22 @@ }; }; +&dcmi { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&dcmi_pins_c>; + pinctrl-1 = <&dcmi_sleep_pins_c>; + status = "disabled"; + + port { + dcmi_0: endpoint { + remote-endpoint = <&stmipi_2>; + bus-type = <5>; + bus-width = <8>; + pclk-sample = <0>; + }; + }; +}; + ðernet0 { status = "okay"; pinctrl-0 = <ðernet0_rgmii_pins_c>; @@ -219,6 +235,45 @@ }; &i2c4 { + stmipi: stmipi@14 { + compatible = "st,st-mipid02"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&mco1_pins_a>; + pinctrl-1 = <&mco1_sleep_pins_a>; + reg = <0x14>; + clocks = <&rcc CK_MCO1>; + clock-names = "xclk"; + assigned-clocks = <&rcc CK_MCO1>; + assigned-clock-parents = <&rcc CK_HSE>; + assigned-clock-rates = <24000000>; + VDDE-supply = <&v1v8>; + VDDIN-supply = <&v1v8>; + reset-gpios = <&gpioz 0 GPIO_ACTIVE_LOW>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + stmipi_0: endpoint { + }; + }; + + port@2 { + reg = <2>; + stmipi_2: endpoint { + bus-width = <8>; + hsync-active = <0>; + vsync-active = <0>; + pclk-sample = <0>; + remote-endpoint = <&dcmi_0>; + }; + }; + }; + }; + hdmi-transmitter@3d { compatible = "adi,adv7513"; reg = <0x3d>, <0x4d>, <0x2d>, <0x5d>; diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcor-drc-compact.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcor-drc-compact.dtsi new file mode 100644 index 000000000000..27477bb219de --- /dev/null +++ b/arch/arm/boot/dts/stm32mp15xx-dhcor-drc-compact.dtsi @@ -0,0 +1,322 @@ +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) +/* + * Copyright (C) 2022 Marek Vasut <marex@denx.de> + */ + +/ { + aliases { + ethernet0 = ðernet0; + ethernet1 = &ksz8851; + mmc0 = &sdmmc1; + rtc0 = &hwrtc; + rtc1 = &rtc; + serial0 = &uart4; + serial1 = &uart8; + serial2 = &usart3; + serial3 = &uart5; + spi0 = &qspi; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + led { + compatible = "gpio-leds"; + led1 { + label = "yellow:user0"; + gpios = <&gpioz 6 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led2 { + label = "red:user1"; + gpios = <&gpioz 3 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + }; + + ethernet_vio: vioregulator { + compatible = "regulator-fixed"; + regulator-name = "vio"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpioh 2 GPIO_ACTIVE_LOW>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vdd>; + }; +}; + +&adc { /* X11 ADC inputs */ + pinctrl-names = "default"; + pinctrl-0 = <&adc12_ain_pins_b>; + vdd-supply = <&vdd>; + vdda-supply = <&vdda>; + vref-supply = <&vdda>; + status = "okay"; + + adc1: adc@0 { + st,adc-channels = <0 1 6>; + st,min-sample-time-nsecs = <5000>; + status = "okay"; + }; + + adc2: adc@100 { + st,adc-channels = <0 1 2>; + st,min-sample-time-nsecs = <5000>; + status = "okay"; + }; +}; + +ðernet0 { + status = "okay"; + pinctrl-0 = <ðernet0_rgmii_pins_c>; + pinctrl-1 = <ðernet0_rgmii_sleep_pins_c>; + pinctrl-names = "default", "sleep"; + phy-mode = "rgmii"; + max-speed = <1000>; + phy-handle = <&phy0>; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + reset-gpios = <&gpioz 2 GPIO_ACTIVE_LOW>; + reset-delay-us = <1000>; + reset-post-delay-us = <1000>; + + phy0: ethernet-phy@7 { + reg = <7>; + + rxc-skew-ps = <1500>; + rxdv-skew-ps = <540>; + rxd0-skew-ps = <420>; + rxd1-skew-ps = <420>; + rxd2-skew-ps = <420>; + rxd3-skew-ps = <420>; + + txc-skew-ps = <1440>; + txen-skew-ps = <540>; + txd0-skew-ps = <420>; + txd1-skew-ps = <420>; + txd2-skew-ps = <420>; + txd3-skew-ps = <420>; + }; + }; +}; + +&fmc { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&fmc_pins_b>; + pinctrl-1 = <&fmc_sleep_pins_b>; + status = "okay"; + + ksz8851: ethernet@1,0 { + compatible = "micrel,ks8851-mll"; + reg = <1 0x0 0x2>, <1 0x2 0x20000>; + interrupt-parent = <&gpioc>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + bank-width = <2>; + + /* Timing values are in nS */ + st,fmc2-ebi-cs-mux-enable; + st,fmc2-ebi-cs-transaction-type = <4>; + st,fmc2-ebi-cs-buswidth = <16>; + st,fmc2-ebi-cs-address-setup-ns = <5>; + st,fmc2-ebi-cs-address-hold-ns = <5>; + st,fmc2-ebi-cs-bus-turnaround-ns = <5>; + st,fmc2-ebi-cs-data-setup-ns = <45>; + st,fmc2-ebi-cs-data-hold-ns = <1>; + st,fmc2-ebi-cs-write-address-setup-ns = <5>; + st,fmc2-ebi-cs-write-address-hold-ns = <5>; + st,fmc2-ebi-cs-write-bus-turnaround-ns = <5>; + st,fmc2-ebi-cs-write-data-setup-ns = <45>; + st,fmc2-ebi-cs-write-data-hold-ns = <1>; + }; +}; + +&gpioa { + gpio-line-names = "", "", "", "", + "DRCC-VAR2", "", "", "", + "", "", "", "", + "", "", "", ""; +}; + +&gpioe { + gpio-line-names = "", "", "", "", + "", "DRCC-GPIO0", "", "", + "", "", "", "", + "", "", "", ""; +}; + +&gpiog { + gpio-line-names = "", "", "", "", + "", "", "", "", + "", "", "", "", + "DRCC-GPIO5", "", "", ""; +}; + +&gpioh { + gpio-line-names = "", "", "", "DRCC-HW2", + "DRCC-GPIO4", "", "", "", + "DRCC-HW1", "DRCC-HW0", "", "DRCC-VAR1", + "DRCC-VAR0", "", "", "DRCC-GPIO6"; +}; + +&gpioi { + gpio-line-names = "", "", "", "", + "", "", "", "DRCC-GPIO2", + "", "DRCC-GPIO1", "", "", + "", "", "", ""; +}; + +&i2c1 { /* X11 I2C1 */ + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins_b>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; + /delete-property/dmas; + /delete-property/dma-names; +}; + +&i2c4 { + hwrtc: rtc@32 { + compatible = "microcrystal,rv8803"; + reg = <0x32>; + }; + + eeprom@50 { + compatible = "atmel,24c04"; + reg = <0x50>; + pagesize = <16>; + }; +}; + +&sdmmc1 { /* MicroSD */ + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc1_b4_pins_a>; + pinctrl-1 = <&sdmmc1_b4_od_pins_a>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; + cd-gpios = <&gpioi 8 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + disable-wp; + st,neg-edge; + bus-width = <4>; + vmmc-supply = <&vdd>; + vqmmc-supply = <&vdd>; + status = "okay"; +}; + +&sdmmc2 { /* eMMC */ + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_c>; + pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_c>; + pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_c>; + bus-width = <8>; + no-sd; + no-sdio; + non-removable; + st,neg-edge; + vmmc-supply = <&v3v3>; + vqmmc-supply = <&vdd>; + status = "okay"; +}; + +&sdmmc3 { /* SDIO Wi-Fi */ + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc3_b4_pins_a>; + pinctrl-1 = <&sdmmc3_b4_od_pins_a>; + pinctrl-2 = <&sdmmc3_b4_sleep_pins_a>; + broken-cd; + bus-width = <4>; + mmc-ddr-3_3v; + st,neg-edge; + vmmc-supply = <&v3v3>; + vqmmc-supply = <&v3v3>; + status = "okay"; +}; + +&spi2 { /* X11 SPI */ + pinctrl-names = "default"; + pinctrl-0 = <&spi2_pins_b>; + cs-gpios = <&gpioi 0 0>; + status = "disabled"; + /delete-property/dmas; + /delete-property/dma-names; +}; + +&uart4 { + label = "UART0"; + pinctrl-names = "default"; + pinctrl-0 = <&uart4_pins_d>; + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; +}; + +&uart5 { /* X11 UART */ + label = "X11-UART5"; + pinctrl-names = "default"; + pinctrl-0 = <&uart5_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; +}; + +&uart8 { + label = "RS485-1"; + pinctrl-names = "default"; + pinctrl-0 = <&uart8_pins_a &uart8_rtscts_pins_a>; + uart-has-rtscts; + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; +}; + +&usart3 { /* RS485 or RS232 */ + label = "RS485-2"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&usart3_pins_e>; + pinctrl-1 = <&usart3_sleep_pins_e>; + uart-has-rtscts; + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; +}; + +&usbh_ehci { + phys = <&usbphyc_port0>; + status = "okay"; +}; + +&usbh_ohci { + phys = <&usbphyc_port0>; + status = "okay"; +}; + +&usbotg_hs { + dr_mode = "otg"; + pinctrl-0 = <&usbotg_hs_pins_a>; + pinctrl-names = "default"; + phy-names = "usb2-phy"; + phys = <&usbphyc_port1 0>; + vbus-supply = <&vbus_otg>; + status = "okay"; +}; + +&usbphyc { + status = "okay"; +}; + +&usbphyc_port0 { + phy-supply = <&vdd_usb>; + connector { + compatible = "usb-a-connector"; + vbus-supply = <&vbus_sw>; + }; +}; + +&usbphyc_port1 { + phy-supply = <&vdd_usb>; +}; diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcor-io1v8.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcor-io1v8.dtsi index 75172314d7af..9937b28548c2 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dhcor-io1v8.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dhcor-io1v8.dtsi @@ -18,6 +18,11 @@ }; }; +&vdd { + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; +}; + &pwr_regulators { vdd-supply = <&vdd_io>; }; diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi index 6336c3ca0f0e..134a798ad3f2 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi @@ -119,8 +119,8 @@ vdd: buck3 { regulator-name = "vdd"; - regulator-min-microvolt = <2900000>; - regulator-max-microvolt = <2900000>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; regulator-always-on; regulator-initial-mode = <0>; regulator-over-current-protection; diff --git a/arch/arm/boot/dts/stm32mp15xx-osd32.dtsi b/arch/arm/boot/dts/stm32mp15xx-osd32.dtsi index 6706d8311a66..935b7084b5a2 100644 --- a/arch/arm/boot/dts/stm32mp15xx-osd32.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-osd32.dtsi @@ -50,12 +50,6 @@ no-map; }; }; - - reg_sip_eeprom: regulator_eeprom { - compatible = "regulator-fixed"; - regulator-name = "sip_eeprom"; - regulator-always-on; - }; }; &i2c4 { @@ -78,6 +72,7 @@ compatible = "st,stpmic1-regulators"; ldo1-supply = <&v3v3>; + ldo3-supply = <&vdd_ddr>; ldo6-supply = <&v3v3>; pwr_sw1-supply = <&bst_out>; @@ -203,7 +198,7 @@ sip_eeprom: eeprom@50 { compatible = "atmel,24c32"; - vcc-supply = <®_sip_eeprom>; + vcc-supply = <&vdd>; reg = <0x50>; }; }; diff --git a/arch/arm/boot/dts/sun4i-a10-inet9f-rev03.dts b/arch/arm/boot/dts/sun4i-a10-inet9f-rev03.dts index 0a562b2cc5bc..62e7aa587f89 100644 --- a/arch/arm/boot/dts/sun4i-a10-inet9f-rev03.dts +++ b/arch/arm/boot/dts/sun4i-a10-inet9f-rev03.dts @@ -63,7 +63,7 @@ compatible = "gpio-keys-polled"; poll-interval = <20>; - left-joystick-left { + event-left-joystick-left { label = "Left Joystick Left"; linux,code = <ABS_X>; linux,input-type = <EV_ABS>; @@ -71,7 +71,7 @@ gpios = <&pio 0 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA6 */ }; - left-joystick-right { + event-left-joystick-right { label = "Left Joystick Right"; linux,code = <ABS_X>; linux,input-type = <EV_ABS>; @@ -79,7 +79,7 @@ gpios = <&pio 0 5 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA5 */ }; - left-joystick-up { + event-left-joystick-up { label = "Left Joystick Up"; linux,code = <ABS_Y>; linux,input-type = <EV_ABS>; @@ -87,7 +87,7 @@ gpios = <&pio 0 8 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA8 */ }; - left-joystick-down { + event-left-joystick-down { label = "Left Joystick Down"; linux,code = <ABS_Y>; linux,input-type = <EV_ABS>; @@ -95,7 +95,7 @@ gpios = <&pio 0 9 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA9 */ }; - right-joystick-left { + event-right-joystick-left { label = "Right Joystick Left"; linux,code = <ABS_Z>; linux,input-type = <EV_ABS>; @@ -103,7 +103,7 @@ gpios = <&pio 0 1 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA1 */ }; - right-joystick-right { + event-right-joystick-right { label = "Right Joystick Right"; linux,code = <ABS_Z>; linux,input-type = <EV_ABS>; @@ -111,7 +111,7 @@ gpios = <&pio 0 0 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA0 */ }; - right-joystick-up { + event-right-joystick-up { label = "Right Joystick Up"; linux,code = <ABS_RZ>; linux,input-type = <EV_ABS>; @@ -119,7 +119,7 @@ gpios = <&pio 0 3 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA3 */ }; - right-joystick-down { + event-right-joystick-down { label = "Right Joystick Down"; linux,code = <ABS_RZ>; linux,input-type = <EV_ABS>; @@ -127,7 +127,7 @@ gpios = <&pio 0 4 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA4 */ }; - dpad-left { + event-dpad-left { label = "DPad Left"; linux,code = <ABS_HAT0X>; linux,input-type = <EV_ABS>; @@ -135,7 +135,7 @@ gpios = <&pio 7 23 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PH23 */ }; - dpad-right { + event-dpad-right { label = "DPad Right"; linux,code = <ABS_HAT0X>; linux,input-type = <EV_ABS>; @@ -143,7 +143,7 @@ gpios = <&pio 7 24 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PH24 */ }; - dpad-up { + event-dpad-up { label = "DPad Up"; linux,code = <ABS_HAT0Y>; linux,input-type = <EV_ABS>; @@ -151,7 +151,7 @@ gpios = <&pio 7 25 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PH25 */ }; - dpad-down { + event-dpad-down { label = "DPad Down"; linux,code = <ABS_HAT0Y>; linux,input-type = <EV_ABS>; @@ -159,49 +159,49 @@ gpios = <&pio 7 26 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PH26 */ }; - x { + event-x { label = "Button X"; linux,code = <BTN_X>; gpios = <&pio 0 16 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA16 */ }; - y { + event-y { label = "Button Y"; linux,code = <BTN_Y>; gpios = <&pio 0 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA14 */ }; - a { + event-a { label = "Button A"; linux,code = <BTN_A>; gpios = <&pio 0 17 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA17 */ }; - b { + event-b { label = "Button B"; linux,code = <BTN_B>; gpios = <&pio 0 15 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA15 */ }; - select { + event-select { label = "Select Button"; linux,code = <BTN_SELECT>; gpios = <&pio 0 11 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA11 */ }; - start { + event-start { label = "Start Button"; linux,code = <BTN_START>; gpios = <&pio 0 12 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA12 */ }; - top-left { + event-top-left { label = "Top Left Button"; linux,code = <BTN_TL>; gpios = <&pio 7 22 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PH22 */ }; - top-right { + event-top-right { label = "Top Right Button"; linux,code = <BTN_TR>; gpios = <&pio 0 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA13 */ diff --git a/arch/arm/boot/dts/sun4i-a10-pcduino.dts b/arch/arm/boot/dts/sun4i-a10-pcduino.dts index 1ac82376baef..a332d61fd561 100644 --- a/arch/arm/boot/dts/sun4i-a10-pcduino.dts +++ b/arch/arm/boot/dts/sun4i-a10-pcduino.dts @@ -77,19 +77,19 @@ gpio-keys { compatible = "gpio-keys"; - back { + key-back { label = "Key Back"; linux,code = <KEY_BACK>; gpios = <&pio 7 17 GPIO_ACTIVE_LOW>; }; - home { + key-home { label = "Key Home"; linux,code = <KEY_HOME>; gpios = <&pio 7 18 GPIO_ACTIVE_LOW>; }; - menu { + key-menu { label = "Key Menu"; linux,code = <KEY_MENU>; gpios = <&pio 7 19 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/sun5i-a13-licheepi-one.dts b/arch/arm/boot/dts/sun5i-a13-licheepi-one.dts index 2ce361f8fede..3a6c4bd0a44f 100644 --- a/arch/arm/boot/dts/sun5i-a13-licheepi-one.dts +++ b/arch/arm/boot/dts/sun5i-a13-licheepi-one.dts @@ -67,18 +67,18 @@ compatible = "gpio-leds"; led-0 { - label ="licheepi:red:usr"; + label = "licheepi:red:usr"; gpios = <&pio 2 5 GPIO_ACTIVE_LOW>; }; led-1 { - label ="licheepi:green:usr"; + label = "licheepi:green:usr"; gpios = <&pio 2 19 GPIO_ACTIVE_LOW>; default-state = "on"; }; led-2 { - label ="licheepi:blue:usr"; + label = "licheepi:blue:usr"; gpios = <&pio 2 4 GPIO_ACTIVE_LOW>; }; diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi index 715d74854449..70e634b37aae 100644 --- a/arch/arm/boot/dts/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/sun6i-a31.dtsi @@ -46,6 +46,7 @@ #include <dt-bindings/thermal/thermal.h> #include <dt-bindings/clock/sun6i-a31-ccu.h> +#include <dt-bindings/clock/sun6i-rtc.h> #include <dt-bindings/reset/sun6i-a31-ccu.h> / { @@ -598,7 +599,7 @@ ccu: clock@1c20000 { compatible = "allwinner,sun6i-a31-ccu"; reg = <0x01c20000 0x400>; - clocks = <&osc24M>, <&rtc 0>; + clocks = <&osc24M>, <&rtc CLK_OSC32K>; clock-names = "hosc", "losc"; #clock-cells = <1>; #reset-cells = <1>; @@ -612,7 +613,8 @@ <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_APB1_PIO>, <&osc24M>, <&rtc 0>; + clocks = <&ccu CLK_APB1_PIO>, <&osc24M>, + <&rtc CLK_OSC32K>; clock-names = "apb", "hosc", "losc"; gpio-controller; interrupt-controller; @@ -1319,7 +1321,7 @@ ar100: ar100_clk { compatible = "allwinner,sun6i-a31-ar100-clk"; #clock-cells = <0>; - clocks = <&rtc 0>, <&osc24M>, + clocks = <&rtc CLK_OSC32K>, <&osc24M>, <&ccu CLK_PLL_PERIPH>, <&ccu CLK_PLL_PERIPH>; clock-output-names = "ar100"; @@ -1354,7 +1356,7 @@ ir_clk: ir_clk { #clock-cells = <0>; compatible = "allwinner,sun4i-a10-mod0-clk"; - clocks = <&rtc 0>, <&osc24M>; + clocks = <&rtc CLK_OSC32K>, <&osc24M>; clock-output-names = "ir"; }; @@ -1385,7 +1387,7 @@ interrupt-parent = <&r_intc>; interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&apb0_gates 0>, <&osc24M>, <&rtc 0>; + clocks = <&apb0_gates 0>, <&osc24M>, <&rtc CLK_OSC32K>; clock-names = "apb", "hosc", "losc"; resets = <&apb0_rst 0>; gpio-controller; diff --git a/arch/arm/boot/dts/sun7i-a20-pcduino3.dts b/arch/arm/boot/dts/sun7i-a20-pcduino3.dts index 4f8d55d3ba79..928b86a95f34 100644 --- a/arch/arm/boot/dts/sun7i-a20-pcduino3.dts +++ b/arch/arm/boot/dts/sun7i-a20-pcduino3.dts @@ -78,19 +78,19 @@ gpio-keys { compatible = "gpio-keys"; - back { + key-back { label = "Key Back"; linux,code = <KEY_BACK>; gpios = <&pio 7 17 GPIO_ACTIVE_LOW>; }; - home { + key-home { label = "Key Home"; linux,code = <KEY_HOME>; gpios = <&pio 7 18 GPIO_ACTIVE_LOW>; }; - menu { + key-menu { label = "Key Menu"; linux,code = <KEY_MENU>; gpios = <&pio 7 19 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi index 4461d5098b20..1a262a05fdcb 100644 --- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi +++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi @@ -44,6 +44,7 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/sun6i-rtc.h> #include <dt-bindings/clock/sun8i-a23-a33-ccu.h> #include <dt-bindings/reset/sun8i-a23-a33-ccu.h> @@ -329,7 +330,7 @@ ccu: clock@1c20000 { reg = <0x01c20000 0x400>; - clocks = <&osc24M>, <&rtc 0>; + clocks = <&osc24M>, <&rtc CLK_OSC32K>; clock-names = "hosc", "losc"; #clock-cells = <1>; #reset-cells = <1>; @@ -340,7 +341,8 @@ reg = <0x01c20800 0x400>; interrupt-parent = <&r_intc>; /* interrupts get set in SoC specific dtsi file */ - clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>; + clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, + <&rtc CLK_OSC32K>; clock-names = "apb", "hosc", "losc"; gpio-controller; interrupt-controller; @@ -810,7 +812,7 @@ reg = <0x01f02c00 0x400>; interrupt-parent = <&r_intc>; interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&apb0_gates 0>, <&osc24M>, <&rtc 0>; + clocks = <&apb0_gates 0>, <&osc24M>, <&rtc CLK_OSC32K>; clock-names = "apb", "hosc", "losc"; resets = <&apb0_rst 0>; gpio-controller; diff --git a/arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts b/arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts index d5c7b7984d85..d729b7c705db 100644 --- a/arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts +++ b/arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts @@ -47,10 +47,10 @@ }; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; - sw4 { + switch-4 { label = "power"; linux,code = <KEY_POWER>; gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; @@ -106,7 +106,7 @@ wifi_pwrseq: wifi_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ - clocks = <&rtc 1>; + clocks = <&rtc CLK_OSC32K_FANOUT>; clock-names = "ext_clock"; }; }; @@ -181,7 +181,7 @@ bluetooth { compatible = "brcm,bcm43438-bt"; max-speed = <1500000>; - clocks = <&rtc 1>; + clocks = <&rtc CLK_OSC32K_FANOUT>; clock-names = "lpo"; vbat-supply = <®_vcc3v3>; vddio-supply = <®_vcc3v3>; diff --git a/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts b/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts index cd9f655e4f92..27a0d51289dd 100644 --- a/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts +++ b/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts @@ -93,10 +93,10 @@ }; }; - r-gpio-keys { + gpio-keys { compatible = "gpio-keys"; - power { + key-power { label = "power"; linux,code = <KEY_POWER>; gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; @@ -125,7 +125,7 @@ wifi_pwrseq: wifi_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ - clocks = <&rtc 1>; + clocks = <&rtc CLK_OSC32K_FANOUT>; clock-names = "ext_clock"; }; }; diff --git a/arch/arm/boot/dts/sun8i-h3-mapleboard-mp130.dts b/arch/arm/boot/dts/sun8i-h3-mapleboard-mp130.dts index ff0a7a952e0c..f5c8ccc5b872 100644 --- a/arch/arm/boot/dts/sun8i-h3-mapleboard-mp130.dts +++ b/arch/arm/boot/dts/sun8i-h3-mapleboard-mp130.dts @@ -39,16 +39,16 @@ }; }; - r_gpio_keys { + gpio-keys { compatible = "gpio-keys"; - power { + key-power { label = "power"; linux,code = <KEY_POWER>; gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; /* PL3 */ }; - user { + key-user { label = "user"; linux,code = <BTN_0>; gpios = <&r_pio 0 4 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-duo2.dts b/arch/arm/boot/dts/sun8i-h3-nanopi-duo2.dts index 8e7dfcffe1fb..43641cb82398 100644 --- a/arch/arm/boot/dts/sun8i-h3-nanopi-duo2.dts +++ b/arch/arm/boot/dts/sun8i-h3-nanopi-duo2.dts @@ -37,10 +37,10 @@ }; }; - r_gpio_keys { + gpio-keys { compatible = "gpio-keys"; - k1 { + key-0 { label = "k1"; linux,code = <BTN_0>; gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; /* PL3 */ @@ -90,7 +90,7 @@ wifi_pwrseq: wifi_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ - clocks = <&rtc 1>; + clocks = <&rtc CLK_OSC32K_FANOUT>; clock-names = "ext_clock"; }; @@ -151,7 +151,7 @@ bluetooth { compatible = "brcm,bcm43438-bt"; - clocks = <&rtc 1>; + clocks = <&rtc CLK_OSC32K_FANOUT>; clock-names = "lpo"; vbat-supply = <®_vcc3v3>; vddio-supply = <®_vcc3v3>; diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-neo-air.dts b/arch/arm/boot/dts/sun8i-h3-nanopi-neo-air.dts index cd3df12b6573..9e1a33f94cad 100644 --- a/arch/arm/boot/dts/sun8i-h3-nanopi-neo-air.dts +++ b/arch/arm/boot/dts/sun8i-h3-nanopi-neo-air.dts @@ -127,7 +127,7 @@ bluetooth { compatible = "brcm,bcm43438-bt"; - clocks = <&rtc 1>; + clocks = <&rtc CLK_OSC32K_FANOUT>; clock-names = "lpo"; vbat-supply = <®_vcc3v3>; vddio-supply = <®_vcc3v3>; diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-r1.dts b/arch/arm/boot/dts/sun8i-h3-nanopi-r1.dts index 26e2e6172e0d..42cd1131adf3 100644 --- a/arch/arm/boot/dts/sun8i-h3-nanopi-r1.dts +++ b/arch/arm/boot/dts/sun8i-h3-nanopi-r1.dts @@ -46,7 +46,7 @@ wifi_pwrseq: wifi_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ - clocks = <&rtc 1>; + clocks = <&rtc CLK_OSC32K_FANOUT>; clock-names = "ext_clock"; }; @@ -147,7 +147,7 @@ bluetooth { compatible = "brcm,bcm43438-bt"; - clocks = <&rtc 1>; + clocks = <&rtc CLK_OSC32K_FANOUT>; clock-names = "lpo"; vbat-supply = <®_vcc3v3>; vddio-supply = <®_vcc3v3>; diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi.dtsi b/arch/arm/boot/dts/sun8i-h3-nanopi.dtsi index a9f749f49beb..cf8413fba6c1 100644 --- a/arch/arm/boot/dts/sun8i-h3-nanopi.dtsi +++ b/arch/arm/boot/dts/sun8i-h3-nanopi.dtsi @@ -73,10 +73,10 @@ }; }; - r_gpio_keys { + gpio-keys { compatible = "gpio-keys"; - k1 { + key-0 { label = "k1"; linux,code = <KEY_POWER>; gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts index 9daffd90c12f..f1f9dbead32a 100644 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts @@ -88,16 +88,16 @@ }; }; - r_gpio_keys { + gpio-keys { compatible = "gpio-keys"; - sw2 { + switch-2 { label = "sw2"; linux,code = <BTN_1>; gpios = <&r_pio 0 4 GPIO_ACTIVE_LOW>; }; - sw4 { + switch-4 { label = "sw4"; linux,code = <KEY_POWER>; gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-lite.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-lite.dts index 6f9c97add54e..305b34a321f5 100644 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-lite.dts +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-lite.dts @@ -87,10 +87,10 @@ }; }; - r_gpio_keys { + gpio-keys { compatible = "gpio-keys"; - sw4 { + switch-4 { label = "sw4"; linux,code = <BTN_0>; gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts index 4759ba3f2986..59f6f6d5e7ca 100644 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts @@ -86,10 +86,10 @@ }; }; - r_gpio_keys { + gpio-keys { compatible = "gpio-keys"; - sw4 { + switch-4 { label = "sw4"; linux,code = <BTN_0>; gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts index 90f75fa85e68..b96e015f54ee 100644 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts @@ -86,10 +86,10 @@ }; }; - r_gpio_keys { + gpio-keys { compatible = "gpio-keys"; - sw4 { + switch-4 { label = "sw4"; linux,code = <KEY_POWER>; gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/sun8i-r16-bananapi-m2m.dts b/arch/arm/boot/dts/sun8i-r16-bananapi-m2m.dts index bf5b5e2f6168..bc394686fedb 100644 --- a/arch/arm/boot/dts/sun8i-r16-bananapi-m2m.dts +++ b/arch/arm/boot/dts/sun8i-r16-bananapi-m2m.dts @@ -91,7 +91,7 @@ wifi_pwrseq: wifi_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&r_pio 0 6 GPIO_ACTIVE_LOW>; /* PL06 */ - clocks = <&rtc 1>; + clocks = <&rtc CLK_OSC32K_FANOUT>; clock-names = "ext_clock"; }; }; @@ -283,7 +283,7 @@ bluetooth { compatible = "brcm,bcm43438-bt"; - clocks = <&rtc 1>; + clocks = <&rtc CLK_OSC32K_FANOUT>; clock-names = "lpo"; vbat-supply = <®_dldo1>; vddio-supply = <®_aldo3>; diff --git a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts index a6a1087a0c9b..28197bbcb1d5 100644 --- a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts +++ b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts @@ -43,6 +43,7 @@ /dts-v1/; #include "sun8i-r40.dtsi" +#include "sun8i-r40-cpu-opp.dtsi" #include <dt-bindings/gpio/gpio.h> @@ -113,6 +114,10 @@ status = "okay"; }; +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + &de { status = "okay"; }; diff --git a/arch/arm/boot/dts/sun8i-r40-cpu-opp.dtsi b/arch/arm/boot/dts/sun8i-r40-cpu-opp.dtsi new file mode 100644 index 000000000000..649928b361af --- /dev/null +++ b/arch/arm/boot/dts/sun8i-r40-cpu-opp.dtsi @@ -0,0 +1,52 @@ +/{ + cpu0_opp_table: opp-table-cpu { + compatible = "operating-points-v2"; + opp-shared; + + opp-720000000 { + opp-hz = /bits/ 64 <720000000>; + opp-microvolt = <1000000 1000000 1300000>; + clock-latency-ns = <2000000>; + }; + + opp-912000000 { + opp-hz = /bits/ 64 <912000000>; + opp-microvolt = <1100000 1100000 1300000>; + clock-latency-ns = <2000000>; + }; + + opp-1008000000 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <1160000 1160000 1300000>; + clock-latency-ns = <2000000>; + }; + + opp-1104000000 { + opp-hz = /bits/ 64 <1104000000>; + opp-microvolt = <1240000 1240000 1300000>; + clock-latency-ns = <2000000>; + }; + + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1300000 1300000 1300000>; + clock-latency-ns = <2000000>; + }; + }; +}; + +&cpu0 { + operating-points-v2 = <&cpu0_opp_table>; +}; + +&cpu1 { + operating-points-v2 = <&cpu0_opp_table>; +}; + +&cpu2 { + operating-points-v2 = <&cpu0_opp_table>; +}; + +&cpu3 { + operating-points-v2 = <&cpu0_opp_table>; +}; diff --git a/arch/arm/boot/dts/sun8i-r40-feta40i.dtsi b/arch/arm/boot/dts/sun8i-r40-feta40i.dtsi index 265e0fa57a32..9f39b5a2bb35 100644 --- a/arch/arm/boot/dts/sun8i-r40-feta40i.dtsi +++ b/arch/arm/boot/dts/sun8i-r40-feta40i.dtsi @@ -5,6 +5,11 @@ // Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io> #include "sun8i-r40.dtsi" +#include "sun8i-r40-cpu-opp.dtsi" + +&cpu0 { + cpu-supply = <®_dcdc2>; +}; &i2c0 { status = "okay"; diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi index 03d3e5f45a09..4ef26d8f5340 100644 --- a/arch/arm/boot/dts/sun8i-r40.dtsi +++ b/arch/arm/boot/dts/sun8i-r40.dtsi @@ -42,6 +42,7 @@ */ #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/sun6i-rtc.h> #include <dt-bindings/clock/sun8i-de2.h> #include <dt-bindings/clock/sun8i-r40-ccu.h> #include <dt-bindings/clock/sun8i-tcon-top.h> @@ -84,24 +85,36 @@ compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <0>; + clocks = <&ccu CLK_CPU>; + clock-names = "cpu"; + #cooling-cells = <2>; }; cpu1: cpu@1 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <1>; + clocks = <&ccu CLK_CPU>; + clock-names = "cpu"; + #cooling-cells = <2>; }; cpu2: cpu@2 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <2>; + clocks = <&ccu CLK_CPU>; + clock-names = "cpu"; + #cooling-cells = <2>; }; cpu3: cpu@3 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <3>; + clocks = <&ccu CLK_CPU>; + clock-names = "cpu"; + #cooling-cells = <2>; }; }; @@ -117,6 +130,30 @@ polling-delay-passive = <0>; polling-delay = <0>; thermal-sensors = <&ths 0>; + + trips { + cpu_hot_trip: cpu-hot { + temperature = <80000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_very_hot_trip: cpu-very-hot { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + cpu-hot-limit { + trip = <&cpu_hot_trip>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; gpu_thermal: gpu-thermal { @@ -485,7 +522,7 @@ ccu: clock@1c20000 { compatible = "allwinner,sun8i-r40-ccu"; reg = <0x01c20000 0x400>; - clocks = <&osc24M>, <&rtc 0>; + clocks = <&osc24M>, <&rtc CLK_OSC32K>; clock-names = "hosc", "losc"; #clock-cells = <1>; #reset-cells = <1>; @@ -504,7 +541,8 @@ compatible = "allwinner,sun8i-r40-pinctrl"; reg = <0x01c20800 0x400>; interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>; + clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, + <&rtc CLK_OSC32K>; clock-names = "apb", "hosc", "losc"; gpio-controller; interrupt-controller; @@ -1231,7 +1269,7 @@ reg-io-width = <1>; interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_BUS_HDMI0>, <&ccu CLK_HDMI_SLOW>, - <&ccu CLK_HDMI>, <&rtc 0>; + <&ccu CLK_HDMI>, <&rtc CLK_OSC32K>; clock-names = "iahb", "isfr", "tmds", "cec"; resets = <&ccu RST_BUS_HDMI1>; reset-names = "ctrl"; diff --git a/arch/arm/boot/dts/sun8i-t3-cqa3t-bv3.dts b/arch/arm/boot/dts/sun8i-t3-cqa3t-bv3.dts index 6931aaab2382..9f472521f4a4 100644 --- a/arch/arm/boot/dts/sun8i-t3-cqa3t-bv3.dts +++ b/arch/arm/boot/dts/sun8i-t3-cqa3t-bv3.dts @@ -45,6 +45,7 @@ /dts-v1/; #include "sun8i-r40.dtsi" +#include "sun8i-r40-cpu-opp.dtsi" #include <dt-bindings/gpio/gpio.h> @@ -88,6 +89,10 @@ status = "okay"; }; +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + &de { status = "okay"; }; diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi index 084323d5c61c..db194c606fdc 100644 --- a/arch/arm/boot/dts/sun8i-v3s.dtsi +++ b/arch/arm/boot/dts/sun8i-v3s.dtsi @@ -42,6 +42,7 @@ */ #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/sun6i-rtc.h> #include <dt-bindings/clock/sun8i-v3s-ccu.h> #include <dt-bindings/reset/sun8i-v3s-ccu.h> #include <dt-bindings/clock/sun8i-de2.h> @@ -321,7 +322,7 @@ ccu: clock@1c20000 { compatible = "allwinner,sun8i-v3s-ccu"; reg = <0x01c20000 0x400>; - clocks = <&osc24M>, <&rtc 0>; + clocks = <&osc24M>, <&rtc CLK_OSC32K>; clock-names = "hosc", "losc"; #clock-cells = <1>; #reset-cells = <1>; @@ -342,7 +343,8 @@ reg = <0x01c20800 0x400>; interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>; + clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, + <&rtc CLK_OSC32K>; clock-names = "apb", "hosc", "losc"; gpio-controller; #gpio-cells = <3>; diff --git a/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts b/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts index 47954551f573..434871040aca 100644 --- a/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts +++ b/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts @@ -42,6 +42,7 @@ /dts-v1/; #include "sun8i-r40.dtsi" +#include "sun8i-r40-cpu-opp.dtsi" #include <dt-bindings/gpio/gpio.h> @@ -107,6 +108,10 @@ status = "okay"; }; +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + &de { status = "okay"; }; diff --git a/arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi b/arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi index d03f5853ef7b..e899d14f38c3 100644 --- a/arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi +++ b/arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi @@ -77,10 +77,10 @@ }; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; - sw4 { + switch-4 { label = "power"; linux,code = <KEY_POWER>; gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; @@ -101,7 +101,7 @@ wifi_pwrseq: wifi_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ - clocks = <&rtc 1>; + clocks = <&rtc CLK_OSC32K_FANOUT>; clock-names = "ext_clock"; }; }; @@ -221,7 +221,7 @@ bluetooth { compatible = "brcm,bcm43438-bt"; max-speed = <1500000>; - clocks = <&rtc 1>; + clocks = <&rtc CLK_OSC32K_FANOUT>; clock-names = "lpo"; vbat-supply = <®_vcc3v3>; vddio-supply = <®_vcc3v3>; diff --git a/arch/arm/boot/dts/sunxi-h3-h5-emlid-neutis.dtsi b/arch/arm/boot/dts/sunxi-h3-h5-emlid-neutis.dtsi index fc67e30fe212..60804b0e6c56 100644 --- a/arch/arm/boot/dts/sunxi-h3-h5-emlid-neutis.dtsi +++ b/arch/arm/boot/dts/sunxi-h3-h5-emlid-neutis.dtsi @@ -22,7 +22,7 @@ compatible = "mmc-pwrseq-simple"; reset-gpios = <&pio 2 7 GPIO_ACTIVE_LOW>; /* PC7 */ post-power-on-delay-ms = <200>; - clocks = <&rtc 1>; + clocks = <&rtc CLK_OSC32K_FANOUT>; clock-names = "ext_clock"; }; }; @@ -124,7 +124,7 @@ bluetooth { compatible = "brcm,bcm43438-bt"; - clocks = <&rtc 1>; + clocks = <&rtc CLK_OSC32K_FANOUT>; clock-names = "lpo"; vbat-supply = <®_vcc3v3>; vddio-supply = <®_vcc3v3>; diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi index d7e9f977f986..09aefb4e90f8 100644 --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi @@ -40,6 +40,7 @@ * OTHER DEALINGS IN THE SOFTWARE. */ +#include <dt-bindings/clock/sun6i-rtc.h> #include <dt-bindings/clock/sun8i-de2.h> #include <dt-bindings/clock/sun8i-h3-ccu.h> #include <dt-bindings/clock/sun8i-r-ccu.h> @@ -386,7 +387,7 @@ ccu: clock@1c20000 { /* compatible is in per SoC .dtsi file */ reg = <0x01c20000 0x400>; - clocks = <&osc24M>, <&rtc 0>; + clocks = <&osc24M>, <&rtc CLK_OSC32K>; clock-names = "hosc", "losc"; #clock-cells = <1>; #reset-cells = <1>; @@ -398,7 +399,8 @@ interrupt-parent = <&r_intc>; interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>; + clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, + <&rtc CLK_OSC32K>; clock-names = "apb", "hosc", "losc"; gpio-controller; #gpio-cells = <3>; @@ -818,7 +820,7 @@ reg-io-width = <1>; interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>, - <&ccu CLK_HDMI>, <&rtc 0>; + <&ccu CLK_HDMI>, <&rtc CLK_OSC32K>; clock-names = "iahb", "isfr", "tmds", "cec"; resets = <&ccu RST_BUS_HDMI1>; reset-names = "ctrl"; @@ -878,7 +880,7 @@ r_ccu: clock@1f01400 { compatible = "allwinner,sun8i-h3-r-ccu"; reg = <0x01f01400 0x100>; - clocks = <&osc24M>, <&rtc 0>, <&rtc 2>, + clocks = <&osc24M>, <&rtc CLK_OSC32K>, <&rtc CLK_IOSC>, <&ccu CLK_PLL_PERIPH0>; clock-names = "hosc", "losc", "iosc", "pll-periph"; #clock-cells = <1>; @@ -931,7 +933,8 @@ reg = <0x01f02c00 0x400>; interrupt-parent = <&r_intc>; interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&rtc 0>; + clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, + <&rtc CLK_OSC32K>; clock-names = "apb", "hosc", "losc"; gpio-controller; #gpio-cells = <3>; diff --git a/arch/arm/boot/dts/sunxi-libretech-all-h3-cc.dtsi b/arch/arm/boot/dts/sunxi-libretech-all-h3-cc.dtsi index 9e14fe5fdcde..89731bb34c6b 100644 --- a/arch/arm/boot/dts/sunxi-libretech-all-h3-cc.dtsi +++ b/arch/arm/boot/dts/sunxi-libretech-all-h3-cc.dtsi @@ -42,10 +42,10 @@ }; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; - power { + key-power { label = "power"; linux,code = <KEY_POWER>; gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */ diff --git a/arch/arm/boot/dts/tegra114-asus-tf701t.dts b/arch/arm/boot/dts/tegra114-asus-tf701t.dts index b791ce97424b..284209b0bd96 100644 --- a/arch/arm/boot/dts/tegra114-asus-tf701t.dts +++ b/arch/arm/boot/dts/tegra114-asus-tf701t.dts @@ -684,7 +684,7 @@ pinctrl-names = "default"; pinctrl-0 = <&gpio_keys_default>; - power { + button-power { label = "Power"; gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; linux,code = <KEY_POWER>; @@ -692,14 +692,14 @@ wakeup-source; }; - volume-up { + button-volume-up { label = "Volume Up"; gpios = <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_LOW>; linux,code = <KEY_VOLUMEUP>; debounce-interval = <10>; }; - volume-down { + button-volume-down { label = "Volume Down"; gpios = <&gpio TEGRA_GPIO(R, 1) GPIO_ACTIVE_LOW>; linux,code = <KEY_VOLUMEDOWN>; @@ -715,7 +715,7 @@ pinctrl-names = "default"; pinctrl-0 = <&gpio_hall_sensor_default>; - hall-sensor { + switch-hall-sensor { label = "Hall Effect Sensor"; gpios = <&gpio TEGRA_GPIO(O, 5) GPIO_ACTIVE_LOW>; linux,input-type = <EV_SW>; diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts b/arch/arm/boot/dts/tegra114-dalmore.dts index 658edfb8d7fa..fffd62bcea6a 100644 --- a/arch/arm/boot/dts/tegra114-dalmore.dts +++ b/arch/arm/boot/dts/tegra114-dalmore.dts @@ -1161,26 +1161,26 @@ gpio-keys { compatible = "gpio-keys"; - home { + key-home { label = "Home"; gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; linux,code = <KEY_HOME>; }; - power { + key-power { label = "Power"; gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; linux,code = <KEY_POWER>; wakeup-source; }; - volume_down { + key-volume-down { label = "Volume Down"; gpios = <&gpio TEGRA_GPIO(R, 1) GPIO_ACTIVE_LOW>; linux,code = <KEY_VOLUMEDOWN>; }; - volume_up { + key-volume-up { label = "Volume Up"; gpios = <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_LOW>; linux,code = <KEY_VOLUMEUP>; diff --git a/arch/arm/boot/dts/tegra114-roth.dts b/arch/arm/boot/dts/tegra114-roth.dts index 2498cf18fd39..b9d00009d1f4 100644 --- a/arch/arm/boot/dts/tegra114-roth.dts +++ b/arch/arm/boot/dts/tegra114-roth.dts @@ -1025,19 +1025,19 @@ gpio-keys { compatible = "gpio-keys"; - back { + key-back { label = "Back"; gpios = <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_LOW>; linux,code = <KEY_BACK>; }; - home { + key-home { label = "Home"; gpios = <&gpio TEGRA_GPIO(R, 1) GPIO_ACTIVE_LOW>; linux,code = <KEY_HOME>; }; - power { + key-power { label = "Power"; gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; linux,code = <KEY_POWER>; diff --git a/arch/arm/boot/dts/tegra114-tn7.dts b/arch/arm/boot/dts/tegra114-tn7.dts index ef8f722dd9cb..f02d8c79eee7 100644 --- a/arch/arm/boot/dts/tegra114-tn7.dts +++ b/arch/arm/boot/dts/tegra114-tn7.dts @@ -282,20 +282,20 @@ gpio-keys { compatible = "gpio-keys"; - power { + key-power { label = "Power"; gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; linux,code = <KEY_POWER>; wakeup-source; }; - volume_down { + key-volume-down { label = "Volume Down"; gpios = <&gpio TEGRA_GPIO(Q, 2) GPIO_ACTIVE_LOW>; linux,code = <KEY_VOLUMEDOWN>; }; - volume_up { + key-volume-up { label = "Volume Up"; gpios = <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_LOW>; linux,code = <KEY_VOLUMEUP>; diff --git a/arch/arm/boot/dts/tegra124-apalis-eval.dts b/arch/arm/boot/dts/tegra124-apalis-eval.dts index 3209554ec7e6..bce12b3411fc 100644 --- a/arch/arm/boot/dts/tegra124-apalis-eval.dts +++ b/arch/arm/boot/dts/tegra124-apalis-eval.dts @@ -191,7 +191,7 @@ gpio-keys { compatible = "gpio-keys"; - wakeup { + key-wakeup { label = "WAKE1_MICO"; gpios = <&gpio TEGRA_GPIO(DD, 3) GPIO_ACTIVE_LOW>; linux,code = <KEY_WAKEUP>; diff --git a/arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts b/arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts index 814257c79bf1..800283ad6bdc 100644 --- a/arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts +++ b/arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts @@ -193,7 +193,7 @@ gpio-keys { compatible = "gpio-keys"; - wakeup { + key-wakeup { label = "WAKE1_MICO"; gpios = <&gpio TEGRA_GPIO(DD, 3) GPIO_ACTIVE_LOW>; linux,code = <KEY_WAKEUP>; diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/tegra124-jetson-tk1.dts index 28b889e4e33b..f41dd4039c07 100644 --- a/arch/arm/boot/dts/tegra124-jetson-tk1.dts +++ b/arch/arm/boot/dts/tegra124-jetson-tk1.dts @@ -1886,7 +1886,7 @@ gpio-keys { compatible = "gpio-keys"; - power { + key-power { label = "Power"; gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; linux,code = <KEY_POWER>; diff --git a/arch/arm/boot/dts/tegra124-nyan.dtsi b/arch/arm/boot/dts/tegra124-nyan.dtsi index a93cfb492ba1..13061ab5247b 100644 --- a/arch/arm/boot/dts/tegra124-nyan.dtsi +++ b/arch/arm/boot/dts/tegra124-nyan.dtsi @@ -603,7 +603,7 @@ gpio-keys { compatible = "gpio-keys"; - lid { + switch-lid { label = "Lid"; gpios = <&gpio TEGRA_GPIO(R, 4) GPIO_ACTIVE_LOW>; linux,input-type = <5>; @@ -612,7 +612,7 @@ wakeup-source; }; - power { + key-power { label = "Power"; gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; linux,code = <KEY_POWER>; diff --git a/arch/arm/boot/dts/tegra124-venice2.dts b/arch/arm/boot/dts/tegra124-venice2.dts index 6a9592ceb5f2..8f40fcfc11b0 100644 --- a/arch/arm/boot/dts/tegra124-venice2.dts +++ b/arch/arm/boot/dts/tegra124-venice2.dts @@ -1078,7 +1078,7 @@ gpio-keys { compatible = "gpio-keys"; - power { + key-power { label = "Power"; gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; linux,code = <KEY_POWER>; diff --git a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts index a170a4ba36c1..dac6d02a1b15 100644 --- a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts +++ b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts @@ -417,7 +417,7 @@ vddio-supply = <&vdd_1v8_sys>; device-wakeup-gpios = <&gpio TEGRA_GPIO(U, 1) GPIO_ACTIVE_HIGH>; - shutdown-gpios = <&gpio TEGRA_GPIO(U, 0) GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio TEGRA_GPIO(U, 0) GPIO_ACTIVE_HIGH>; }; }; @@ -905,7 +905,7 @@ gpio-keys { compatible = "gpio-keys"; - power { + key-power { label = "Power"; gpios = <&gpio TEGRA_GPIO(I, 3) GPIO_ACTIVE_HIGH>; linux,code = <KEY_POWER>; @@ -914,7 +914,7 @@ wakeup-source; }; - rotation-lock { + key-rotation-lock { label = "Rotate-lock"; gpios = <&gpio TEGRA_GPIO(Q, 2) GPIO_ACTIVE_HIGH>; linux,code = <SW_ROTATE_LOCK>; @@ -922,7 +922,7 @@ debounce-interval = <10>; }; - volume-up { + key-volume-up { label = "Volume Up"; gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>; linux,code = <KEY_VOLUMEUP>; @@ -931,7 +931,7 @@ wakeup-source; }; - volume-down { + key-volume-down { label = "Volume Down"; gpios = <&gpio TEGRA_GPIO(Q, 5) GPIO_ACTIVE_LOW>; linux,code = <KEY_VOLUMEDOWN>; diff --git a/arch/arm/boot/dts/tegra20-asus-tf101.dts b/arch/arm/boot/dts/tegra20-asus-tf101.dts index a054d39db466..bf797a1f27ea 100644 --- a/arch/arm/boot/dts/tegra20-asus-tf101.dts +++ b/arch/arm/boot/dts/tegra20-asus-tf101.dts @@ -477,7 +477,7 @@ vddio-supply = <&vdd_1v8_sys>; device-wakeup-gpios = <&gpio TEGRA_GPIO(U, 1) GPIO_ACTIVE_HIGH>; - shutdown-gpios = <&gpio TEGRA_GPIO(U, 0) GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio TEGRA_GPIO(U, 0) GPIO_ACTIVE_HIGH>; }; }; @@ -980,7 +980,7 @@ gpio-keys { compatible = "gpio-keys"; - dock-hall-sensor { + switch-dock-hall-sensor { label = "Lid"; gpios = <&gpio TEGRA_GPIO(S, 4) GPIO_ACTIVE_LOW>; linux,input-type = <EV_SW>; @@ -990,7 +990,7 @@ wakeup-source; }; - power { + key-power { label = "Power"; gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; linux,code = <KEY_POWER>; @@ -999,7 +999,7 @@ wakeup-source; }; - volume-up { + key-volume-up { label = "Volume Up"; gpios = <&gpio TEGRA_GPIO(Q, 5) GPIO_ACTIVE_LOW>; linux,code = <KEY_VOLUMEUP>; @@ -1008,7 +1008,7 @@ wakeup-source; }; - volume-down { + key-volume-down { label = "Volume Down"; gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>; linux,code = <KEY_VOLUMEDOWN>; diff --git a/arch/arm/boot/dts/tegra20-colibri-eval-v3.dts b/arch/arm/boot/dts/tegra20-colibri-eval-v3.dts index d2a3bf9d28bd..cb1190b77db3 100644 --- a/arch/arm/boot/dts/tegra20-colibri-eval-v3.dts +++ b/arch/arm/boot/dts/tegra20-colibri-eval-v3.dts @@ -209,7 +209,7 @@ gpio-keys { compatible = "gpio-keys"; - wakeup { + key-wakeup { label = "SODIMM pin 45 wakeup"; gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_HIGH>; linux,code = <KEY_WAKEUP>; diff --git a/arch/arm/boot/dts/tegra20-colibri-iris.dts b/arch/arm/boot/dts/tegra20-colibri-iris.dts index 00ecbbd5e9e1..53487cc21513 100644 --- a/arch/arm/boot/dts/tegra20-colibri-iris.dts +++ b/arch/arm/boot/dts/tegra20-colibri-iris.dts @@ -191,7 +191,7 @@ gpio-keys { compatible = "gpio-keys"; - wakeup { + key-wakeup { label = "SODIMM pin 45 wakeup"; gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_HIGH>; linux,code = <KEY_WAKEUP>; diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts index 79b6b79fab65..11f21aeba8e9 100644 --- a/arch/arm/boot/dts/tegra20-harmony.dts +++ b/arch/arm/boot/dts/tegra20-harmony.dts @@ -648,7 +648,7 @@ gpio-keys { compatible = "gpio-keys"; - power { + key-power { label = "Power"; gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; linux,code = <KEY_POWER>; diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts index 0fb4b1f5bc1c..48fe628c6d87 100644 --- a/arch/arm/boot/dts/tegra20-paz00.dts +++ b/arch/arm/boot/dts/tegra20-paz00.dts @@ -596,7 +596,7 @@ gpio-keys { compatible = "gpio-keys"; - wakeup { + key-wakeup { label = "Wakeup"; gpios = <&gpio TEGRA_GPIO(J, 7) GPIO_ACTIVE_LOW>; linux,code = <KEY_WAKEUP>; diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts index c4a6a6a94559..5b4c5ef30996 100644 --- a/arch/arm/boot/dts/tegra20-seaboard.dts +++ b/arch/arm/boot/dts/tegra20-seaboard.dts @@ -800,14 +800,14 @@ gpio-keys { compatible = "gpio-keys"; - power { + key-power { label = "Power"; gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; linux,code = <KEY_POWER>; wakeup-source; }; - lid { + switch-lid { label = "Lid"; gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_HIGH>; linux,input-type = <5>; /* EV_SW */ diff --git a/arch/arm/boot/dts/tegra20-trimslice.dts b/arch/arm/boot/dts/tegra20-trimslice.dts index 9d0c86711de2..dc51835423a9 100644 --- a/arch/arm/boot/dts/tegra20-trimslice.dts +++ b/arch/arm/boot/dts/tegra20-trimslice.dts @@ -388,7 +388,7 @@ gpio-keys { compatible = "gpio-keys"; - power { + key-power { label = "Power"; gpios = <&gpio TEGRA_GPIO(X, 6) GPIO_ACTIVE_LOW>; linux,code = <KEY_POWER>; diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts index b0a00970b61c..caa17e876e41 100644 --- a/arch/arm/boot/dts/tegra20-ventana.dts +++ b/arch/arm/boot/dts/tegra20-ventana.dts @@ -628,7 +628,7 @@ gpio-keys { compatible = "gpio-keys"; - power { + key-power { label = "Power"; gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; linux,code = <KEY_POWER>; diff --git a/arch/arm/boot/dts/tegra30-apalis-eval.dts b/arch/arm/boot/dts/tegra30-apalis-eval.dts index 93b83b3c5655..ad968ff968d7 100644 --- a/arch/arm/boot/dts/tegra30-apalis-eval.dts +++ b/arch/arm/boot/dts/tegra30-apalis-eval.dts @@ -181,7 +181,7 @@ gpio-keys { compatible = "gpio-keys"; - wakeup { + key-wakeup { label = "WAKE1_MICO"; gpios = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_LOW>; linux,code = <KEY_WAKEUP>; diff --git a/arch/arm/boot/dts/tegra30-apalis-v1.1-eval.dts b/arch/arm/boot/dts/tegra30-apalis-v1.1-eval.dts index fbfa75e53f32..c172fdb5e1ae 100644 --- a/arch/arm/boot/dts/tegra30-apalis-v1.1-eval.dts +++ b/arch/arm/boot/dts/tegra30-apalis-v1.1-eval.dts @@ -182,7 +182,7 @@ gpio-keys { compatible = "gpio-keys"; - wakeup { + key-wakeup { label = "WAKE1_MICO"; gpios = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_LOW>; linux,code = <KEY_WAKEUP>; diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi index 2c2ad2a38f04..ee683c5a9c62 100644 --- a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi +++ b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi @@ -63,7 +63,7 @@ gpio@6000d000 { init-mode-hog { gpio-hog; - gpios = <TEGRA_GPIO(DD, 7) GPIO_ACTIVE_HIGH>, + gpios = <TEGRA_GPIO(DD, 7) GPIO_ACTIVE_HIGH>, <TEGRA_GPIO(CC, 6) GPIO_ACTIVE_HIGH>, <TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>; output-low; @@ -820,7 +820,7 @@ vddio-supply = <&vdd_1v8>; device-wakeup-gpios = <&gpio TEGRA_GPIO(U, 1) GPIO_ACTIVE_HIGH>; - shutdown-gpios = <&gpio TEGRA_GPIO(U, 0) GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio TEGRA_GPIO(U, 0) GPIO_ACTIVE_HIGH>; }; }; @@ -833,7 +833,7 @@ status = "okay"; touchscreen@10 { - compatible ="elan,ektf3624"; + compatible = "elan,ektf3624"; reg = <0x10>; interrupt-parent = <&gpio>; @@ -1124,7 +1124,7 @@ gpio-keys { compatible = "gpio-keys"; - hall-sensor { + switch-hall-sensor { label = "Lid"; gpios = <&gpio TEGRA_GPIO(S, 6) GPIO_ACTIVE_LOW>; linux,input-type = <EV_SW>; @@ -1134,7 +1134,7 @@ wakeup-source; }; - power { + key-power { label = "Power"; gpios = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>; linux,code = <KEY_POWER>; @@ -1143,7 +1143,7 @@ wakeup-source; }; - volume-up { + key-volume-up { label = "Volume Up"; gpios = <&gpio TEGRA_GPIO(Q, 2) GPIO_ACTIVE_LOW>; linux,code = <KEY_VOLUMEUP>; @@ -1152,7 +1152,7 @@ wakeup-source; }; - volume-down { + key-volume-down { label = "Volume Down"; gpios = <&gpio TEGRA_GPIO(Q, 3) GPIO_ACTIVE_LOW>; linux,code = <KEY_VOLUMEDOWN>; diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-tilapia.dtsi b/arch/arm/boot/dts/tegra30-asus-nexus7-tilapia.dtsi index cd63e0ef7445..1b241f0542b8 100644 --- a/arch/arm/boot/dts/tegra30-asus-nexus7-tilapia.dtsi +++ b/arch/arm/boot/dts/tegra30-asus-nexus7-tilapia.dtsi @@ -25,7 +25,7 @@ gpio@6000d000 { init-mode-3g-hog { gpio-hog; - gpios = <TEGRA_GPIO(D, 2) GPIO_ACTIVE_HIGH>, + gpios = <TEGRA_GPIO(D, 2) GPIO_ACTIVE_HIGH>, <TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>, <TEGRA_GPIO(W, 3) GPIO_ACTIVE_HIGH>, <TEGRA_GPIO(P, 1) GPIO_ACTIVE_HIGH>, diff --git a/arch/arm/boot/dts/tegra30-asus-transformer-common.dtsi b/arch/arm/boot/dts/tegra30-asus-transformer-common.dtsi index c662ab261ed5..c27e70d8bf2b 100644 --- a/arch/arm/boot/dts/tegra30-asus-transformer-common.dtsi +++ b/arch/arm/boot/dts/tegra30-asus-transformer-common.dtsi @@ -1511,7 +1511,7 @@ compatible = "gpio-keys"; interrupt-parent = <&gpio>; - dock-hall-sensor { + switch-dock-hall-sensor { label = "Lid sensor"; gpios = <&gpio TEGRA_GPIO(S, 6) GPIO_ACTIVE_LOW>; linux,input-type = <EV_SW>; @@ -1521,7 +1521,7 @@ wakeup-source; }; - lineout-detect { + switch-lineout-detect { label = "Audio dock line-out detect"; gpios = <&gpio TEGRA_GPIO(X, 3) GPIO_ACTIVE_LOW>; linux,input-type = <EV_SW>; @@ -1544,7 +1544,7 @@ compatible = "gpio-keys"; interrupt-parent = <&gpio>; - power { + key-power { label = "Power"; gpios = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>; linux,code = <KEY_POWER>; @@ -1553,7 +1553,7 @@ wakeup-source; }; - volume-up { + key-volume-up { label = "Volume Up"; gpios = <&gpio TEGRA_GPIO(Q, 2) GPIO_ACTIVE_LOW>; linux,code = <KEY_VOLUMEUP>; @@ -1562,7 +1562,7 @@ wakeup-source; }; - volume-down { + key-volume-down { label = "Volume Down"; gpios = <&gpio TEGRA_GPIO(Q, 3) GPIO_ACTIVE_LOW>; linux,code = <KEY_VOLUMEDOWN>; diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi index ba257ed36d9c..540530c983ff 100644 --- a/arch/arm/boot/dts/tegra30-cardhu.dtsi +++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi @@ -685,7 +685,7 @@ gpio-keys { compatible = "gpio-keys"; - power { + key-power { label = "Power"; interrupt-parent = <&pmic>; interrupts = <2 0>; @@ -694,14 +694,14 @@ wakeup-source; }; - volume-down { + key-volume-down { label = "Volume Down"; gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_LOW>; linux,code = <KEY_VOLUMEDOWN>; debounce-interval = <10>; }; - volume-up { + key-volume-up { label = "Volume Up"; gpios = <&gpio TEGRA_GPIO(R, 1) GPIO_ACTIVE_LOW>; linux,code = <KEY_VOLUMEUP>; diff --git a/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts b/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts index 7d4a6ca4936a..8dbc15f9a9e4 100644 --- a/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts +++ b/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts @@ -145,7 +145,7 @@ gpio-keys { compatible = "gpio-keys"; - wakeup { + key-wakeup { label = "SODIMM pin 45 wakeup"; gpios = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>; linux,code = <KEY_WAKEUP>; diff --git a/arch/arm/boot/dts/tegra30-colibri.dtsi b/arch/arm/boot/dts/tegra30-colibri.dtsi index 22231d450b1b..310dff05910d 100644 --- a/arch/arm/boot/dts/tegra30-colibri.dtsi +++ b/arch/arm/boot/dts/tegra30-colibri.dtsi @@ -239,7 +239,7 @@ nvidia,enable-input = <TEGRA_PIN_ENABLE>; }; spdif-in-pk6 { - nvidia,pins = "spdif_in_pk6"; + nvidia,pins = "spdif_in_pk6"; nvidia,function = "hda"; nvidia,pull = <TEGRA_PIN_PULL_NONE>; nvidia,tristate = <TEGRA_PIN_DISABLE>; @@ -364,7 +364,7 @@ }; /* Multiplexed and therefore disabled */ cam-mclk-pcc0 { - nvidia,pins = "cam_mclk_pcc0"; + nvidia,pins = "cam_mclk_pcc0"; nvidia,function = "vi_alt3"; nvidia,pull = <TEGRA_PIN_PULL_DOWN>; nvidia,tristate = <TEGRA_PIN_ENABLE>; @@ -511,7 +511,7 @@ /* Colibri USBC_DET */ spdif-out-pk5 { - nvidia,pins = "spdif_out_pk5"; + nvidia,pins = "spdif_out_pk5"; nvidia,function = "rsvd2"; nvidia,pull = <TEGRA_PIN_PULL_NONE>; nvidia,tristate = <TEGRA_PIN_DISABLE>; diff --git a/arch/arm/boot/dts/tegra30-ouya.dts b/arch/arm/boot/dts/tegra30-ouya.dts index e58dda4f9d2c..b7acea39b942 100644 --- a/arch/arm/boot/dts/tegra30-ouya.dts +++ b/arch/arm/boot/dts/tegra30-ouya.dts @@ -4764,7 +4764,7 @@ gpio-keys { compatible = "gpio-keys"; - power { + key-power { gpios = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>; debounce-interval = <10>; linux,code = <KEY_POWER>; diff --git a/arch/arm/boot/dts/tegra30-pegatron-chagall.dts b/arch/arm/boot/dts/tegra30-pegatron-chagall.dts index 8ce61035290b..7c81f0205549 100644 --- a/arch/arm/boot/dts/tegra30-pegatron-chagall.dts +++ b/arch/arm/boot/dts/tegra30-pegatron-chagall.dts @@ -2655,7 +2655,7 @@ compatible = "gpio-keys"; interrupt-parent = <&gpio>; - dock-insert { + switch-dock-insert { label = "Chagall Dock"; gpios = <&gpio TEGRA_GPIO(S, 4) GPIO_ACTIVE_LOW>; linux,input-type = <EV_SW>; @@ -2665,7 +2665,7 @@ wakeup-source; }; - lineout-detect { + switch-lineout-detect { label = "Audio dock line-out detect"; gpios = <&gpio TEGRA_GPIO(S, 3) GPIO_ACTIVE_LOW>; linux,input-type = <EV_SW>; @@ -2688,7 +2688,7 @@ compatible = "gpio-keys"; interrupt-parent = <&gpio>; - power { + key-power { label = "Power"; gpios = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>; linux,code = <KEY_POWER>; @@ -2697,7 +2697,7 @@ wakeup-source; }; - volume-up { + key-volume-up { label = "Volume Up"; gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; linux,code = <KEY_VOLUMEUP>; @@ -2706,7 +2706,7 @@ wakeup-source; }; - volume-down { + key-volume-down { label = "Volume Down"; gpios = <&gpio TEGRA_GPIO(Q, 1) GPIO_ACTIVE_LOW>; linux,code = <KEY_VOLUMEDOWN>; diff --git a/arch/arm/boot/dts/zynq-zc702.dts b/arch/arm/boot/dts/zynq-zc702.dts index cf70aff26c66..d23201ba8cd7 100644 --- a/arch/arm/boot/dts/zynq-zc702.dts +++ b/arch/arm/boot/dts/zynq-zc702.dts @@ -30,14 +30,14 @@ gpio-keys { compatible = "gpio-keys"; autorepeat; - sw14 { + switch-14 { label = "sw14"; gpios = <&gpio0 12 0>; linux,code = <108>; /* down */ wakeup-source; autorepeat; }; - sw13 { + switch-13 { label = "sw13"; gpios = <&gpio0 14 0>; linux,code = <103>; /* up */ diff --git a/arch/arm/boot/dts/zynq-zturn-common.dtsi b/arch/arm/boot/dts/zynq-zturn-common.dtsi index bf5d1c4568b0..dfb1fbafe3aa 100644 --- a/arch/arm/boot/dts/zynq-zturn-common.dtsi +++ b/arch/arm/boot/dts/zynq-zturn-common.dtsi @@ -49,7 +49,7 @@ gpio-keys { compatible = "gpio-keys"; autorepeat; - K1 { + key { label = "K1"; gpios = <&gpio0 0x32 0x1>; linux,code = <0x66>; diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 4e6d635a1731..1a8510a7ba8f 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -49,6 +49,7 @@ config ARCH_BCM2835 config ARCH_BCM4908 bool "Broadcom BCM4908 family" + select ARCH_BCMBCA select GPIOLIB help This enables support for the Broadcom BCM4906, BCM4908 and @@ -63,6 +64,15 @@ config ARCH_BCM_IPROC help This enables support for Broadcom iProc based SoCs +config ARCH_BCMBCA + bool "Broadcom Broadband Carrier Access (BCA) origin SoC" + help + Say Y if you intend to run the kernel on a Broadcom Broadband ARM-based + BCA chipset. + + This enables support for Broadcom BCA ARM-based broadband chipsets, + including the DSL, PON and Wireless family of chips. + config ARCH_BERLIN bool "Marvell Berlin SoC Family" select DW_APB_ICTL @@ -182,11 +192,13 @@ config ARCH_MVEBU select PINCTRL_ARMADA_37XX select PINCTRL_ARMADA_AP806 select PINCTRL_ARMADA_CP110 + select PINCTRL_AC5 help This enables support for Marvell EBU familly, including: - Armada 3700 SoC Family - Armada 7K SoC Family - Armada 8K SoC Family + - 98DX2530 SoC Family config ARCH_MXC bool "ARMv8 based NXP i.MX SoC family" @@ -248,7 +260,8 @@ config ARCH_INTEL_SOCFPGA bool "Intel's SoCFPGA ARMv8 Families" help This enables support for Intel's SoCFPGA ARMv8 families: - Stratix 10 (ex. Altera), Agilex and eASIC N5X. + Stratix 10 (ex. Altera), Stratix10 Software Virtual Platform, + Agilex and eASIC N5X. config ARCH_SYNQUACER bool "Socionext SynQuacer SoC Family" diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile index 8fa5c060a4fe..6a96494a2e0a 100644 --- a/arch/arm64/boot/dts/allwinner/Makefile +++ b/arch/arm64/boot/dts/allwinner/Makefile @@ -38,3 +38,5 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-pine-h64.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-pine-h64-model-b.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-tanix-tx6.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-tanix-tx6-mini.dtb +dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-orangepi-zero2.dtb +dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-x96-mate.dtb diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi index f6d7d7f7fdab..548539c93ab0 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi @@ -203,6 +203,7 @@ i2c0: i2c@5002000 { compatible = "allwinner,sun50i-a100-i2c", + "allwinner,sun8i-v536-i2c", "allwinner,sun6i-a31-i2c"; reg = <0x05002000 0x400>; interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; @@ -215,6 +216,7 @@ i2c1: i2c@5002400 { compatible = "allwinner,sun50i-a100-i2c", + "allwinner,sun8i-v536-i2c", "allwinner,sun6i-a31-i2c"; reg = <0x05002400 0x400>; interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; @@ -227,6 +229,7 @@ i2c2: i2c@5002800 { compatible = "allwinner,sun50i-a100-i2c", + "allwinner,sun8i-v536-i2c", "allwinner,sun6i-a31-i2c"; reg = <0x05002800 0x400>; interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; @@ -239,6 +242,7 @@ i2c3: i2c@5002c00 { compatible = "allwinner,sun50i-a100-i2c", + "allwinner,sun8i-v536-i2c", "allwinner,sun6i-a31-i2c"; reg = <0x05002c00 0x400>; interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; @@ -315,6 +319,7 @@ r_i2c0: i2c@7081400 { compatible = "allwinner,sun50i-a100-i2c", + "allwinner,sun8i-v536-i2c", "allwinner,sun6i-a31-i2c"; reg = <0x07081400 0x400>; interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; @@ -329,6 +334,7 @@ r_i2c1: i2c@7081800 { compatible = "allwinner,sun50i-a100-i2c", + "allwinner,sun8i-v536-i2c", "allwinner,sun6i-a31-i2c"; reg = <0x07081800 0x400>; interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-amarula-relic.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-amarula-relic.dts index f17cc89f472d..8233582f6288 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-amarula-relic.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-amarula-relic.dts @@ -58,7 +58,7 @@ wifi_pwrseq: wifi-pwrseq { compatible = "mmc-pwrseq-simple"; - clocks = <&rtc 1>; + clocks = <&rtc CLK_OSC32K_FANOUT>; clock-names = "ext_clock"; reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* WL-PMU-EN: PL2 */ }; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts index 997a19372683..e6d5bc0f7a61 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts @@ -56,7 +56,7 @@ wifi_pwrseq: wifi_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */ - clocks = <&rtc 1>; + clocks = <&rtc CLK_OSC32K_FANOUT>; clock-names = "ext_clock"; }; }; @@ -355,7 +355,7 @@ bluetooth { compatible = "brcm,bcm43438-bt"; - clocks = <&rtc 1>; + clocks = <&rtc CLK_OSC32K_FANOUT>; clock-names = "lpo"; vbat-supply = <®_dldo2>; vddio-supply = <®_dldo4>; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts index e47ff06a6fa9..0af6dcdf7515 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts @@ -43,7 +43,7 @@ wifi_pwrseq: wifi_pwrseq { compatible = "mmc-pwrseq-simple"; - clocks = <&rtc 1>; + clocks = <&rtc CLK_OSC32K_FANOUT>; clock-names = "ext_clock"; reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */ }; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts index c519d9fa6967..4f8529d5ac00 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts @@ -40,7 +40,7 @@ leds { compatible = "gpio-leds"; - status { + led-0 { label = "orangepi:green:status"; gpios = <&pio 7 11 GPIO_ACTIVE_HIGH>; /* PH11 */ }; @@ -71,7 +71,7 @@ wifi_pwrseq: wifi_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&r_pio 0 8 GPIO_ACTIVE_LOW>; /* PL8 */ - clocks = <&rtc 1>; + clocks = <&rtc CLK_OSC32K_FANOUT>; clock-names = "ext_clock"; }; }; @@ -369,7 +369,7 @@ bluetooth { compatible = "brcm,bcm43438-bt"; max-speed = <1500000>; - clocks = <&rtc 1>; + clocks = <&rtc CLK_OSC32K_FANOUT>; clock-names = "lpo"; vbat-supply = <®_dldo2>; vddio-supply = <®_dldo4>; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts index 63571df24da4..620cb3ef5f6c 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts @@ -35,10 +35,10 @@ stdout-path = "serial0:115200n8"; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; - lid_switch { + lid-switch { label = "Lid Switch"; gpios = <&r_pio 0 12 GPIO_ACTIVE_LOW>; /* PL12 */ linux,input-type = <EV_SW>; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.0.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.0.dts index fb65319a3bd3..219f720b8b7d 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.0.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.0.dts @@ -10,6 +10,10 @@ compatible = "pine64,pinephone-1.0", "pine64,pinephone", "allwinner,sun50i-a64"; }; +&codec_analog { + allwinner,internal-bias-resistor; +}; + &sgm3140 { enable-gpios = <&pio 2 3 GPIO_ACTIVE_HIGH>; /* PC3 */ flash-gpios = <&pio 3 24 GPIO_ACTIVE_HIGH>; /* PD24 */ diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.1.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.1.dts index 5e59d3752178..723af64a9cee 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.1.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.1.dts @@ -29,6 +29,10 @@ default-brightness-level = <400>; }; +&codec_analog { + allwinner,internal-bias-resistor; +}; + &sgm3140 { enable-gpios = <&pio 3 24 GPIO_ACTIVE_HIGH>; /* PD24 */ flash-gpios = <&pio 2 3 GPIO_ACTIVE_HIGH>; /* PC3 */ diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index de77c87481fd..77b5349f6087 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -4,6 +4,7 @@ // Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com> #include <dt-bindings/clock/sun50i-a64-ccu.h> +#include <dt-bindings/clock/sun6i-rtc.h> #include <dt-bindings/clock/sun8i-de2.h> #include <dt-bindings/clock/sun8i-r-ccu.h> #include <dt-bindings/interrupt-controller/arm-gic.h> @@ -660,7 +661,7 @@ ccu: clock@1c20000 { compatible = "allwinner,sun50i-a64-ccu"; reg = <0x01c20000 0x400>; - clocks = <&osc24M>, <&rtc 0>; + clocks = <&osc24M>, <&rtc CLK_OSC32K>; clock-names = "hosc", "losc"; #clock-cells = <1>; #reset-cells = <1>; @@ -673,7 +674,8 @@ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>; + clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, + <&rtc CLK_OSC32K>; clock-names = "apb", "hosc", "losc"; gpio-controller; #gpio-cells = <3>; @@ -1226,7 +1228,7 @@ reg-io-width = <1>; interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>, - <&ccu CLK_HDMI>, <&rtc 0>; + <&ccu CLK_HDMI>, <&rtc CLK_OSC32K>; clock-names = "iahb", "isfr", "tmds", "cec"; resets = <&ccu RST_BUS_HDMI1>; reset-names = "ctrl"; @@ -1287,7 +1289,7 @@ r_ccu: clock@1f01400 { compatible = "allwinner,sun50i-a64-r-ccu"; reg = <0x01f01400 0x100>; - clocks = <&osc24M>, <&rtc 0>, <&rtc 2>, + clocks = <&osc24M>, <&rtc CLK_OSC32K>, <&rtc CLK_IOSC>, <&ccu CLK_PLL_PERIPH0>; clock-names = "hosc", "losc", "iosc", "pll-periph"; #clock-cells = <1>; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts index 55b369534a08..a3e040da38a0 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts @@ -52,10 +52,10 @@ }; }; - r-gpio-keys { + gpio-keys { compatible = "gpio-keys"; - reset { + key-reset { label = "reset"; linux,code = <KEY_RESTART>; gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts index 1010c1b22d2e..b5c1ff19b4c4 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts @@ -54,10 +54,10 @@ }; }; - r-gpio-keys { + gpio-keys { compatible = "gpio-keys"; - sw4 { + key-sw4 { label = "sw4"; linux,code = <BTN_0>; gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts index 74e0444af19b..d7f8bad6bb98 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts @@ -48,10 +48,10 @@ }; }; - r-gpio-keys { + gpio-keys { compatible = "gpio-keys"; - sw4 { + key-sw4 { label = "sw4"; linux,code = <BTN_0>; gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts index c45d7b7fb39a..6fc65e8db220 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts @@ -86,7 +86,7 @@ wifi_pwrseq: wifi-pwrseq { compatible = "mmc-pwrseq-simple"; - clocks = <&rtc 1>; + clocks = <&rtc CLK_OSC32K_FANOUT>; clock-names = "ext_clock"; reset-gpios = <&r_pio 1 3 GPIO_ACTIVE_LOW>; /* PM3 */ post-power-on-delay-ms = <200>; @@ -314,7 +314,7 @@ bluetooth { compatible = "brcm,bcm4345c5"; - clocks = <&rtc 1>; + clocks = <&rtc CLK_OSC32K_FANOUT>; clock-names = "lpo"; device-wakeup-gpios = <&r_pio 1 2 GPIO_ACTIVE_HIGH>; /* PM2 */ host-wakeup-gpios = <&r_pio 1 1 GPIO_ACTIVE_HIGH>; /* PM1 */ diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-lite2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-lite2.dts index e8770858b5d0..fb31dcb1cb6d 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-lite2.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-lite2.dts @@ -13,7 +13,7 @@ wifi_pwrseq: wifi_pwrseq { compatible = "mmc-pwrseq-simple"; - clocks = <&rtc 1>; + clocks = <&rtc CLK_OSC32K_FANOUT>; clock-names = "ext_clock"; reset-gpios = <&r_pio 1 3 GPIO_ACTIVE_LOW>; /* PM3 */ post-power-on-delay-ms = <200>; @@ -64,7 +64,7 @@ bluetooth { compatible = "brcm,bcm4345c5"; - clocks = <&rtc 1>; + clocks = <&rtc CLK_OSC32K_FANOUT>; clock-names = "lpo"; device-wakeup-gpios = <&r_pio 1 2 GPIO_ACTIVE_HIGH>; /* PM2 */ host-wakeup-gpios = <&r_pio 1 1 GPIO_ACTIVE_HIGH>; /* PM1 */ diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix.dtsi index edb71e4a0304..4903d6358112 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix.dtsi @@ -78,7 +78,7 @@ wifi_pwrseq: wifi-pwrseq { compatible = "mmc-pwrseq-simple"; - clocks = <&rtc 1>; + clocks = <&rtc CLK_OSC32K_FANOUT>; clock-names = "ext_clock"; reset-gpios = <&r_pio 1 3 GPIO_ACTIVE_LOW>; /* PM3 */ }; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi index fbe94abbb1f9..5a28303d3d4c 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi @@ -4,6 +4,7 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/clock/sun50i-h6-ccu.h> #include <dt-bindings/clock/sun50i-h6-r-ccu.h> +#include <dt-bindings/clock/sun6i-rtc.h> #include <dt-bindings/clock/sun8i-de2.h> #include <dt-bindings/clock/sun8i-tcon-top.h> #include <dt-bindings/reset/sun50i-h6-ccu.h> @@ -237,7 +238,7 @@ ccu: clock@3001000 { compatible = "allwinner,sun50i-h6-ccu"; reg = <0x03001000 0x1000>; - clocks = <&osc24M>, <&rtc 0>, <&rtc 2>; + clocks = <&osc24M>, <&rtc CLK_OSC32K>, <&rtc CLK_IOSC>; clock-names = "hosc", "losc", "iosc"; #clock-cells = <1>; #reset-cells = <1>; @@ -317,7 +318,7 @@ <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_APB1>, <&osc24M>, <&rtc 0>; + clocks = <&ccu CLK_APB1>, <&osc24M>, <&rtc CLK_OSC32K>; clock-names = "apb", "hosc", "losc"; gpio-controller; #gpio-cells = <3>; @@ -725,7 +726,7 @@ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_BUS_XHCI>, <&ccu CLK_BUS_XHCI>, - <&rtc 0>; + <&rtc CLK_OSC32K>; clock-names = "ref", "bus_early", "suspend"; resets = <&ccu RST_BUS_XHCI>; /* @@ -931,7 +932,7 @@ r_ccu: clock@7010000 { compatible = "allwinner,sun50i-h6-r-ccu"; reg = <0x07010000 0x400>; - clocks = <&osc24M>, <&rtc 0>, <&rtc 2>, + clocks = <&osc24M>, <&rtc CLK_OSC32K>, <&rtc CLK_IOSC>, <&ccu CLK_PLL_PERIPH0>; clock-names = "hosc", "losc", "iosc", "pll-periph"; #clock-cells = <1>; @@ -960,7 +961,8 @@ interrupt-parent = <&r_intc>; interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&r_ccu CLK_R_APB1>, <&osc24M>, <&rtc 0>; + clocks = <&r_ccu CLK_R_APB1>, <&osc24M>, + <&rtc CLK_OSC32K>; clock-names = "apb", "hosc", "losc"; gpio-controller; #gpio-cells = <3>; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts new file mode 100644 index 000000000000..02893f3ac99d --- /dev/null +++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts @@ -0,0 +1,213 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +/* + * Copyright (C) 2020 Arm Ltd. + */ + +/dts-v1/; + +#include "sun50i-h616.dtsi" + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/leds/common.h> + +/ { + model = "OrangePi Zero2"; + compatible = "xunlong,orangepi-zero2", "allwinner,sun50i-h616"; + + aliases { + ethernet0 = &emac0; + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + function = LED_FUNCTION_POWER; + color = <LED_COLOR_ID_RED>; + gpios = <&pio 2 12 GPIO_ACTIVE_HIGH>; /* PC12 */ + default-state = "on"; + }; + + led-1 { + function = LED_FUNCTION_STATUS; + color = <LED_COLOR_ID_GREEN>; + gpios = <&pio 2 13 GPIO_ACTIVE_HIGH>; /* PC13 */ + }; + }; + + reg_vcc5v: vcc5v { + /* board wide 5V supply directly from the USB-C socket */ + compatible = "regulator-fixed"; + regulator-name = "vcc-5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; +}; + +&emac0 { + pinctrl-names = "default"; + pinctrl-0 = <&ext_rgmii_pins>; + phy-mode = "rgmii"; + phy-handle = <&ext_rgmii_phy>; + phy-supply = <®_dcdce>; + allwinner,rx-delay-ps = <3100>; + allwinner,tx-delay-ps = <700>; + status = "okay"; +}; + +&mdio0 { + ext_rgmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; +}; + +&mmc0 { + vmmc-supply = <®_dcdce>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ + bus-width = <4>; + status = "okay"; +}; + +&r_rsb { + status = "okay"; + + axp305: pmic@745 { + compatible = "x-powers,axp305", "x-powers,axp805", + "x-powers,axp806"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0x745>; + + x-powers,self-working-mode; + vina-supply = <®_vcc5v>; + vinb-supply = <®_vcc5v>; + vinc-supply = <®_vcc5v>; + vind-supply = <®_vcc5v>; + vine-supply = <®_vcc5v>; + aldoin-supply = <®_vcc5v>; + bldoin-supply = <®_vcc5v>; + cldoin-supply = <®_vcc5v>; + + regulators { + reg_aldo1: aldo1 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-sys"; + }; + + reg_aldo2: aldo2 { /* 3.3V on headers */ + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3-ext"; + }; + + reg_aldo3: aldo3 { /* 3.3V on headers */ + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3-ext2"; + }; + + reg_bldo1: bldo1 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc1v8"; + }; + + bldo2 { + /* unused */ + }; + + bldo3 { + /* unused */ + }; + + bldo4 { + /* unused */ + }; + + cldo1 { + /* reserved */ + }; + + cldo2 { + /* unused */ + }; + + cldo3 { + /* unused */ + }; + + reg_dcdca: dcdca { + regulator-always-on; + regulator-min-microvolt = <810000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-cpu"; + }; + + reg_dcdcc: dcdcc { + regulator-always-on; + regulator-min-microvolt = <810000>; + regulator-max-microvolt = <990000>; + regulator-name = "vdd-gpu-sys"; + }; + + reg_dcdcd: dcdcd { + regulator-always-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vdd-dram"; + }; + + reg_dcdce: dcdce { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-eth-mmc"; + }; + + sw { + /* unused */ + }; + }; + }; +}; + +&pio { + vcc-pc-supply = <®_aldo1>; + vcc-pf-supply = <®_aldo1>; + vcc-pg-supply = <®_bldo1>; + vcc-ph-supply = <®_aldo1>; + vcc-pi-supply = <®_aldo1>; +}; + +&spi0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins>, <&spi0_cs0_pin>; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <40000000>; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_ph_pins>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts b/arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts new file mode 100644 index 000000000000..6619db34714a --- /dev/null +++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts @@ -0,0 +1,177 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +/* + * Copyright (C) 2021 Arm Ltd. + */ + +/dts-v1/; + +#include "sun50i-h616.dtsi" + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + model = "X96 Mate"; + compatible = "hechuang,x96-mate", "allwinner,sun50i-h616"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + reg_vcc5v: vcc5v { + /* board wide 5V supply directly from the DC input */ + compatible = "regulator-fixed"; + regulator-name = "vcc-5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; +}; + +&ir { + status = "okay"; +}; + +&mmc0 { + vmmc-supply = <®_dcdce>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ + bus-width = <4>; + status = "okay"; +}; + +&mmc2 { + vmmc-supply = <®_dcdce>; + vqmmc-supply = <®_bldo1>; + bus-width = <8>; + non-removable; + cap-mmc-hw-reset; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + status = "okay"; +}; + +&r_rsb { + status = "okay"; + + axp305: pmic@745 { + compatible = "x-powers,axp305", "x-powers,axp805", + "x-powers,axp806"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0x745>; + + x-powers,self-working-mode; + vina-supply = <®_vcc5v>; + vinb-supply = <®_vcc5v>; + vinc-supply = <®_vcc5v>; + vind-supply = <®_vcc5v>; + vine-supply = <®_vcc5v>; + aldoin-supply = <®_vcc5v>; + bldoin-supply = <®_vcc5v>; + cldoin-supply = <®_vcc5v>; + + regulators { + reg_aldo1: aldo1 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-sys"; + }; + + /* Enabled by the Android BSP */ + reg_aldo2: aldo2 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3-ext"; + status = "disabled"; + }; + + /* Enabled by the Android BSP */ + reg_aldo3: aldo3 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3-ext2"; + status = "disabled"; + }; + + reg_bldo1: bldo1 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc1v8"; + }; + + /* Enabled by the Android BSP */ + reg_bldo2: bldo2 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc1v8-2"; + status = "disabled"; + }; + + bldo3 { + /* unused */ + }; + + bldo4 { + /* unused */ + }; + + cldo1 { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-name = "vcc2v5"; + }; + + cldo2 { + /* unused */ + }; + + cldo3 { + /* unused */ + }; + + reg_dcdca: dcdca { + regulator-always-on; + regulator-min-microvolt = <810000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-cpu"; + }; + + reg_dcdcc: dcdcc { + regulator-always-on; + regulator-min-microvolt = <810000>; + regulator-max-microvolt = <990000>; + regulator-name = "vdd-gpu-sys"; + }; + + reg_dcdcd: dcdcd { + regulator-always-on; + regulator-min-microvolt = <1360000>; + regulator-max-microvolt = <1360000>; + regulator-name = "vdd-dram"; + }; + + reg_dcdce: dcdce { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-eth-mmc"; + }; + + sw { + /* unused */ + }; + }; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_ph_pins>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi new file mode 100644 index 000000000000..622a1f7d1641 --- /dev/null +++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi @@ -0,0 +1,591 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// Copyright (C) 2020 Arm Ltd. +// based on the H6 dtsi, which is: +// Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io> + +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/sun50i-h616-ccu.h> +#include <dt-bindings/clock/sun50i-h6-r-ccu.h> +#include <dt-bindings/clock/sun6i-rtc.h> +#include <dt-bindings/reset/sun50i-h616-ccu.h> +#include <dt-bindings/reset/sun50i-h6-r-ccu.h> + +/ { + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + reg = <0>; + enable-method = "psci"; + clocks = <&ccu CLK_CPUX>; + }; + + cpu1: cpu@1 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + reg = <1>; + enable-method = "psci"; + clocks = <&ccu CLK_CPUX>; + }; + + cpu2: cpu@2 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + reg = <2>; + enable-method = "psci"; + clocks = <&ccu CLK_CPUX>; + }; + + cpu3: cpu@3 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + reg = <3>; + enable-method = "psci"; + clocks = <&ccu CLK_CPUX>; + }; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* + * 256 KiB reserved for Trusted Firmware-A (BL31). + * This is added by BL31 itself, but some bootloaders fail + * to propagate this into the DTB handed to kernels. + */ + secmon@40000000 { + reg = <0x0 0x40000000 0x0 0x40000>; + no-map; + }; + }; + + osc24M: osc24M-clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "osc24M"; + }; + + pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + arm,no-tick-in-suspend; + interrupts = <GIC_PPI 13 + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, + <GIC_PPI 14 + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, + <GIC_PPI 11 + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, + <GIC_PPI 10 + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x0 0x40000000>; + + syscon: syscon@3000000 { + compatible = "allwinner,sun50i-h616-system-control"; + reg = <0x03000000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + sram_c: sram@28000 { + compatible = "mmio-sram"; + reg = <0x00028000 0x30000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x00028000 0x30000>; + }; + }; + + ccu: clock@3001000 { + compatible = "allwinner,sun50i-h616-ccu"; + reg = <0x03001000 0x1000>; + clocks = <&osc24M>, <&rtc CLK_OSC32K>, <&rtc CLK_IOSC>; + clock-names = "hosc", "losc", "iosc"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + watchdog: watchdog@30090a0 { + compatible = "allwinner,sun50i-h616-wdt", + "allwinner,sun6i-a31-wdt"; + reg = <0x030090a0 0x20>; + interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&osc24M>; + }; + + pio: pinctrl@300b000 { + compatible = "allwinner,sun50i-h616-pinctrl"; + reg = <0x0300b000 0x400>; + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_APB1>, <&osc24M>, <&rtc CLK_OSC32K>; + clock-names = "apb", "hosc", "losc"; + gpio-controller; + #gpio-cells = <3>; + interrupt-controller; + #interrupt-cells = <3>; + + ext_rgmii_pins: rgmii-pins { + pins = "PI0", "PI1", "PI2", "PI3", "PI4", + "PI5", "PI7", "PI8", "PI9", "PI10", + "PI11", "PI12", "PI13", "PI14", "PI15", + "PI16"; + function = "emac0"; + drive-strength = <40>; + }; + + i2c0_pins: i2c0-pins { + pins = "PI6", "PI7"; + function = "i2c0"; + }; + + i2c3_ph_pins: i2c3-ph-pins { + pins = "PH4", "PH5"; + function = "i2c3"; + }; + + ir_rx_pin: ir-rx-pin { + pins = "PH10"; + function = "ir_rx"; + }; + + mmc0_pins: mmc0-pins { + pins = "PF0", "PF1", "PF2", "PF3", + "PF4", "PF5"; + function = "mmc0"; + drive-strength = <30>; + bias-pull-up; + }; + + /omit-if-no-ref/ + mmc1_pins: mmc1-pins { + pins = "PG0", "PG1", "PG2", "PG3", + "PG4", "PG5"; + function = "mmc1"; + drive-strength = <30>; + bias-pull-up; + }; + + mmc2_pins: mmc2-pins { + pins = "PC0", "PC1", "PC5", "PC6", + "PC8", "PC9", "PC10", "PC11", + "PC13", "PC14", "PC15", "PC16"; + function = "mmc2"; + drive-strength = <30>; + bias-pull-up; + }; + + /omit-if-no-ref/ + spi0_pins: spi0-pins { + pins = "PC0", "PC2", "PC4"; + function = "spi0"; + }; + + /omit-if-no-ref/ + spi0_cs0_pin: spi0-cs0-pin { + pins = "PC3"; + function = "spi0"; + }; + + /omit-if-no-ref/ + spi1_pins: spi1-pins { + pins = "PH6", "PH7", "PH8"; + function = "spi1"; + }; + + /omit-if-no-ref/ + spi1_cs0_pin: spi1-cs0-pin { + pins = "PH5"; + function = "spi1"; + }; + + uart0_ph_pins: uart0-ph-pins { + pins = "PH0", "PH1"; + function = "uart0"; + }; + + /omit-if-no-ref/ + uart1_pins: uart1-pins { + pins = "PG6", "PG7"; + function = "uart1"; + }; + + /omit-if-no-ref/ + uart1_rts_cts_pins: uart1-rts-cts-pins { + pins = "PG8", "PG9"; + function = "uart1"; + }; + }; + + gic: interrupt-controller@3021000 { + compatible = "arm,gic-400"; + reg = <0x03021000 0x1000>, + <0x03022000 0x2000>, + <0x03024000 0x2000>, + <0x03026000 0x2000>; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + interrupt-controller; + #interrupt-cells = <3>; + }; + + mmc0: mmc@4020000 { + compatible = "allwinner,sun50i-h616-mmc", + "allwinner,sun50i-a100-mmc"; + reg = <0x04020000 0x1000>; + clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; + clock-names = "ahb", "mmc"; + resets = <&ccu RST_BUS_MMC0>; + reset-names = "ahb"; + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins>; + status = "disabled"; + max-frequency = <150000000>; + cap-sd-highspeed; + cap-mmc-highspeed; + mmc-ddr-3_3v; + cap-sdio-irq; + #address-cells = <1>; + #size-cells = <0>; + }; + + mmc1: mmc@4021000 { + compatible = "allwinner,sun50i-h616-mmc", + "allwinner,sun50i-a100-mmc"; + reg = <0x04021000 0x1000>; + clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; + clock-names = "ahb", "mmc"; + resets = <&ccu RST_BUS_MMC1>; + reset-names = "ahb"; + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + status = "disabled"; + max-frequency = <150000000>; + cap-sd-highspeed; + cap-mmc-highspeed; + mmc-ddr-3_3v; + cap-sdio-irq; + #address-cells = <1>; + #size-cells = <0>; + }; + + mmc2: mmc@4022000 { + compatible = "allwinner,sun50i-h616-emmc", + "allwinner,sun50i-a100-emmc"; + reg = <0x04022000 0x1000>; + clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; + clock-names = "ahb", "mmc"; + resets = <&ccu RST_BUS_MMC2>; + reset-names = "ahb"; + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins>; + status = "disabled"; + max-frequency = <150000000>; + cap-sd-highspeed; + cap-mmc-highspeed; + mmc-ddr-3_3v; + cap-sdio-irq; + #address-cells = <1>; + #size-cells = <0>; + }; + + uart0: serial@5000000 { + compatible = "snps,dw-apb-uart"; + reg = <0x05000000 0x400>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART0>; + resets = <&ccu RST_BUS_UART0>; + status = "disabled"; + }; + + uart1: serial@5000400 { + compatible = "snps,dw-apb-uart"; + reg = <0x05000400 0x400>; + interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART1>; + resets = <&ccu RST_BUS_UART1>; + status = "disabled"; + }; + + uart2: serial@5000800 { + compatible = "snps,dw-apb-uart"; + reg = <0x05000800 0x400>; + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART2>; + resets = <&ccu RST_BUS_UART2>; + status = "disabled"; + }; + + uart3: serial@5000c00 { + compatible = "snps,dw-apb-uart"; + reg = <0x05000c00 0x400>; + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART3>; + resets = <&ccu RST_BUS_UART3>; + status = "disabled"; + }; + + uart4: serial@5001000 { + compatible = "snps,dw-apb-uart"; + reg = <0x05001000 0x400>; + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART4>; + resets = <&ccu RST_BUS_UART4>; + status = "disabled"; + }; + + uart5: serial@5001400 { + compatible = "snps,dw-apb-uart"; + reg = <0x05001400 0x400>; + interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART5>; + resets = <&ccu RST_BUS_UART5>; + status = "disabled"; + }; + + i2c0: i2c@5002000 { + compatible = "allwinner,sun50i-h616-i2c", + "allwinner,sun8i-v536-i2c", + "allwinner,sun6i-a31-i2c"; + reg = <0x05002000 0x400>; + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_I2C0>; + resets = <&ccu RST_BUS_I2C0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c1: i2c@5002400 { + compatible = "allwinner,sun50i-h616-i2c", + "allwinner,sun8i-v536-i2c", + "allwinner,sun6i-a31-i2c"; + reg = <0x05002400 0x400>; + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_I2C1>; + resets = <&ccu RST_BUS_I2C1>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c2: i2c@5002800 { + compatible = "allwinner,sun50i-h616-i2c", + "allwinner,sun8i-v536-i2c", + "allwinner,sun6i-a31-i2c"; + reg = <0x05002800 0x400>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_I2C2>; + resets = <&ccu RST_BUS_I2C2>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c3: i2c@5002c00 { + compatible = "allwinner,sun50i-h616-i2c", + "allwinner,sun8i-v536-i2c", + "allwinner,sun6i-a31-i2c"; + reg = <0x05002c00 0x400>; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_I2C3>; + resets = <&ccu RST_BUS_I2C3>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c4: i2c@5003000 { + compatible = "allwinner,sun50i-h616-i2c", + "allwinner,sun8i-v536-i2c", + "allwinner,sun6i-a31-i2c"; + reg = <0x05003000 0x400>; + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_I2C4>; + resets = <&ccu RST_BUS_I2C4>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + spi0: spi@5010000 { + compatible = "allwinner,sun50i-h616-spi", + "allwinner,sun8i-h3-spi"; + reg = <0x05010000 0x1000>; + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; + clock-names = "ahb", "mod"; + resets = <&ccu RST_BUS_SPI0>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + spi1: spi@5011000 { + compatible = "allwinner,sun50i-h616-spi", + "allwinner,sun8i-h3-spi"; + reg = <0x05011000 0x1000>; + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; + clock-names = "ahb", "mod"; + resets = <&ccu RST_BUS_SPI1>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + emac0: ethernet@5020000 { + compatible = "allwinner,sun50i-h616-emac0", + "allwinner,sun50i-a64-emac"; + reg = <0x05020000 0x10000>; + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq"; + clocks = <&ccu CLK_BUS_EMAC0>; + clock-names = "stmmaceth"; + resets = <&ccu RST_BUS_EMAC0>; + reset-names = "stmmaceth"; + syscon = <&syscon>; + status = "disabled"; + + mdio0: mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + rtc: rtc@7000000 { + compatible = "allwinner,sun50i-h616-rtc"; + reg = <0x07000000 0x400>; + interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&r_ccu CLK_R_APB1_RTC>, <&osc24M>, + <&ccu CLK_PLL_SYSTEM_32K>; + clock-names = "bus", "hosc", + "pll-32k"; + #clock-cells = <1>; + }; + + r_ccu: clock@7010000 { + compatible = "allwinner,sun50i-h616-r-ccu"; + reg = <0x07010000 0x210>; + clocks = <&osc24M>, <&rtc CLK_OSC32K>, <&rtc CLK_IOSC>, + <&ccu CLK_PLL_PERIPH0>; + clock-names = "hosc", "losc", "iosc", "pll-periph"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + r_pio: pinctrl@7022000 { + compatible = "allwinner,sun50i-h616-r-pinctrl"; + reg = <0x07022000 0x400>; + clocks = <&r_ccu CLK_R_APB1>, <&osc24M>, + <&rtc CLK_OSC32K>; + clock-names = "apb", "hosc", "losc"; + gpio-controller; + #gpio-cells = <3>; + + /omit-if-no-ref/ + r_i2c_pins: r-i2c-pins { + pins = "PL0", "PL1"; + function = "s_i2c"; + }; + + r_rsb_pins: r-rsb-pins { + pins = "PL0", "PL1"; + function = "s_rsb"; + }; + }; + + ir: ir@7040000 { + compatible = "allwinner,sun50i-h616-ir", + "allwinner,sun6i-a31-ir"; + reg = <0x07040000 0x400>; + interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&r_ccu CLK_R_APB1_IR>, + <&r_ccu CLK_IR>; + clock-names = "apb", "ir"; + resets = <&r_ccu RST_R_APB1_IR>; + pinctrl-names = "default"; + pinctrl-0 = <&ir_rx_pin>; + status = "disabled"; + }; + + r_i2c: i2c@7081400 { + compatible = "allwinner,sun50i-h616-i2c", + "allwinner,sun8i-v536-i2c", + "allwinner,sun6i-a31-i2c"; + reg = <0x07081400 0x400>; + interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&r_ccu CLK_R_APB2_I2C>; + resets = <&r_ccu RST_R_APB2_I2C>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + r_rsb: rsb@7083000 { + compatible = "allwinner,sun50i-h616-rsb", + "allwinner,sun8i-a23-rsb"; + reg = <0x07083000 0x400>; + interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&r_ccu CLK_R_APB2_RSB>; + clock-frequency = <3000000>; + resets = <&r_ccu RST_R_APB2_RSB>; + pinctrl-names = "default"; + pinctrl-0 = <&r_rsb_pins>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/altera/Makefile b/arch/arm64/boot/dts/altera/Makefile index 4db83fbeb115..1bf0c472f6b4 100644 --- a/arch/arm64/boot/dts/altera/Makefile +++ b/arch/arm64/boot/dts/altera/Makefile @@ -1,3 +1,4 @@ # SPDX-License-Identifier: GPL-2.0-only dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += socfpga_stratix10_socdk.dtb \ - socfpga_stratix10_socdk_nand.dtb + socfpga_stratix10_socdk_nand.dtb \ + socfpga_stratix10_swvp.dtb diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi index aa2bba75265f..14c220d87807 100644 --- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi @@ -97,6 +97,34 @@ <0x0 0xfffc6000 0x0 0x2000>; }; + clocks { + cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + }; + + cb_intosc_ls_clk: cb-intosc-ls-clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + }; + + f2s_free_clk: f2s-free-clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + }; + + osc1: osc1 { + #clock-cells = <0>; + compatible = "fixed-clock"; + }; + + qspi_clk: qspi-clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <200000000>; + }; + }; + soc { #address-cells = <1>; #size-cells = <1>; @@ -119,34 +147,6 @@ #clock-cells = <1>; }; - clocks { - cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - }; - - cb_intosc_ls_clk: cb-intosc-ls-clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - }; - - f2s_free_clk: f2s-free-clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - }; - - osc1: osc1 { - #clock-cells = <0>; - compatible = "fixed-clock"; - }; - - qspi_clk: qspi-clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <200000000>; - }; - }; - gmac0: ethernet@ff800000 { compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac"; reg = <0xff800000 0x2000>; @@ -594,7 +594,7 @@ }; qspi: spi@ff8d2000 { - compatible = "intel,socfpga-qspi", "cdns,qspi-nor"; + compatible = "intel,socfpga-qspi", "cdns,qspi-nor"; #address-cells = <1>; #size-cells = <0>; reg = <0xff8d2000 0x100>, diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts index 5159cd5771dc..48424e459f12 100644 --- a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts @@ -52,12 +52,6 @@ }; soc { - clocks { - osc1 { - clock-frequency = <25000000>; - }; - }; - eccmgr { sdmmca-ecc@ff8c8c00 { compatible = "altr,socfpga-s10-sdmmc-ecc", @@ -113,6 +107,10 @@ bus-width = <4>; }; +&osc1 { + clock-frequency = <25000000>; +}; + &uart0 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts index 0ab676c639a1..847a7c01f5af 100644 --- a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts @@ -52,12 +52,6 @@ }; soc { - clocks { - osc1 { - clock-frequency = <25000000>; - }; - }; - eccmgr { sdmmca-ecc@ff8c8c00 { compatible = "altr,socfpga-s10-sdmmc-ecc", @@ -126,6 +120,10 @@ }; }; +&osc1 { + clock-frequency = <25000000>; +}; + &uart0 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_swvp.dts b/arch/arm64/boot/dts/altera/socfpga_stratix10_swvp.dts new file mode 100644 index 000000000000..a8db58573954 --- /dev/null +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10_swvp.dts @@ -0,0 +1,117 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2022, Intel Corporation + */ + +#include "socfpga_stratix10.dtsi" + +/ { + model = "SOCFPGA Stratix 10 SWVP"; + compatible = "altr,socfpga-stratix10-swvp", "altr,socfpga-stratix10"; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + + timer0 = &timer0; + timer1 = &timer1; + timer2 = &timer2; + timer3 = &timer3; + + ethernet0 = &gmac0; + ethernet1 = &gmac1; + ethernet2 = &gmac2; + }; + + chosen { + stdout-path = "serial1:115200n8"; + linux,initrd-start = <0x10000000>; + linux,initrd-end = <0x125c8324>; + }; + + memory { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; +}; + +&cpu0 { + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x0000fff8>; +}; + +&cpu1 { + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x0000fff8>; +}; + +&cpu2 { + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x0000fff8>; +}; + +&cpu3 { + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x0000fff8>; +}; + +&osc1 { + clock-frequency = <25000000>; +}; + +&gmac0 { + status = "okay"; + phy-mode = "rgmii"; + phy-addr = <0xffffffff>; + snps,max-mtu = <0x0>; +}; + +&gmac1 { + status = "okay"; + phy-mode = "rgmii"; + phy-addr = <0xffffffff>; +}; + +&gmac2 { + status = "okay"; + phy-mode = "rgmii"; + phy-addr = <0xffffffff>; +}; + +&mmc { + status = "okay"; + altr,dw-mshc-ciu-div = <0x3>; + altr,dw-mshc-sdr-timing = <0x0 0x3>; + cap-sd-highspeed; + cap-mmc-highspeed; + broken-cd; + bus-width = <4>; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&usb0 { + clocks = <&clkmgr STRATIX10_L4_MP_CLK>; + status = "okay"; +}; + +&usb1 { + clocks = <&clkmgr STRATIX10_L4_MP_CLK>; + status = "okay"; +}; + +&rst { + altr,modrst-offset = <0x20>; +}; + +&sysmgr { + reg = <0xffd12000 0x1000>; + interrupts = <0x0 0x10 0x4>; + cpu1-start-addr = <0xffd06230>; +}; diff --git a/arch/arm64/boot/dts/amd/amd-overdrive-rev-b0.dts b/arch/arm64/boot/dts/amd/amd-overdrive-rev-b0.dts index c290d1ce2b03..02bff65e5fd6 100644 --- a/arch/arm64/boot/dts/amd/amd-overdrive-rev-b0.dts +++ b/arch/arm64/boot/dts/amd/amd-overdrive-rev-b0.dts @@ -20,8 +20,8 @@ }; psci { - compatible = "arm,psci-0.2"; - method = "smc"; + compatible = "arm,psci-0.2"; + method = "smc"; }; }; diff --git a/arch/arm64/boot/dts/amd/amd-overdrive-rev-b1.dts b/arch/arm64/boot/dts/amd/amd-overdrive-rev-b1.dts index e0926f6bb7c3..07dab1f1e3c8 100644 --- a/arch/arm64/boot/dts/amd/amd-overdrive-rev-b1.dts +++ b/arch/arm64/boot/dts/amd/amd-overdrive-rev-b1.dts @@ -20,8 +20,8 @@ }; psci { - compatible = "arm,psci-0.2"; - method = "smc"; + compatible = "arm,psci-0.2"; + method = "smc"; }; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi index 3f5254eeb47b..04f797b5a012 100644 --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi @@ -1535,7 +1535,7 @@ sysctrl_AO: sys-ctrl@0 { compatible = "amlogic,meson-axg-ao-sysctrl", "simple-mfd", "syscon"; - reg = <0x0 0x0 0x0 0x100>; + reg = <0x0 0x0 0x0 0x100>; clkc_AO: clock-controller { compatible = "amlogic,meson-axg-aoclkc"; diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-gsking-x.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-gsking-x.dts index 6c7bfacbad78..1fa6e75abd21 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-gsking-x.dts +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-gsking-x.dts @@ -20,10 +20,16 @@ rtc1 = &vrtc; }; + gpio_fan: gpio-fan { + compatible = "gpio-fan"; + gpios = <&gpio GPIOH_5 GPIO_ACTIVE_HIGH>; + /* Using Dummy Speed */ + gpio-fan,speed-map = <0 0>, <1 1>; + #cooling-cells = <2>; + }; + gpio-keys-polled { compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; poll-interval = <100>; power-button { @@ -96,6 +102,23 @@ status = "okay"; }; +&cpu_thermal { + trips { + cpu_active: cpu-active { + temperature = <70000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + }; + + cooling-maps { + map { + trip = <&cpu_active>; + cooling-device = <&gpio_fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; +}; + &frddr_a { status = "okay"; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-gtking-pro.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-gtking-pro.dts index 707daf92787b..afe375fa83ca 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-gtking-pro.dts +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-gtking-pro.dts @@ -21,8 +21,6 @@ gpio-keys-polled { compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; poll-interval = <100>; power-button { diff --git a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi index aa14ea017a61..023a52005494 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi @@ -450,7 +450,7 @@ sysctrl_AO: sys-ctrl@0 { compatible = "amlogic,meson-gx-ao-sysctrl", "simple-mfd", "syscon"; - reg = <0x0 0x0 0x0 0x100>; + reg = <0x0 0x0 0x0 0x100>; clkc_AO: clock-controller { compatible = "amlogic,meson-gx-aoclkc"; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-kii-pro.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-kii-pro.dts index e8394a8269ee..6d8cc00fedc7 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-kii-pro.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-kii-pro.dts @@ -26,8 +26,6 @@ gpio-keys-polled { compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; poll-interval = <20>; button-reset { diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts index f887bfb445fd..63137ce3cb9d 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts @@ -42,11 +42,9 @@ gpio-keys-polled { compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; poll-interval = <100>; - button@0 { + button { label = "reset"; linux,code = <KEY_RESTART>; gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_LOW>; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-play2.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-play2.dts index 6eae692792ec..505ffcd8eb76 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-play2.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-play2.dts @@ -37,11 +37,9 @@ gpio-keys-polled { compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; poll-interval = <100>; - button@0 { + button { label = "reset"; linux,code = <KEY_RESTART>; gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_LOW>; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-mecool-kii-pro.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-mecool-kii-pro.dts index c529b6c860a4..a4fa186f0458 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-mecool-kii-pro.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-mecool-kii-pro.dts @@ -30,11 +30,9 @@ gpio-keys-polled { compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; poll-interval = <100>; - button@0 { + button { label = "power"; linux,code = <KEY_POWER>; gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW>; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts index b2ab05c22090..c1470416faad 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts @@ -30,11 +30,9 @@ gpio-keys-polled { compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; poll-interval = <100>; - button@0 { + button { label = "power"; linux,code = <KEY_POWER>; gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW>; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-vero4k-plus.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-vero4k-plus.dts index 4b0ff707e21b..595b49085074 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-vero4k-plus.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-vero4k-plus.dts @@ -16,11 +16,9 @@ gpio-keys-polled { compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; poll-interval = <20>; - button@0 { + button { label = "power"; linux,code = <KEY_POWER>; gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_HIGH>; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905w-jethome-jethub-j80.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905w-jethome-jethub-j80.dts index fcb304c5a40f..6831137c5c10 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905w-jethome-jethub-j80.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905w-jethome-jethub-j80.dts @@ -216,7 +216,7 @@ bluetooth { compatible = "realtek,rtl8822cs-bt"; - enable-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; + enable-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; host-wake-gpios = <&gpio GPIOX_18 GPIO_ACTIVE_HIGH>; }; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-mecool-kiii-pro.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-mecool-kiii-pro.dts index ebebf344b715..f5b3424c0f61 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxm-mecool-kiii-pro.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxm-mecool-kiii-pro.dts @@ -35,11 +35,9 @@ gpio-keys-polled { compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; poll-interval = <100>; - button@0 { + button { label = "power"; linux,code = <KEY_POWER>; gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW>; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-minix-neo-u9h.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-minix-neo-u9h.dts index ea9f234d1fc7..b8ef3bd8b840 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxm-minix-neo-u9h.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxm-minix-neo-u9h.dts @@ -41,11 +41,9 @@ gpio-keys-polled { compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; poll-interval = <100>; - button@0 { + button { label = "power"; linux,code = <KEY_POWER>; gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW>; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-q200.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-q200.dts index 8edbfe040805..d4858afa0e9c 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxm-q200.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxm-q200.dts @@ -30,11 +30,9 @@ gpio-keys-polled { compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; poll-interval = <100>; - button@0 { + button { label = "power"; linux,code = <KEY_POWER>; gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW>; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-wetek-core2.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-wetek-core2.dts index 1e7f77f9b533..f8c40340b9c5 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxm-wetek-core2.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxm-wetek-core2.dts @@ -45,8 +45,6 @@ gpio-keys-polled { compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; poll-interval = <100>; button-power { diff --git a/arch/arm64/boot/dts/amlogic/meson-s4.dtsi b/arch/arm64/boot/dts/amlogic/meson-s4.dtsi index ff213618a598..ad50cba42d19 100644 --- a/arch/arm64/boot/dts/amlogic/meson-s4.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-s4.dtsi @@ -127,6 +127,12 @@ clocks = <&xtal>, <&xtal>, <&xtal>; clock-names = "xtal", "pclk", "baud"; }; + + reset: reset-controller@2000 { + compatible = "amlogic,meson-s4-reset"; + reg = <0x0 0x2000 0x0 0x98>; + #reset-cells = <1>; + }; }; }; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-sei610.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-sei610.dts index a5d79f2f7c19..603337ca5608 100644 --- a/arch/arm64/boot/dts/amlogic/meson-sm1-sei610.dts +++ b/arch/arm64/boot/dts/amlogic/meson-sm1-sei610.dts @@ -48,7 +48,7 @@ gpio-keys { compatible = "gpio-keys"; - key1 { + key-1 { label = "A"; linux,code = <BTN_0>; gpios = <&gpio GPIOH_6 GPIO_ACTIVE_LOW>; @@ -56,7 +56,7 @@ interrupts = <34 IRQ_TYPE_EDGE_BOTH>; }; - key2 { + key-2 { label = "B"; linux,code = <BTN_1>; gpios = <&gpio GPIOH_7 GPIO_ACTIVE_LOW>; @@ -64,7 +64,7 @@ interrupts = <35 IRQ_TYPE_EDGE_BOTH>; }; - key3 { + key-3 { label = "C"; linux,code = <BTN_2>; gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW>; @@ -72,7 +72,7 @@ interrupts = <2 IRQ_TYPE_EDGE_BOTH>; }; - mic_mute { + key-mic-mute { label = "MicMute"; linux,code = <SW_MUTE_DEVICE>; linux,input-type = <EV_SW>; @@ -81,7 +81,7 @@ interrupts = <99 IRQ_TYPE_EDGE_BOTH>; }; - power_key { + key-power { label = "PowerKey"; linux,code = <KEY_POWER>; gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_LOW>; diff --git a/arch/arm64/boot/dts/apm/apm-merlin.dts b/arch/arm64/boot/dts/apm/apm-merlin.dts index 217d7728b63a..049e7a5edca7 100644 --- a/arch/arm64/boot/dts/apm/apm-merlin.dts +++ b/arch/arm64/boot/dts/apm/apm-merlin.dts @@ -22,7 +22,7 @@ gpio-keys { compatible = "gpio-keys"; - button@1 { + button { label = "POWER"; linux,code = <116>; linux,input-type = <0x1>; diff --git a/arch/arm64/boot/dts/apm/apm-mustang.dts b/arch/arm64/boot/dts/apm/apm-mustang.dts index e927811ade28..efac50aeca64 100644 --- a/arch/arm64/boot/dts/apm/apm-mustang.dts +++ b/arch/arm64/boot/dts/apm/apm-mustang.dts @@ -22,7 +22,7 @@ gpio-keys { compatible = "gpio-keys"; - button@1 { + button { label = "POWER"; linux,code = <116>; linux,input-type = <0x1>; diff --git a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi index a83c82c50e29..a8526f8157ec 100644 --- a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi +++ b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi @@ -597,11 +597,11 @@ interrupts = <0x0 0x4c 0x4>; }; - /* Do not change dwusb name, coded for backward compatibility */ - usb0: dwusb@19000000 { + /* Node-name might need to be coded as dwusb for backward compatibility */ + usb0: usb@19000000 { status = "disabled"; compatible = "snps,dwc3"; - reg = <0x0 0x19000000 0x0 0x100000>; + reg = <0x0 0x19000000 0x0 0x100000>; interrupts = <0x0 0x5d 0x4>; dma-coherent; dr_mode = "host"; diff --git a/arch/arm64/boot/dts/apm/apm-storm.dtsi b/arch/arm64/boot/dts/apm/apm-storm.dtsi index 0f37e77f5459..f56d687f772d 100644 --- a/arch/arm64/boot/dts/apm/apm-storm.dtsi +++ b/arch/arm64/boot/dts/apm/apm-storm.dtsi @@ -923,20 +923,20 @@ phy-names = "sata-phy"; }; - /* Do not change dwusb name, coded for backward compatibility */ - usb0: dwusb@19000000 { + /* Node-name might need to be coded as dwusb for backward compatibility */ + usb0: usb@19000000 { status = "disabled"; compatible = "snps,dwc3"; - reg = <0x0 0x19000000 0x0 0x100000>; + reg = <0x0 0x19000000 0x0 0x100000>; interrupts = <0x0 0x89 0x4>; dma-coherent; dr_mode = "host"; }; - usb1: dwusb@19800000 { + usb1: usb@19800000 { status = "disabled"; compatible = "snps,dwc3"; - reg = <0x0 0x19800000 0x0 0x100000>; + reg = <0x0 0x19800000 0x0 0x100000>; interrupts = <0x0 0x8a 0x4>; dma-coherent; dr_mode = "host"; diff --git a/arch/arm64/boot/dts/arm/fvp-base-revc.dts b/arch/arm64/boot/dts/arm/fvp-base-revc.dts index a496e39e6204..5f6f30c801a7 100644 --- a/arch/arm64/boot/dts/arm/fvp-base-revc.dts +++ b/arch/arm64/boot/dts/arm/fvp-base-revc.dts @@ -186,7 +186,7 @@ }; panel { - compatible = "arm,rtsm-display", "panel-dpi"; + compatible = "arm,rtsm-display"; port { panel_in: endpoint { remote-endpoint = <&clcd_pads>; diff --git a/arch/arm64/boot/dts/arm/juno-base.dtsi b/arch/arm64/boot/dts/arm/juno-base.dtsi index 065381c1cbf5..8d0d45d168d1 100644 --- a/arch/arm64/boot/dts/arm/juno-base.dtsi +++ b/arch/arm64/boot/dts/arm/juno-base.dtsi @@ -581,36 +581,36 @@ trig-conns@0 { reg = <0>; - arm,trig-in-sigs=<2 3>; - arm,trig-in-types=<SNK_FULL SNK_ACQCOMP>; - arm,trig-out-sigs=<0 1>; - arm,trig-out-types=<SNK_FLUSHIN SNK_TRIGIN>; + arm,trig-in-sigs = <2 3>; + arm,trig-in-types = <SNK_FULL SNK_ACQCOMP>; + arm,trig-out-sigs = <0 1>; + arm,trig-out-types = <SNK_FLUSHIN SNK_TRIGIN>; arm,cs-dev-assoc = <&etr_sys>; }; trig-conns@1 { reg = <1>; - arm,trig-in-sigs=<0 1>; - arm,trig-in-types=<SNK_FULL SNK_ACQCOMP>; - arm,trig-out-sigs=<7 6>; - arm,trig-out-types=<SNK_FLUSHIN SNK_TRIGIN>; + arm,trig-in-sigs = <0 1>; + arm,trig-in-types = <SNK_FULL SNK_ACQCOMP>; + arm,trig-out-sigs = <7 6>; + arm,trig-out-types = <SNK_FLUSHIN SNK_TRIGIN>; arm,cs-dev-assoc = <&etf_sys0>; }; trig-conns@2 { reg = <2>; - arm,trig-in-sigs=<4 5 6 7>; - arm,trig-in-types=<STM_TOUT_SPTE STM_TOUT_SW + arm,trig-in-sigs = <4 5 6 7>; + arm,trig-in-types = <STM_TOUT_SPTE STM_TOUT_SW STM_TOUT_HETE STM_ASYNCOUT>; - arm,trig-out-sigs=<4 5>; - arm,trig-out-types=<STM_HWEVENT STM_HWEVENT>; + arm,trig-out-sigs = <4 5>; + arm,trig-out-types = <STM_HWEVENT STM_HWEVENT>; arm,cs-dev-assoc = <&stm_sys>; }; trig-conns@3 { reg = <3>; - arm,trig-out-sigs=<2 3>; - arm,trig-out-types=<SNK_FLUSHIN SNK_TRIGIN>; + arm,trig-out-sigs = <2 3>; + arm,trig-out-types = <SNK_FLUSHIN SNK_TRIGIN>; arm,cs-dev-assoc = <&tpiu_sys>; }; }; @@ -628,24 +628,24 @@ trig-conns@0 { reg = <0>; - arm,trig-in-sigs=<0>; - arm,trig-in-types=<GEN_INTREQ>; - arm,trig-out-sigs=<0>; - arm,trig-out-types=<GEN_HALTREQ>; + arm,trig-in-sigs = <0>; + arm,trig-in-types = <GEN_INTREQ>; + arm,trig-out-sigs = <0>; + arm,trig-out-types = <GEN_HALTREQ>; arm,trig-conn-name = "sys_profiler"; }; trig-conns@1 { reg = <1>; - arm,trig-out-sigs=<2 3>; - arm,trig-out-types=<GEN_HALTREQ GEN_RESTARTREQ>; + arm,trig-out-sigs = <2 3>; + arm,trig-out-types = <GEN_HALTREQ GEN_RESTARTREQ>; arm,trig-conn-name = "watchdog"; }; trig-conns@2 { reg = <2>; - arm,trig-out-sigs=<1 6>; - arm,trig-out-types=<GEN_HALTREQ GEN_RESTARTREQ>; + arm,trig-out-sigs = <1 6>; + arm,trig-out-types = <GEN_HALTREQ GEN_RESTARTREQ>; arm,trig-conn-name = "g_counter"; }; }; diff --git a/arch/arm64/boot/dts/arm/juno-cs-r1r2.dtsi b/arch/arm64/boot/dts/arm/juno-cs-r1r2.dtsi index 2e43f4531308..ba88d1596f6f 100644 --- a/arch/arm64/boot/dts/arm/juno-cs-r1r2.dtsi +++ b/arch/arm64/boot/dts/arm/juno-cs-r1r2.dtsi @@ -96,24 +96,24 @@ trig-conns@0 { reg = <0>; - arm,trig-in-sigs=<0 1>; - arm,trig-in-types=<SNK_FULL SNK_ACQCOMP>; - arm,trig-out-sigs=<0 1>; - arm,trig-out-types=<SNK_FLUSHIN SNK_TRIGIN>; + arm,trig-in-sigs = <0 1>; + arm,trig-in-types = <SNK_FULL SNK_ACQCOMP>; + arm,trig-out-sigs = <0 1>; + arm,trig-out-types = <SNK_FLUSHIN SNK_TRIGIN>; arm,cs-dev-assoc = <&etf_sys1>; }; trig-conns@1 { reg = <1>; - arm,trig-in-sigs=<2 3 4>; - arm,trig-in-types=<ELA_DBGREQ ELA_TSTART ELA_TSTOP>; + arm,trig-in-sigs = <2 3 4>; + arm,trig-in-types = <ELA_DBGREQ ELA_TSTART ELA_TSTOP>; arm,trig-conn-name = "ela_clus_0"; }; trig-conns@2 { reg = <2>; - arm,trig-in-sigs=<5 6 7>; - arm,trig-in-types=<ELA_DBGREQ ELA_TSTART ELA_TSTOP>; + arm,trig-in-sigs = <5 6 7>; + arm,trig-in-types = <ELA_DBGREQ ELA_TSTART ELA_TSTOP>; arm,trig-conn-name = "ela_clus_1"; }; }; diff --git a/arch/arm64/boot/dts/arm/juno-r1.dts b/arch/arm64/boot/dts/arm/juno-r1.dts index f099fb611d4e..6451c62146fd 100644 --- a/arch/arm64/boot/dts/arm/juno-r1.dts +++ b/arch/arm64/boot/dts/arm/juno-r1.dts @@ -192,6 +192,7 @@ cache-size = <0x200000>; cache-line-size = <64>; cache-sets = <2048>; + cache-level = <2>; }; A53_L2: l2-cache1 { @@ -199,6 +200,7 @@ cache-size = <0x100000>; cache-line-size = <64>; cache-sets = <1024>; + cache-level = <2>; }; }; diff --git a/arch/arm64/boot/dts/arm/juno-r2.dts b/arch/arm64/boot/dts/arm/juno-r2.dts index 709389582ae3..438cd1ff4bd0 100644 --- a/arch/arm64/boot/dts/arm/juno-r2.dts +++ b/arch/arm64/boot/dts/arm/juno-r2.dts @@ -198,6 +198,7 @@ cache-size = <0x200000>; cache-line-size = <64>; cache-sets = <2048>; + cache-level = <2>; }; A53_L2: l2-cache1 { @@ -205,6 +206,7 @@ cache-size = <0x100000>; cache-line-size = <64>; cache-sets = <1024>; + cache-level = <2>; }; }; diff --git a/arch/arm64/boot/dts/arm/juno-scmi.dtsi b/arch/arm64/boot/dts/arm/juno-scmi.dtsi index 4135d62e44a2..ec85cd2c733c 100644 --- a/arch/arm64/boot/dts/arm/juno-scmi.dtsi +++ b/arch/arm64/boot/dts/arm/juno-scmi.dtsi @@ -187,7 +187,6 @@ &mailbox { compatible = "arm,mhu-doorbell", "arm,primecell"; #mbox-cells = <2>; - mbox-name = "ARM-MHU"; }; &smmu_etr { diff --git a/arch/arm64/boot/dts/arm/juno.dts b/arch/arm64/boot/dts/arm/juno.dts index dbc22e70b62c..cf4a58211399 100644 --- a/arch/arm64/boot/dts/arm/juno.dts +++ b/arch/arm64/boot/dts/arm/juno.dts @@ -197,6 +197,7 @@ cache-size = <0x200000>; cache-line-size = <64>; cache-sets = <2048>; + cache-level = <2>; }; A53_L2: l2-cache1 { @@ -204,6 +205,7 @@ cache-size = <0x100000>; cache-line-size = <64>; cache-sets = <1024>; + cache-level = <2>; }; }; diff --git a/arch/arm64/boot/dts/broadcom/Makefile b/arch/arm64/boot/dts/broadcom/Makefile index 5082fcd1fea5..e8584d3b698f 100644 --- a/arch/arm64/boot/dts/broadcom/Makefile +++ b/arch/arm64/boot/dts/broadcom/Makefile @@ -9,5 +9,6 @@ dtb-$(CONFIG_ARCH_BCM2835) += bcm2711-rpi-400.dtb \ bcm2837-rpi-zero-2-w.dtb subdir-y += bcm4908 +subdir-y += bcmbca subdir-y += northstar2 subdir-y += stingray diff --git a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4906-tplink-archer-c2300-v1.dts b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4906-tplink-archer-c2300-v1.dts index b63eefab48bd..064f7f549665 100644 --- a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4906-tplink-archer-c2300-v1.dts +++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4906-tplink-archer-c2300-v1.dts @@ -83,25 +83,25 @@ compatible = "gpio-keys-polled"; poll-interval = <100>; - brightness { + key-brightness { label = "LEDs"; linux,code = <KEY_BRIGHTNESS_ZERO>; gpios = <&gpio0 18 GPIO_ACTIVE_LOW>; }; - wps { + key-wps { label = "WPS"; linux,code = <KEY_WPS_BUTTON>; gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; }; - wifi { + key-wifi { label = "WiFi"; linux,code = <KEY_RFKILL>; gpios = <&gpio0 22 GPIO_ACTIVE_LOW>; }; - restart { + key-restart { label = "Reset"; linux,code = <KEY_RESTART>; gpios = <&gpio0 23 GPIO_ACTIVE_LOW>; diff --git a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908-asus-gt-ac5300.dts b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908-asus-gt-ac5300.dts index 169fbb7cfd34..04f8524b5335 100644 --- a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908-asus-gt-ac5300.dts +++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908-asus-gt-ac5300.dts @@ -18,25 +18,25 @@ compatible = "gpio-keys-polled"; poll-interval = <100>; - wifi { + key-wifi { label = "WiFi"; linux,code = <KEY_RFKILL>; gpios = <&gpio0 28 GPIO_ACTIVE_LOW>; }; - wps { + key-wps { label = "WPS"; linux,code = <KEY_WPS_BUTTON>; gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; }; - restart { + key-restart { label = "Reset"; linux,code = <KEY_RESTART>; gpios = <&gpio0 30 GPIO_ACTIVE_LOW>; }; - brightness { + key-brightness { label = "LEDs"; linux,code = <KEY_BRIGHTNESS_ZERO>; gpios = <&gpio0 31 GPIO_ACTIVE_LOW>; diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/Makefile b/arch/arm64/boot/dts/broadcom/bcmbca/Makefile new file mode 100644 index 000000000000..38f14307184b --- /dev/null +++ b/arch/arm64/boot/dts/broadcom/bcmbca/Makefile @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_BCMBCA) += \ + bcm4912-asus-gt-ax6000.dtb \ + bcm94912.dtb \ + bcm963158.dtb \ + bcm96858.dtb \ + bcm963146.dtb \ + bcm96856.dtb \ + bcm96813.dtb diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4912-asus-gt-ax6000.dts b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4912-asus-gt-ax6000.dts new file mode 100644 index 000000000000..ed554666e95e --- /dev/null +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4912-asus-gt-ax6000.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +/dts-v1/; + +#include "bcm4912.dtsi" + +/ { + compatible = "asus,gt-ax6000", "brcm,bcm4912", "brcm,bcmbca"; + model = "Asus GT-AX6000"; + + memory@0 { + device_type = "memory"; + reg = <0x00 0x00 0x00 0x40000000>; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi new file mode 100644 index 000000000000..3d016c2ce675 --- /dev/null +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi @@ -0,0 +1,128 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Broadcom Ltd. + */ + +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + compatible = "brcm,bcm4912", "brcm,bcmbca"; + #address-cells = <2>; + #size-cells = <2>; + + interrupt-parent = <&gic>; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + B53_0: cpu@0 { + compatible = "brcm,brahma-b53"; + device_type = "cpu"; + reg = <0x0 0x0>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + B53_1: cpu@1 { + compatible = "brcm,brahma-b53"; + device_type = "cpu"; + reg = <0x0 0x1>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + B53_2: cpu@2 { + compatible = "brcm,brahma-b53"; + device_type = "cpu"; + reg = <0x0 0x2>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + B53_3: cpu@3 { + compatible = "brcm,brahma-b53"; + device_type = "cpu"; + reg = <0x0 0x3>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + L2_0: l2-cache0 { + compatible = "cache"; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; + }; + + pmu: pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&B53_0>, <&B53_1>, + <&B53_2>, <&B53_3>; + }; + + clocks: clocks { + periph_clk: periph-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; + uart_clk: uart-clk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&periph_clk>; + clock-div = <4>; + clock-mult = <1>; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + axi@81000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x81000000 0x8000>; + + gic: interrupt-controller@1000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + interrupt-controller; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + reg = <0x1000 0x1000>, + <0x2000 0x2000>, + <0x4000 0x2000>, + <0x6000 0x2000>; + }; + }; + + bus@ff800000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0xff800000 0x800000>; + + uart0: serial@12000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x12000 0x1000>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&uart_clk>, <&uart_clk>; + clock-names = "uartclk", "apb_pclk"; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi b/arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi new file mode 100644 index 000000000000..04de96bd0a03 --- /dev/null +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi @@ -0,0 +1,110 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Broadcom Ltd. + */ + +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + compatible = "brcm,bcm63146", "brcm,bcmbca"; + #address-cells = <2>; + #size-cells = <2>; + + interrupt-parent = <&gic>; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + B53_0: cpu@0 { + compatible = "brcm,brahma-b53"; + device_type = "cpu"; + reg = <0x0 0x0>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + B53_1: cpu@1 { + compatible = "brcm,brahma-b53"; + device_type = "cpu"; + reg = <0x0 0x1>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + L2_0: l2-cache0 { + compatible = "cache"; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; + }; + + pmu: pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&B53_0>, <&B53_1>; + }; + + clocks: clocks { + periph_clk: periph-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; + uart_clk: uart-clk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&periph_clk>; + clock-div = <4>; + clock-mult = <1>; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + axi@81000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x81000000 0x8000>; + + gic: interrupt-controller@1000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x1000 0x1000>, + <0x2000 0x2000>, + <0x4000 0x2000>, + <0x6000 0x2000>; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | + IRQ_TYPE_LEVEL_HIGH)>; + }; + }; + + bus@ff800000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0xff800000 0x800000>; + + uart0: serial@12000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x12000 0x1000>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&uart_clk>, <&uart_clk>; + clock-names = "uartclk", "apb_pclk"; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi b/arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi new file mode 100644 index 000000000000..13629702f70b --- /dev/null +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi @@ -0,0 +1,128 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Broadcom Ltd. + */ + +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + compatible = "brcm,bcm63158", "brcm,bcmbca"; + #address-cells = <2>; + #size-cells = <2>; + + interrupt-parent = <&gic>; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + B53_0: cpu@0 { + compatible = "brcm,brahma-b53"; + device_type = "cpu"; + reg = <0x0 0x0>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + B53_1: cpu@1 { + compatible = "brcm,brahma-b53"; + device_type = "cpu"; + reg = <0x0 0x1>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + B53_2: cpu@2 { + compatible = "brcm,brahma-b53"; + device_type = "cpu"; + reg = <0x0 0x2>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + B53_3: cpu@3 { + compatible = "brcm,brahma-b53"; + device_type = "cpu"; + reg = <0x0 0x3>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + L2_0: l2-cache0 { + compatible = "cache"; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; + }; + + pmu: pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&B53_0>, <&B53_1>, + <&B53_2>, <&B53_3>; + }; + + clocks: clocks { + periph_clk: periph-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; + uart_clk: uart-clk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&periph_clk>; + clock-div = <4>; + clock-mult = <1>; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + axi@81000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x81000000 0x8000>; + + gic: interrupt-controller@1000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + interrupt-controller; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + reg = <0x1000 0x1000>, + <0x2000 0x2000>, + <0x4000 0x2000>, + <0x6000 0x2000>; + }; + }; + + bus@ff800000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0xff800000 0x800000>; + + uart0: serial@12000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x12000 0x1000>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&uart_clk>, <&uart_clk>; + clock-names = "uartclk", "apb_pclk"; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6813.dtsi b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6813.dtsi new file mode 100644 index 000000000000..c3e6197be808 --- /dev/null +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6813.dtsi @@ -0,0 +1,128 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Broadcom Ltd. + */ + +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + compatible = "brcm,bcm6813", "brcm,bcmbca"; + #address-cells = <2>; + #size-cells = <2>; + + interrupt-parent = <&gic>; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + B53_0: cpu@0 { + compatible = "brcm,brahma-b53"; + device_type = "cpu"; + reg = <0x0 0x0>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + B53_1: cpu@1 { + compatible = "brcm,brahma-b53"; + device_type = "cpu"; + reg = <0x0 0x1>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + B53_2: cpu@2 { + compatible = "brcm,brahma-b53"; + device_type = "cpu"; + reg = <0x0 0x2>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + B53_3: cpu@3 { + compatible = "brcm,brahma-b53"; + device_type = "cpu"; + reg = <0x0 0x3>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + L2_0: l2-cache0 { + compatible = "cache"; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; + }; + + pmu: pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&B53_0>, <&B53_1>, + <&B53_2>, <&B53_3>; + }; + + clocks: clocks { + periph_clk: periph-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; + uart_clk: uart-clk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&periph_clk>; + clock-div = <4>; + clock-mult = <1>; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + axi@81000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x81000000 0x8000>; + + gic: interrupt-controller@1000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + interrupt-controller; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + reg = <0x1000 0x1000>, + <0x2000 0x2000>, + <0x4000 0x2000>, + <0x6000 0x2000>; + }; + }; + + bus@ff800000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0xff800000 0x800000>; + + uart0: serial@12000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x12000 0x1000>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&uart_clk>, <&uart_clk>; + clock-names = "uartclk", "apb_pclk"; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi new file mode 100644 index 000000000000..0bce6497219f --- /dev/null +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi @@ -0,0 +1,103 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Broadcom Ltd. + */ + +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + compatible = "brcm,bcm6856", "brcm,bcmbca"; + #address-cells = <2>; + #size-cells = <2>; + + interrupt-parent = <&gic>; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + B53_0: cpu@0 { + compatible = "brcm,brahma-b53"; + device_type = "cpu"; + reg = <0x0 0x0>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + B53_1: cpu@1 { + compatible = "brcm,brahma-b53"; + device_type = "cpu"; + reg = <0x0 0x1>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + L2_0: l2-cache0 { + compatible = "cache"; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; + }; + + pmu: pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&B53_0>, <&B53_1>; + }; + + clocks: clocks { + periph_clk:periph-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + axi@81000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x81000000 0x8000>; + + gic: interrupt-controller@1000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x1000 0x1000>, /* GICD */ + <0x2000 0x2000>, /* GICC */ + <0x4000 0x2000>, /* GICH */ + <0x6000 0x2000>; /* GICV */ + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | + IRQ_TYPE_LEVEL_HIGH)>; + }; + }; + + bus@ff800000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0xff800000 0x800000>; + + uart0: serial@640 { + compatible = "brcm,bcm6345-uart"; + reg = <0x640 0x18>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&periph_clk>; + clock-names = "refclk"; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi new file mode 100644 index 000000000000..29a880c6c858 --- /dev/null +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi @@ -0,0 +1,121 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Broadcom Ltd. + */ + +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + compatible = "brcm,bcm6858", "brcm,bcmbca"; + #address-cells = <2>; + #size-cells = <2>; + + interrupt-parent = <&gic>; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + B53_0: cpu@0 { + compatible = "brcm,brahma-b53"; + device_type = "cpu"; + reg = <0x0 0x0>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + B53_1: cpu@1 { + compatible = "brcm,brahma-b53"; + device_type = "cpu"; + reg = <0x0 0x1>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + B53_2: cpu@2 { + compatible = "brcm,brahma-b53"; + device_type = "cpu"; + reg = <0x0 0x2>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + B53_3: cpu@3 { + compatible = "brcm,brahma-b53"; + device_type = "cpu"; + reg = <0x0 0x3>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + L2_0: l2-cache0 { + compatible = "cache"; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; + }; + + pmu: pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&B53_0>, <&B53_1>, + <&B53_2>, <&B53_3>; + }; + + clocks: clocks { + periph_clk:periph-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + axi@81000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x81000000 0x8000>; + + gic: interrupt-controller@1000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x1000 0x1000>, /* GICD */ + <0x2000 0x2000>, /* GICC */ + <0x4000 0x2000>, /* GICH */ + <0x6000 0x2000>; /* GICV */ + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | + IRQ_TYPE_LEVEL_HIGH)>; + }; + }; + + bus@ff800000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0xff800000 0x62000>; + + uart0: serial@640 { + compatible = "brcm,bcm6345-uart"; + reg = <0x640 0x18>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&periph_clk>; + clock-names = "refclk"; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm94912.dts b/arch/arm64/boot/dts/broadcom/bcmbca/bcm94912.dts new file mode 100644 index 000000000000..a3623e6f6919 --- /dev/null +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm94912.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Broadcom Ltd. + */ + +/dts-v1/; + +#include "bcm4912.dtsi" + +/ { + model = "Broadcom BCM94912 Reference Board"; + compatible = "brcm,bcm94912", "brcm,bcm4912", "brcm,bcmbca"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x08000000>; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm963146.dts b/arch/arm64/boot/dts/broadcom/bcmbca/bcm963146.dts new file mode 100644 index 000000000000..e39f1e6d4774 --- /dev/null +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm963146.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Broadcom Ltd. + */ + +/dts-v1/; + +#include "bcm63146.dtsi" + +/ { + model = "Broadcom BCM963146 Reference Board"; + compatible = "brcm,bcm963146", "brcm,bcm63146", "brcm,bcmbca"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x08000000>; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm963158.dts b/arch/arm64/boot/dts/broadcom/bcmbca/bcm963158.dts new file mode 100644 index 000000000000..eba07e0b1ca6 --- /dev/null +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm963158.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Broadcom Ltd. + */ + +/dts-v1/; + +#include "bcm63158.dtsi" + +/ { + model = "Broadcom BCM963158 Reference Board"; + compatible = "brcm,bcm963158", "brcm,bcm63158", "brcm,bcmbca"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x08000000>; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm96813.dts b/arch/arm64/boot/dts/broadcom/bcmbca/bcm96813.dts new file mode 100644 index 000000000000..af17091ae764 --- /dev/null +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm96813.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Broadcom Ltd. + */ + +/dts-v1/; + +#include "bcm6813.dtsi" + +/ { + model = "Broadcom BCM96813 Reference Board"; + compatible = "brcm,bcm96813", "brcm,bcm6813", "brcm,bcmbca"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x08000000>; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm96856.dts b/arch/arm64/boot/dts/broadcom/bcmbca/bcm96856.dts new file mode 100644 index 000000000000..032aeb75c983 --- /dev/null +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm96856.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Broadcom Ltd. + */ + +/dts-v1/; + +#include "bcm6856.dtsi" + +/ { + model = "Broadcom BCM96856 Reference Board"; + compatible = "brcm,bcm96856", "brcm,bcm6856", "brcm,bcmbca"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x08000000>; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm96858.dts b/arch/arm64/boot/dts/broadcom/bcmbca/bcm96858.dts new file mode 100644 index 000000000000..0cbf582f5d54 --- /dev/null +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm96858.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Broadcom Ltd. + */ + +/dts-v1/; + +#include "bcm6858.dtsi" + +/ { + model = "Broadcom BCM96858 Reference Board"; + compatible = "brcm,bcm96858", "brcm,bcm6858", "brcm,bcmbca"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x08000000>; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi b/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi index 09d4aa8ae1d6..8f8c25e51194 100644 --- a/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi +++ b/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi @@ -567,7 +567,7 @@ reg-names = "amac_base"; dma-coherent; interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>; - status= "disabled"; + status = "disabled"; }; nand: nand@360000 { diff --git a/arch/arm64/boot/dts/exynos/exynos-pinctrl.h b/arch/arm64/boot/dts/exynos/exynos-pinctrl.h new file mode 100644 index 000000000000..7dd94a9b3652 --- /dev/null +++ b/arch/arm64/boot/dts/exynos/exynos-pinctrl.h @@ -0,0 +1,79 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Samsung Exynos DTS pinctrl constants + * + * Copyright (c) 2016 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * Copyright (c) 2022 Linaro Ltd + * Author: Krzysztof Kozlowski <krzk@kernel.org> + */ + +#ifndef __DTS_ARM64_SAMSUNG_EXYNOS_PINCTRL_H__ +#define __DTS_ARM64_SAMSUNG_EXYNOS_PINCTRL_H__ + +#define EXYNOS_PIN_PULL_NONE 0 +#define EXYNOS_PIN_PULL_DOWN 1 +#define EXYNOS_PIN_PULL_UP 3 + +/* Pin function in power down mode */ +#define EXYNOS_PIN_PDN_OUT0 0 +#define EXYNOS_PIN_PDN_OUT1 1 +#define EXYNOS_PIN_PDN_INPUT 2 +#define EXYNOS_PIN_PDN_PREV 3 + +/* + * Drive strengths for Exynos5410, Exynos542x, Exynos5800, Exynos7885, Exynos850 + * (except GPIO_HSI block), ExynosAutov9 (FSI0, PERIC1) + */ +#define EXYNOS5420_PIN_DRV_LV1 0 +#define EXYNOS5420_PIN_DRV_LV2 1 +#define EXYNOS5420_PIN_DRV_LV3 2 +#define EXYNOS5420_PIN_DRV_LV4 3 + +/* Drive strengths for Exynos5433 */ +#define EXYNOS5433_PIN_DRV_FAST_SR1 0 +#define EXYNOS5433_PIN_DRV_FAST_SR2 1 +#define EXYNOS5433_PIN_DRV_FAST_SR3 2 +#define EXYNOS5433_PIN_DRV_FAST_SR4 3 +#define EXYNOS5433_PIN_DRV_FAST_SR5 4 +#define EXYNOS5433_PIN_DRV_FAST_SR6 5 +#define EXYNOS5433_PIN_DRV_SLOW_SR1 8 +#define EXYNOS5433_PIN_DRV_SLOW_SR2 9 +#define EXYNOS5433_PIN_DRV_SLOW_SR3 0xa +#define EXYNOS5433_PIN_DRV_SLOW_SR4 0xb +#define EXYNOS5433_PIN_DRV_SLOW_SR5 0xc +#define EXYNOS5433_PIN_DRV_SLOW_SR6 0xf + +/* Drive strengths for Exynos7 (except FSYS1) */ +#define EXYNOS7_PIN_DRV_LV1 0 +#define EXYNOS7_PIN_DRV_LV2 2 +#define EXYNOS7_PIN_DRV_LV3 1 +#define EXYNOS7_PIN_DRV_LV4 3 + +/* Drive strengths for Exynos7 FSYS1 block */ +#define EXYNOS7_FSYS1_PIN_DRV_LV1 0 +#define EXYNOS7_FSYS1_PIN_DRV_LV2 4 +#define EXYNOS7_FSYS1_PIN_DRV_LV3 2 +#define EXYNOS7_FSYS1_PIN_DRV_LV4 6 +#define EXYNOS7_FSYS1_PIN_DRV_LV5 1 +#define EXYNOS7_FSYS1_PIN_DRV_LV6 5 + +/* Drive strengths for Exynos850 GPIO_HSI block */ +#define EXYNOS850_HSI_PIN_DRV_LV1 0 /* 1x */ +#define EXYNOS850_HSI_PIN_DRV_LV1_5 1 /* 1.5x */ +#define EXYNOS850_HSI_PIN_DRV_LV2 2 /* 2x */ +#define EXYNOS850_HSI_PIN_DRV_LV2_5 3 /* 2.5x */ +#define EXYNOS850_HSI_PIN_DRV_LV3 4 /* 3x */ +#define EXYNOS850_HSI_PIN_DRV_LV4 5 /* 4x */ + +#define EXYNOS_PIN_FUNC_INPUT 0 +#define EXYNOS_PIN_FUNC_OUTPUT 1 +#define EXYNOS_PIN_FUNC_2 2 +#define EXYNOS_PIN_FUNC_3 3 +#define EXYNOS_PIN_FUNC_4 4 +#define EXYNOS_PIN_FUNC_5 5 +#define EXYNOS_PIN_FUNC_6 6 +#define EXYNOS_PIN_FUNC_EINT 0xf +#define EXYNOS_PIN_FUNC_F EXYNOS_PIN_FUNC_EINT + +#endif /* __DTS_ARM64_SAMSUNG_EXYNOS_PINCTRL_H__ */ diff --git a/arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi index 4b46af3e164d..681553577ebc 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi @@ -9,7 +9,7 @@ * tree nodes are listed in this file. */ -#include <dt-bindings/pinctrl/samsung.h> +#include "exynos-pinctrl.h" #define PIN(_pin, _func, _pull, _drv) \ pin- ## _pin { \ diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi index 75b548e495a0..bd6a354b9cb5 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi @@ -1820,7 +1820,7 @@ }; }; - mshc_0: mshc@15540000 { + mshc_0: mmc@15540000 { compatible = "samsung,exynos7-dw-mshc-smu"; interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; @@ -1833,7 +1833,7 @@ status = "disabled"; }; - mshc_1: mshc@15550000 { + mshc_1: mmc@15550000 { compatible = "samsung,exynos7-dw-mshc-smu"; interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; @@ -1846,7 +1846,7 @@ status = "disabled"; }; - mshc_2: mshc@15560000 { + mshc_2: mmc@15560000 { compatible = "samsung,exynos7-dw-mshc-smu"; interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; diff --git a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts index 0895e818d3c1..e38c59cf18dc 100644 --- a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts +++ b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts @@ -357,7 +357,7 @@ pmic_irq: pmic-irq-pins { samsung,pins = "gpa0-2"; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; + samsung,pin-drv = <EXYNOS7_PIN_DRV_LV4>; }; }; @@ -397,14 +397,14 @@ samsung,pins = "gph1-1"; samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>; }; usb3drd_boost_en: usb3drd-boost-en-pins { samsung,pins = "gpf4-1"; samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>; }; }; diff --git a/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi index be9b971f3697..ee9c24a226f3 100644 --- a/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi @@ -9,7 +9,7 @@ * device tree nodes in this file. */ -#include <dt-bindings/pinctrl/samsung.h> +#include "exynos-pinctrl.h" &pinctrl_alive { gpa0: gpa0-gpio-bank { @@ -188,161 +188,161 @@ samsung,pins = "gpb0-1", "gpb0-0"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>; }; hs_i2c11_bus: hs-i2c11-bus-pins { samsung,pins = "gpb0-3", "gpb0-2"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>; }; hs_i2c2_bus: hs-i2c2-bus-pins { samsung,pins = "gpd0-3", "gpd0-2"; samsung,pin-function = <EXYNOS_PIN_FUNC_3>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>; }; uart0_data: uart0-data-pins { samsung,pins = "gpd0-0", "gpd0-1"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>; }; uart0_fctl: uart0-fctl-pins { samsung,pins = "gpd0-2", "gpd0-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>; }; uart2_data: uart2-data-pins { samsung,pins = "gpd1-4", "gpd1-5"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>; }; hs_i2c3_bus: hs-i2c3-bus-pins { samsung,pins = "gpd1-3", "gpd1-2"; samsung,pin-function = <EXYNOS_PIN_FUNC_3>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>; }; uart1_data: uart1-data-pins { samsung,pins = "gpd1-0", "gpd1-1"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>; }; uart1_fctl: uart1-fctl-pins { samsung,pins = "gpd1-2", "gpd1-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>; }; hs_i2c0_bus: hs-i2c0-bus-pins { samsung,pins = "gpd2-1", "gpd2-0"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>; }; hs_i2c1_bus: hs-i2c1-bus-pins { samsung,pins = "gpd2-3", "gpd2-2"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>; }; hs_i2c9_bus: hs-i2c9-bus-pins { samsung,pins = "gpd2-7", "gpd2-6"; samsung,pin-function = <EXYNOS_PIN_FUNC_3>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>; }; pwm0_out: pwm0-out-pins { samsung,pins = "gpd2-4"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>; }; pwm1_out: pwm1-out-pins { samsung,pins = "gpd2-5"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>; }; pwm2_out: pwm2-out-pins { samsung,pins = "gpd2-6"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>; }; pwm3_out: pwm3-out-pins { samsung,pins = "gpd2-7"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>; }; hs_i2c8_bus: hs-i2c8-bus-pins { samsung,pins = "gpd5-3", "gpd5-2"; samsung,pin-function = <EXYNOS_PIN_FUNC_3>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>; }; uart3_data: uart3-data-pins { samsung,pins = "gpd5-0", "gpd5-1"; samsung,pin-function = <EXYNOS_PIN_FUNC_3>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>; }; spi2_bus: spi2-bus-pins { samsung,pins = "gpd5-0", "gpd5-1", "gpd5-2", "gpd5-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>; }; spi1_bus: spi1-bus-pins { samsung,pins = "gpd6-2", "gpd6-3", "gpd6-4", "gpd6-5"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>; }; spi0_bus: spi0-bus-pins { samsung,pins = "gpd8-0", "gpd8-1", "gpd6-0", "gpd6-1"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>; }; hs_i2c4_bus: hs-i2c4-bus-pins { samsung,pins = "gpg3-1", "gpg3-0"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>; }; hs_i2c5_bus: hs-i2c5-bus-pins { samsung,pins = "gpg3-3", "gpg3-2"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>; }; }; @@ -359,7 +359,7 @@ samsung,pins = "gpj0-1", "gpj0-0"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>; }; }; @@ -376,7 +376,7 @@ samsung,pins = "gpj1-1", "gpj1-0"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>; }; }; @@ -393,7 +393,7 @@ samsung,pins = "gpg4-0", "gpg4-1", "gpg4-2", "gpg4-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>; }; }; @@ -410,7 +410,7 @@ samsung,pins = "gpv7-0", "gpv7-1", "gpv7-2", "gpv7-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>; }; }; @@ -427,35 +427,35 @@ samsung,pins = "gpr4-0"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; + samsung,pin-drv = <EXYNOS7_PIN_DRV_LV4>; }; sd2_cmd: sd2-cmd-pins { samsung,pins = "gpr4-1"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; + samsung,pin-drv = <EXYNOS7_PIN_DRV_LV4>; }; sd2_cd: sd2-cd-pins { samsung,pins = "gpr4-2"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; + samsung,pin-drv = <EXYNOS7_PIN_DRV_LV4>; }; sd2_bus1: sd2-bus-width1-pins { samsung,pins = "gpr4-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; + samsung,pin-drv = <EXYNOS7_PIN_DRV_LV4>; }; sd2_bus4: sd2-bus-width4-pins { samsung,pins = "gpr4-4", "gpr4-5", "gpr4-6"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; + samsung,pin-drv = <EXYNOS7_PIN_DRV_LV4>; }; }; @@ -683,20 +683,20 @@ samsung,pins = "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>; }; ufs_refclk_out: ufs-refclk-out-pins { samsung,pins = "gpg2-4"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV2>; + samsung,pin-drv = <EXYNOS7_PIN_DRV_LV2>; }; ufs_rst_n: ufs-rst-n-pins { samsung,pins = "gph1-5"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>; }; }; diff --git a/arch/arm64/boot/dts/exynos/exynos7885-jackpotlte.dts b/arch/arm64/boot/dts/exynos/exynos7885-jackpotlte.dts index 4cf9aa25f618..5db9a81ac7bb 100644 --- a/arch/arm64/boot/dts/exynos/exynos7885-jackpotlte.dts +++ b/arch/arm64/boot/dts/exynos/exynos7885-jackpotlte.dts @@ -60,6 +60,26 @@ }; }; +&mmc_0 { + status = "okay"; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + cap-mmc-highspeed; + non-removable; + mmc-hs400-enhanced-strobe; + card-detect-delay = <200>; + clock-frequency = <800000000>; + bus-width = <8>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <0 4>; + samsung,dw-mshc-ddr-timing = <2 4>; + samsung,dw-mshc-hs400-timing = <0 2>; + + pinctrl-names = "default"; + pinctrl-0 = <&sd0_clk_fast_slew_rate_3x &sd0_cmd &sd0_rdqs + &sd0_bus1 &sd0_bus4 &sd0_bus8>; +}; + &oscclk { clock-frequency = <26000000>; }; diff --git a/arch/arm64/boot/dts/exynos/exynos7885-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/exynos7885-pinctrl.dtsi index a50c1dbd5545..34bb12191955 100644 --- a/arch/arm64/boot/dts/exynos/exynos7885-pinctrl.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos7885-pinctrl.dtsi @@ -9,8 +9,8 @@ * device tree nodes in this file. */ -#include <dt-bindings/pinctrl/samsung.h> #include <dt-bindings/interrupt-controller/arm-gic.h> +#include "exynos-pinctrl.h" &pinctrl_alive { etc0: etc0-gpio-bank { diff --git a/arch/arm64/boot/dts/exynos/exynos7885.dtsi b/arch/arm64/boot/dts/exynos/exynos7885.dtsi index 9c233c56558c..23c2e0bb0a2c 100644 --- a/arch/arm64/boot/dts/exynos/exynos7885.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos7885.dtsi @@ -240,6 +240,25 @@ clock-names = "oscclk"; }; + cmu_fsys: clock-controller@13400000 { + compatible = "samsung,exynos7885-cmu-fsys"; + reg = <0x13400000 0x8000>; + #clock-cells = <1>; + + clocks = <&oscclk>, + <&cmu_top CLK_DOUT_FSYS_BUS>, + <&cmu_top CLK_DOUT_FSYS_MMC_CARD>, + <&cmu_top CLK_DOUT_FSYS_MMC_EMBD>, + <&cmu_top CLK_DOUT_FSYS_MMC_SDIO>, + <&cmu_top CLK_DOUT_FSYS_USB30DRD>; + clock-names = "oscclk", + "dout_fsys_bus", + "dout_fsys_mmc_card", + "dout_fsys_mmc_embd", + "dout_fsys_mmc_sdio", + "dout_fsys_usb30drd"; + }; + pinctrl_alive: pinctrl@11cb0000 { compatible = "samsung,exynos7885-pinctrl"; reg = <0x11cb0000 0x1000>; @@ -274,6 +293,19 @@ reg = <0x11c80000 0x10000>; }; + mmc_0: mmc@13500000 { + compatible = "samsung,exynos7-dw-mshc-smu"; + reg = <0x13500000 0x2000>; + interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_fsys CLK_GOUT_MMC_EMBD_ACLK>, + <&cmu_fsys CLK_GOUT_MMC_EMBD_SDCLKIN>; + clock-names = "biu", "ciu"; + fifo-depth = <0x40>; + status = "disabled"; + }; + serial_0: serial@13800000 { compatible = "samsung,exynos5433-uart"; reg = <0x13800000 0x100>; diff --git a/arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi index f43e4a206282..424bc80bde68 100644 --- a/arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi @@ -10,7 +10,7 @@ */ #include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/pinctrl/samsung.h> +#include "exynos-pinctrl.h" &pinctrl_alive { gpa0: gpa0-gpio-bank { diff --git a/arch/arm64/boot/dts/exynos/exynosautov9-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/exynosautov9-pinctrl.dtsi index ef0349d1c3d0..e413a51c2d08 100644 --- a/arch/arm64/boot/dts/exynos/exynosautov9-pinctrl.dtsi +++ b/arch/arm64/boot/dts/exynos/exynosautov9-pinctrl.dtsi @@ -8,7 +8,7 @@ * device tree nodes in this file. */ -#include <dt-bindings/pinctrl/samsung.h> +#include "exynos-pinctrl.h" &pinctrl_alive { gpa0: gpa0-gpio-bank { @@ -1089,21 +1089,21 @@ /* PERIC1 USI11_SPI */ spi11_bus: spi11-pins { - samsung,pins = "gpp3-6", "gpp3-5", "gpp3-4"; + samsung,pins = "gpp5-6", "gpp5-5", "gpp5-4"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; spi11_cs: spi11-cs-pins { - samsung,pins = "gpp3-7"; + samsung,pins = "gpp5-7"; samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; spi11_cs_func: spi11-cs-func-pins { - samsung,pins = "gpp3-7"; + samsung,pins = "gpp5-7"; samsung,pin-function = <EXYNOS_PIN_FUNC_2>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; diff --git a/arch/arm64/boot/dts/exynos/exynosautov9-sadk.dts b/arch/arm64/boot/dts/exynos/exynosautov9-sadk.dts index 17e568853eb6..eec3192c0631 100644 --- a/arch/arm64/boot/dts/exynos/exynosautov9-sadk.dts +++ b/arch/arm64/boot/dts/exynos/exynosautov9-sadk.dts @@ -39,9 +39,18 @@ regulator-boot-on; enable-active-high; }; + + ufs_1_fixed_vcc_reg: regulator-1 { + compatible = "regulator-fixed"; + regulator-name = "ufs-vcc"; + gpio = <&gpg2 2 GPIO_ACTIVE_HIGH>; + regulator-boot-on; + enable-active-high; + }; }; &serial_0 { + pinctrl-0 = <&uart0_bus_dual>; status = "okay"; }; @@ -49,13 +58,24 @@ status = "okay"; }; +&ufs_1_phy { + status = "okay"; +}; + &ufs_0 { status = "okay"; vcc-supply = <&ufs_0_fixed_vcc_reg>; vcc-fixed-regulator; }; +&ufs_1 { + status = "okay"; + vcc-supply = <&ufs_1_fixed_vcc_reg>; + vcc-fixed-regulator; +}; + &usi_0 { + samsung,clkreq-on; /* needed for UART mode */ status = "okay"; }; diff --git a/arch/arm64/boot/dts/exynos/exynosautov9.dtsi b/arch/arm64/boot/dts/exynos/exynosautov9.dtsi index 0ce46ec5cdc3..2013718532f3 100644 --- a/arch/arm64/boot/dts/exynos/exynosautov9.dtsi +++ b/arch/arm64/boot/dts/exynos/exynosautov9.dtsi @@ -8,6 +8,7 @@ #include <dt-bindings/clock/samsung,exynosautov9.h> #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/soc/samsung,boot-mode.h> #include <dt-bindings/soc/samsung,exynos-usi.h> / { @@ -265,6 +266,16 @@ IRQ_TYPE_LEVEL_HIGH)>; }; + pdma0: dma-controller@1b2e0000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x1b2e0000 0x1000>; + interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cmu_busmc CLK_GOUT_BUSMC_PDMA0_PCLK>; + clock-names = "apb_pclk"; + arm,pl330-broken-no-flushp; + #dma-cells = <1>; + }; + pinctrl_alive: pinctrl@10450000 { compatible = "samsung,exynosautov9-pinctrl"; reg = <0x10450000 0x1000>; @@ -312,6 +323,22 @@ pmu_system_controller: system-controller@10460000 { compatible = "samsung,exynos7-pmu", "syscon"; reg = <0x10460000 0x10000>; + + reboot: syscon-reboot { + compatible = "syscon-reboot"; + regmap = <&pmu_system_controller>; + offset = <0x3a00>; /* SYSTEM_CONFIGURATION */ + value = <0x2>; + mask = <0x2>; + }; + + reboot-mode { + compatible = "syscon-reboot-mode"; + offset = <0x810>; /* SYSIP_DAT0 */ + mode-bootloader = <EXYNOSAUTOV9_BOOT_BOOTLOADER>; + mode-fastboot = <EXYNOSAUTOV9_BOOT_FASTBOOT>; + mode-recovery = <EXYNOSAUTOV9_BOOT_RECOVERY>; + }; }; syscon_fsys2: syscon@17c20000 { @@ -324,12 +351,17 @@ reg = <0x10220000 0x2000>; }; + syscon_peric1: syscon@10820000 { + compatible = "samsung,exynosautov9-sysreg", "syscon"; + reg = <0x10820000 0x2000>; + }; + usi_0: usi@103000c0 { - compatible = "samsung,exynos850-usi"; + compatible = "samsung,exynosautov9-usi", + "samsung,exynos850-usi"; reg = <0x103000c0 0x20>; samsung,sysreg = <&syscon_peric0 0x1000>; samsung,mode = <USI_V2_UART>; - samsung,clkreq-on; /* needed for UART mode */ #address-cells = <1>; #size-cells = <1>; ranges; @@ -338,21 +370,1083 @@ clock-names = "pclk", "ipclk"; status = "disabled"; - /* USI: UART */ serial_0: serial@10300000 { - compatible = "samsung,exynos850-uart"; + compatible = "samsung,exynosautov9-uart", + "samsung,exynos850-uart"; reg = <0x10300000 0xc0>; interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; - pinctrl-0 = <&uart0_bus_dual>; + pinctrl-0 = <&uart0_bus>; clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_0>, <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_0>; clock-names = "uart", "clk_uart_baud0"; + samsung,uart-fifosize = <256>; + status = "disabled"; + }; + + spi_0: spi@10300000 { + compatible = "samsung,exynosautov9-spi"; + reg = <0x10300000 0x30>; + interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&spi0_bus &spi0_cs_func>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_0>, + <&cmu_peric0 CLK_DOUT_PERIC0_USI00_USI>, + <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_0>; + clock-names = "spi", "spi_busclk0", "spi_ioclk"; + samsung,spi-src-clk = <0>; + dmas = <&pdma0 1>, <&pdma0 0>; + dma-names = "tx", "rx"; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + hsi2c_0: i2c@10300000 { + compatible = "samsung,exynosautov9-hsi2c"; + reg = <0x10300000 0xc0>; + interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c0_bus>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_0>, + <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_0>; + clock-names = "hsi2c", "hsi2c_pclk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + usi_i2c_0: usi@103100c0 { + compatible = "samsung,exynosautov9-usi", + "samsung,exynos850-usi"; + reg = <0x103100c0 0x20>; + samsung,sysreg = <&syscon_peric0 0x1004>; + samsung,mode = <USI_V2_I2C>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_1>, + <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_1>; + clock-names = "pclk", "ipclk"; + status = "disabled"; + + hsi2c_1: i2c@10310000 { + compatible = "samsung,exynosautov9-hsi2c"; + reg = <0x10310000 0xc0>; + interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c1_bus>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_1>, + <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_1>; + clock-names = "hsi2c", "hsi2c_pclk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + usi_1: usi@103200c0 { + compatible = "samsung,exynosautov9-usi", + "samsung,exynos850-usi"; + reg = <0x103200c0 0x20>; + samsung,sysreg = <&syscon_peric0 0x1008>; + samsung,mode = <USI_V2_UART>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_2>, + <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_2>; + clock-names = "pclk", "ipclk"; + status = "disabled"; + + serial_1: serial@10320000 { + compatible = "samsung,exynosautov9-uart", + "samsung,exynos850-uart"; + reg = <0x10320000 0xc0>; + interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&uart1_bus>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_2>, + <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_2>; + clock-names = "uart", "clk_uart_baud0"; + samsung,uart-fifosize = <256>; + status = "disabled"; + }; + + spi_1: spi@10320000 { + compatible = "samsung,exynosautov9-spi"; + reg = <0x10320000 0x30>; + interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&spi1_bus &spi1_cs_func>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_2>, + <&cmu_peric0 CLK_DOUT_PERIC0_USI01_USI>, + <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_2>; + clock-names = "spi", "spi_busclk0", "spi_ioclk"; + samsung,spi-src-clk = <0>; + dmas = <&pdma0 3>, <&pdma0 2>; + dma-names = "tx", "rx"; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + hsi2c_2: i2c@10320000 { + compatible = "samsung,exynosautov9-hsi2c"; + reg = <0x10320000 0xc0>; + interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c2_bus>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_2>, + <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_2>; + clock-names = "hsi2c", "hsi2c_pclk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + usi_i2c_1: usi@103300c0 { + compatible = "samsung,exynosautov9-usi", + "samsung,exynos850-usi"; + reg = <0x103300c0 0x20>; + samsung,sysreg = <&syscon_peric0 0x100c>; + samsung,mode = <USI_V2_I2C>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_3>, + <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_3>; + clock-names = "pclk", "ipclk"; + status = "disabled"; + + hsi2c_3: i2c@10330000 { + compatible = "samsung,exynosautov9-hsi2c"; + reg = <0x10330000 0xc0>; + interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c3_bus>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_3>, + <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_3>; + clock-names = "hsi2c", "hsi2c_pclk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + usi_2: usi@103400c0 { + compatible = "samsung,exynosautov9-usi", + "samsung,exynos850-usi"; + reg = <0x103400c0 0x20>; + samsung,sysreg = <&syscon_peric0 0x1010>; + samsung,mode = <USI_V2_UART>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_4>, + <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_4>; + clock-names = "pclk", "ipclk"; + status = "disabled"; + + serial_2: serial@10340000 { + compatible = "samsung,exynosautov9-uart", + "samsung,exynos850-uart"; + reg = <0x10340000 0xc0>; + interrupts = <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&uart2_bus>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_4>, + <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_4>; + clock-names = "uart", "clk_uart_baud0"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + + spi_2: spi@10340000 { + compatible = "samsung,exynosautov9-spi"; + reg = <0x10340000 0x30>; + interrupts = <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&spi2_bus &spi2_cs_func>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_4>, + <&cmu_peric0 CLK_DOUT_PERIC0_USI02_USI>, + <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_4>; + clock-names = "spi", "spi_busclk0", "spi_ioclk"; + samsung,spi-src-clk = <0>; + dmas = <&pdma0 5>, <&pdma0 4>; + dma-names = "tx", "rx"; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + hsi2c_4: i2c@10340000 { + compatible = "samsung,exynosautov9-hsi2c"; + reg = <0x10340000 0xc0>; + interrupts = <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c4_bus>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_4>, + <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_4>; + clock-names = "hsi2c", "hsi2c_pclk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + usi_i2c_2: usi@103500c0 { + compatible = "samsung,exynosautov9-usi", + "samsung,exynos850-usi"; + reg = <0x103500c0 0x20>; + samsung,sysreg = <&syscon_peric0 0x1014>; + samsung,mode = <USI_V2_I2C>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_5>, + <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_5>; + clock-names = "pclk", "ipclk"; + status = "disabled"; + + hsi2c_5: i2c@10350000 { + compatible = "samsung,exynosautov9-hsi2c"; + reg = <0x10350000 0xc0>; + interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c5_bus>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_5>, + <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_5>; + clock-names = "hsi2c", "hsi2c_pclk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + usi_3: usi@103600c0 { + compatible = "samsung,exynosautov9-usi", + "samsung,exynos850-usi"; + reg = <0x103600c0 0x20>; + samsung,sysreg = <&syscon_peric0 0x1018>; + samsung,mode = <USI_V2_UART>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_6>, + <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_6>; + clock-names = "pclk", "ipclk"; + status = "disabled"; + + serial_3: serial@10360000 { + compatible = "samsung,exynosautov9-uart", + "samsung,exynos850-uart"; + reg = <0x10360000 0xc0>; + interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&uart3_bus>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_6>, + <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_6>; + clock-names = "uart", "clk_uart_baud0"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + + spi_3: spi@10360000 { + compatible = "samsung,exynosautov9-spi"; + reg = <0x10360000 0x30>; + interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&spi3_bus &spi3_cs_func>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_6>, + <&cmu_peric0 CLK_DOUT_PERIC0_USI03_USI>, + <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_6>; + clock-names = "spi", "spi_busclk0", "spi_ioclk"; + samsung,spi-src-clk = <0>; + dmas = <&pdma0 7>, <&pdma0 6>; + dma-names = "tx", "rx"; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + hsi2c_6: i2c@10360000 { + compatible = "samsung,exynosautov9-hsi2c"; + reg = <0x10360000 0xc0>; + interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c6_bus>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_6>, + <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_6>; + clock-names = "hsi2c", "hsi2c_pclk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + usi_i2c_3: usi@103700c0 { + compatible = "samsung,exynosautov9-usi", + "samsung,exynos850-usi"; + reg = <0x103700c0 0x20>; + samsung,sysreg = <&syscon_peric0 0x101c>; + samsung,mode = <USI_V2_I2C>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_7>, + <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_7>; + clock-names = "pclk", "ipclk"; + status = "disabled"; + + hsi2c_7: i2c@10370000 { + compatible = "samsung,exynosautov9-hsi2c"; + reg = <0x10370000 0xc0>; + interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c7_bus>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_7>, + <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_7>; + clock-names = "hsi2c", "hsi2c_pclk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + usi_4: usi@103800c0 { + compatible = "samsung,exynosautov9-usi", + "samsung,exynos850-usi"; + reg = <0x103800c0 0x20>; + samsung,sysreg = <&syscon_peric0 0x1020>; + samsung,mode = <USI_V2_UART>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_8>, + <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_8>; + clock-names = "pclk", "ipclk"; + status = "disabled"; + + serial_4: serial@10380000 { + compatible = "samsung,exynosautov9-uart", + "samsung,exynos850-uart"; + reg = <0x10380000 0xc0>; + interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&uart4_bus>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_8>, + <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_8>; + clock-names = "uart", "clk_uart_baud0"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + + spi_4: spi@10380000 { + compatible = "samsung,exynosautov9-spi"; + reg = <0x10380000 0x30>; + interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&spi4_bus &spi4_cs_func>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_8>, + <&cmu_peric0 CLK_DOUT_PERIC0_USI04_USI>, + <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_8>; + clock-names = "spi", "spi_busclk0", "spi_ioclk"; + samsung,spi-src-clk = <0>; + dmas = <&pdma0 9>, <&pdma0 8>; + dma-names = "tx", "rx"; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + hsi2c_8: i2c@10380000 { + compatible = "samsung,exynosautov9-hsi2c"; + reg = <0x10380000 0xc0>; + interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c8_bus>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_8>, + <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_8>; + clock-names = "hsi2c", "hsi2c_pclk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + usi_i2c_4: usi@103900c0 { + compatible = "samsung,exynosautov9-usi", + "samsung,exynos850-usi"; + reg = <0x103900c0 0x20>; + samsung,sysreg = <&syscon_peric0 0x1024>; + samsung,mode = <USI_V2_I2C>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_9>, + <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_9>; + clock-names = "pclk", "ipclk"; + status = "disabled"; + + hsi2c_9: i2c@10390000 { + compatible = "samsung,exynosautov9-hsi2c"; + reg = <0x10390000 0xc0>; + interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c9_bus>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_9>, + <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_9>; + clock-names = "hsi2c", "hsi2c_pclk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + usi_5: usi@103a00c0 { + compatible = "samsung,exynosautov9-usi", + "samsung,exynos850-usi"; + reg = <0x103a00c0 0x20>; + samsung,sysreg = <&syscon_peric0 0x1028>; + samsung,mode = <USI_V2_UART>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_10>, + <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_10>; + clock-names = "pclk", "ipclk"; + status = "disabled"; + + serial_5: serial@103a0000 { + compatible = "samsung,exynosautov9-uart", + "samsung,exynos850-uart"; + reg = <0x103a0000 0xc0>; + interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&uart5_bus>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_10>, + <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_10>; + clock-names = "uart", "clk_uart_baud0"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + + spi_5: spi@103a0000 { + compatible = "samsung,exynosautov9-spi"; + reg = <0x103a0000 0x30>; + interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&spi5_bus &spi5_cs_func>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_10>, + <&cmu_peric0 CLK_DOUT_PERIC0_USI05_USI>, + <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_10>; + clock-names = "spi", "spi_busclk0", "spi_ioclk"; + samsung,spi-src-clk = <0>; + dmas = <&pdma0 11>, <&pdma0 10>; + dma-names = "tx", "rx"; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + hsi2c_10: i2c@103a0000 { + compatible = "samsung,exynosautov9-hsi2c"; + reg = <0x103a0000 0xc0>; + interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c10_bus>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_10>, + <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_10>; + clock-names = "hsi2c", "hsi2c_pclk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + usi_i2c_5: usi@103b00c0 { + compatible = "samsung,exynosautov9-usi", + "samsung,exynos850-usi"; + reg = <0x103b00c0 0x20>; + samsung,sysreg = <&syscon_peric0 0x102c>; + samsung,mode = <USI_V2_I2C>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_11>, + <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_11>; + clock-names = "pclk", "ipclk"; + status = "disabled"; + + hsi2c_11: i2c@103b0000 { + compatible = "samsung,exynosautov9-hsi2c"; + reg = <0x103b0000 0xc0>; + interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c11_bus>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_11>, + <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_11>; + clock-names = "hsi2c", "hsi2c_pclk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + usi_6: usi@109000c0 { + compatible = "samsung,exynosautov9-usi", + "samsung,exynos850-usi"; + reg = <0x109000c0 0x20>; + samsung,sysreg = <&syscon_peric1 0x1000>; + samsung,mode = <USI_V2_UART>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_0>, + <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_0>; + clock-names = "pclk", "ipclk"; + status = "disabled"; + + serial_6: serial@10900000 { + compatible = "samsung,exynosautov9-uart", + "samsung,exynos850-uart"; + reg = <0x10900000 0xc0>; + interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&uart6_bus>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_0>, + <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_0>; + clock-names = "uart", "clk_uart_baud0"; + samsung,uart-fifosize = <256>; + status = "disabled"; + }; + + spi_6: spi@10900000 { + compatible = "samsung,exynosautov9-spi"; + reg = <0x10900000 0x30>; + interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&spi6_bus &spi6_cs_func>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_0>, + <&cmu_peric1 CLK_DOUT_PERIC1_USI06_USI>, + <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_0>; + clock-names = "spi", "spi_busclk0", "spi_ioclk"; + samsung,spi-src-clk = <0>; + dmas = <&pdma0 13>, <&pdma0 12>; + dma-names = "tx", "rx"; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + hsi2c_12: i2c@10900000 { + compatible = "samsung,exynosautov9-hsi2c"; + reg = <0x10900000 0xc0>; + interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c12_bus>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_0>, + <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_0>; + clock-names = "hsi2c", "hsi2c_pclk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + usi_i2c_6: usi@109100c0 { + compatible = "samsung,exynosautov9-usi", + "samsung,exynos850-usi"; + reg = <0x109100c0 0x20>; + samsung,sysreg = <&syscon_peric1 0x1004>; + samsung,mode = <USI_V2_I2C>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_1>, + <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_1>; + clock-names = "pclk", "ipclk"; + status = "disabled"; + + hsi2c_13: i2c@10910000 { + compatible = "samsung,exynosautov9-hsi2c"; + reg = <0x10910000 0xc0>; + interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c13_bus>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_1>, + <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_1>; + clock-names = "hsi2c", "hsi2c_pclk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + usi_7: usi@109200c0 { + compatible = "samsung,exynosautov9-usi", + "samsung,exynos850-usi"; + reg = <0x109200c0 0x20>; + samsung,sysreg = <&syscon_peric1 0x1008>; + samsung,mode = <USI_V2_UART>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_2>, + <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_2>; + clock-names = "pclk", "ipclk"; + status = "disabled"; + + serial_7: serial@10920000 { + compatible = "samsung,exynosautov9-uart", + "samsung,exynos850-uart"; + reg = <0x10920000 0xc0>; + interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&uart7_bus>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_2>, + <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_2>; + clock-names = "uart", "clk_uart_baud0"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + + spi_7: spi@10920000 { + compatible = "samsung,exynosautov9-spi"; + reg = <0x10920000 0x30>; + interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&spi7_bus &spi7_cs_func>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_2>, + <&cmu_peric1 CLK_DOUT_PERIC1_USI07_USI>, + <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_2>; + clock-names = "spi", "spi_busclk0", "spi_ioclk"; + samsung,spi-src-clk = <0>; + dmas = <&pdma0 15>, <&pdma0 14>; + dma-names = "tx", "rx"; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + hsi2c_14: i2c@10920000 { + compatible = "samsung,exynosautov9-hsi2c"; + reg = <0x10920000 0xc0>; + interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c14_bus>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_2>, + <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_2>; + clock-names = "hsi2c", "hsi2c_pclk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + usi_i2c_7: usi@109300c0 { + compatible = "samsung,exynosautov9-usi", + "samsung,exynos850-usi"; + reg = <0x109300c0 0x20>; + samsung,sysreg = <&syscon_peric1 0x100c>; + samsung,mode = <USI_V2_I2C>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_3>, + <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_3>; + clock-names = "pclk", "ipclk"; + status = "disabled"; + + hsi2c_15: i2c@10930000 { + compatible = "samsung,exynosautov9-hsi2c"; + reg = <0x10930000 0xc0>; + interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c15_bus>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_3>, + <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_3>; + clock-names = "hsi2c", "hsi2c_pclk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + usi_8: usi@109400c0 { + compatible = "samsung,exynosautov9-usi", + "samsung,exynos850-usi"; + reg = <0x109400c0 0x20>; + samsung,sysreg = <&syscon_peric1 0x1010>; + samsung,mode = <USI_V2_UART>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_4>, + <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_4>; + clock-names = "pclk", "ipclk"; + status = "disabled"; + + serial_8: serial@10940000 { + compatible = "samsung,exynosautov9-uart", + "samsung,exynos850-uart"; + reg = <0x10940000 0xc0>; + interrupts = <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&uart8_bus>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_4>, + <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_4>; + clock-names = "uart", "clk_uart_baud0"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + + spi_8: spi@10940000 { + compatible = "samsung,exynosautov9-spi"; + reg = <0x10940000 0x30>; + interrupts = <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&spi8_bus &spi8_cs_func>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_4>, + <&cmu_peric1 CLK_DOUT_PERIC1_USI08_USI>, + <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_4>; + clock-names = "spi", "spi_busclk0", "spi_ioclk"; + samsung,spi-src-clk = <0>; + dmas = <&pdma0 17>, <&pdma0 16>; + dma-names = "tx", "rx"; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + hsi2c_16: i2c@10940000 { + compatible = "samsung,exynosautov9-hsi2c"; + reg = <0x10940000 0xc0>; + interrupts = <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c16_bus>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_4>, + <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_4>; + clock-names = "hsi2c", "hsi2c_pclk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + usi_i2c_8: usi@109500c0 { + compatible = "samsung,exynosautov9-usi", + "samsung,exynos850-usi"; + reg = <0x109500c0 0x20>; + samsung,sysreg = <&syscon_peric1 0x1014>; + samsung,mode = <USI_V2_I2C>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_5>, + <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_5>; + clock-names = "pclk", "ipclk"; + status = "disabled"; + + hsi2c_17: i2c@10950000 { + compatible = "samsung,exynosautov9-hsi2c"; + reg = <0x10950000 0xc0>; + interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c17_bus>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_5>, + <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_5>; + clock-names = "hsi2c", "hsi2c_pclk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + usi_9: usi@109600c0 { + compatible = "samsung,exynosautov9-usi", + "samsung,exynos850-usi"; + reg = <0x109600c0 0x20>; + samsung,sysreg = <&syscon_peric1 0x1018>; + samsung,mode = <USI_V2_UART>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_6>, + <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_6>; + clock-names = "pclk", "ipclk"; + status = "disabled"; + + serial_9: serial@10960000 { + compatible = "samsung,exynosautov9-uart", + "samsung,exynos850-uart"; + reg = <0x10960000 0xc0>; + interrupts = <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&uart9_bus>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_6>, + <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_6>; + clock-names = "uart", "clk_uart_baud0"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + + spi_9: spi@10960000 { + compatible = "samsung,exynosautov9-spi"; + reg = <0x10960000 0x30>; + interrupts = <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&spi9_bus &spi9_cs_func>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_6>, + <&cmu_peric1 CLK_DOUT_PERIC1_USI09_USI>, + <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_6>; + clock-names = "spi", "spi_busclk0", "spi_ioclk"; + samsung,spi-src-clk = <0>; + dmas = <&pdma0 19>, <&pdma0 18>; + dma-names = "tx", "rx"; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + hsi2c_18: i2c@10960000 { + compatible = "samsung,exynosautov9-hsi2c"; + reg = <0x10960000 0xc0>; + interrupts = <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c18_bus>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_6>, + <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_6>; + clock-names = "hsi2c", "hsi2c_pclk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + usi_i2c_9: usi@109700c0 { + compatible = "samsung,exynosautov9-usi", + "samsung,exynos850-usi"; + reg = <0x109700c0 0x20>; + samsung,sysreg = <&syscon_peric1 0x101c>; + samsung,mode = <USI_V2_I2C>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_7>, + <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_7>; + clock-names = "pclk", "ipclk"; + status = "disabled"; + + hsi2c_19: i2c@10970000 { + compatible = "samsung,exynosautov9-hsi2c"; + reg = <0x10970000 0xc0>; + interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c19_bus>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_7>, + <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_7>; + clock-names = "hsi2c", "hsi2c_pclk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + usi_10: usi@109800c0 { + compatible = "samsung,exynosautov9-usi", + "samsung,exynos850-usi"; + reg = <0x109800c0 0x20>; + samsung,sysreg = <&syscon_peric1 0x1020>; + samsung,mode = <USI_V2_UART>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_8>, + <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_8>; + clock-names = "pclk", "ipclk"; + status = "disabled"; + + serial_10: serial@10980000 { + compatible = "samsung,exynosautov9-uart", + "samsung,exynos850-uart"; + reg = <0x10980000 0xc0>; + interrupts = <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&uart10_bus>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_8>, + <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_8>; + clock-names = "uart", "clk_uart_baud0"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + + spi_10: spi@10980000 { + compatible = "samsung,exynosautov9-spi"; + reg = <0x10980000 0x30>; + interrupts = <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&spi10_bus &spi10_cs_func>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_8>, + <&cmu_peric1 CLK_DOUT_PERIC1_USI10_USI>, + <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_8>; + clock-names = "spi", "spi_busclk0", "spi_ioclk"; + samsung,spi-src-clk = <0>; + dmas = <&pdma0 21>, <&pdma0 20>; + dma-names = "tx", "rx"; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + hsi2c_20: i2c@10980000 { + compatible = "samsung,exynosautov9-hsi2c"; + reg = <0x10980000 0xc0>; + interrupts = <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c20_bus>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_8>, + <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_8>; + clock-names = "hsi2c", "hsi2c_pclk"; + #address-cells = <1>; + #size-cells = <0>; status = "disabled"; }; }; - ufs_0_phy: ufs0-phy@17e04000 { + usi_i2c_10: usi@109900c0 { + compatible = "samsung,exynosautov9-usi", + "samsung,exynos850-usi"; + reg = <0x109900c0 0x20>; + samsung,sysreg = <&syscon_peric1 0x1024>; + samsung,mode = <USI_V2_I2C>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_9>, + <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_9>; + clock-names = "pclk", "ipclk"; + status = "disabled"; + + hsi2c_21: i2c@10990000 { + compatible = "samsung,exynosautov9-hsi2c"; + reg = <0x10990000 0xc0>; + interrupts = <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c21_bus>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_9>, + <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_9>; + clock-names = "hsi2c", "hsi2c_pclk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + usi_11: usi@109a00c0 { + compatible = "samsung,exynosautov9-usi", + "samsung,exynos850-usi"; + reg = <0x109a00c0 0x20>; + samsung,sysreg = <&syscon_peric1 0x1028>; + samsung,mode = <USI_V2_UART>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_10>, + <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_10>; + clock-names = "pclk", "ipclk"; + status = "disabled"; + + serial_11: serial@109a0000 { + compatible = "samsung,exynosautov9-uart", + "samsung,exynos850-uart"; + reg = <0x109a0000 0xc0>; + interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&uart11_bus>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_10>, + <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_10>; + clock-names = "uart", "clk_uart_baud0"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + + spi_11: spi@109a0000 { + compatible = "samsung,exynosautov9-spi"; + reg = <0x109a0000 0x30>; + interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&spi11_bus &spi11_cs_func>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_10>, + <&cmu_peric1 CLK_DOUT_PERIC1_USI11_USI>, + <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_10>; + clock-names = "spi", "spi_busclk0", "spi_ioclk"; + samsung,spi-src-clk = <0>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + hsi2c_22: i2c@109a0000 { + compatible = "samsung,exynosautov9-hsi2c"; + reg = <0x109a0000 0xc0>; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c22_bus>; + interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_10>, + <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_10>; + clock-names = "hsi2c", "hsi2c_pclk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + usi_i2c_11: usi@109b00c0 { + compatible = "samsung,exynosautov9-usi", + "samsung,exynos850-usi"; + reg = <0x109b00c0 0x20>; + samsung,sysreg = <&syscon_peric1 0x102c>; + samsung,mode = <USI_V2_I2C>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_11>, + <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_11>; + clock-names = "pclk", "ipclk"; + status = "disabled"; + + hsi2c_23: i2c@109b0000 { + compatible = "samsung,exynosautov9-hsi2c"; + reg = <0x109b0000 0xc0>; + interrupts = <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c23_bus>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_11>, + <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_11>; + clock-names = "hsi2c", "hsi2c_pclk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + ufs_0_phy: phy@17e04000 { compatible = "samsung,exynosautov9-ufs-phy"; reg = <0x17e04000 0xc00>; reg-names = "phy-pma"; @@ -363,13 +1457,13 @@ status = "disabled"; }; - ufs_0: ufs0@17e00000 { - compatible ="samsung,exynosautov9-ufs"; + ufs_0: ufs@17e00000 { + compatible = "samsung,exynosautov9-ufs"; - reg = <0x17e00000 0x100>, /* 0: HCI standard */ - <0x17e01100 0x410>, /* 1: Vendor-specific */ - <0x17e80000 0x8000>, /* 2: UNIPRO */ - <0x17dc0000 0x2200>; /* 3: UFS protector */ + reg = <0x17e00000 0x100>, + <0x17e01100 0x410>, + <0x17e80000 0x8000>, + <0x17dc0000 0x2200>; reg-names = "hci", "vs_hci", "unipro", "ufsp"; interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cmu_fsys2 CLK_GOUT_FSYS2_UFS_EMBD0_ACLK>, @@ -383,6 +1477,58 @@ samsung,sysreg = <&syscon_fsys2 0x710>; status = "disabled"; }; + + ufs_1_phy: phy@17f04000 { + compatible = "samsung,exynosautov9-ufs-phy"; + reg = <0x17f04000 0xc00>; + reg-names = "phy-pma"; + samsung,pmu-syscon = <&pmu_system_controller 0x72c>; + #phy-cells = <0>; + clocks = <&xtcxo>; + clock-names = "ref_clk"; + status = "disabled"; + }; + + ufs_1: ufs@17f00000 { + compatible = "samsung,exynosautov9-ufs"; + + reg = <0x17f00000 0x100>, + <0x17f01100 0x410>, + <0x17f80000 0x8000>, + <0x17de0000 0x2200>; + reg-names = "hci", "vs_hci", "unipro", "ufsp"; + interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cmu_fsys2 CLK_GOUT_FSYS2_UFS_EMBD1_ACLK>, + <&cmu_fsys2 CLK_GOUT_FSYS2_UFS_EMBD1_UNIPRO>; + clock-names = "core_clk", "sclk_unipro_main"; + freq-table-hz = <0 0>, <0 0>; + pinctrl-names = "default"; + pinctrl-0 = <&ufs_rst_n_1 &ufs_refclk_out_1>; + phys = <&ufs_1_phy>; + phy-names = "ufs-phy"; + samsung,sysreg = <&syscon_fsys2 0x714>; + status = "disabled"; + }; + + watchdog_cl0: watchdog@10050000 { + compatible = "samsung,exynosautov9-wdt"; + reg = <0x10050000 0x100>; + interrupts = <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cmu_peris CLK_GOUT_WDT_CLUSTER0>, <&xtcxo>; + clock-names = "watchdog", "watchdog_src"; + samsung,syscon-phandle = <&pmu_system_controller>; + samsung,cluster-index = <0>; + }; + + watchdog_cl1: watchdog@10060000 { + compatible = "samsung,exynosautov9-wdt"; + reg = <0x10060000 0x100>; + interrupts = <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cmu_peris CLK_GOUT_WDT_CLUSTER1>, <&xtcxo>; + clock-names = "watchdog", "watchdog_src"; + samsung,syscon-phandle = <&pmu_system_controller>; + samsung,cluster-index = <1>; + }; }; }; diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 238a83e5b8c6..8bf7f7ecebaa 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -58,6 +58,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-icore-mx8mm-edimm2.2.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-kontron-n801x-s.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-mx8menlo.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-nitrogen-r2.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-phyboard-polis-rdk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-tqma8mqml-mba8mx.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-var-som-symphony.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw71xx-0x.dtb @@ -79,9 +80,11 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mn-ddr4-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-tqma8mqnl-mba8mx.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-var-som-symphony.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-venice-gw7902.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-dhcom-pdk2.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-icore-mx8mp-edimm2.2.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-rdk.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpql-mba8mpxl.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw74xx.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-nonwifi-dahlia.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-nonwifi-dev.dtb @@ -107,6 +110,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8qxp-ai_ml.dtb dtb-$(CONFIG_ARCH_MXC) += imx8qxp-colibri-eval-v3.dtb dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek.dtb dtb-$(CONFIG_ARCH_MXC) += imx8ulp-evk.dtb +dtb-$(CONFIG_ARCH_MXC) += imx93-11x11-evk.dtb imx8mm-venice-gw72xx-0x-imx219-dtbs := imx8mm-venice-gw73xx-0x.dtb imx8mm-venice-gw73xx-0x-imx219.dtbo imx8mm-venice-gw72xx-0x-rs232-rts-dtbs := imx8mm-venice-gw72xx-0x.dtb imx8mm-venice-gw72xx-0x-rs232-rts.dtbo diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts index e22c5e77fecd..5a8d85a7d161 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts @@ -69,7 +69,7 @@ flash@0 { #address-cells = <1>; #size-cells = <1>; - compatible = "n25q128a11", "jedec,spi-nor"; + compatible = "micron,n25q128a11", "jedec,spi-nor"; reg = <0>; spi-max-frequency = <10000000>; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi index 50a72cda4727..a863022529ac 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi @@ -204,7 +204,7 @@ compatible = "fsl,sec-v5.4-job-ring", "fsl,sec-v5.0-job-ring", "fsl,sec-v4.0-job-ring"; - reg = <0x10000 0x10000>; + reg = <0x10000 0x10000>; interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; }; @@ -212,7 +212,7 @@ compatible = "fsl,sec-v5.4-job-ring", "fsl,sec-v5.0-job-ring", "fsl,sec-v4.0-job-ring"; - reg = <0x20000 0x10000>; + reg = <0x20000 0x10000>; interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; }; @@ -220,7 +220,7 @@ compatible = "fsl,sec-v5.4-job-ring", "fsl,sec-v5.0-job-ring", "fsl,sec-v4.0-job-ring"; - reg = <0x30000 0x10000>; + reg = <0x30000 0x10000>; interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; }; @@ -228,7 +228,7 @@ compatible = "fsl,sec-v5.4-job-ring", "fsl,sec-v5.0-job-ring", "fsl,sec-v4.0-job-ring"; - reg = <0x40000 0x10000>; + reg = <0x40000 0x10000>; interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; }; @@ -271,6 +271,14 @@ }; }; + sfp: efuse@1e80000 { + compatible = "fsl,ls1021a-sfp"; + reg = <0x0 0x1e80000 0x0 0x10000>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(4)>; + clock-names = "sfp"; + }; + sec_mon: sec_mon@1e90000 { compatible = "fsl,sec-v5.4-mon", "fsl,sec-v5.0-mon", "fsl,sec-v4.0-mon"; @@ -465,7 +473,7 @@ status = "disabled"; }; - edma0: edma@2c00000 { + edma0: dma-controller@2c00000 { #dma-cells = <2>; compatible = "fsl,vf610-edma"; reg = <0x0 0x2c00000 0x0 0x10000>, diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts index 5baf060acf93..0bb2f28a0441 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts @@ -93,7 +93,7 @@ compatible = "mdio-mux-multiplexer"; mux-controls = <&mux 0>; mdio-parent-bus = <&enetc_mdio_pf3>; - #address-cells=<1>; + #address-cells = <1>; #size-cells = <0>; /* on-board RGMII PHY */ diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi index d5cdd77e5a95..5627dd7734f3 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi @@ -96,7 +96,7 @@ }; reboot { - compatible ="syscon-reboot"; + compatible = "syscon-reboot"; regmap = <&rst>; offset = <0>; mask = <0x02>; @@ -120,13 +120,13 @@ }; gic: interrupt-controller@6000000 { - compatible= "arm,gic-v3"; + compatible = "arm,gic-v3"; #address-cells = <2>; #size-cells = <2>; ranges; - reg= <0x0 0x06000000 0 0x10000>, /* GIC Dist */ + reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */ <0x0 0x06040000 0 0x40000>; /* GIC Redistributor */ - #interrupt-cells= <3>; + #interrupt-cells = <3>; interrupt-controller; interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) | IRQ_TYPE_LEVEL_LOW)>; @@ -772,28 +772,28 @@ sec_jr0: jr@10000 { compatible = "fsl,sec-v5.0-job-ring", "fsl,sec-v4.0-job-ring"; - reg = <0x10000 0x10000>; + reg = <0x10000 0x10000>; interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; }; sec_jr1: jr@20000 { compatible = "fsl,sec-v5.0-job-ring", "fsl,sec-v4.0-job-ring"; - reg = <0x20000 0x10000>; + reg = <0x20000 0x10000>; interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; }; sec_jr2: jr@30000 { compatible = "fsl,sec-v5.0-job-ring", "fsl,sec-v4.0-job-ring"; - reg = <0x30000 0x10000>; + reg = <0x30000 0x10000>; interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; }; sec_jr3: jr@40000 { compatible = "fsl,sec-v5.0-job-ring", "fsl,sec-v4.0-job-ring"; - reg = <0x40000 0x10000>; + reg = <0x40000 0x10000>; interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; }; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi index 21200cbf7161..ca3d5a90d6d4 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi @@ -144,7 +144,7 @@ }; reboot { - compatible ="syscon-reboot"; + compatible = "syscon-reboot"; regmap = <&dcfg>; offset = <0xb0>; mask = <0x02>; @@ -354,7 +354,7 @@ compatible = "fsl,sec-v5.4-job-ring", "fsl,sec-v5.0-job-ring", "fsl,sec-v4.0-job-ring"; - reg = <0x10000 0x10000>; + reg = <0x10000 0x10000>; interrupts = <0 71 0x4>; }; @@ -362,7 +362,7 @@ compatible = "fsl,sec-v5.4-job-ring", "fsl,sec-v5.0-job-ring", "fsl,sec-v4.0-job-ring"; - reg = <0x20000 0x10000>; + reg = <0x20000 0x10000>; interrupts = <0 72 0x4>; }; @@ -370,7 +370,7 @@ compatible = "fsl,sec-v5.4-job-ring", "fsl,sec-v5.0-job-ring", "fsl,sec-v4.0-job-ring"; - reg = <0x30000 0x10000>; + reg = <0x30000 0x10000>; interrupts = <0 73 0x4>; }; @@ -378,11 +378,19 @@ compatible = "fsl,sec-v5.4-job-ring", "fsl,sec-v5.0-job-ring", "fsl,sec-v4.0-job-ring"; - reg = <0x40000 0x10000>; + reg = <0x40000 0x10000>; interrupts = <0 74 0x4>; }; }; + sfp: efuse@1e80000 { + compatible = "fsl,ls1021a-sfp"; + reg = <0x0 0x1e80000 0x0 0x10000>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(4)>; + clock-names = "sfp"; + }; + dcfg: dcfg@1ee0000 { compatible = "fsl,ls1043a-dcfg", "syscon"; reg = <0x0 0x1ee0000 0x0 0x10000>; @@ -784,7 +792,7 @@ big-endian; }; - edma0: edma@2c00000 { + edma0: dma-controller@2c00000 { #dma-cells = <2>; compatible = "fsl,vf610-edma"; reg = <0x0 0x2c00000 0x0 0x10000>, diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi index 0085e83adf65..feab604322cf 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi @@ -112,7 +112,7 @@ }; reboot { - compatible ="syscon-reboot"; + compatible = "syscon-reboot"; regmap = <&dcfg>; offset = <0xb0>; mask = <0x02>; @@ -360,7 +360,7 @@ compatible = "fsl,sec-v5.4-job-ring", "fsl,sec-v5.0-job-ring", "fsl,sec-v4.0-job-ring"; - reg = <0x10000 0x10000>; + reg = <0x10000 0x10000>; interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; }; @@ -368,7 +368,7 @@ compatible = "fsl,sec-v5.4-job-ring", "fsl,sec-v5.0-job-ring", "fsl,sec-v4.0-job-ring"; - reg = <0x20000 0x10000>; + reg = <0x20000 0x10000>; interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; }; @@ -376,7 +376,7 @@ compatible = "fsl,sec-v5.4-job-ring", "fsl,sec-v5.0-job-ring", "fsl,sec-v4.0-job-ring"; - reg = <0x30000 0x10000>; + reg = <0x30000 0x10000>; interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; }; @@ -384,7 +384,7 @@ compatible = "fsl,sec-v5.4-job-ring", "fsl,sec-v5.0-job-ring", "fsl,sec-v4.0-job-ring"; - reg = <0x40000 0x10000>; + reg = <0x40000 0x10000>; interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; }; }; @@ -413,6 +413,14 @@ ranges = <0x0 0x5 0x08000000 0x8000000>; }; + sfp: efuse@1e80000 { + compatible = "fsl,ls1021a-sfp"; + reg = <0x0 0x1e80000 0x0 0x10000>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(4)>; + clock-names = "sfp"; + }; + dcfg: dcfg@1ee0000 { compatible = "fsl,ls1046a-dcfg", "syscon"; reg = <0x0 0x1ee0000 0x0 0x1000>; @@ -683,7 +691,7 @@ big-endian; }; - edma0: edma@2c00000 { + edma0: dma-controller@2c00000 { #dma-cells = <2>; compatible = "fsl,vf610-edma"; reg = <0x0 0x2c00000 0x0 0x10000>, diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a-ten64.dts b/arch/arm64/boot/dts/freescale/fsl-ls1088a-ten64.dts index d3f03dcbb8c3..ef6c8967533e 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a-ten64.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a-ten64.dts @@ -35,14 +35,14 @@ * external power off (e.g ATX Power Button) * asserted */ - powerdn { + button-powerdn { label = "External Power Down"; gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; linux,code = <KEY_POWER>; }; /* Rear Panel 'ADMIN' button (GPIO_H) */ - admin { + button-admin { label = "ADMIN button"; gpios = <&gpio3 8 GPIO_ACTIVE_HIGH>; linux,code = <KEY_WPS_BUTTON>; @@ -52,17 +52,17 @@ leds { compatible = "gpio-leds"; - sfp1down { + led-0 { label = "ten64:green:sfp1:down"; gpios = <&gpio3 11 GPIO_ACTIVE_HIGH>; }; - sfp2up { + led-1 { label = "ten64:green:sfp2:up"; gpios = <&gpio3 12 GPIO_ACTIVE_HIGH>; }; - admin { + led-2 { label = "ten64:admin"; gpios = <&sfpgpio 12 GPIO_ACTIVE_HIGH>; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi index f476b7d8b056..421d879013d7 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi @@ -269,6 +269,14 @@ }; }; + sfp: efuse@1e80000 { + compatible = "fsl,ls1028a-sfp"; + reg = <0x0 0x1e80000 0x0 0x10000>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(4)>; + clock-names = "sfp"; + }; + tmu: tmu@1f80000 { compatible = "fsl,qoriq-tmu"; reg = <0x0 0x1f80000 0x0 0x10000>; @@ -526,28 +534,28 @@ sec_jr0: jr@10000 { compatible = "fsl,sec-v5.0-job-ring", "fsl,sec-v4.0-job-ring"; - reg = <0x10000 0x10000>; + reg = <0x10000 0x10000>; interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; }; sec_jr1: jr@20000 { compatible = "fsl,sec-v5.0-job-ring", "fsl,sec-v4.0-job-ring"; - reg = <0x20000 0x10000>; + reg = <0x20000 0x10000>; interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; }; sec_jr2: jr@30000 { compatible = "fsl,sec-v5.0-job-ring", "fsl,sec-v4.0-job-ring"; - reg = <0x30000 0x10000>; + reg = <0x30000 0x10000>; interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; }; sec_jr3: jr@40000 { compatible = "fsl,sec-v5.0-job-ring", "fsl,sec-v4.0-job-ring"; - reg = <0x40000 0x10000>; + reg = <0x40000 0x10000>; interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; }; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi index 4ba1e0499dfd..d76f1c42f3fa 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi @@ -73,7 +73,7 @@ }; reboot { - compatible ="syscon-reboot"; + compatible = "syscon-reboot"; regmap = <&rstcr>; offset = <0x0>; mask = <0x2>; @@ -278,6 +278,14 @@ little-endian; }; + sfp: efuse@1e80000 { + compatible = "fsl,ls1028a-sfp"; + reg = <0x0 0x1e80000 0x0 0x10000>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(4)>; + clock-names = "sfp"; + }; + isc: syscon@1f70000 { compatible = "fsl,ls2080a-isc", "syscon"; reg = <0x0 0x1f70000 0x0 0x10000>; @@ -479,28 +487,28 @@ sec_jr0: jr@10000 { compatible = "fsl,sec-v5.0-job-ring", "fsl,sec-v4.0-job-ring"; - reg = <0x10000 0x10000>; + reg = <0x10000 0x10000>; interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; }; sec_jr1: jr@20000 { compatible = "fsl,sec-v5.0-job-ring", "fsl,sec-v4.0-job-ring"; - reg = <0x20000 0x10000>; + reg = <0x20000 0x10000>; interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; }; sec_jr2: jr@30000 { compatible = "fsl,sec-v5.0-job-ring", "fsl,sec-v4.0-job-ring"; - reg = <0x30000 0x10000>; + reg = <0x30000 0x10000>; interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; }; sec_jr3: jr@40000 { compatible = "fsl,sec-v5.0-job-ring", "fsl,sec-v4.0-job-ring"; - reg = <0x40000 0x10000>; + reg = <0x40000 0x10000>; interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; }; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts index 2ecfa90f5e28..4d721197d837 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts @@ -36,7 +36,7 @@ compatible = "mdio-mux-multiplexer"; mux-controls = <&mux 0>; mdio-parent-bus = <&emdio1>; - #address-cells=<1>; + #address-cells = <1>; #size-cells = <0>; mdio@0 { /* On-board PHY #1 RGMI1*/ @@ -104,7 +104,7 @@ compatible = "mdio-mux-multiplexer"; mux-controls = <&mux 1>; mdio-parent-bus = <&emdio2>; - #address-cells=<1>; + #address-cells = <1>; #size-cells = <0>; mdio@0 { /* Slot #1 (secondary EMI) */ diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi index 47ea854720ce..6680fb2a6dc9 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi @@ -632,28 +632,28 @@ sec_jr0: jr@10000 { compatible = "fsl,sec-v5.0-job-ring", "fsl,sec-v4.0-job-ring"; - reg = <0x10000 0x10000>; + reg = <0x10000 0x10000>; interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; }; sec_jr1: jr@20000 { compatible = "fsl,sec-v5.0-job-ring", "fsl,sec-v4.0-job-ring"; - reg = <0x20000 0x10000>; + reg = <0x20000 0x10000>; interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; }; sec_jr2: jr@30000 { compatible = "fsl,sec-v5.0-job-ring", "fsl,sec-v4.0-job-ring"; - reg = <0x30000 0x10000>; + reg = <0x30000 0x10000>; interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; }; sec_jr3: jr@40000 { compatible = "fsl,sec-v5.0-job-ring", "fsl,sec-v4.0-job-ring"; - reg = <0x40000 0x10000>; + reg = <0x40000 0x10000>; interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; }; }; @@ -671,6 +671,14 @@ little-endian; }; + sfp: efuse@1e80000 { + compatible = "fsl,ls1028a-sfp"; + reg = <0x0 0x1e80000 0x0 0x10000>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(4)>; + clock-names = "sfp"; + }; + isc: syscon@1f70000 { compatible = "fsl,lx2160a-isc", "syscon"; reg = <0x0 0x1f70000 0x0 0x10000>; diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts index a1644ceed154..9f5ff1ffe7d5 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts +++ b/arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts @@ -34,7 +34,7 @@ compatible = "mdio-mux-multiplexer"; mux-controls = <&mux 0>; mdio-parent-bus = <&emdio1>; - #address-cells=<1>; + #address-cells = <1>; #size-cells = <0>; mdio@0 { /* On-board RTL8211F PHY #1 RGMII1 */ @@ -114,7 +114,7 @@ compatible = "mdio-mux-multiplexer"; mux-controls = <&mux 1>; mdio-parent-bus = <&emdio2>; - #address-cells=<1>; + #address-cells = <1>; #size-cells = <0>; mdio@0 { /* Slot #1 (secondary EMI) */ diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi index a79f42a9618e..82a1c4488378 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi @@ -54,7 +54,7 @@ conn_subsys: bus@5b000000 { clock-names = "ipg", "per", "ahb"; power-domains = <&pd IMX_SC_R_SDHC_1>; fsl,tuning-start-tap = <20>; - fsl,tuning-step= <2>; + fsl,tuning-step = <2>; status = "disabled"; }; @@ -83,8 +83,8 @@ conn_subsys: bus@5b000000 { assigned-clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>, <&clk IMX_SC_R_ENET_0 IMX_SC_C_CLKDIV>; assigned-clock-rates = <250000000>, <125000000>; - fsl,num-tx-queues=<3>; - fsl,num-rx-queues=<3>; + fsl,num-tx-queues = <3>; + fsl,num-rx-queues = <3>; power-domains = <&pd IMX_SC_R_ENET_0>; status = "disabled"; }; @@ -103,8 +103,8 @@ conn_subsys: bus@5b000000 { assigned-clocks = <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>, <&clk IMX_SC_R_ENET_1 IMX_SC_C_CLKDIV>; assigned-clock-rates = <250000000>, <125000000>; - fsl,num-tx-queues=<3>; - fsl,num-rx-queues=<3>; + fsl,num-tx-queues = <3>; + fsl,num-rx-queues = <3>; power-domains = <&pd IMX_SC_R_ENET_1>; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi index f338a886d811..03266bd90a06 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi @@ -285,14 +285,14 @@ &usbotg1 { vbus-supply = <®_usbotg1>; disable-over-current; - dr_mode="otg"; + dr_mode = "otg"; status = "okay"; }; &usbotg2 { pinctrl-names = "default"; disable-over-current; - dr_mode="host"; + dr_mode = "host"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi index c42b966f7a64..7d6317d95b13 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi @@ -75,6 +75,11 @@ linux,autosuspend-period = <125>; }; + audio_codec_bt_sco: audio-codec-bt-sco { + compatible = "linux,bt-sco"; + #sound-dai-cells = <1>; + }; + wm8524: audio-codec { #sound-dai-cells = <0>; compatible = "wlf,wm8524"; @@ -83,6 +88,25 @@ wlf,mute-gpios = <&gpio5 21 GPIO_ACTIVE_LOW>; }; + sound-bt-sco { + compatible = "simple-audio-card"; + simple-audio-card,name = "bt-sco-audio"; + simple-audio-card,format = "dsp_a"; + simple-audio-card,bitclock-inversion; + simple-audio-card,frame-master = <&btcpu>; + simple-audio-card,bitclock-master = <&btcpu>; + + btcpu: simple-audio-card,cpu { + sound-dai = <&sai2>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <16>; + }; + + simple-audio-card,codec { + sound-dai = <&audio_codec_bt_sco 1>; + }; + }; + sound-wm8524 { compatible = "simple-audio-card"; simple-audio-card,name = "wm8524-audio"; @@ -346,6 +370,16 @@ status = "okay"; }; +&sai2 { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai2>; + assigned-clocks = <&clk IMX8MM_CLK_SAI2>; + assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; + assigned-clock-rates = <24576000>; + status = "okay"; +}; + &sai3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sai3>; @@ -494,6 +528,15 @@ >; }; + pinctrl_sai2: sai2grp { + fsl,pins = < + MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6 + MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6 + MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6 + MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6 + >; + }; + pinctrl_sai3: sai3grp { fsl,pins = < MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 diff --git a/arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm.dtsi index b40148d728ea..9e6170d9394e 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm.dtsi @@ -84,42 +84,42 @@ }; reg_buck1: buck1 { - regulator-min-microvolt = <400000>; + regulator-min-microvolt = <400000>; regulator-max-microvolt = <1800000>; regulator-always-on; regulator-boot-on; }; reg_buck2: buck2 { - regulator-min-microvolt = <400000>; + regulator-min-microvolt = <400000>; regulator-max-microvolt = <1800000>; regulator-always-on; regulator-boot-on; }; reg_buck3: buck3 { - regulator-min-microvolt = <400000>; + regulator-min-microvolt = <400000>; regulator-max-microvolt = <1800000>; regulator-always-on; regulator-boot-on; }; reg_buck4: buck4 { - regulator-min-microvolt = <400000>; + regulator-min-microvolt = <400000>; regulator-max-microvolt = <1800000>; regulator-always-on; regulator-boot-on; }; reg_buck5: buck5 { - regulator-min-microvolt = <400000>; + regulator-min-microvolt = <400000>; regulator-max-microvolt = <1800000>; regulator-always-on; regulator-boot-on; }; reg_buck6: buck6 { - regulator-min-microvolt = <400000>; + regulator-min-microvolt = <400000>; regulator-max-microvolt = <1800000>; regulator-always-on; regulator-boot-on; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-mx8menlo.dts b/arch/arm64/boot/dts/freescale/imx8mm-mx8menlo.dts index 92eaf4ef4563..c97f4e06ae5f 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-mx8menlo.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-mx8menlo.dts @@ -20,13 +20,13 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_led>; - user1 { + led-1 { label = "TestLed601"; gpios = <&gpio4 18 GPIO_ACTIVE_HIGH>; linux,default-trigger = "mmc0"; }; - user2 { + led-2 { label = "TestLed602"; gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts b/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts new file mode 100644 index 000000000000..4a3df2b77b0b --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts @@ -0,0 +1,450 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2022 PHYTEC Messtechnik GmbH + * Author: Teresa Remmet <t.remmet@phytec.de> + */ + +/dts-v1/; + +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/phy/phy-imx8-pcie.h> +#include "imx8mm-phycore-som.dtsi" + +/ { + model = "PHYTEC phyBOARD-Polis-i.MX8MM RDK"; + compatible = "phytec,imx8mm-phyboard-polis-rdk", + "phytec,imx8mm-phycore-som", "fsl,imx8mm"; + + chosen { + stdout-path = &uart3; + }; + + bt_osc_32k: bt-lp-clock { + compatible = "fixed-clock"; + clock-frequency = <32768>; + clock-output-names = "bt_osc_32k"; + #clock-cells = <0>; + }; + + can_osc_40m: can-clock { + compatible = "fixed-clock"; + clock-frequency = <40000000>; + clock-output-names = "can_osc_40m"; + #clock-cells = <0>; + }; + + fan { + compatible = "gpio-fan"; + gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>; + gpio-fan,speed-map = <0 0 + 13000 1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fan>; + #cooling-cells = <2>; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_leds>; + + led-0 { + color = <LED_COLOR_ID_RED>; + function = LED_FUNCTION_DISK; + gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc2"; + }; + + led-1 { + color = <LED_COLOR_ID_BLUE>; + function = LED_FUNCTION_DISK; + gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc1"; + }; + + led-2 { + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_CPU; + gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + usdhc1_pwrseq: pwr-seq { + compatible = "mmc-pwrseq-simple"; + post-power-on-delay-ms = <100>; + power-off-delay-us = <60>; + reset-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>; + }; + + reg_can_en: regulator-can-en { + compatible = "regulator-fixed"; + gpio = <&gpio1 9 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can_en>; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "CAN_EN"; + startup-delay-us = <20>; + }; + + reg_usb_otg1_vbus: regulator-usb-otg1 { + compatible = "regulator-fixed"; + gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1pwrgrp>; + regulator-name = "usb_otg1_vbus"; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + off-on-delay-us = <20000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "VSD_3V3"; + }; + + reg_vcc_3v3: regulator-vcc-3v3 { + compatible = "regulator-fixed"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "VCC_3V3"; + }; +}; + +/* SPI - CAN MCP251XFD */ +&ecspi1 { + cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + status = "okay"; + + can0: can@0 { + compatible = "microchip,mcp251xfd"; + clocks = <&can_osc_40m>; + interrupt-parent = <&gpio1>; + interrupts = <8 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can_int>; + reg = <0>; + spi-max-frequency = <20000000>; + xceiver-supply = <®_can_en>; + }; +}; + +&gpio1 { + gpio-line-names = "nINT_ETHPHY", "LED_RED", "WDOG_INT", "X_RTC_INT", + "", "", "", "RESET_ETHPHY", + "CAN_nINT", "CAN_EN", "nENABLE_FLATLINK", "", + "USB_OTG_VBUS_EN", "", "LED_GREEN", "LED_BLUE"; +}; + +&gpio2 { + gpio-line-names = "", "", "", "", + "", "", "BT_REG_ON", "WL_REG_ON", + "BT_DEV_WAKE", "BT_HOST_WAKE", "", "", + "X_SD2_CD_B", "", "", "", + "", "", "", "SD2_RESET_B"; +}; + +&gpio4 { + gpio-line-names = "", "", "", "", + "", "", "", "", + "FAN", "miniPCIe_nPERST", "", "", + "COEX1", "COEX2"; +}; + +&gpio5 { + gpio-line-names = "", "", "", "", + "", "", "", "", + "", "ECSPI1_SS0"; +}; + +/* PCIe */ +&pcie0 { + assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, + <&clk IMX8MM_CLK_PCIE1_CTRL>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, + <&clk IMX8MM_SYS_PLL2_250M>; + assigned-clock-rates = <10000000>, <250000000>; + clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>, + <&clk IMX8MM_CLK_PCIE1_PHY>; + clock-names = "pcie", "pcie_aux", "pcie_bus"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpio = <&gpio4 9 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pcie_phy { + clocks = <&clk IMX8MM_CLK_PCIE1_PHY>; + fsl,clkreq-unsupported; + fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>; + fsl,tx-deemph-gen1 = <0x2d>; + fsl,tx-deemph-gen2 = <0xf>; + status = "okay"; +}; + +&rv3028 { + trickle-resistor-ohms = <3000>; +}; + +&snvs_pwrkey { + status = "okay"; +}; + +/* UART - RS232/RS485 */ +&uart1 { + assigned-clocks = <&clk IMX8MM_CLK_UART1>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + uart-has-rtscts; + status = "okay"; +}; + +/* UART - Sterling-LWB Bluetooth */ +&uart2 { + assigned-clocks = <&clk IMX8MM_CLK_UART2>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; + fsl,dte-mode; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2_bt>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + clocks = <&bt_osc_32k>; + clock-names = "lpo"; + device-wakeup-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>; + interrupt-names = "host-wakeup"; + interrupt-parent = <&gpio2>; + interrupts = <9 IRQ_TYPE_EDGE_BOTH>; + max-speed = <2000000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_bt>; + shutdown-gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>; + vddio-supply = <®_vcc_3v3>; + }; +}; + +/* UART - console */ +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +/* USB */ +&usbotg1 { + adp-disable; + dr_mode = "otg"; + over-current-active-low; + samsung,picophy-pre-emp-curr-control = <3>; + samsung,picophy-dc-vol-level-adjust = <7>; + srp-disable; + vbus-supply = <®_usb_otg1_vbus>; + status = "okay"; +}; + +&usbotg2 { + disable-over-current; + dr_mode = "host"; + samsung,picophy-pre-emp-curr-control = <3>; + samsung,picophy-dc-vol-level-adjust = <7>; + status = "okay"; +}; + +/* SDIO - Sterling-LWB Wifi */ +&usdhc1 { + assigned-clocks = <&clk IMX8MM_CLK_USDHC1>; + assigned-clock-rates = <200000000>; + bus-width = <4>; + mmc-pwrseq = <&usdhc1_pwrseq>; + non-removable; + no-1-8-v; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_wlan>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + brcmf: wifi@1 { + compatible = "brcm,bcm4329-fmac"; + reg = <1>; + }; +}; + +/* SD-Card */ +&usdhc2 { + assigned-clocks = <&clk IMX8MM_CLK_USDHC2>; + assigned-clock-rates = <200000000>; + bus-width = <4>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + disable-wp; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + vmmc-supply = <®_usdhc2_vmmc>; + vqmmc-supply = <®_nvcc_sd2>; + status = "okay"; +}; + +&iomuxc { + pinctrl_bt: btgrp { + fsl,pins = < + MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x00 + MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x00 + MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x00 + >; + }; + + pinctrl_can_en: can-engrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x00 + >; + }; + + pinctrl_can_int: can-intgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x00 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x80 + MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x80 + MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x80 + MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x00 + >; + }; + + pinctrl_fan: fan0grp { + fsl,pins = < + MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x16 + >; + }; + + pinctrl_leds: leds1grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x16 + MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x16 + MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x16 + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = < + MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x00 + MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x12 + MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x12 + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = < + MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x40 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x00 + MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 0x00 + MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x00 + MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 0x00 + >; + }; + + pinctrl_uart2_bt: uart2btgrp { + fsl,pins = < + MX8MM_IOMUXC_SAI3_RXC_UART2_DTE_RTS_B 0x00 + MX8MM_IOMUXC_SAI3_RXD_UART2_DTE_CTS_B 0x00 + MX8MM_IOMUXC_SAI3_TXC_UART2_DTE_RX 0x00 + MX8MM_IOMUXC_SAI3_TXFS_UART2_DTE_TX 0x00 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x40 + MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x40 + >; + }; + + pinctrl_usbotg1pwrgrp: usbotg1pwrgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x00 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x182 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0xc6 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc6 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc6 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc6 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc6 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x40 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x192 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d2 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d2 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d2 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d2 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d2 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 + >; + }; + + pinctrl_wlan: wlangrp { + fsl,pins = < + MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7 0x00 + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-phycore-som.dtsi new file mode 100644 index 000000000000..995b44efb1b6 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-phycore-som.dtsi @@ -0,0 +1,440 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2022 PHYTEC Messtechnik GmbH + * Author: Teresa Remmet <t.remmet@phytec.de> + */ + +#include "imx8mm.dtsi" +#include <dt-bindings/net/ti-dp83867.h> + +/ { + model = "PHYTEC phyCORE-i.MX8MM"; + compatible = "phytec,imx8mm-phycore-som", "fsl,imx8mm"; + + aliases { + rtc0 = &rv3028; + rtc1 = &snvs_rtc; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0x0 0x40000000 0 0x80000000>; + }; + + reg_vdd_3v3_s: regulator-vdd-3v3-s { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "VDD_3V3_S"; + }; +}; + +&A53_0 { + cpu-supply = <®_vdd_arm>; +}; + +&A53_1 { + cpu-supply = <®_vdd_arm>; +}; + +&A53_2 { + cpu-supply = <®_vdd_arm>; +}; + +&A53_3 { + cpu-supply = <®_vdd_arm>; +}; + +&ddrc { + operating-points-v2 = <&ddrc_opp_table>; + + ddrc_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-25M { + opp-hz = /bits/ 64 <25000000>; + }; + + opp-100M { + opp-hz = /bits/ 64 <100000000>; + }; + + opp-750M { + opp-hz = /bits/ 64 <750000000>; + }; + }; +}; + +/* Ethernet */ +&fec1 { + fsl,magic-packet; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + enet-phy-lane-no-swap; + ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; + ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; + reg = <0>; + reset-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; + reset-assert-us = <1000>; + reset-deassert-us = <1000>; + }; + }; +}; + +/* SPI Flash */ +&flexspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; + + som_flash: flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <80000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <1>; + }; +}; + +&gpio1 { + gpio-line-names = "nINT_ETHPHY", "", "WDOG_INT", "X_RTC_INT", + "", "", "", "RESET_ETHPHY", + "", "", "nENABLE_FLATLINK"; +}; + +/* I2C1 */ +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default","gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + pmic@8 { + compatible = "nxp,pf8121a"; + reg = <0x08>; + + regulators { + reg_nvcc_sd1: ldo1 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "NVCC_SD1 (LDO1)"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + reg_nvcc_sd2: ldo2 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1800000>; + regulator-name = "NVCC_SD2 (LDO2)"; + vselect-en; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + reg_vcc_enet: ldo3 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <2500000>; + regulator-min-microvolt = <1500000>; + regulator-name = "VCC_ENET_2V5 (LDO3)"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + reg_vdda_1v8: ldo4 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1500000>; + regulator-name = "VDDA_1V8 (LDO4)"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-min-microvolt = <1500000>; + regulator-suspend-max-microvolt = <1500000>; + }; + }; + + reg_soc_vdda_phy: buck1 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <900000>; + regulator-min-microvolt = <400000>; + regulator-name = "VDD_SOC_VDDA_PHY_0P8 (BUCK1)"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-min-microvolt = <400000>; + regulator-suspend-max-microvolt = <400000>; + }; + }; + + reg_vdd_gpu_dram: buck2 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1000000>; + regulator-min-microvolt = <1000000>; + regulator-name = "VDD_GPU_DRAM (BUCK2)"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-max-microvolt = <1000000>; + regulator-suspend-min-microvolt = <1000000>; + }; + }; + + reg_vdd_gpu: buck3 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1000000>; + regulator-min-microvolt = <400000>; + regulator-name = "VDD_VPU (BUCK3)"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + reg_vdd_mipi: buck4 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1050000>; + regulator-min-microvolt = <900000>; + regulator-name = "VDD_MIPI_0P9 (BUCK4)"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + reg_vdd_arm: buck5 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1050000>; + regulator-min-microvolt = <400000>; + regulator-name = "VDD_ARM (BUCK5)"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + reg_vdd_1v8: buck6 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "VDD_1V8 (BUCK6)"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-max-microvolt = <1800000>; + regulator-suspend-min-microvolt = <1800000>; + }; + }; + + reg_nvcc_dram: buck7 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1100000>; + regulator-min-microvolt = <1100000>; + regulator-name = "NVCC_DRAM_1P1V (BUCK7)"; + }; + + reg_vsnvs: vsnvs { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "NVCC_SNVS_1P8 (VSNVS)"; + }; + }; + }; + + sn65dsi83: bridge@2d { + compatible = "ti,sn65dsi83"; + enable-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sn65dsi83>; + reg = <0x2d>; + status = "disabled"; + }; + + eeprom@51 { + compatible = "atmel,24c32"; + pagesize = <32>; + reg = <0x51>; + vcc-supply = <®_vdd_3v3_s>; + }; + + rv3028: rtc@52 { + compatible = "microcrystal,rv3028"; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rtc>; + reg = <0x52>; + }; +}; + +/* EMMC */ +&usdhc3 { + assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>; + assigned-clock-rates = <400000000>; + bus-width = <8>; + keep-power-in-suspend; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + non-removable; + status = "okay"; +}; + +/* Watchdog */ +&wdog1 { + fsl,ext-reset-output; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + status = "okay"; +}; + +&iomuxc { + pinctrl_fec1: fec1grp { + fsl,pins = < + MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x2 + MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x2 + MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x90 + MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x90 + MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x90 + MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x90 + MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x90 + MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x90 + MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x16 + MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x16 + MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x16 + MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x16 + MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x16 + MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x16 + MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x10 + >; + }; + + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2 + MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 + MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 + MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 + MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 + MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c0 + MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c0 + >; + }; + + pinctrl_i2c1_gpio: i2c1gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x1e0 + MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x1e0 + >; + }; + + pinctrl_rtc: rtcgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x1c0 + >; + }; + + pinctrl_sn65dsi83: sn65dsi83grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x0 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x26 + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts index ac1fe1530ac7..d643381417f1 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts @@ -36,19 +36,19 @@ gpio-keys { compatible = "gpio-keys"; - back { + key-back { label = "Back"; gpios = <&pca9534 1 GPIO_ACTIVE_LOW>; linux,code = <KEY_BACK>; }; - home { + key-home { label = "Home"; gpios = <&pca9534 2 GPIO_ACTIVE_LOW>; linux,code = <KEY_HOME>; }; - menu { + key-menu { label = "Menu"; gpios = <&pca9534 3 GPIO_ACTIVE_LOW>; linux,code = <KEY_MENU>; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw700x.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw700x.dtsi index 00f86cada30d..66a0d103c90f 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw700x.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw700x.dtsi @@ -16,13 +16,13 @@ gpio-keys { compatible = "gpio-keys"; - user-pb { + key-user-pb { label = "user_pb"; gpios = <&gpio 2 GPIO_ACTIVE_LOW>; linux,code = <BTN_0>; }; - user-pb1x { + key-user-pb1x { label = "user_pb1x"; linux,code = <BTN_1>; interrupt-parent = <&gsc>; @@ -36,14 +36,14 @@ interrupts = <1>; }; - eeprom-wp { + key-eeprom-wp { label = "eeprom_wp"; linux,code = <BTN_3>; interrupt-parent = <&gsc>; interrupts = <2>; }; - tamper { + key-tamper { label = "tamper"; linux,code = <BTN_4>; interrupt-parent = <&gsc>; @@ -286,8 +286,8 @@ regulator-name = "buck1"; regulator-min-microvolt = <800000>; regulator-max-microvolt = <1000000>; - regulator-min-microamp = <3800000>; - regulator-max-microamp = <6800000>; + regulator-min-microamp = <3800000>; + regulator-max-microamp = <6800000>; regulator-boot-on; regulator-always-on; }; @@ -297,8 +297,8 @@ regulator-name = "buck2"; regulator-min-microvolt = <800000>; regulator-max-microvolt = <900000>; - regulator-min-microamp = <2200000>; - regulator-max-microamp = <5200000>; + regulator-min-microamp = <2200000>; + regulator-max-microamp = <5200000>; regulator-boot-on; regulator-always-on; }; @@ -308,8 +308,8 @@ regulator-name = "buck3"; regulator-min-microvolt = <800000>; regulator-max-microvolt = <1000000>; - regulator-min-microamp = <3800000>; - regulator-max-microamp = <6800000>; + regulator-min-microamp = <3800000>; + regulator-max-microamp = <6800000>; regulator-always-on; }; @@ -318,8 +318,8 @@ regulator-name = "buck4"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; - regulator-min-microamp = <2200000>; - regulator-max-microamp = <5200000>; + regulator-min-microamp = <2200000>; + regulator-max-microamp = <5200000>; regulator-boot-on; regulator-always-on; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts index 24737e89038a..35fb929e7bcc 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts @@ -38,13 +38,13 @@ gpio-keys { compatible = "gpio-keys"; - user-pb { + key-user-pb { label = "user_pb"; gpios = <&gpio 2 GPIO_ACTIVE_LOW>; linux,code = <BTN_0>; }; - user-pb1x { + key-user-pb1x { label = "user_pb1x"; linux,code = <BTN_1>; interrupt-parent = <&gsc>; @@ -58,14 +58,14 @@ interrupts = <1>; }; - eeprom-wp { + key-eeprom-wp { label = "eeprom_wp"; linux,code = <BTN_3>; interrupt-parent = <&gsc>; interrupts = <2>; }; - tamper { + key-tamper { label = "tamper"; linux,code = <BTN_4>; interrupt-parent = <&gsc>; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts index 407ab4592b4c..6dc5eda2d256 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts @@ -42,13 +42,13 @@ gpio-keys { compatible = "gpio-keys"; - user-pb { + key-user-pb { label = "user_pb"; gpios = <&gpio 2 GPIO_ACTIVE_LOW>; linux,code = <BTN_0>; }; - user-pb1x { + key-user-pb1x { label = "user_pb1x"; linux,code = <BTN_1>; interrupt-parent = <&gsc>; @@ -62,14 +62,14 @@ interrupts = <1>; }; - eeprom-wp { + key-eeprom-wp { label = "eeprom_wp"; linux,code = <BTN_3>; interrupt-parent = <&gsc>; interrupts = <2>; }; - tamper { + key-tamper { label = "tamper"; linux,code = <BTN_4>; interrupt-parent = <&gsc>; @@ -651,7 +651,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>, <&pinctrl_uart1_gpio>; rts-gpios = <&gpio4 10 GPIO_ACTIVE_LOW>; - cts-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>; + cts-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; uart-has-rtscts; status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts index a7dae9bd4c11..a65761a53f23 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts @@ -33,13 +33,13 @@ gpio-keys { compatible = "gpio-keys"; - user-pb { + key-user-pb { label = "user_pb"; gpios = <&gpio 2 GPIO_ACTIVE_LOW>; linux,code = <BTN_0>; }; - user-pb1x { + key-user-pb1x { label = "user_pb1x"; linux,code = <BTN_1>; interrupt-parent = <&gsc>; @@ -53,7 +53,7 @@ interrupts = <1>; }; - eeprom-wp { + key-eeprom-wp { label = "eeprom_wp"; linux,code = <BTN_3>; interrupt-parent = <&gsc>; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi index eafa88d980b3..d1b4582f44c4 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi @@ -43,7 +43,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_keys>; - wakeup { + key-wakeup { debounce-interval = <10>; /* Verdin CTRL_WAKE1_MICO# (SODIMM 252) */ gpios = <&gpio4 28 GPIO_ACTIVE_LOW>; @@ -154,6 +154,14 @@ cpu-supply = <®_vdd_arm>; }; +&cpu_alert0 { + temperature = <95000>; +}; + +&cpu_crit0 { + temperature = <105000>; +}; + &ddrc { operating-points-v2 = <&ddrc_opp_table>; diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index 1bf070473829..afb90f59c83c 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -212,7 +212,7 @@ clk_ext4: clock-ext4 { compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency= <133000000>; + clock-frequency = <133000000>; clock-output-names = "clk_ext4"; }; @@ -287,7 +287,7 @@ clock-names = "main_clk"; }; - soc@0 { + soc: soc@0 { compatible = "fsl,imx8mm-soc", "simple-bus"; #address-cells = <1>; #size-cells = <1>; @@ -602,6 +602,11 @@ wakeup-source; status = "disabled"; }; + + snvs_lpgpr: snvs-lpgpr { + compatible = "fsl,imx8mm-snvs-lpgpr", + "fsl,imx7d-snvs-lpgpr"; + }; }; clk: clock-controller@30380000 { @@ -911,6 +916,7 @@ compatible = "fsl,sec-v4.0-job-ring"; reg = <0x1000 0x1000>; interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; }; sec_jr1: jr@2000 { @@ -995,7 +1001,7 @@ <&clk IMX8MM_CLK_USDHC1_ROOT>; clock-names = "ipg", "ahb", "per"; fsl,tuning-start-tap = <20>; - fsl,tuning-step= <2>; + fsl,tuning-step = <2>; bus-width = <4>; status = "disabled"; }; @@ -1009,7 +1015,7 @@ <&clk IMX8MM_CLK_USDHC2_ROOT>; clock-names = "ipg", "ahb", "per"; fsl,tuning-start-tap = <20>; - fsl,tuning-step= <2>; + fsl,tuning-step = <2>; bus-width = <4>; status = "disabled"; }; @@ -1023,7 +1029,7 @@ <&clk IMX8MM_CLK_USDHC3_ROOT>; clock-names = "ipg", "ahb", "per"; fsl,tuning-start-tap = <20>; - fsl,tuning-step= <2>; + fsl,tuning-step = <2>; bus-width = <4>; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-beacon-baseboard.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-beacon-baseboard.dtsi index 02f37dcda7ed..9e82069c941f 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-beacon-baseboard.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn-beacon-baseboard.dtsi @@ -146,7 +146,7 @@ }; &easrc { - fsl,asrc-rate = <48000>; + fsl,asrc-rate = <48000>; status = "okay"; }; @@ -182,7 +182,7 @@ &usbotg1 { vbus-supply = <®_usb_otg_vbus>; disable-over-current; - dr_mode="otg"; + dr_mode = "otg"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi index d1f6cccfa00d..261c36540079 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi @@ -47,6 +47,11 @@ linux,autosuspend-period = <125>; }; + audio_codec_bt_sco: audio-codec-bt-sco { + compatible = "linux,bt-sco"; + #sound-dai-cells = <1>; + }; + wm8524: audio-codec { #sound-dai-cells = <0>; compatible = "wlf,wm8524"; @@ -57,6 +62,25 @@ clock-names = "mclk"; }; + sound-bt-sco { + compatible = "simple-audio-card"; + simple-audio-card,name = "bt-sco-audio"; + simple-audio-card,format = "dsp_a"; + simple-audio-card,bitclock-inversion; + simple-audio-card,frame-master = <&btcpu>; + simple-audio-card,bitclock-master = <&btcpu>; + + btcpu: simple-audio-card,cpu { + sound-dai = <&sai2>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <16>; + }; + + simple-audio-card,codec { + sound-dai = <&audio_codec_bt_sco 1>; + }; + }; + sound-wm8524 { compatible = "fsl,imx-audio-wm8524"; model = "wm8524-audio"; @@ -78,7 +102,7 @@ }; &easrc { - fsl,asrc-rate = <48000>; + fsl,asrc-rate = <48000>; status = "okay"; }; @@ -183,6 +207,16 @@ }; }; +&sai2 { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai2>; + assigned-clocks = <&clk IMX8MN_CLK_SAI2>; + assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>; + assigned-clock-rates = <24576000>; + status = "okay"; +}; + &sai3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sai3>; @@ -354,6 +388,15 @@ >; }; + pinctrl_sai2: sai2grp { + fsl,pins = < + MX8MN_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6 + MX8MN_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6 + MX8MN_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6 + MX8MN_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6 + >; + }; + pinctrl_sai3: sai3grp { fsl,pins = < MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 diff --git a/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts index f61c48776cf3..3ed7021a487c 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts +++ b/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts @@ -26,19 +26,19 @@ gpio-keys { compatible = "gpio-keys"; - back { + key-back { label = "Back"; gpios = <&pca9534 1 GPIO_ACTIVE_LOW>; linux,code = <KEY_BACK>; }; - home { + key-home { label = "Home"; gpios = <&pca9534 2 GPIO_ACTIVE_LOW>; linux,code = <KEY_HOME>; }; - menu { + key-menu { label = "Menu"; gpios = <&pca9534 3 GPIO_ACTIVE_LOW>; linux,code = <KEY_MENU>; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts b/arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts index 367a232675aa..636f8602b979 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts +++ b/arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts @@ -39,13 +39,13 @@ gpio-keys { compatible = "gpio-keys"; - user-pb { + key-user-pb { label = "user_pb"; gpios = <&gpio 2 GPIO_ACTIVE_LOW>; linux,code = <BTN_0>; }; - user-pb1x { + key-user-pb1x { label = "user_pb1x"; linux,code = <BTN_1>; interrupt-parent = <&gsc>; @@ -59,14 +59,14 @@ interrupts = <1>; }; - eeprom-wp { + key-eeprom-wp { label = "eeprom_wp"; linux,code = <BTN_3>; interrupt-parent = <&gsc>; interrupts = <2>; }; - tamper { + key-tamper { label = "tamper"; linux,code = <BTN_4>; interrupt-parent = <&gsc>; diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi index e41e1d56f980..0c71b740a316 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi @@ -212,7 +212,7 @@ clk_ext4: clock-ext4 { compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency= <133000000>; + clock-frequency = <133000000>; clock-output-names = "clk_ext4"; }; @@ -269,7 +269,7 @@ arm,no-tick-in-suspend; }; - soc@0 { + soc: soc@0 { compatible = "fsl,imx8mn-soc", "simple-bus"; #address-cells = <1>; #size-cells = <1>; @@ -422,7 +422,7 @@ "ctx2_rx", "ctx2_tx", "ctx3_rx", "ctx3_tx"; firmware-name = "imx/easrc/easrc-imx8mn.bin"; - fsl,asrc-rate = <8000>; + fsl,asrc-rate = <8000>; fsl,asrc-format = <2>; status = "disabled"; }; @@ -857,6 +857,7 @@ compatible = "fsl,sec-v4.0-job-ring"; reg = <0x1000 0x1000>; interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; }; sec_jr1: jr@2000 { @@ -941,7 +942,7 @@ <&clk IMX8MN_CLK_USDHC1_ROOT>; clock-names = "ipg", "ahb", "per"; fsl,tuning-start-tap = <20>; - fsl,tuning-step= <2>; + fsl,tuning-step = <2>; bus-width = <4>; status = "disabled"; }; @@ -955,7 +956,7 @@ <&clk IMX8MN_CLK_USDHC2_ROOT>; clock-names = "ipg", "ahb", "per"; fsl,tuning-start-tap = <20>; - fsl,tuning-step= <2>; + fsl,tuning-step = <2>; bus-width = <4>; status = "disabled"; }; @@ -969,7 +970,7 @@ <&clk IMX8MN_CLK_USDHC3_ROOT>; clock-names = "ipg", "ahb", "per"; fsl,tuning-start-tap = <20>; - fsl,tuning-step= <2>; + fsl,tuning-step = <2>; bus-width = <4>; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk2.dts b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk2.dts new file mode 100644 index 000000000000..2ca2ede2e94e --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk2.dts @@ -0,0 +1,163 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2022 Marek Vasut <marex@denx.de> + */ + +/dts-v1/; + +#include <dt-bindings/leds/common.h> +#include <dt-bindings/net/qca-ar803x.h> +#include <dt-bindings/phy/phy-imx8-pcie.h> +#include "imx8mp-dhcom-som.dtsi" + +/ { + model = "DH electronics i.MX8M Plus DHCOM Premium Developer Kit (2)"; + compatible = "dh,imx8mp-dhcom-pdk2", "fsl,imx8mp"; + + chosen { + stdout-path = &uart1; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-0 { + gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; /* GPIO A */ + label = "TA1-GPIO-A"; + linux,code = <KEY_A>; + pinctrl-0 = <&pinctrl_dhcom_a>; + pinctrl-names = "default"; + wakeup-source; + }; + + button-1 { + gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; /* GPIO B */ + label = "TA2-GPIO-B"; + linux,code = <KEY_B>; + pinctrl-0 = <&pinctrl_dhcom_b>; + pinctrl-names = "default"; + wakeup-source; + }; + + button-2 { + gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; /* GPIO C */ + label = "TA3-GPIO-C"; + linux,code = <KEY_C>; + pinctrl-0 = <&pinctrl_dhcom_c>; + pinctrl-names = "default"; + wakeup-source; + }; + + button-3 { + gpios = <&gpio4 27 GPIO_ACTIVE_LOW>; /* GPIO D */ + label = "TA4-GPIO-D"; + linux,code = <KEY_D>; + pinctrl-0 = <&pinctrl_dhcom_d>; + pinctrl-names = "default"; + wakeup-source; + }; + }; + + led { + compatible = "gpio-leds"; + + led-0 { + color = <LED_COLOR_ID_GREEN>; + default-state = "off"; + function = LED_FUNCTION_INDICATOR; + gpios = <&gpio5 22 GPIO_ACTIVE_HIGH>; /* GPIO E */ + pinctrl-0 = <&pinctrl_dhcom_e>; + pinctrl-names = "default"; + }; + + led-1 { + color = <LED_COLOR_ID_GREEN>; + default-state = "off"; + function = LED_FUNCTION_INDICATOR; + gpios = <&gpio5 23 GPIO_ACTIVE_HIGH>; /* GPIO F */ + pinctrl-0 = <&pinctrl_dhcom_f>; + pinctrl-names = "default"; + }; + + led-2 { + color = <LED_COLOR_ID_GREEN>; + default-state = "off"; + function = LED_FUNCTION_INDICATOR; + gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>; /* GPIO H */ + pinctrl-0 = <&pinctrl_dhcom_h>; + pinctrl-names = "default"; + }; + + led-3 { + color = <LED_COLOR_ID_GREEN>; + default-state = "off"; + function = LED_FUNCTION_INDICATOR; + gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; /* GPIO I */ + pinctrl-0 = <&pinctrl_dhcom_i>; + pinctrl-names = "default"; + }; + }; +}; + +/* + * PDK2 carrier board uses SoM with KSZ9131 populated and connected to + * SoM EQoS ethernet RGMII interface. Remove the other SoM PHY DT node. + */ +/delete-node/ ðphy0f; + +/* + * PDK2 carrier board has KSZ9021 PHY populated and connected to SoM FEC + * ethernet RGMII interface. The SoM is not populated with second FEC PHY. + */ +/delete-node/ ðphy1f; + +&fec { /* Second ethernet */ + phy-handle = <ðphypdk>; + + mdio { + ethphypdk: ethernet-phy@7 { /* KSZ 9021 */ + compatible = "ethernet-phy-ieee802.3-c22"; + pinctrl-0 = <&pinctrl_ethphy1>; + pinctrl-names = "default"; + interrupt-parent = <&gpio4>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + max-speed = <100>; + reg = <7>; + reset-assert-us = <1000>; + reset-deassert-us = <1000>; + reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>; + rxc-skew-ps = <3000>; + rxd0-skew-ps = <0>; + rxd1-skew-ps = <0>; + rxd2-skew-ps = <0>; + rxd3-skew-ps = <0>; + rxdv-skew-ps = <0>; + txc-skew-ps = <3000>; + txd0-skew-ps = <0>; + txd1-skew-ps = <0>; + txd2-skew-ps = <0>; + txd3-skew-ps = <0>; + txen-skew-ps = <0>; + }; + }; +}; + +&flexcan1 { + status = "okay"; +}; + +&usb3_1 { + fsl,over-current-active-low; +}; + +&iomuxc { + /* + * GPIO_A,B,C,D are connected to buttons. + * GPIO_E,F,H,I are connected to LEDs. + * GPIO_M is connected to CLKOUT2. + */ + pinctrl-0 = <&pinctrl_hog_base + &pinctrl_dhcom_g &pinctrl_dhcom_j + &pinctrl_dhcom_k &pinctrl_dhcom_l + &pinctrl_dhcom_int>; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi new file mode 100644 index 000000000000..a616eb378002 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi @@ -0,0 +1,1030 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2021-2022 Marek Vasut <marex@denx.de> + */ + +#include "imx8mp.dtsi" + +/ { + model = "DH electronics i.MX8M Plus DHCOM SoM"; + compatible = "dh,imx8mp-dhcom-som", "fsl,imx8mp"; + + aliases { + ethernet0 = &eqos; + ethernet1 = &fec; + rtc0 = &rv3032; + rtc1 = &snvs_rtc; + spi0 = &flexspi; + }; + + memory@40000000 { + device_type = "memory"; + /* Memory size 512 MiB..8 GiB will be filled by U-Boot */ + reg = <0x0 0x40000000 0 0x08000000>; + }; + + reg_eth_vio: regulator-eth-vio { + compatible = "regulator-fixed"; + gpio = <&gpio2 10 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&pinctrl_enet_vio>; + pinctrl-names = "default"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "eth_vio"; + vin-supply = <&buck4>; + }; + + reg_usdhc2_vmmc: regulator-usdhc2-vmmc { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio2 19 0>; /* SD2_RESET */ + off-on-delay-us = <12000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2_vmmc>; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "VDD_3V3_SD"; + startup-delay-us = <100>; + vin-supply = <&buck4>; + }; +}; + +&A53_0 { + cpu-supply = <&buck2>; +}; + +&A53_1 { + cpu-supply = <&buck2>; +}; + +&A53_2 { + cpu-supply = <&buck2>; +}; + +&A53_3 { + cpu-supply = <&buck2>; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; + status = "disabled"; +}; + +&ecspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; + status = "disabled"; +}; + +&eqos { /* First ethernet */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eqos>; + phy-handle = <ðphy0g>; + phy-mode = "rgmii-id"; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + /* Up to one of these two PHYs may be populated. */ + ethphy0f: ethernet-phy@1 { /* SMSC LAN8740Ai */ + compatible = "ethernet-phy-id0007.c110", + "ethernet-phy-ieee802.3-c22"; + interrupt-parent = <&gpio3>; + interrupts = <19 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&pinctrl_ethphy0>; + pinctrl-names = "default"; + reg = <1>; + reset-assert-us = <1000>; + reset-deassert-us = <1000>; + reset-gpios = <&gpio3 20 GPIO_ACTIVE_LOW>; + /* Non-default PHY population option. */ + status = "disabled"; + }; + + ethphy0g: ethernet-phy@5 { /* Micrel KSZ9131RNXI */ + compatible = "ethernet-phy-id0022.1642", + "ethernet-phy-ieee802.3-c22"; + interrupt-parent = <&gpio3>; + interrupts = <19 IRQ_TYPE_LEVEL_LOW>; + micrel,led-mode = <0>; + pinctrl-0 = <&pinctrl_ethphy0>; + pinctrl-names = "default"; + reg = <5>; + reset-assert-us = <1000>; + reset-deassert-us = <1000>; + reset-gpios = <&gpio3 20 GPIO_ACTIVE_LOW>; + /* Default PHY population option. */ + status = "okay"; + }; + }; +}; + +&fec { /* Second ethernet */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + phy-handle = <ðphy1f>; + phy-mode = "rgmii"; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + /* Up to one PHY may be populated. */ + ethphy1f: ethernet-phy@1 { /* SMSC LAN8740Ai */ + compatible = "ethernet-phy-id0007.c110", + "ethernet-phy-ieee802.3-c22"; + interrupt-parent = <&gpio4>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&pinctrl_ethphy1>; + pinctrl-names = "default"; + reg = <1>; + reset-assert-us = <1000>; + reset-deassert-us = <1000>; + reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>; + /* Non-default PHY population option. */ + status = "disabled"; + }; + }; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + status = "disabled"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + status = "disabled"; +}; + +&flexspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi>; + status = "okay"; + + flash@0 { /* W25Q128JWPIM */ + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <80000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; +}; + +&gpio1 { + gpio-line-names = + "DHCOM-G", "", "", "", "", "DHCOM-I", "DHCOM-J", "DHCOM-L", + "DHCOM-B", "DHCOM-A", "", "DHCOM-H", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio2 { + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "", "DHCOM-K", "", "", "", "", + "", "", "", "", "DHCOM-INT", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio3 { + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "SOM-HW0", "", + "", "", "", "", "", "", "SOM-MEM0", "SOM-MEM1", + "SOM-MEM2", "SOM-HW2", "", "", "", "", "", ""; +}; + +&gpio4 { + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "SOM-HW1", "", "", "", "", + "", "", "", "DHCOM-D", "", "", "", ""; +}; + +&gpio5 { + gpio-line-names = + "", "", "DHCOM-C", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "DHCOM-E", "DHCOM-F", + "", "", "", "", "", "", "", ""; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + pmic: pmic@25 { + compatible = "nxp,pca9450c"; + reg = <0x25>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + interrupt-parent = <&gpio1>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + sd-vsel-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; + + /* + * i.MX 8M Plus Data Sheet for Consumer Products + * 3.1.4 Operating ranges + * MIMX8ML8CVNKZAB + */ + regulators { + buck1: BUCK1 { /* VDD_SOC (dual-phase with BUCK3) */ + regulator-compatible = "BUCK1"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1000000>; + regulator-ramp-delay = <3125>; + regulator-always-on; + regulator-boot-on; + }; + + buck2: BUCK2 { /* VDD_ARM */ + regulator-compatible = "BUCK2"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1000000>; + regulator-ramp-delay = <3125>; + regulator-always-on; + regulator-boot-on; + }; + + buck4: BUCK4 { /* VDD_3V3 */ + regulator-compatible = "BUCK4"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + buck5: BUCK5 { /* VDD_1V8 */ + regulator-compatible = "BUCK5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + buck6: BUCK6 { /* NVCC_DRAM_1V1 */ + regulator-compatible = "BUCK6"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo1: LDO1 { /* NVCC_SNVS_1V8 */ + regulator-compatible = "LDO1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo3: LDO3 { /* VDDA_1V8 */ + regulator-compatible = "LDO3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo4: LDO4 { /* PMIC_LDO4 */ + regulator-compatible = "LDO4"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + ldo5: LDO5 { /* NVCC_SD2 */ + regulator-compatible = "LDO5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; + + adc@48 { + compatible = "ti,tla2024"; + reg = <0x48>; + #address-cells = <1>; + #size-cells = <0>; + + channel@0 { /* Voltage over AIN0 and AIN1. */ + reg = <0>; + }; + + channel@1 { /* Voltage over AIN0 and AIN3. */ + reg = <1>; + }; + + channel@2 { /* Voltage over AIN1 and AIN3. */ + reg = <2>; + }; + + channel@3 { /* Voltage over AIN2 and AIN3. */ + reg = <3>; + }; + + channel@4 { /* Voltage over AIN0 and GND. */ + reg = <4>; + }; + + channel@5 { /* Voltage over AIN1 and GND. */ + reg = <5>; + }; + + channel@6 { /* Voltage over AIN2 and GND. */ + reg = <6>; + }; + + channel@7 { /* Voltage over AIN3 and GND. */ + reg = <7>; + }; + }; + + touchscreen@49 { + compatible = "ti,tsc2004"; + reg = <0x49>; + interrupts-extended = <&gpio4 0 IRQ_TYPE_EDGE_FALLING>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_touch>; + vio-supply = <&buck4>; + }; + + eeprom0: eeprom@50 { /* EEPROM with EQoS MAC address */ + compatible = "atmel,24c02"; + pagesize = <16>; + reg = <0x50>; + }; + + rv3032: rtc@51 { + compatible = "microcrystal,rv3032"; + reg = <0x51>; + interrupts-extended = <&gpio5 5 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rtc>; + }; + + eeprom1: eeprom@53 { /* EEPROM with FEC MAC address */ + compatible = "atmel,24c02"; + pagesize = <16>; + reg = <0x53>; + }; +}; + +&i2c4 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c4>; + pinctrl-1 = <&pinctrl_i2c4_gpio>; + scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; +}; + +&i2c5 { /* HDMI EDID bus */ + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c5>; + pinctrl-1 = <&pinctrl_i2c5_gpio>; + scl-gpios = <&gpio5 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; +}; + +&pwm1 { + pinctrl-0 = <&pinctrl_pwm1>; + pinctrl-names = "default"; + status = "disabled"; +}; + +&uart1 { + /* CA53 console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + /* Bluetooth */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + uart-has-rtscts; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + uart-has-rtscts; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&usb3_phy0 { + status = "okay"; +}; + +&usb3_0 { + status = "okay"; +}; + +&usb_dwc3_0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0_vbus>; + dr_mode = "otg"; + status = "okay"; +}; + +&usb3_phy1 { + status = "okay"; +}; + +&usb3_1 { + status = "okay"; +}; + +&usb_dwc3_1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1_vbus>; + dr_mode = "host"; + status = "okay"; +}; + +/* SDIO WiFi */ +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + vmmc-supply = <&buck4>; + bus-width = <4>; + non-removable; + cap-power-off-card; + keep-power-in-suspend; + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + + brcmf: bcrmf@1 { /* muRata 2AE */ + reg = <1>; + compatible = "cypress,cyw4373-fmac", "brcm,bcm4329-fmac"; + /* + * The "host-wake" interrupt output is by default not + * connected to the SoC, but can be connected on to + * SoC pin on the carrier board. + */ + reset-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; + }; +}; + +/* SD slot */ +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_usdhc2_vmmc>; + bus-width = <4>; + status = "okay"; +}; + +/* eMMC */ +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + vmmc-supply = <&buck4>; + vqmmc-supply = <&buck5>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl-0 = <&pinctrl_hog_base + &pinctrl_dhcom_a &pinctrl_dhcom_b &pinctrl_dhcom_c + &pinctrl_dhcom_d &pinctrl_dhcom_e &pinctrl_dhcom_f + &pinctrl_dhcom_g &pinctrl_dhcom_h &pinctrl_dhcom_i + &pinctrl_dhcom_j &pinctrl_dhcom_k &pinctrl_dhcom_l + /* GPIO_M is connected to CLKOUT2 */ + &pinctrl_dhcom_int>; + pinctrl-names = "default"; + + pinctrl_dhcom_a: dhcom-a-grp { + fsl,pins = < + /* ENET_QOS_EVENT0-OUT */ + MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 0x2 + >; + }; + + pinctrl_dhcom_b: dhcom-b-grp { + fsl,pins = < + /* ENET_QOS_EVENT0-IN */ + MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08 0x2 + >; + }; + + pinctrl_dhcom_c: dhcom-c-grp { + fsl,pins = < + /* GPIO_C */ + MX8MP_IOMUXC_SAI3_MCLK__GPIO5_IO02 0x2 + >; + }; + + pinctrl_dhcom_d: dhcom-d-grp { + fsl,pins = < + /* GPIO_D */ + MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x2 + >; + }; + + pinctrl_dhcom_e: dhcom-e-grp { + fsl,pins = < + /* GPIO_E */ + MX8MP_IOMUXC_UART1_RXD__GPIO5_IO22 0x2 + >; + }; + + pinctrl_dhcom_f: dhcom-f-grp { + fsl,pins = < + /* GPIO_F */ + MX8MP_IOMUXC_UART1_TXD__GPIO5_IO23 0x2 + >; + }; + + pinctrl_dhcom_g: dhcom-g-grp { + fsl,pins = < + /* GPIO_G */ + MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x2 + >; + }; + + pinctrl_dhcom_h: dhcom-h-grp { + fsl,pins = < + /* GPIO_H */ + MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11 0x2 + >; + }; + + pinctrl_dhcom_i: dhcom-i-grp { + fsl,pins = < + /* CSI1_SYNC */ + MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x2 + >; + }; + + pinctrl_dhcom_j: dhcom-j-grp { + fsl,pins = < + /* CSIx_#RST */ + MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x2 + >; + }; + + pinctrl_dhcom_k: dhcom-k-grp { + fsl,pins = < + /* CSIx_PWDN */ + MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x2 + >; + }; + + pinctrl_dhcom_l: dhcom-l-grp { + fsl,pins = < + /* CSI2_SYNC */ + MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x2 + >; + }; + + pinctrl_dhcom_int: dhcom-int-grp { + fsl,pins = < + /* INT_HIGHEST_PRIO */ + MX8MP_IOMUXC_SD2_WP__GPIO2_IO20 0x2 + >; + }; + + pinctrl_hog_base: dhcom-hog-base-grp { + fsl,pins = < + /* GPIOs for memory coding */ + MX8MP_IOMUXC_SAI5_RXD1__GPIO3_IO22 0x40000080 + MX8MP_IOMUXC_SAI5_RXD2__GPIO3_IO23 0x40000080 + MX8MP_IOMUXC_SAI5_RXD3__GPIO3_IO24 0x40000080 + /* GPIOs for hardware coding */ + MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14 0x40000080 + MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x40000080 + MX8MP_IOMUXC_SAI5_MCLK__GPIO3_IO25 0x40000080 + >; + }; + + pinctrl_ecspi1: dhcom-ecspi1-grp { + fsl,pins = < + MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK 0x44 + MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI 0x44 + MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO 0x44 + MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x40 + >; + }; + + pinctrl_ecspi2: dhcom-ecspi2-grp { + fsl,pins = < + MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x44 + MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x44 + MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x44 + MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x40 + >; + }; + + pinctrl_eqos: dhcom-eqos-grp { /* RGMII */ + fsl,pins = < + MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3 + MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3 + MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f + MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f + MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f + MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f + MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f + MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f + MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91 + MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91 + MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91 + MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91 + MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91 + MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91 + >; + }; + + pinctrl_enet_vio: dhcom-enet-vio-grp { + fsl,pins = < + MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x22 + >; + }; + + pinctrl_ethphy0: dhcom-ethphy0-grp { + fsl,pins = < + /* ENET1_#RST Reset */ + MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x22 + /* ENET1_#INT Interrupt */ + MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19 0x22 + >; + }; + + pinctrl_ethphy1: dhcom-ethphy1-grp { + fsl,pins = < + /* ENET1_#RST Reset */ + MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x11 + /* ENET1_#INT Interrupt */ + MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x11 + >; + }; + + pinctrl_fec: dhcom-fec-grp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_MCLK__ENET1_TX_CLK 0x1f + MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3 + MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3 + MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91 + MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91 + MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91 + MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91 + MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91 + MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91 + MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f + MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f + MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f + MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f + MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f + MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f + MX8MP_IOMUXC_SAI1_TXD6__ENET1_RX_ER 0x1f + >; + }; + + pinctrl_flexcan1: dhcom-flexcan1-grp { + fsl,pins = < + MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154 + MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154 + >; + }; + + pinctrl_flexcan2: dhcom-flexcan2-grp { + fsl,pins = < + MX8MP_IOMUXC_UART3_RXD__CAN2_TX 0x154 + MX8MP_IOMUXC_UART3_TXD__CAN2_RX 0x154 + >; + }; + + pinctrl_flexspi: dhcom-flexspi-grp { + fsl,pins = < + MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2 + MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82 + MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82 + MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82 + MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82 + MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82 + >; + }; + + pinctrl_hdmi: dhcom-hdmi-grp { + fsl,pins = < + MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x154 + MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x154 + >; + }; + + pinctrl_i2c3: dhcom-i2c3-grp { + fsl,pins = < + MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x40000084 + MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x40000084 + >; + }; + + pinctrl_i2c3_gpio: dhcom-i2c3-gpio-grp { + fsl,pins = < + MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x84 + MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x84 + >; + }; + + pinctrl_i2c4: dhcom-i2c4-grp { + fsl,pins = < + MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x40000084 + MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x40000084 + >; + }; + + pinctrl_i2c4_gpio: dhcom-i2c4-gpio-grp { + fsl,pins = < + MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x84 + MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x84 + >; + }; + + pinctrl_i2c5: dhcom-i2c5-grp { + fsl,pins = < + MX8MP_IOMUXC_HDMI_DDC_SCL__I2C5_SCL 0x40000084 + MX8MP_IOMUXC_HDMI_DDC_SDA__I2C5_SDA 0x40000084 + >; + }; + + pinctrl_i2c5_gpio: dhcom-i2c5-gpio-grp { + fsl,pins = < + MX8MP_IOMUXC_HDMI_DDC_SCL__GPIO3_IO26 0x84 + MX8MP_IOMUXC_HDMI_DDC_SDA__GPIO3_IO27 0x84 + >; + }; + + pinctrl_pmic: dhcom-pmic-grp { + fsl,pins = < + /* PMIC_nINT */ + MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x40000090 + >; + }; + + pinctrl_pwm1: dhcom-pwm1-grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x6 + >; + }; + + pinctrl_rtc: dhcom-rtc-grp { + fsl,pins = < + /* RTC_#INT Interrupt */ + MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x40000080 + >; + }; + + pinctrl_touch: dhcom-touch-grp { + fsl,pins = < + /* #TOUCH_INT */ + MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00 0x40000080 + >; + }; + + pinctrl_uart1: dhcom-uart1-grp { + fsl,pins = < + /* Console UART */ + MX8MP_IOMUXC_SAI2_RXC__UART1_DCE_RX 0x49 + MX8MP_IOMUXC_SAI2_RXFS__UART1_DCE_TX 0x49 + MX8MP_IOMUXC_SAI2_RXD0__UART1_DCE_RTS 0x49 + MX8MP_IOMUXC_SAI2_TXFS__UART1_DCE_CTS 0x49 + >; + }; + + pinctrl_uart2: dhcom-uart2-grp { + fsl,pins = < + /* Bluetooth UART */ + MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x49 + MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x49 + MX8MP_IOMUXC_SD1_DATA4__UART2_DCE_RTS 0x49 + MX8MP_IOMUXC_SD1_DATA5__UART2_DCE_CTS 0x49 + >; + }; + + pinctrl_uart3: dhcom-uart3-grp { + fsl,pins = < + MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX 0x49 + MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX 0x49 + MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS 0x49 + MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS 0x49 + >; + }; + + pinctrl_uart4: dhcom-uart4-grp { + fsl,pins = < + MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x49 + MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x49 + >; + }; + + pinctrl_usb0_vbus: dhcom-usb0-grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO10__USB1_OTG_ID 0x0 + >; + }; + + pinctrl_usb1_vbus: dhcom-usb1-grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR 0x6 + MX8MP_IOMUXC_GPIO1_IO15__USB2_OTG_OC 0x80 + >; + }; + + pinctrl_usdhc1: dhcom-usdhc1-grp { + fsl,pins = < + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0 + /* BT_REG_EN */ + MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x144 + /* WL_REG_EN */ + MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x144 + >; + }; + + pinctrl_usdhc1_100mhz: dhcom-usdhc1-100mhz-grp { + fsl,pins = < + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4 + /* BT_REG_EN */ + MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x144 + /* WL_REG_EN */ + MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x144 + >; + }; + + pinctrl_usdhc1_200mhz: dhcom-usdhc1-200mhz-grp { + fsl,pins = < + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6 + /* BT_REG_EN */ + MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x144 + /* WL_REG_EN */ + MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x144 + >; + }; + + pinctrl_usdhc2: dhcom-usdhc2-grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_100mhz: dhcom-usdhc2-100mhz-grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_200mhz: dhcom-usdhc2-200mhz-grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_vmmc: dhcom-usdhc2-vmmc-grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x20 + >; + }; + + pinctrl_usdhc2_gpio: dhcom-usdhc2-gpio-grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x40000080 + >; + }; + + pinctrl_usdhc3: dhcom-usdhc3-grp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 + MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B 0x141 + >; + }; + + pinctrl_usdhc3_100mhz: dhcom-usdhc3-100mhz-grp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 + MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B 0x141 + >; + }; + + pinctrl_usdhc3_200mhz: dhcom-usdhc3-200mhz-grp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 + MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B 0x141 + >; + }; + + pinctrl_wdog: dhcom-wdog-grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6 + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts index 9a4de739e6a2..f6b017ab5f53 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts @@ -67,18 +67,20 @@ }; }; -&flexcan1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; - xceiver-supply = <®_can1_stby>; - status = "okay"; +&A53_0 { + cpu-supply = <®_arm>; }; -&flexcan2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2>; - xceiver-supply = <®_can2_stby>; - status = "disabled";/* can2 pin conflict with pdm */ +&A53_1 { + cpu-supply = <®_arm>; +}; + +&A53_2 { + cpu-supply = <®_arm>; +}; + +&A53_3 { + cpu-supply = <®_arm>; }; &eqos { @@ -197,6 +199,20 @@ }; }; +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_can1_stby>; + status = "okay"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can2_stby>; + status = "disabled";/* can2 pin conflict with pdm */ +}; + &i2c1 { clock-frequency = <400000>; pinctrl-names = "default"; @@ -221,7 +237,7 @@ regulator-ramp-delay = <3125>; }; - BUCK2 { + reg_arm: BUCK2 { regulator-name = "BUCK2"; regulator-min-microvolt = <720000>; regulator-max-microvolt = <1025000>; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts new file mode 100644 index 000000000000..d8ca52976170 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts @@ -0,0 +1,702 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2021-2022 TQ-Systems GmbH + * Author: Alexander Stein <alexander.stein@tq-group.com> + */ + +/dts-v1/; + +#include <dt-bindings/leds/common.h> +#include <dt-bindings/net/ti-dp83867.h> +#include <dt-bindings/pwm/pwm.h> +#include "imx8mp-tqma8mpql.dtsi" + +/ { + model = "TQ-Systems i.MX8MPlus TQMa8MPxL on MBa8MPxL"; + compatible = "tq,imx8mp-tqma8mpql-mba8mpxl", "tq,imx8mp-tqma8mpql", "fsl,imx8mp"; + + chosen { + stdout-path = &uart4; + }; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc 0>, <&adc 1>; + }; + + aliases { + mmc0 = &usdhc3; + mmc1 = &usdhc2; + mmc2 = &usdhc1; + rtc0 = &pcf85063; + rtc1 = &snvs_rtc; + spi0 = &flexspi; + spi1 = &ecspi1; + spi2 = &ecspi2; + spi3 = &ecspi3; + }; + + backlight_lvds: backlight { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_backlight>; + pwms = <&pwm2 0 5000000 0>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <7>; + power-supply = <®_vcc_12v0>; + enable-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; + status = "disabled"; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpiobutton>; + autorepeat; + + switch-1 { + label = "S12"; + linux,code = <BTN_0>; + gpios = <&gpio5 26 GPIO_ACTIVE_LOW>; + }; + + switch-2 { + label = "S13"; + linux,code = <BTN_1>; + gpios = <&gpio5 27 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpioled>; + + led-0 { + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_STATUS; + function-enumerator = <0>; + gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + + led-1 { + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_HEARTBEAT; + gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + + led-2 { + color = <LED_COLOR_ID_YELLOW>; + function = LED_FUNCTION_STATUS; + function-enumerator = <1>; + gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>; + }; + }; + + display: display { + /* + * Display is not fixed, so compatible has to be added from + * DT overlay + */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lvdsdisplay>; + power-supply = <®_vcc_3v3>; + enable-gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>; + backlight = <&backlight_lvds>; + status = "disabled"; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <100>; + off-on-delay-us = <12000>; + }; + + reg_vcc_12v0: regulator-12v0 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg12v0>; + regulator-name = "VCC_12V0"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + gpio = <&gpio2 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_vcc_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "VCC_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ocram: ocram@900000 { + no-map; + reg = <0 0x900000 0 0x70000>; + }; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x38000000>; + alloc-ranges = <0 0x40000000 0 0xB0000000>; + linux,cma-default; + }; + }; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&ecspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&ecspi3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi3>; + cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>; + status = "okay"; + + adc: adc@0 { + reg = <0>; + compatible = "microchip,mcp3202"; + /* 100 ksps * 18 */ + spi-max-frequency = <1800000>; + vref-supply = <®_vcc_3v3>; + #io-channel-cells = <1>; + }; +}; + +&eqos { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eqos>, <&pinctrl_eqos_phy>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy3>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + ethphy3: ethernet-phy@3 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <3>; + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; + ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; + ti,dp83867-rxctrl-strap-quirk; + ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; + reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>; + reset-assert-us = <500000>; + reset-deassert-us = <50000>; + enet-phy-lane-no-swap; + interrupt-parent = <&gpio4>; + interrupts = <3 IRQ_TYPE_EDGE_FALLING>; + }; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>, <&pinctrl_fec_phy>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; + ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; + ti,dp83867-rxctrl-strap-quirk; + ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; + reset-gpios = <&gpio4 0 GPIO_ACTIVE_LOW>; + reset-assert-us = <500000>; + reset-deassert-us = <50000>; + enet-phy-lane-no-swap; + interrupt-parent = <&gpio4>; + interrupts = <1 IRQ_TYPE_EDGE_FALLING>; + }; + }; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_vcc_3v3>; + status = "okay"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_vcc_3v3>; + status = "okay"; +}; + +&gpio1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio1>; + + gpio-line-names = "GPO1", "GPO0", "", "GPO3", + "", "", "GPO2", "GPI0", + "PMIC_IRQ", "GPI1", "OTG_ID", "USB_HUB_RST#", + "OTG_PWR", "", "GPI2", "GPI3", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", ""; +}; + +&gpio2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hoggpio2>; + + gpio-line-names = "", "", "", "", + "", "", "VCC12V_EN", "PERST#", + "", "", "CLKREQ#", "PEWAKE#", + "USDHC2_CD", "", "", "", + "", "", "", "V_SD3V3_EN", + "", "", "", "", + "", "", "", "", + "", "", "", ""; + + perst-hog { + gpio-hog; + gpios = <7 0>; + output-high; + line-name = "PERST#"; + }; + + clkreq-hog { + gpio-hog; + gpios = <10 0>; + input; + line-name = "CLKREQ#"; + }; + + pewake-hog { + gpio-hog; + gpios = <11 0>; + input; + line-name = "PEWAKE#"; + }; +}; + +&gpio3 { + gpio-line-names = "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "LVDS0_RESET#", "", + "", "", "", "LVDS0_BLT_EN", + "LVDS0_PWR_EN", "", "", "", + "", "", "", "", + "", "", "", ""; +}; + +&gpio4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio4>; + + gpio-line-names = "ENET0_RST#", "ENET0_INT#", "ENET1_RST#", "ENET1_INT#", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "DP_IRQ", "DSI_EN", + "HDMI_OC#", "TEMP_EVENT#", "PCIE_CLK_OE#", "", + "", "", "", "FAN_PWR", + "RTC_EVENT#", "CODEC_RST#", "", ""; +}; + +&gpio5 { + gpio-line-names = "", "", "", "LED2", + "LED1", "LED0", "CSI0_RESET#", "CSI0_SYNC", + "CSI0_TRIGGER", "CSI0_ENABLE", "", "", + "", "ECSPI2_SS0", "", "", + "", "", "", "", + "", "", "", "", + "", "ECSPI3_SS0", "SWITCH_A", "SWITCH_B", + "", "", "", ""; +}; + +&i2c2 { + clock-frequency = <384000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + /* NXP SE97BTP with temperature sensor + eeprom */ + se97_1c: temperature-sensor-eeprom@1c { + compatible = "nxp,se97", "jedec,jc-42.4-temp"; + reg = <0x1c>; + }; + + at24c02_54: eeprom@54 { + compatible = "nxp,se97b", "atmel,24c02"; + reg = <0x54>; + pagesize = <16>; + vcc-supply = <®_vcc_3v3>; + }; +}; + +&i2c4 { + clock-frequency = <384000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c4>; + pinctrl-1 = <&pinctrl_i2c4_gpio>; + scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; +}; + +&i2c6 { + clock-frequency = <384000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c6>; + pinctrl-1 = <&pinctrl_i2c6_gpio>; + scl-gpios = <&gpio2 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio2 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; +}; + +&pcf85063 { + /* RTC_EVENT# is connected on MBa8MPxL */ + interrupt-parent = <&gpio4>; + interrupts = <28 IRQ_TYPE_EDGE_FALLING>; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + status = "disabled"; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; + status = "okay"; +}; + +&snvs_pwrkey { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + assigned-clocks = <&clk IMX8MP_CLK_UART1>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + assigned-clocks = <&clk IMX8MP_CLK_UART2>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + assigned-clocks = <&clk IMX8MP_CLK_UART3>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; + status = "okay"; +}; + +&uart4 { + /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_usdhc2_vmmc>; + no-mmc; + no-sdio; + disable-wp; + bus-width = <4>; + status = "okay"; +}; + +&iomuxc { + pinctrl_backlight: backlightgrp { + fsl,pins = <MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19 0x14>; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = <MX8MP_IOMUXC_SAI5_RXD1__CAN1_TX 0x150>, + <MX8MP_IOMUXC_SAI5_RXD2__CAN1_RX 0x150>; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = <MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x150>, + <MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x150>; + }; + + /* only on X57, primary used as CSI0 control signals */ + pinctrl_ecspi1: ecspi1grp { + fsl,pins = <MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO 0x1c0>, + <MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI 0x1c0>, + <MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK 0x1c0>, + <MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x1c0>; + }; + + /* on X63 and optionally on X57, can also be used as CSI1 control signals */ + pinctrl_ecspi2: ecspi2grp { + fsl,pins = <MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x1c0>, + <MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x1c0>, + <MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x1c0>, + <MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x1c0>; + }; + + pinctrl_ecspi3: ecspi3grp { + fsl,pins = <MX8MP_IOMUXC_UART1_TXD__ECSPI3_MOSI 0x1c0>, + <MX8MP_IOMUXC_UART1_RXD__ECSPI3_SCLK 0x1c0>, + <MX8MP_IOMUXC_UART2_RXD__ECSPI3_MISO 0x1c0>, + <MX8MP_IOMUXC_UART2_TXD__GPIO5_IO25 0x1c0>; + }; + + pinctrl_eqos: eqosgrp { + fsl,pins = <MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x40000044>, + <MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x40000044>, + <MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90>, + <MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90>, + <MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90>, + <MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90>, + <MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90>, + <MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90>, + <MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x12>, + <MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x12>, + <MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x12>, + <MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x12>, + <MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x12>, + <MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x14>; + }; + + pinctrl_eqos_event: eqosevtgrp { + fsl,pins = <MX8MP_IOMUXC_SAI2_RXD0__ENET_QOS_1588_EVENT2_OUT 0x100>, + <MX8MP_IOMUXC_SAI2_TXD0__ENET_QOS_1588_EVENT2_IN 0x1c0>; + }; + + pinctrl_eqos_phy: eqosphygrp { + fsl,pins = <MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x100>, + <MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x1c0>; + }; + + pinctrl_fec: fecgrp { + fsl,pins = <MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x40000044>, + <MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x40000044>, + <MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90>, + <MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90>, + <MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90>, + <MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90>, + <MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90>, + <MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90>, + <MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x12>, + <MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x12>, + <MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x12>, + <MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x12>, + <MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x12>, + <MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x14>; + }; + + pinctrl_fec_event: fecevtgrp { + fsl,pins = <MX8MP_IOMUXC_SAI1_RXFS__ENET1_1588_EVENT0_IN 0x100>, + <MX8MP_IOMUXC_SAI1_RXC__ENET1_1588_EVENT0_OUT 0x1c0>; + }; + + pinctrl_fec_phy: fecphygrp { + fsl,pins = <MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00 0x100>, + <MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x1c0>; + }; + + pinctrl_fec_phyalt: fecphyaltgrp { + fsl,pins = <MX8MP_IOMUXC_SAI2_TXFS__GPIO4_IO24 0x180>, + <MX8MP_IOMUXC_SAI2_TXC__GPIO4_IO25 0x180>; + }; + + pinctrl_gpiobutton: gpiobuttongrp { + fsl,pins = <MX8MP_IOMUXC_UART3_RXD__GPIO5_IO26 0x10>, + <MX8MP_IOMUXC_UART3_TXD__GPIO5_IO27 0x10>; + }; + + pinctrl_gpioled: gpioledgrp { + fsl,pins = <MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x14>, + <MX8MP_IOMUXC_SPDIF_RX__GPIO5_IO04 0x14>, + <MX8MP_IOMUXC_SPDIF_TX__GPIO5_IO03 0x14>; + }; + + pinctrl_gpio1: gpio1grp { + fsl,pins = <MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x10>, + <MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x10>, + <MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x10>, + <MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x10>, + <MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x80>, + <MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 0x80>, + <MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x80>, + <MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0x80>; + }; + + pinctrl_gpio4: gpio4grp { + fsl,pins = <MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x180>, + <MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x180>; + }; + + pinctrl_hdmi: hdmigrp { + fsl,pins = <MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x400001c2>, + <MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x400001c2>, + <MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x40000010>, + <MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x40000010>; + }; + + pinctrl_hoggpio2: hoggpio2grp { + fsl,pins = <MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07 0x140>, + <MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x140>, + <MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x140>; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = <MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001e2>, + <MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001e2>; + }; + + pinctrl_i2c2_gpio: i2c2-gpiogrp { + fsl,pins = <MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x400001e2>, + <MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x400001e2>; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = <MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001e2>, + <MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001e2>; + }; + + pinctrl_i2c4_gpio: i2c4-gpiogrp { + fsl,pins = <MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x400001e2>, + <MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x400001e2>; + }; + + pinctrl_i2c6: i2c6grp { + fsl,pins = <MX8MP_IOMUXC_SD1_DATA0__I2C6_SCL 0x400001e2>, + <MX8MP_IOMUXC_SD1_DATA1__I2C6_SDA 0x400001e2>; + }; + + pinctrl_i2c6_gpio: i2c6-gpiogrp { + fsl,pins = <MX8MP_IOMUXC_SD1_DATA0__GPIO2_IO02 0x400001e2>, + <MX8MP_IOMUXC_SD1_DATA1__GPIO2_IO03 0x400001e2>; + }; + + pinctrl_lvdsdisplay: lvdsdisplaygrp { + fsl,pins = <MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x10>; /* Power enable */ + }; + + /* LVDS Backlight */ + pinctrl_pwm2: pwm2grp { + fsl,pins = <MX8MP_IOMUXC_SAI5_RXD0__PWM2_OUT 0x14>; + }; + + /* FAN */ + pinctrl_pwm3: pwm3grp { + fsl,pins = <MX8MP_IOMUXC_I2C3_SDA__PWM3_OUT 0x14>; + }; + + pinctrl_reg12v0: reg12v0grp { + fsl,pins = <MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x140>; /* VCC12V enable */ + }; + + /* X61 */ + pinctrl_uart1: uart1grp { + fsl,pins = <MX8MP_IOMUXC_SD1_CLK__UART1_DCE_TX 0x140>, + <MX8MP_IOMUXC_SD1_CMD__UART1_DCE_RX 0x140>; + }; + + /* X61 */ + pinctrl_uart2: uart2grp { + fsl,pins = <MX8MP_IOMUXC_SD1_DATA2__UART2_DCE_TX 0x140>, + <MX8MP_IOMUXC_SD1_DATA3__UART2_DCE_RX 0x140>; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = <MX8MP_IOMUXC_SD1_DATA6__UART3_DCE_TX 0x140>, + <MX8MP_IOMUXC_SD1_DATA7__UART3_DCE_RX 0x140>; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = <MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x140>, + <MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x140>; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x192>, + <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d2>, + <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d2>, + <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d2>, + <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d2>, + <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d2>, + <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0>; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194>, + <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4>, + <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4>, + <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4>, + <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4>, + <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4>, + <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0>; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194>, + <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4>, + <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4>, + <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4>, + <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4>, + <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4>, + <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0>; + }; + + pinctrl_usdhc2_gpio: usdhc2-gpiogrp { + fsl,pins = <MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c0>; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql.dtsi new file mode 100644 index 000000000000..7bd680a926ce --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql.dtsi @@ -0,0 +1,284 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2021-2022 TQ-Systems GmbH + * Author: Alexander Stein <alexander.stein@tq-group.com> + */ + +#include "imx8mp.dtsi" + +/ { + model = "TQ-Systems i.MX8MPlus TQMa8MPxL"; + compatible = "tq,imx8mp-tqma8mpql", "fsl,imx8mp"; + + memory@40000000 { + device_type = "memory"; + reg = <0x0 0x40000000 0 0x80000000>; + }; + + /* identical to buck4_reg, but should never change */ + reg_vcc3v3: regulator-vcc3v3 { + compatible = "regulator-fixed"; + regulator-name = "VCC3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + /* e-MMC IO, needed for HS modes */ + reg_vcc1v8: regulator-vcc1v8 { + compatible = "regulator-fixed"; + regulator-name = "VCC1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; +}; + +&A53_0 { + cpu-supply = <&buck2_reg>; +}; + +&flexspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; + + flash0: flash@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <80000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + }; +}; + +&i2c1 { + clock-frequency = <384000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + /* NXP SE97BTP with temperature sensor + eeprom */ + se97: temperature-sensor-eeprom@1b { + compatible = "nxp,se97", "jedec,jc-42.4-temp"; + reg = <0x1b>; + }; + + pmic: pmic@25 { + reg = <0x25>; + compatible = "nxp,pca9450c"; + + /* PMIC PCA9450 PMIC_nINT GPIO1_IO08 */ + pinctrl-0 = <&pinctrl_pmic>; + pinctrl-names = "default"; + interrupt-parent = <&gpio1>; + interrupts = <8 IRQ_TYPE_LEVEL_LOW>; + + regulators { + /* V_0V85_SOC: 0.85 .. 0.95 */ + buck1_reg: BUCK1 { + regulator-name = "BUCK1"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <950000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + /* VDD_ARM */ + buck2_reg: BUCK2 { + regulator-name = "BUCK2"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1000000>; + regulator-boot-on; + regulator-always-on; + nxp,dvs-run-voltage = <950000>; + nxp,dvs-standby-voltage = <850000>; + regulator-ramp-delay = <3125>; + }; + + /* VCC3V3 -> VMMC, ... must not be changed */ + buck4_reg: BUCK4 { + regulator-name = "BUCK4"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + /* V_1V8 -> VQMMC, SPI-NOR, ... must not be changed */ + buck5_reg: BUCK5 { + regulator-name = "BUCK5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + /* V_1V1 -> RAM, ... must not be changed */ + buck6_reg: BUCK6 { + regulator-name = "BUCK6"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-boot-on; + regulator-always-on; + }; + + /* V_1V8_SNVS */ + ldo1_reg: LDO1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + /* V_1V8_ANA */ + ldo3_reg: LDO3 { + regulator-name = "LDO3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + /* unused */ + ldo4_reg: LDO4 { + regulator-name = "LDO4"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + }; + + /* VCC SD IO - switched using SD2 VSELECT */ + ldo5_reg: LDO5 { + regulator-name = "LDO5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; + + pcf85063: rtc@51 { + compatible = "nxp,pcf85063a"; + reg = <0x51>; + }; + + at24c02: eeprom@53 { + compatible = "nxp,se97b", "atmel,24c02"; + read-only; + reg = <0x53>; + pagesize = <16>; + vcc-supply = <®_vcc3v3>; + }; + + m24c64: eeprom@57 { + compatible = "atmel,24c64"; + reg = <0x57>; + pagesize = <32>; + vcc-supply = <®_vcc3v3>; + }; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + bus-width = <8>; + non-removable; + no-sd; + no-sdio; + vmmc-supply = <®_vcc3v3>; + vqmmc-supply = <®_vcc1v8>; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl_flexspi0: flexspi0grp { + fsl,pins = <MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x142>, + <MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82>, + <MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82>, + <MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82>, + <MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82>, + <MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82>; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = <MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001e2>, + <MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001e2>; + }; + + pinctrl_i2c1_gpio: i2c1-gpiogrp { + fsl,pins = <MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x400001e2>, + <MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x400001e2>; + }; + + pinctrl_pmic: pmicirqgrp { + fsl,pins = <MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08 0x1c0>; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = <MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x10>; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194>, + <MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4>, + <MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4>, + <MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4>, + <MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4>, + <MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4>, + <MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4>, + <MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4>, + <MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4>, + <MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4>, + <MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x84>, + <MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B 0x84>; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194>, + <MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4>, + <MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4>, + <MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4>, + <MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4>, + <MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4>, + <MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4>, + <MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4>, + <MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4>, + <MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4>, + <MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x84>, + <MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B 0x84>; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194>, + <MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4>, + <MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4>, + <MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4>, + <MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4>, + <MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4>, + <MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4>, + <MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4>, + <MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4>, + <MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4>, + <MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x84>, + <MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B 0x84>; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = <MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x1c4>; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi index fb17e329cd37..c5987bdbb383 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi @@ -49,7 +49,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_keys>; - wakeup { + button-wakeup { debounce-interval = <10>; /* Verdin CTRL_WAKE1_MICO# (SODIMM 252) */ gpios = <&gpio4 0 GPIO_ACTIVE_LOW>; @@ -146,6 +146,14 @@ }; }; +&cpu_alert0 { + temperature = <95000>; +}; + +&cpu_crit0 { + temperature = <105000>; +}; + /* Verdin SPI_1 */ &ecspi1 { #address-cells = <1>; diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index 410d0d5e6f1e..fe178b7d063c 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -195,7 +195,7 @@ clk_ext4: clock-ext4 { compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency= <133000000>; + clock-frequency = <133000000>; clock-output-names = "clk_ext4"; }; @@ -293,7 +293,7 @@ arm,no-tick-in-suspend; }; - soc@0 { + soc: soc@0 { compatible = "fsl,imx8mp-soc", "simple-bus"; #address-cells = <1>; #size-cells = <1>; @@ -791,6 +791,7 @@ compatible = "fsl,sec-v4.0-job-ring"; reg = <0x1000 0x1000>; interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; }; sec_jr1: jr@2000 { @@ -903,7 +904,7 @@ <&clk IMX8MP_CLK_USDHC1_ROOT>; clock-names = "ipg", "ahb", "per"; fsl,tuning-start-tap = <20>; - fsl,tuning-step= <2>; + fsl,tuning-step = <2>; bus-width = <4>; status = "disabled"; }; @@ -917,7 +918,7 @@ <&clk IMX8MP_CLK_USDHC2_ROOT>; clock-names = "ipg", "ahb", "per"; fsl,tuning-start-tap = <20>; - fsl,tuning-step= <2>; + fsl,tuning-step = <2>; bus-width = <4>; status = "disabled"; }; @@ -931,7 +932,7 @@ <&clk IMX8MP_CLK_USDHC3_ROOT>; clock-names = "ipg", "ahb", "per"; fsl,tuning-start-tap = <20>; - fsl,tuning-step= <2>; + fsl,tuning-step = <2>; bus-width = <4>; status = "disabled"; }; @@ -1018,6 +1019,26 @@ }; }; + noc: interconnect@32700000 { + compatible = "fsl,imx8mp-noc", "fsl,imx8m-noc"; + reg = <0x32700000 0x100000>; + clocks = <&clk IMX8MP_CLK_NOC>; + #interconnect-cells = <1>; + operating-points-v2 = <&noc_opp_table>; + + noc_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-200M { + opp-hz = /bits/ 64 <200000000>; + }; + + opp-1000M { + opp-hz = /bits/ 64 <1000000000>; + }; + }; + }; + aips4: bus@32c00000 { compatible = "fsl,aips-bus", "simple-bus"; reg = <0x32c00000 0x400000>; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts index 99fed35168eb..82387b9cb800 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts @@ -71,12 +71,36 @@ linux,autosuspend-period = <125>; }; + audio_codec_bt_sco: audio-codec-bt-sco { + compatible = "linux,bt-sco"; + #sound-dai-cells = <1>; + }; + wm8524: audio-codec { #sound-dai-cells = <0>; compatible = "wlf,wm8524"; wlf,mute-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; }; + sound-bt-sco { + compatible = "simple-audio-card"; + simple-audio-card,name = "bt-sco-audio"; + simple-audio-card,format = "dsp_a"; + simple-audio-card,bitclock-inversion; + simple-audio-card,frame-master = <&btcpu>; + simple-audio-card,bitclock-master = <&btcpu>; + + btcpu: simple-audio-card,cpu { + sound-dai = <&sai3>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <16>; + }; + + simple-audio-card,codec { + sound-dai = <&audio_codec_bt_sco 1>; + }; + }; + sound-wm8524 { compatible = "simple-audio-card"; simple-audio-card,name = "wm8524-audio"; @@ -386,6 +410,16 @@ status = "okay"; }; +&sai3 { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3>; + assigned-clocks = <&clk IMX8MQ_CLK_SAI3>; + assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; + assigned-clock-rates = <24576000>; + status = "okay"; +}; + &snvs_pwrkey { status = "okay"; }; @@ -548,6 +582,15 @@ >; }; + pinctrl_sai3: sai3grp { + fsl,pins = < + MX8MQ_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 + MX8MQ_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6 + MX8MQ_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6 + MX8MQ_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6 + >; + }; + pinctrl_spdif1: spdif1grp { fsl,pins = < MX8MQ_IOMUXC_SPDIF_TX_SPDIF1_OUT 0xd6 diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts b/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts index b86f188a440d..6445c6b90b5b 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts @@ -36,21 +36,21 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_keys>; - btn1 { + button-1 { label = "VOL_UP"; gpios = <&gpio4 21 GPIO_ACTIVE_LOW>; wakeup-source; linux,code = <KEY_VOLUMEUP>; }; - btn2 { + button-2 { label = "VOL_DOWN"; gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; wakeup-source; linux,code = <KEY_VOLUMEDOWN>; }; - wwan-wake { + button-3 { label = "WWAN_WAKE"; gpios = <&gpio3 8 GPIO_ACTIVE_LOW>; interrupt-parent = <&gpio3>; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi index 587e55aaa57b..9eec8a7eecfc 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi @@ -37,7 +37,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_keys>; - vol-down { + key-vol-down { label = "VOL_DOWN"; gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; linux,code = <KEY_VOLUMEDOWN>; @@ -45,7 +45,7 @@ wakeup-source; }; - vol-up { + key-vol-up { label = "VOL_UP"; gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; linux,code = <KEY_VOLUMEUP>; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-nitrogen.dts b/arch/arm64/boot/dts/freescale/imx8mq-nitrogen.dts index f70fb32b96b0..9dda2a1554c3 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-nitrogen.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-nitrogen.dts @@ -26,7 +26,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_keys>; - power { + button-power { label = "Power Button"; gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; linux,code = <KEY_POWER>; @@ -152,7 +152,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_reg_arm_dram>; reg = <0x60>; - regulator-min-microvolt = <900000>; + regulator-min-microvolt = <900000>; regulator-max-microvolt = <1000000>; regulator-always-on; vsel-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>; @@ -186,7 +186,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_reg_soc_gpu_vpu>; reg = <0x60>; - regulator-min-microvolt = <900000>; + regulator-min-microvolt = <900000>; regulator-max-microvolt = <1000000>; regulator-always-on; vsel-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi index 2222ef7b3eab..4e05120c62d4 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi @@ -443,7 +443,7 @@ status = "okay"; usbhub: usbhub@2c { - compatible ="microchip,usb2513b"; + compatible = "microchip,usb2513b"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usbhub>; reg = <0x2c>; diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index 49eadb081b19..e9f0cdd10ab6 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -94,7 +94,7 @@ clk_ext4: clock-ext4 { compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency= <133000000>; + clock-frequency = <133000000>; clock-output-names = "clk_ext4"; }; @@ -320,7 +320,7 @@ arm,no-tick-in-suspend; }; - soc@0 { + soc: soc@0 { compatible = "fsl,imx8mq-soc", "simple-bus"; #address-cells = <1>; #size-cells = <1>; @@ -329,7 +329,7 @@ nvmem-cells = <&imx8mq_uid>; nvmem-cell-names = "soc_unique_id"; - bus@30000000 { /* AIPS1 */ + aips1: bus@30000000 { /* AIPS1 */ compatible = "fsl,aips-bus", "simple-bus"; reg = <0x30000000 0x400000>; #address-cells = <1>; @@ -507,7 +507,7 @@ <0x00030005 0x00000053>, <0x00030006 0x0000005f>, <0x00030007 0x00000071>; - #thermal-sensor-cells = <1>; + #thermal-sensor-cells = <1>; }; wdog1: watchdog@30280000 { @@ -784,7 +784,7 @@ }; }; - bus@30400000 { /* AIPS2 */ + aips2: bus@30400000 { /* AIPS2 */ compatible = "fsl,aips-bus", "simple-bus"; reg = <0x30400000 0x400000>; #address-cells = <1>; @@ -844,7 +844,7 @@ }; }; - bus@30800000 { /* AIPS3 */ + aips3: bus@30800000 { /* AIPS3 */ compatible = "fsl,aips-bus", "simple-bus"; reg = <0x30800000 0x400000>; #address-cells = <1>; @@ -1018,6 +1018,7 @@ compatible = "fsl,sec-v4.0-job-ring"; reg = <0x1000 0x1000>; interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; }; sec_jr1: jr@2000 { @@ -1369,7 +1370,7 @@ }; }; - bus@32c00000 { /* AIPS4 */ + aips4: bus@32c00000 { /* AIPS4 */ compatible = "fsl,aips-bus", "simple-bus"; reg = <0x32c00000 0x400000>; #address-cells = <1>; diff --git a/arch/arm64/boot/dts/freescale/imx8qm.dtsi b/arch/arm64/boot/dts/freescale/imx8qm.dtsi index 4f767012f1f5..c9c2b6536233 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qm.dtsi @@ -181,7 +181,7 @@ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */ }; - scu { + system-controller { compatible = "fsl,imx-scu"; mbox-names = "tx0", "rx0", @@ -190,7 +190,7 @@ &lsio_mu1 1 0 &lsio_mu1 3 3>; - pd: imx8qx-pd { + pd: power-controller { compatible = "fsl,imx8qm-scu-pd", "fsl,scu-pd"; #power-domain-cells = <1>; }; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-colibri-eval-v3.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-colibri-eval-v3.dtsi index 144fc9e82da7..a08e70fb7c7a 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp-colibri-eval-v3.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qxp-colibri-eval-v3.dtsi @@ -16,7 +16,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpiokeys>; - wakeup { + key-wakeup { label = "Wake-Up"; gpios = <&lsio_gpio3 10 GPIO_ACTIVE_HIGH>; linux,code = <KEY_WAKEUP>; @@ -38,17 +38,17 @@ /* Colibri UART_B */ &lpuart0 { - status= "okay"; + status = "okay"; }; /* Colibri UART_C */ &lpuart2 { - status= "okay"; + status = "okay"; }; /* Colibri UART_A */ &lpuart3 { - status= "okay"; + status = "okay"; }; /* Colibri FastEthernet */ diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi index a79ae33cbad2..f4ea18bb95ab 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi @@ -201,7 +201,7 @@ method = "smc"; }; - scu { + system-controller { compatible = "fsl,imx-scu"; mbox-names = "tx0", "rx0", @@ -210,29 +210,27 @@ &lsio_mu1 1 0 &lsio_mu1 3 3>; - pd: imx8qx-pd { + pd: power-controller { compatible = "fsl,imx8qxp-scu-pd", "fsl,scu-pd"; #power-domain-cells = <1>; }; clk: clock-controller { - compatible = "fsl,imx8qxp-clk"; + compatible = "fsl,imx8qxp-clk", "fsl,scu-clk"; #clock-cells = <2>; - clocks = <&xtal32k &xtal24m>; - clock-names = "xtal_32KHz", "xtal_24Mhz"; }; iomuxc: pinctrl { compatible = "fsl,imx8qxp-iomuxc"; }; - ocotp: imx8qx-ocotp { + ocotp: ocotp { compatible = "fsl,imx8qxp-scu-ocotp"; #address-cells = <1>; #size-cells = <1>; }; - scu_key: scu-key { + scu_key: keys { compatible = "fsl,imx8qxp-sc-key", "fsl,imx-sc-key"; linux,keycodes = <KEY_POWER>; status = "disabled"; @@ -276,7 +274,7 @@ }; thermal_zones: thermal-zones { - cpu-thermal0 { + cpu0-thermal { polling-delay-passive = <250>; polling-delay = <2000>; thermal-sensors = <&tsens IMX_SC_R_SYSTEM>; diff --git a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi index 09f7364dd1d0..60c1b018bf03 100644 --- a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi @@ -137,7 +137,7 @@ }; }; - soc@0 { + soc: soc@0 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; @@ -331,7 +331,7 @@ clock-names = "ipg", "ahb", "per"; power-domains = <&scmi_devpd IMX8ULP_PD_USDHC0>; fsl,tuning-start-tap = <20>; - fsl,tuning-step= <2>; + fsl,tuning-step = <2>; bus-width = <4>; status = "disabled"; }; @@ -346,7 +346,7 @@ clock-names = "ipg", "ahb", "per"; power-domains = <&scmi_devpd IMX8ULP_PD_USDHC1>; fsl,tuning-start-tap = <20>; - fsl,tuning-step= <2>; + fsl,tuning-step = <2>; bus-width = <4>; status = "disabled"; }; @@ -361,13 +361,13 @@ clock-names = "ipg", "ahb", "per"; power-domains = <&scmi_devpd IMX8ULP_PD_USDHC2_USB1>; fsl,tuning-start-tap = <20>; - fsl,tuning-step= <2>; + fsl,tuning-step = <2>; bus-width = <4>; status = "disabled"; }; }; - gpioe: gpio@2d000000 { + gpioe: gpio@2d000080 { compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio"; reg = <0x2d000080 0x1000>, <0x2d000040 0x40>; gpio-controller; @@ -381,7 +381,7 @@ gpio-ranges = <&iomuxc1 0 32 24>; }; - gpiof: gpio@2d010000 { + gpiof: gpio@2d010080 { compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio"; reg = <0x2d010080 0x1000>, <0x2d010040 0x40>; gpio-controller; @@ -417,7 +417,7 @@ }; }; - gpiod: gpio@2e200000 { + gpiod: gpio@2e200080 { compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio"; reg = <0x2e200080 0x1000>, <0x2e200040 0x40>; gpio-controller; diff --git a/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts b/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts new file mode 100644 index 000000000000..69786c326db0 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts @@ -0,0 +1,114 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 NXP + */ + +/dts-v1/; + +#include "imx93.dtsi" + +/ { + model = "NXP i.MX93 11X11 EVK board"; + compatible = "fsl,imx93-11x11-evk", "fsl,imx93"; + + chosen { + stdout-path = &lpuart1; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&mu1 { + status = "okay"; +}; + +&mu2 { + status = "okay"; +}; + +&lpuart1 { /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1>; + pinctrl-2 = <&pinctrl_usdhc1>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_usdhc2_vmmc>; + bus-width = <4>; + status = "okay"; + no-sdio; + no-mmc; +}; + +&iomuxc { + pinctrl_uart1: uart1grp { + fsl,pins = < + MX93_PAD_UART1_RXD__LPUART1_RX 0x31e + MX93_PAD_UART1_TXD__LPUART1_TX 0x31e + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX93_PAD_SD1_CLK__USDHC1_CLK 0x17fe + MX93_PAD_SD1_CMD__USDHC1_CMD 0x13fe + MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe + MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe + MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe + MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe + MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe + MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe + MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe + MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe + MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x17fe + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = < + MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x31e + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX93_PAD_SD2_CLK__USDHC2_CLK 0x17fe + MX93_PAD_SD2_CMD__USDHC2_CMD 0x13fe + MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe + MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe + MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe + MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe + MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx93-pinfunc.h b/arch/arm64/boot/dts/freescale/imx93-pinfunc.h new file mode 100755 index 000000000000..4298a145f8a9 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx93-pinfunc.h @@ -0,0 +1,623 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright 2022 NXP + */ + +#ifndef __DTS_IMX93_PINFUNC_H +#define __DTS_IMX93_PINFUNC_H + +/* + * The pin function ID is a tuple of + * <mux_reg conf_reg input_reg mux_mode input_val> + */ +#define MX93_PAD_DAP_TDI__JTAG_MUX_TDI 0x0000 0x01B0 0x03D8 0x0 0x0 +#define MX93_PAD_DAP_TDI__MQS2_LEFT 0x0000 0x01B0 0x0000 0x1 0x0 +#define MX93_PAD_DAP_TDI__CAN2_TX 0x0000 0x01B0 0x0000 0x3 0x0 +#define MX93_PAD_DAP_TDI__FLEXIO2_FLEXIO30 0x0000 0x01B0 0x0000 0x4 0x0 +#define MX93_PAD_DAP_TDI__GPIO3_IO28 0x0000 0x01B0 0x0000 0x5 0x0 +#define MX93_PAD_DAP_TDI__LPUART5_RX 0x0000 0x01B0 0x0430 0x6 0x0 +#define MX93_PAD_DAP_TMS_SWDIO__JTAG_MUX_TMS 0x0004 0x01B4 0x03DC 0x0 0x0 +#define MX93_PAD_DAP_TMS_SWDIO__FLEXIO2_FLEXIO31 0x0004 0x01B4 0x0000 0x4 0x0 +#define MX93_PAD_DAP_TMS_SWDIO__GPIO3_IO29 0x0004 0x01B4 0x0000 0x5 0x0 +#define MX93_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x0004 0x01B4 0x0000 0x6 0x0 +#define MX93_PAD_DAP_TCLK_SWCLK__JTAG_MUX_TCK 0x0008 0x01B8 0x03D4 0x0 0x0 +#define MX93_PAD_DAP_TCLK_SWCLK__FLEXIO1_FLEXIO30 0x0008 0x01B8 0x0000 0x4 0x0 +#define MX93_PAD_DAP_TCLK_SWCLK__GPIO3_IO30 0x0008 0x01B8 0x0000 0x5 0x0 +#define MX93_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x0008 0x01B8 0x042C 0x6 0x0 +#define MX93_PAD_DAP_TDO_TRACESWO__JTAG_MUX_TDO 0x000C 0x01BC 0x0000 0x0 0x0 +#define MX93_PAD_DAP_TDO_TRACESWO__MQS2_RIGHT 0x000C 0x01BC 0x0000 0x1 0x0 +#define MX93_PAD_DAP_TDO_TRACESWO__CAN2_RX 0x000C 0x01BC 0x0364 0x3 0x0 +#define MX93_PAD_DAP_TDO_TRACESWO__FLEXIO1_FLEXIO31 0x000C 0x01BC 0x0000 0x4 0x0 +#define MX93_PAD_DAP_TDO_TRACESWO__GPIO3_IO31 0x000C 0x01BC 0x0000 0x5 0x0 +#define MX93_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x000C 0x01BC 0x0434 0x6 0x0 +#define MX93_PAD_GPIO_IO00__GPIO2_IO00 0x0010 0x01C0 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO00__LPI2C3_SDA 0x0010 0x01C0 0x03E4 0x11 0x0 +#define MX93_PAD_GPIO_IO00__MEDIAMIX_CAM_CLK 0x0010 0x01C0 0x0000 0x2 0x0 +#define MX93_PAD_GPIO_IO00__MEDIAMIX_DISP_CLK 0x0010 0x01C0 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO00__LPSPI6_PCS0 0x0010 0x01C0 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO00__LPUART5_TX 0x0010 0x01C0 0x0434 0x5 0x1 +#define MX93_PAD_GPIO_IO00__LPI2C5_SDA 0x0010 0x01C0 0x03EC 0x16 0x0 +#define MX93_PAD_GPIO_IO00__FLEXIO1_FLEXIO00 0x0010 0x01C0 0x036C 0x7 0x0 +#define MX93_PAD_GPIO_IO01__GPIO2_IO01 0x0014 0x01C4 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO01__LPI2C3_SCL 0x0014 0x01C4 0x03E0 0x11 0x0 +#define MX93_PAD_GPIO_IO01__MEDIAMIX_CAM_DATA00 0x0014 0x01C4 0x0000 0x2 0x0 +#define MX93_PAD_GPIO_IO01__MEDIAMIX_DISP_DE 0x0014 0x01C4 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO01__LPSPI6_SIN 0x0014 0x01C4 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO01__LPUART5_RX 0x0014 0x01C4 0x0430 0x5 0x1 +#define MX93_PAD_GPIO_IO01__LPI2C5_SCL 0x0014 0x01C4 0x03E8 0x16 0x0 +#define MX93_PAD_GPIO_IO01__FLEXIO1_FLEXIO01 0x0014 0x01C4 0x0370 0x7 0x0 +#define MX93_PAD_GPIO_IO02__GPIO2_IO02 0x0018 0x01C8 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO02__LPI2C4_SDA 0x0018 0x01C8 0x0000 0x11 0x0 +#define MX93_PAD_GPIO_IO02__MEDIAMIX_CAM_VSYNC 0x0018 0x01C8 0x0000 0x2 0x0 +#define MX93_PAD_GPIO_IO02__MEDIAMIX_DISP_VSYNC 0x0018 0x01C8 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO02__LPSPI6_SOUT 0x0018 0x01C8 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO02__LPUART5_CTS_B 0x0018 0x01C8 0x042C 0x5 0x1 +#define MX93_PAD_GPIO_IO02__LPI2C6_SDA 0x0018 0x01C8 0x03F4 0x16 0x0 +#define MX93_PAD_GPIO_IO02__FLEXIO1_FLEXIO02 0x0018 0x01C8 0x0374 0x7 0x0 +#define MX93_PAD_GPIO_IO03__GPIO2_IO03 0x001C 0x01CC 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO03__LPI2C4_SCL 0x001C 0x01CC 0x0000 0x11 0x0 +#define MX93_PAD_GPIO_IO03__MEDIAMIX_CAM_HSYNC 0x001C 0x01CC 0x0000 0x2 0x0 +#define MX93_PAD_GPIO_IO03__MEDIAMIX_DISP_HSYNC 0x001C 0x01CC 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO03__LPSPI6_SCK 0x001C 0x01CC 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO03__LPUART5_RTS_B 0x001C 0x01CC 0x0000 0x5 0x0 +#define MX93_PAD_GPIO_IO03__LPI2C6_SCL 0x001C 0x01CC 0x03F0 0x16 0x0 +#define MX93_PAD_GPIO_IO03__FLEXIO1_FLEXIO03 0x001C 0x01CC 0x0378 0x7 0x0 +#define MX93_PAD_GPIO_IO04__GPIO2_IO04 0x0020 0x01D0 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO04__TPM3_CH0 0x0020 0x01D0 0x0000 0x1 0x0 +#define MX93_PAD_GPIO_IO04__PDM_CLK 0x0020 0x01D0 0x0000 0x2 0x0 +#define MX93_PAD_GPIO_IO04__MEDIAMIX_DISP_DATA00 0x0020 0x01D0 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO04__LPSPI7_PCS0 0x0020 0x01D0 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO04__LPUART6_TX 0x0020 0x01D0 0x0000 0x5 0x0 +#define MX93_PAD_GPIO_IO04__LPI2C6_SDA 0x0020 0x01D0 0x03F4 0x16 0x1 +#define MX93_PAD_GPIO_IO04__FLEXIO1_FLEXIO04 0x0020 0x01D0 0x037C 0x7 0x0 +#define MX93_PAD_GPIO_IO05__GPIO2_IO05 0x0024 0x01D4 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO05__TPM4_CH0 0x0024 0x01D4 0x0000 0x1 0x0 +#define MX93_PAD_GPIO_IO05__PDM_BIT_STREAM00 0x0024 0x01D4 0x0438 0x2 0x0 +#define MX93_PAD_GPIO_IO05__MEDIAMIX_DISP_DATA01 0x0024 0x01D4 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO05__LPSPI7_SIN 0x0024 0x01D4 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO05__LPUART6_RX 0x0024 0x01D4 0x0000 0x5 0x0 +#define MX93_PAD_GPIO_IO05__LPI2C6_SCL 0x0024 0x01D4 0x03F0 0x16 0x1 +#define MX93_PAD_GPIO_IO05__FLEXIO1_FLEXIO05 0x0024 0x01D4 0x0380 0x7 0x0 +#define MX93_PAD_GPIO_IO06__GPIO2_IO06 0x0028 0x01D8 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO06__TPM5_CH0 0x0028 0x01D8 0x0000 0x1 0x0 +#define MX93_PAD_GPIO_IO06__PDM_BIT_STREAM01 0x0028 0x01D8 0x043C 0x2 0x0 +#define MX93_PAD_GPIO_IO06__MEDIAMIX_DISP_DATA02 0x0028 0x01D8 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO06__LPSPI7_SOUT 0x0028 0x01D8 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO06__LPUART6_CTS_B 0x0028 0x01D8 0x0000 0x5 0x0 +#define MX93_PAD_GPIO_IO06__LPI2C7_SDA 0x0028 0x01D8 0x03FC 0x16 0x0 +#define MX93_PAD_GPIO_IO06__FLEXIO1_FLEXIO06 0x0028 0x01D8 0x0384 0x7 0x0 +#define MX93_PAD_GPIO_IO07__GPIO2_IO07 0x002C 0x01DC 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO07__LPSPI3_PCS1 0x002C 0x01DC 0x0000 0x1 0x0 +#define MX93_PAD_GPIO_IO07__MEDIAMIX_CAM_DATA01 0x002C 0x01DC 0x0000 0x2 0x0 +#define MX93_PAD_GPIO_IO07__MEDIAMIX_DISP_DATA03 0x002C 0x01DC 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO07__LPSPI7_SCK 0x002C 0x01DC 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO07__LPUART6_RTS_B 0x002C 0x01DC 0x0000 0x5 0x0 +#define MX93_PAD_GPIO_IO07__LPI2C7_SCL 0x002C 0x01DC 0x03F8 0x16 0x0 +#define MX93_PAD_GPIO_IO07__FLEXIO1_FLEXIO07 0x002C 0x01DC 0x0388 0x7 0x0 +#define MX93_PAD_GPIO_IO08__GPIO2_IO08 0x0030 0x01E0 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO08__LPSPI3_PCS0 0x0030 0x01E0 0x0000 0x1 0x0 +#define MX93_PAD_GPIO_IO08__MEDIAMIX_CAM_DATA02 0x0030 0x01E0 0x0000 0x2 0x0 +#define MX93_PAD_GPIO_IO08__MEDIAMIX_DISP_DATA04 0x0030 0x01E0 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO08__TPM6_CH0 0x0030 0x01E0 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO08__LPUART7_TX 0x0030 0x01E0 0x0000 0x5 0x0 +#define MX93_PAD_GPIO_IO08__LPI2C7_SDA 0x0030 0x01E0 0x03FC 0x16 0x1 +#define MX93_PAD_GPIO_IO08__FLEXIO1_FLEXIO08 0x0030 0x01E0 0x038C 0x7 0x0 +#define MX93_PAD_GPIO_IO09__GPIO2_IO09 0x0034 0x01E4 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO09__LPSPI3_SIN 0x0034 0x01E4 0x0000 0x1 0x0 +#define MX93_PAD_GPIO_IO09__MEDIAMIX_CAM_DATA03 0x0034 0x01E4 0x0000 0x2 0x0 +#define MX93_PAD_GPIO_IO09__MEDIAMIX_DISP_DATA05 0x0034 0x01E4 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO09__TPM3_EXTCLK 0x0034 0x01E4 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO09__LPUART7_RX 0x0034 0x01E4 0x0000 0x5 0x0 +#define MX93_PAD_GPIO_IO09__LPI2C7_SCL 0x0034 0x01E4 0x03F8 0x16 0x1 +#define MX93_PAD_GPIO_IO09__FLEXIO1_FLEXIO09 0x0034 0x01E4 0x0390 0x7 0x0 +#define MX93_PAD_GPIO_IO10__GPIO2_IO10 0x0038 0x01E8 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO10__LPSPI3_SOUT 0x0038 0x01E8 0x0000 0x1 0x0 +#define MX93_PAD_GPIO_IO10__MEDIAMIX_CAM_DATA04 0x0038 0x01E8 0x0000 0x2 0x0 +#define MX93_PAD_GPIO_IO10__MEDIAMIX_DISP_DATA06 0x0038 0x01E8 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO10__TPM4_EXTCLK 0x0038 0x01E8 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO10__LPUART7_CTS_B 0x0038 0x01E8 0x0000 0x5 0x0 +#define MX93_PAD_GPIO_IO10__LPI2C8_SDA 0x0038 0x01E8 0x0404 0x16 0x0 +#define MX93_PAD_GPIO_IO10__FLEXIO1_FLEXIO10 0x0038 0x01E8 0x0394 0x7 0x0 +#define MX93_PAD_GPIO_IO11__GPIO2_IO11 0x003C 0x01EC 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO11__LPSPI3_SCK 0x003C 0x01EC 0x0000 0x1 0x0 +#define MX93_PAD_GPIO_IO11__MEDIAMIX_CAM_DATA05 0x003C 0x01EC 0x0000 0x2 0x0 +#define MX93_PAD_GPIO_IO11__MEDIAMIX_DISP_DATA07 0x003C 0x01EC 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO11__TPM5_EXTCLK 0x003C 0x01EC 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO11__LPUART7_RTS_B 0x003C 0x01EC 0x0000 0x5 0x0 +#define MX93_PAD_GPIO_IO11__LPI2C8_SCL 0x003C 0x01EC 0x0400 0x16 0x0 +#define MX93_PAD_GPIO_IO11__FLEXIO1_FLEXIO11 0x003C 0x01EC 0x0398 0x7 0x0 +#define MX93_PAD_GPIO_IO12__GPIO2_IO12 0x0040 0x01F0 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO12__TPM3_CH2 0x0040 0x01F0 0x0000 0x1 0x0 +#define MX93_PAD_GPIO_IO12__PDM_BIT_STREAM02 0x0040 0x01F0 0x0440 0x2 0x0 +#define MX93_PAD_GPIO_IO12__MEDIAMIX_DISP_DATA08 0x0040 0x01F0 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO12__LPSPI8_PCS0 0x0040 0x01F0 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO12__LPUART8_TX 0x0040 0x01F0 0x0000 0x5 0x0 +#define MX93_PAD_GPIO_IO12__LPI2C8_SDA 0x0040 0x01F0 0x0404 0x16 0x1 +#define MX93_PAD_GPIO_IO12__SAI3_RX_SYNC 0x0040 0x01F0 0x0450 0x7 0x0 +#define MX93_PAD_GPIO_IO13__GPIO2_IO13 0x0044 0x01F4 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO13__TPM4_CH2 0x0044 0x01F4 0x0000 0x1 0x0 +#define MX93_PAD_GPIO_IO13__PDM_BIT_STREAM03 0x0044 0x01F4 0x0444 0x2 0x0 +#define MX93_PAD_GPIO_IO13__MEDIAMIX_DISP_DATA09 0x0044 0x01F4 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO13__LPSPI8_SIN 0x0044 0x01F4 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO13__LPUART8_RX 0x0044 0x01F4 0x0000 0x5 0x0 +#define MX93_PAD_GPIO_IO13__LPI2C8_SCL 0x0044 0x01F4 0x0400 0x16 0x1 +#define MX93_PAD_GPIO_IO13__FLEXIO1_FLEXIO13 0x0044 0x01F4 0x039C 0x7 0x0 +#define MX93_PAD_GPIO_IO14__GPIO2_IO14 0x0048 0x01F8 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO14__LPUART3_TX 0x0048 0x01F8 0x041C 0x1 0x0 +#define MX93_PAD_GPIO_IO14__MEDIAMIX_CAM_DATA06 0x0048 0x01F8 0x0000 0x2 0x0 +#define MX93_PAD_GPIO_IO14__MEDIAMIX_DISP_DATA10 0x0048 0x01F8 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO14__LPSPI8_SOUT 0x0048 0x01F8 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO14__LPUART8_CTS_B 0x0048 0x01F8 0x0000 0x5 0x0 +#define MX93_PAD_GPIO_IO14__LPUART4_TX 0x0048 0x01F8 0x0428 0x6 0x0 +#define MX93_PAD_GPIO_IO14__FLEXIO1_FLEXIO14 0x0048 0x01F8 0x03A0 0x7 0x0 +#define MX93_PAD_GPIO_IO15__GPIO2_IO15 0x004C 0x01FC 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO15__LPUART3_RX 0x004C 0x01FC 0x0418 0x1 0x0 +#define MX93_PAD_GPIO_IO15__MEDIAMIX_CAM_DATA07 0x004C 0x01FC 0x0000 0x2 0x0 +#define MX93_PAD_GPIO_IO15__MEDIAMIX_DISP_DATA11 0x004C 0x01FC 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO15__LPSPI8_SCK 0x004C 0x01FC 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO15__LPUART8_RTS_B 0x004C 0x01FC 0x0000 0x5 0x0 +#define MX93_PAD_GPIO_IO15__LPUART4_RX 0x004C 0x01FC 0x0424 0x6 0x0 +#define MX93_PAD_GPIO_IO15__FLEXIO1_FLEXIO15 0x004C 0x01FC 0x03A4 0x7 0x0 +#define MX93_PAD_GPIO_IO16__GPIO2_IO16 0x0050 0x0200 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO16__SAI3_TX_BCLK 0x0050 0x0200 0x0000 0x1 0x0 +#define MX93_PAD_GPIO_IO16__PDM_BIT_STREAM02 0x0050 0x0200 0x0440 0x2 0x1 +#define MX93_PAD_GPIO_IO16__MEDIAMIX_DISP_DATA12 0x0050 0x0200 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO16__LPUART3_CTS_B 0x0050 0x0200 0x0414 0x4 0x0 +#define MX93_PAD_GPIO_IO16__LPSPI4_PCS2 0x0050 0x0200 0x0000 0x5 0x0 +#define MX93_PAD_GPIO_IO16__LPUART4_CTS_B 0x0050 0x0200 0x0420 0x6 0x0 +#define MX93_PAD_GPIO_IO16__FLEXIO1_FLEXIO16 0x0050 0x0200 0x03A8 0x7 0x0 +#define MX93_PAD_GPIO_IO17__GPIO2_IO17 0x0054 0x0204 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO17__SAI3_MCLK 0x0054 0x0204 0x0000 0x1 0x0 +#define MX93_PAD_GPIO_IO17__MEDIAMIX_CAM_DATA08 0x0054 0x0204 0x0000 0x2 0x0 +#define MX93_PAD_GPIO_IO17__MEDIAMIX_DISP_DATA13 0x0054 0x0204 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO17__LPUART3_RTS_B 0x0054 0x0204 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO17__LPSPI4_PCS1 0x0054 0x0204 0x0000 0x5 0x0 +#define MX93_PAD_GPIO_IO17__LPUART4_RTS_B 0x0054 0x0204 0x0000 0x6 0x0 +#define MX93_PAD_GPIO_IO17__FLEXIO1_FLEXIO17 0x0054 0x0204 0x03AC 0x7 0x0 +#define MX93_PAD_GPIO_IO18__GPIO2_IO18 0x0058 0x0208 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO18__SAI3_RX_BCLK 0x0058 0x0208 0x044C 0x1 0x0 +#define MX93_PAD_GPIO_IO18__MEDIAMIX_CAM_DATA09 0x0058 0x0208 0x0000 0x2 0x0 +#define MX93_PAD_GPIO_IO18__MEDIAMIX_DISP_DATA14 0x0058 0x0208 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO18__LPSPI5_PCS0 0x0058 0x0208 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO18__LPSPI4_PCS0 0x0058 0x0208 0x0000 0x5 0x0 +#define MX93_PAD_GPIO_IO18__TPM5_CH2 0x0058 0x0208 0x0000 0x6 0x0 +#define MX93_PAD_GPIO_IO18__FLEXIO1_FLEXIO18 0x0058 0x0208 0x03B0 0x7 0x0 +#define MX93_PAD_GPIO_IO19__GPIO2_IO19 0x005C 0x020C 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO19__SAI3_RX_SYNC 0x005C 0x020C 0x0450 0x1 0x1 +#define MX93_PAD_GPIO_IO19__PDM_BIT_STREAM03 0x005C 0x020C 0x0444 0x2 0x1 +#define MX93_PAD_GPIO_IO19__MEDIAMIX_DISP_DATA15 0x005C 0x020C 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO19__LPSPI5_SIN 0x005C 0x020C 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO19__LPSPI4_SIN 0x005C 0x020C 0x0000 0x5 0x0 +#define MX93_PAD_GPIO_IO19__TPM6_CH2 0x005C 0x020C 0x0000 0x6 0x0 +#define MX93_PAD_GPIO_IO19__SAI3_TX_DATA00 0x005C 0x020C 0x0000 0x7 0x0 +#define MX93_PAD_GPIO_IO20__GPIO2_IO20 0x0060 0x0210 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO20__SAI3_RX_DATA00 0x0060 0x0210 0x0000 0x1 0x0 +#define MX93_PAD_GPIO_IO20__PDM_BIT_STREAM00 0x0060 0x0210 0x0438 0x2 0x1 +#define MX93_PAD_GPIO_IO20__MEDIAMIX_DISP_DATA16 0x0060 0x0210 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO20__LPSPI5_SOUT 0x0060 0x0210 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO20__LPSPI4_SOUT 0x0060 0x0210 0x0000 0x5 0x0 +#define MX93_PAD_GPIO_IO20__TPM3_CH1 0x0060 0x0210 0x0000 0x6 0x0 +#define MX93_PAD_GPIO_IO20__FLEXIO1_FLEXIO20 0x0060 0x0210 0x03B4 0x7 0x0 +#define MX93_PAD_GPIO_IO21__GPIO2_IO21 0x0064 0x0214 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO21__SAI3_TX_DATA00 0x0064 0x0214 0x0000 0x1 0x0 +#define MX93_PAD_GPIO_IO21__PDM_CLK 0x0064 0x0214 0x0000 0x2 0x0 +#define MX93_PAD_GPIO_IO21__MEDIAMIX_DISP_DATA17 0x0064 0x0214 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO21__LPSPI5_SCK 0x0064 0x0214 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO21__LPSPI4_SCK 0x0064 0x0214 0x0000 0x5 0x0 +#define MX93_PAD_GPIO_IO21__TPM4_CH1 0x0064 0x0214 0x0000 0x6 0x0 +#define MX93_PAD_GPIO_IO21__SAI3_RX_BCLK 0x0064 0x0214 0x044C 0x7 0x1 +#define MX93_PAD_GPIO_IO22__GPIO2_IO22 0x0068 0x0218 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO22__USDHC3_CLK 0x0068 0x0218 0x0458 0x1 0x0 +#define MX93_PAD_GPIO_IO22__SPDIF_IN 0x0068 0x0218 0x0454 0x2 0x0 +#define MX93_PAD_GPIO_IO22__MEDIAMIX_DISP_DATA18 0x0068 0x0218 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO22__TPM5_CH1 0x0068 0x0218 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO22__TPM6_EXTCLK 0x0068 0x0218 0x0000 0x5 0x0 +#define MX93_PAD_GPIO_IO22__LPI2C5_SDA 0x0068 0x0218 0x03EC 0x16 0x1 +#define MX93_PAD_GPIO_IO22__FLEXIO1_FLEXIO22 0x0068 0x0218 0x03B8 0x7 0x0 +#define MX93_PAD_GPIO_IO23__GPIO2_IO23 0x006C 0x021C 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO23__USDHC3_CMD 0x006C 0x021C 0x045C 0x1 0x0 +#define MX93_PAD_GPIO_IO23__SPDIF_OUT 0x006C 0x021C 0x0000 0x2 0x0 +#define MX93_PAD_GPIO_IO23__MEDIAMIX_DISP_DATA19 0x006C 0x021C 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO23__TPM6_CH1 0x006C 0x021C 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO23__LPI2C5_SCL 0x006C 0x021C 0x03E8 0x16 0x1 +#define MX93_PAD_GPIO_IO23__FLEXIO1_FLEXIO23 0x006C 0x021C 0x03BC 0x7 0x0 +#define MX93_PAD_GPIO_IO24__GPIO2_IO24 0x0070 0x0220 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO24__USDHC3_DATA0 0x0070 0x0220 0x0460 0x1 0x0 +#define MX93_PAD_GPIO_IO24__MEDIAMIX_DISP_DATA20 0x0070 0x0220 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO24__TPM3_CH3 0x0070 0x0220 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO24__JTAG_MUX_TDO 0x0070 0x0220 0x0000 0x5 0x0 +#define MX93_PAD_GPIO_IO24__LPSPI6_PCS1 0x0070 0x0220 0x0000 0x6 0x0 +#define MX93_PAD_GPIO_IO24__FLEXIO1_FLEXIO24 0x0070 0x0220 0x03C0 0x7 0x0 +#define MX93_PAD_GPIO_IO25__GPIO2_IO25 0x0074 0x0224 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO25__USDHC3_DATA1 0x0074 0x0224 0x0464 0x1 0x0 +#define MX93_PAD_GPIO_IO25__CAN2_TX 0x0074 0x0224 0x0000 0x2 0x0 +#define MX93_PAD_GPIO_IO25__MEDIAMIX_DISP_DATA21 0x0074 0x0224 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO25__TPM4_CH3 0x0074 0x0224 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO25__JTAG_MUX_TCK 0x0074 0x0224 0x03D4 0x5 0x1 +#define MX93_PAD_GPIO_IO25__LPSPI7_PCS1 0x0074 0x0224 0x0000 0x6 0x0 +#define MX93_PAD_GPIO_IO25__FLEXIO1_FLEXIO25 0x0074 0x0224 0x03C4 0x7 0x0 +#define MX93_PAD_GPIO_IO26__GPIO2_IO26 0x0078 0x0228 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO26__USDHC3_DATA2 0x0078 0x0228 0x0468 0x1 0x0 +#define MX93_PAD_GPIO_IO26__PDM_BIT_STREAM01 0x0078 0x0228 0x043C 0x2 0x1 +#define MX93_PAD_GPIO_IO26__MEDIAMIX_DISP_DATA22 0x0078 0x0228 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO26__TPM5_CH3 0x0078 0x0228 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO26__JTAG_MUX_TDI 0x0078 0x0228 0x03D8 0x5 0x1 +#define MX93_PAD_GPIO_IO26__LPSPI8_PCS1 0x0078 0x0228 0x0000 0x6 0x0 +#define MX93_PAD_GPIO_IO26__SAI3_TX_SYNC 0x0078 0x0228 0x0000 0x7 0x0 +#define MX93_PAD_GPIO_IO27__GPIO2_IO27 0x007C 0x022C 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO27__USDHC3_DATA3 0x007C 0x022C 0x046C 0x1 0x0 +#define MX93_PAD_GPIO_IO27__CAN2_RX 0x007C 0x022C 0x0364 0x2 0x1 +#define MX93_PAD_GPIO_IO27__MEDIAMIX_DISP_DATA23 0x007C 0x022C 0x0000 0x3 0x0 +#define MX93_PAD_GPIO_IO27__TPM6_CH3 0x007C 0x022C 0x0000 0x4 0x0 +#define MX93_PAD_GPIO_IO27__JTAG_MUX_TMS 0x007C 0x022C 0x03DC 0x5 0x1 +#define MX93_PAD_GPIO_IO27__LPSPI5_PCS1 0x007C 0x022C 0x0000 0x6 0x0 +#define MX93_PAD_GPIO_IO27__FLEXIO1_FLEXIO27 0x007C 0x022C 0x03C8 0x7 0x0 +#define MX93_PAD_GPIO_IO28__GPIO2_IO28 0x0080 0x0230 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO28__LPI2C3_SDA 0x0080 0x0230 0x03E4 0x11 0x1 +#define MX93_PAD_GPIO_IO28__FLEXIO1_FLEXIO28 0x0080 0x0230 0x0000 0x7 0x0 +#define MX93_PAD_GPIO_IO29__GPIO2_IO29 0x0084 0x0234 0x0000 0x0 0x0 +#define MX93_PAD_GPIO_IO29__LPI2C3_SCL 0x0084 0x0234 0x03E0 0x11 0x1 +#define MX93_PAD_GPIO_IO29__FLEXIO1_FLEXIO29 0x0084 0x0234 0x0000 0x7 0x0 +#define MX93_PAD_CCM_CLKO1__CCMSRCGPCMIX_CLKO1 0x0088 0x0238 0x0000 0x0 0x0 +#define MX93_PAD_CCM_CLKO1__FLEXIO1_FLEXIO26 0x0088 0x0238 0x0000 0x4 0x0 +#define MX93_PAD_CCM_CLKO1__GPIO3_IO26 0x0088 0x0238 0x0000 0x5 0x0 +#define MX93_PAD_CCM_CLKO2__GPIO3_IO27 0x008C 0x023C 0x0000 0x5 0x0 +#define MX93_PAD_CCM_CLKO2__CCMSRCGPCMIX_CLKO2 0x008C 0x023C 0x0000 0x0 0x0 +#define MX93_PAD_CCM_CLKO2__FLEXIO1_FLEXIO27 0x008C 0x023C 0x03C8 0x4 0x1 +#define MX93_PAD_CCM_CLKO3__CCMSRCGPCMIX_CLKO3 0x0090 0x0240 0x0000 0x0 0x0 +#define MX93_PAD_CCM_CLKO3__FLEXIO2_FLEXIO28 0x0090 0x0240 0x0000 0x4 0x0 +#define MX93_PAD_CCM_CLKO3__GPIO4_IO28 0x0090 0x0240 0x0000 0x5 0x0 +#define MX93_PAD_CCM_CLKO4__CCMSRCGPCMIX_CLKO4 0x0094 0x0244 0x0000 0x0 0x0 +#define MX93_PAD_CCM_CLKO4__FLEXIO2_FLEXIO29 0x0094 0x0244 0x0000 0x4 0x0 +#define MX93_PAD_CCM_CLKO4__GPIO4_IO29 0x0094 0x0244 0x0000 0x5 0x0 +#define MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x0098 0x0248 0x0000 0x0 0x0 +#define MX93_PAD_ENET1_MDC__LPUART3_DCB_B 0x0098 0x0248 0x0000 0x1 0x0 +#define MX93_PAD_ENET1_MDC__I3C2_SCL 0x0098 0x0248 0x03CC 0x2 0x0 +#define MX93_PAD_ENET1_MDC__HSIOMIX_OTG_ID1 0x0098 0x0248 0x0000 0x3 0x0 +#define MX93_PAD_ENET1_MDC__FLEXIO2_FLEXIO00 0x0098 0x0248 0x0000 0x4 0x0 +#define MX93_PAD_ENET1_MDC__GPIO4_IO00 0x0098 0x0248 0x0000 0x5 0x0 +#define MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x009C 0x024C 0x0000 0x0 0x0 +#define MX93_PAD_ENET1_MDIO__LPUART3_RIN_B 0x009C 0x024C 0x0000 0x1 0x0 +#define MX93_PAD_ENET1_MDIO__I3C2_SDA 0x009C 0x024C 0x03D0 0x2 0x0 +#define MX93_PAD_ENET1_MDIO__HSIOMIX_OTG_PWR1 0x009C 0x024C 0x0000 0x3 0x0 +#define MX93_PAD_ENET1_MDIO__FLEXIO2_FLEXIO01 0x009C 0x024C 0x0000 0x4 0x0 +#define MX93_PAD_ENET1_MDIO__GPIO4_IO01 0x009C 0x024C 0x0000 0x5 0x0 +#define MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x00A0 0x0250 0x0000 0x0 0x0 +#define MX93_PAD_ENET1_TD3__CAN2_TX 0x00A0 0x0250 0x0000 0x2 0x0 +#define MX93_PAD_ENET1_TD3__HSIOMIX_OTG_ID2 0x00A0 0x0250 0x0000 0x3 0x0 +#define MX93_PAD_ENET1_TD3__FLEXIO2_FLEXIO02 0x00A0 0x0250 0x0000 0x4 0x0 +#define MX93_PAD_ENET1_TD3__GPIO4_IO02 0x00A0 0x0250 0x0000 0x5 0x0 +#define MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x00A4 0x0254 0x0000 0x0 0x0 +#define MX93_PAD_ENET1_TD2__CCM_ENET_QOS_CLOCK_GENERATE_REF_CLK 0x00A4 0x0254 0x0000 0x1 0x0 +#define MX93_PAD_ENET1_TD2__CAN2_RX 0x00A4 0x0254 0x0364 0x2 0x2 +#define MX93_PAD_ENET1_TD2__HSIOMIX_OTG_OC2 0x00A4 0x0254 0x0000 0x3 0x0 +#define MX93_PAD_ENET1_TD2__FLEXIO2_FLEXIO03 0x00A4 0x0254 0x0000 0x4 0x0 +#define MX93_PAD_ENET1_TD2__GPIO4_IO03 0x00A4 0x0254 0x0000 0x5 0x0 +#define MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x00A8 0x0258 0x0000 0x0 0x0 +#define MX93_PAD_ENET1_TD1__LPUART3_RTS_B 0x00A8 0x0258 0x0000 0x1 0x0 +#define MX93_PAD_ENET1_TD1__I3C2_PUR 0x00A8 0x0258 0x0000 0x2 0x0 +#define MX93_PAD_ENET1_TD1__HSIOMIX_OTG_OC1 0x00A8 0x0258 0x0000 0x3 0x0 +#define MX93_PAD_ENET1_TD1__FLEXIO2_FLEXIO04 0x00A8 0x0258 0x0000 0x4 0x0 +#define MX93_PAD_ENET1_TD1__GPIO4_IO04 0x00A8 0x0258 0x0000 0x5 0x0 +#define MX93_PAD_ENET1_TD1__I3C2_PUR_B 0x00A8 0x0258 0x0000 0x6 0x0 +#define MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x00AC 0x025C 0x0000 0x0 0x0 +#define MX93_PAD_ENET1_TD0__LPUART3_TX 0x00AC 0x025C 0x041C 0x1 0x1 +#define MX93_PAD_ENET1_TD0__FLEXIO2_FLEXIO05 0x00AC 0x025C 0x0000 0x4 0x0 +#define MX93_PAD_ENET1_TD0__GPIO4_IO05 0x00AC 0x025C 0x0000 0x5 0x0 +#define MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x00B0 0x0260 0x0000 0x0 0x0 +#define MX93_PAD_ENET1_TX_CTL__LPUART3_DTR_B 0x00B0 0x0260 0x0000 0x1 0x0 +#define MX93_PAD_ENET1_TX_CTL__FLEXIO2_FLEXIO06 0x00B0 0x0260 0x0000 0x4 0x0 +#define MX93_PAD_ENET1_TX_CTL__GPIO4_IO06 0x00B0 0x0260 0x0000 0x5 0x0 +#define MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x00B4 0x0264 0x0000 0x0 0x0 +#define MX93_PAD_ENET1_TXC__ENET_QOS_TX_ER 0x00B4 0x0264 0x0000 0x1 0x0 +#define MX93_PAD_ENET1_TXC__FLEXIO2_FLEXIO07 0x00B4 0x0264 0x0000 0x4 0x0 +#define MX93_PAD_ENET1_TXC__GPIO4_IO07 0x00B4 0x0264 0x0000 0x5 0x0 +#define MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x00B8 0x0268 0x0000 0x0 0x0 +#define MX93_PAD_ENET1_RX_CTL__LPUART3_DSR_B 0x00B8 0x0268 0x0000 0x1 0x0 +#define MX93_PAD_ENET1_RX_CTL__HSIOMIX_OTG_PWR2 0x00B8 0x0268 0x0000 0x3 0x0 +#define MX93_PAD_ENET1_RX_CTL__FLEXIO2_FLEXIO08 0x00B8 0x0268 0x0000 0x4 0x0 +#define MX93_PAD_ENET1_RX_CTL__GPIO4_IO08 0x00B8 0x0268 0x0000 0x5 0x0 +#define MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x00BC 0x026C 0x0000 0x0 0x0 +#define MX93_PAD_ENET1_RXC__ENET_QOS_RX_ER 0x00BC 0x026C 0x0000 0x1 0x0 +#define MX93_PAD_ENET1_RXC__FLEXIO2_FLEXIO09 0x00BC 0x026C 0x0000 0x4 0x0 +#define MX93_PAD_ENET1_RXC__GPIO4_IO09 0x00BC 0x026C 0x0000 0x5 0x0 +#define MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x00C0 0x0270 0x0000 0x0 0x0 +#define MX93_PAD_ENET1_RD0__LPUART3_RX 0x00C0 0x0270 0x0418 0x1 0x1 +#define MX93_PAD_ENET1_RD0__FLEXIO2_FLEXIO10 0x00C0 0x0270 0x0000 0x4 0x0 +#define MX93_PAD_ENET1_RD0__GPIO4_IO10 0x00C0 0x0270 0x0000 0x5 0x0 +#define MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x00C4 0x0274 0x0000 0x0 0x0 +#define MX93_PAD_ENET1_RD1__LPUART3_CTS_B 0x00C4 0x0274 0x0414 0x1 0x1 +#define MX93_PAD_ENET1_RD1__LPTMR2_ALT1 0x00C4 0x0274 0x0408 0x3 0x0 +#define MX93_PAD_ENET1_RD1__FLEXIO2_FLEXIO11 0x00C4 0x0274 0x0000 0x4 0x0 +#define MX93_PAD_ENET1_RD1__GPIO4_IO11 0x00C4 0x0274 0x0000 0x5 0x0 +#define MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x00C8 0x0278 0x0000 0x0 0x0 +#define MX93_PAD_ENET1_RD2__LPTMR2_ALT2 0x00C8 0x0278 0x040C 0x3 0x0 +#define MX93_PAD_ENET1_RD2__FLEXIO2_FLEXIO12 0x00C8 0x0278 0x0000 0x4 0x0 +#define MX93_PAD_ENET1_RD2__GPIO4_IO12 0x00C8 0x0278 0x0000 0x5 0x0 +#define MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x00CC 0x027C 0x0000 0x0 0x0 +#define MX93_PAD_ENET1_RD3__FLEXSPI1_TESTER_TRIGGER 0x00CC 0x027C 0x0000 0x2 0x0 +#define MX93_PAD_ENET1_RD3__LPTMR2_ALT3 0x00CC 0x027C 0x0410 0x3 0x0 +#define MX93_PAD_ENET1_RD3__FLEXIO2_FLEXIO13 0x00CC 0x027C 0x0000 0x4 0x0 +#define MX93_PAD_ENET1_RD3__GPIO4_IO13 0x00CC 0x027C 0x0000 0x5 0x0 +#define MX93_PAD_ENET2_MDC__ENET1_MDC 0x00D0 0x0280 0x0000 0x0 0x0 +#define MX93_PAD_ENET2_MDC__LPUART4_DCB_B 0x00D0 0x0280 0x0000 0x1 0x0 +#define MX93_PAD_ENET2_MDC__SAI2_RX_SYNC 0x00D0 0x0280 0x0000 0x2 0x0 +#define MX93_PAD_ENET2_MDC__FLEXIO2_FLEXIO14 0x00D0 0x0280 0x0000 0x4 0x0 +#define MX93_PAD_ENET2_MDC__GPIO4_IO14 0x00D0 0x0280 0x0000 0x5 0x0 +#define MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x00D4 0x0284 0x0000 0x0 0x0 +#define MX93_PAD_ENET2_MDIO__LPUART4_RIN_B 0x00D4 0x0284 0x0000 0x1 0x0 +#define MX93_PAD_ENET2_MDIO__SAI2_RX_BCLK 0x00D4 0x0284 0x0000 0x2 0x0 +#define MX93_PAD_ENET2_MDIO__FLEXIO2_FLEXIO15 0x00D4 0x0284 0x0000 0x4 0x0 +#define MX93_PAD_ENET2_MDIO__GPIO4_IO15 0x00D4 0x0284 0x0000 0x5 0x0 +#define MX93_PAD_ENET2_TD3__SAI2_RX_DATA00 0x00D8 0x0288 0x0000 0x2 0x0 +#define MX93_PAD_ENET2_TD3__FLEXIO2_FLEXIO16 0x00D8 0x0288 0x0000 0x4 0x0 +#define MX93_PAD_ENET2_TD3__GPIO4_IO16 0x00D8 0x0288 0x0000 0x5 0x0 +#define MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3 0x00D8 0x0288 0x0000 0x0 0x0 +#define MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2 0x00DC 0x028C 0x0000 0x0 0x0 +#define MX93_PAD_ENET2_TD2__ENET1_TX_CLK 0x00DC 0x028C 0x0000 0x1 0x0 +#define MX93_PAD_ENET2_TD2__SAI2_RX_DATA01 0x00DC 0x028C 0x0000 0x2 0x0 +#define MX93_PAD_ENET2_TD2__FLEXIO2_FLEXIO17 0x00DC 0x028C 0x0000 0x4 0x0 +#define MX93_PAD_ENET2_TD2__GPIO4_IO17 0x00DC 0x028C 0x0000 0x5 0x0 +#define MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x00E0 0x0290 0x0000 0x0 0x0 +#define MX93_PAD_ENET2_TD1__LPUART4_RTS_B 0x00E0 0x0290 0x0000 0x1 0x0 +#define MX93_PAD_ENET2_TD1__SAI2_RX_DATA02 0x00E0 0x0290 0x0000 0x2 0x0 +#define MX93_PAD_ENET2_TD1__FLEXIO2_FLEXIO18 0x00E0 0x0290 0x0000 0x4 0x0 +#define MX93_PAD_ENET2_TD1__GPIO4_IO18 0x00E0 0x0290 0x0000 0x5 0x0 +#define MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x00E4 0x0294 0x0000 0x0 0x0 +#define MX93_PAD_ENET2_TD0__LPUART4_TX 0x00E4 0x0294 0x0428 0x1 0x1 +#define MX93_PAD_ENET2_TD0__SAI2_RX_DATA03 0x00E4 0x0294 0x0000 0x2 0x0 +#define MX93_PAD_ENET2_TD0__FLEXIO2_FLEXIO19 0x00E4 0x0294 0x0000 0x4 0x0 +#define MX93_PAD_ENET2_TD0__GPIO4_IO19 0x00E4 0x0294 0x0000 0x5 0x0 +#define MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x00E8 0x0298 0x0000 0x0 0x0 +#define MX93_PAD_ENET2_TX_CTL__LPUART4_DTR_B 0x00E8 0x0298 0x0000 0x1 0x0 +#define MX93_PAD_ENET2_TX_CTL__SAI2_TX_SYNC 0x00E8 0x0298 0x0000 0x2 0x0 +#define MX93_PAD_ENET2_TX_CTL__FLEXIO2_FLEXIO20 0x00E8 0x0298 0x0000 0x4 0x0 +#define MX93_PAD_ENET2_TX_CTL__GPIO4_IO20 0x00E8 0x0298 0x0000 0x5 0x0 +#define MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC 0x00EC 0x029C 0x0000 0x0 0x0 +#define MX93_PAD_ENET2_TXC__ENET1_TX_ER 0x00EC 0x029C 0x0000 0x1 0x0 +#define MX93_PAD_ENET2_TXC__SAI2_TX_BCLK 0x00EC 0x029C 0x0000 0x2 0x0 +#define MX93_PAD_ENET2_TXC__FLEXIO2_FLEXIO21 0x00EC 0x029C 0x0000 0x4 0x0 +#define MX93_PAD_ENET2_TXC__GPIO4_IO21 0x00EC 0x029C 0x0000 0x5 0x0 +#define MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x00F0 0x02A0 0x0000 0x0 0x0 +#define MX93_PAD_ENET2_RX_CTL__LPUART4_DSR_B 0x00F0 0x02A0 0x0000 0x1 0x0 +#define MX93_PAD_ENET2_RX_CTL__SAI2_TX_DATA00 0x00F0 0x02A0 0x0000 0x2 0x0 +#define MX93_PAD_ENET2_RX_CTL__FLEXIO2_FLEXIO22 0x00F0 0x02A0 0x0000 0x4 0x0 +#define MX93_PAD_ENET2_RX_CTL__GPIO4_IO22 0x00F0 0x02A0 0x0000 0x5 0x0 +#define MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC 0x00F4 0x02A4 0x0000 0x0 0x0 +#define MX93_PAD_ENET2_RXC__ENET1_RX_ER 0x00F4 0x02A4 0x0000 0x1 0x0 +#define MX93_PAD_ENET2_RXC__SAI2_TX_DATA01 0x00F4 0x02A4 0x0000 0x2 0x0 +#define MX93_PAD_ENET2_RXC__FLEXIO2_FLEXIO23 0x00F4 0x02A4 0x0000 0x4 0x0 +#define MX93_PAD_ENET2_RXC__GPIO4_IO23 0x00F4 0x02A4 0x0000 0x5 0x0 +#define MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x00F8 0x02A8 0x0000 0x0 0x0 +#define MX93_PAD_ENET2_RD0__LPUART4_RX 0x00F8 0x02A8 0x0424 0x1 0x1 +#define MX93_PAD_ENET2_RD0__SAI2_TX_DATA02 0x00F8 0x02A8 0x0000 0x2 0x0 +#define MX93_PAD_ENET2_RD0__FLEXIO2_FLEXIO24 0x00F8 0x02A8 0x0000 0x4 0x0 +#define MX93_PAD_ENET2_RD0__GPIO4_IO24 0x00F8 0x02A8 0x0000 0x5 0x0 +#define MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x00FC 0x02AC 0x0000 0x0 0x0 +#define MX93_PAD_ENET2_RD1__SPDIF_IN 0x00FC 0x02AC 0x0454 0x1 0x1 +#define MX93_PAD_ENET2_RD1__SAI2_TX_DATA03 0x00FC 0x02AC 0x0000 0x2 0x0 +#define MX93_PAD_ENET2_RD1__FLEXIO2_FLEXIO25 0x00FC 0x02AC 0x0000 0x4 0x0 +#define MX93_PAD_ENET2_RD1__GPIO4_IO25 0x00FC 0x02AC 0x0000 0x5 0x0 +#define MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2 0x0100 0x02B0 0x0000 0x0 0x0 +#define MX93_PAD_ENET2_RD2__LPUART4_CTS_B 0x0100 0x02B0 0x0420 0x1 0x1 +#define MX93_PAD_ENET2_RD2__SAI2_MCLK 0x0100 0x02B0 0x0000 0x2 0x0 +#define MX93_PAD_ENET2_RD2__MQS2_RIGHT 0x0100 0x02B0 0x0000 0x3 0x0 +#define MX93_PAD_ENET2_RD2__FLEXIO2_FLEXIO26 0x0100 0x02B0 0x0000 0x4 0x0 +#define MX93_PAD_ENET2_RD2__GPIO4_IO26 0x0100 0x02B0 0x0000 0x5 0x0 +#define MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3 0x0104 0x02B4 0x0000 0x0 0x0 +#define MX93_PAD_ENET2_RD3__SPDIF_OUT 0x0104 0x02B4 0x0000 0x1 0x0 +#define MX93_PAD_ENET2_RD3__SPDIF_IN 0x0104 0x02B4 0x0454 0x2 0x2 +#define MX93_PAD_ENET2_RD3__MQS2_LEFT 0x0104 0x02B4 0x0000 0x3 0x0 +#define MX93_PAD_ENET2_RD3__FLEXIO2_FLEXIO27 0x0104 0x02B4 0x0000 0x4 0x0 +#define MX93_PAD_ENET2_RD3__GPIO4_IO27 0x0104 0x02B4 0x0000 0x5 0x0 +#define MX93_PAD_SD1_CLK__FLEXIO1_FLEXIO08 0x0108 0x02B8 0x038C 0x4 0x1 +#define MX93_PAD_SD1_CLK__GPIO3_IO08 0x0108 0x02B8 0x0000 0x5 0x0 +#define MX93_PAD_SD1_CLK__USDHC1_CLK 0x0108 0x02B8 0x0000 0x0 0x0 +#define MX93_PAD_SD1_CMD__USDHC1_CMD 0x010C 0x02BC 0x0000 0x0 0x0 +#define MX93_PAD_SD1_CMD__FLEXIO1_FLEXIO09 0x010C 0x02BC 0x0390 0x4 0x1 +#define MX93_PAD_SD1_CMD__GPIO3_IO09 0x010C 0x02BC 0x0000 0x5 0x0 +#define MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x0110 0x02C0 0x0000 0x0 0x0 +#define MX93_PAD_SD1_DATA0__FLEXIO1_FLEXIO10 0x0110 0x02C0 0x0394 0x4 0x1 +#define MX93_PAD_SD1_DATA0__GPIO3_IO10 0x0110 0x02C0 0x0000 0x5 0x0 +#define MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x0114 0x02C4 0x0000 0x0 0x0 +#define MX93_PAD_SD1_DATA1__FLEXIO1_FLEXIO11 0x0114 0x02C4 0x0398 0x4 0x1 +#define MX93_PAD_SD1_DATA1__GPIO3_IO11 0x0114 0x02C4 0x0000 0x5 0x0 +#define MX93_PAD_SD1_DATA1__CCMSRCGPCMIX_INT_BOOT 0x0114 0x02C4 0x0000 0x6 0x0 +#define MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x0118 0x02C8 0x0000 0x0 0x0 +#define MX93_PAD_SD1_DATA2__FLEXIO1_FLEXIO12 0x0118 0x02C8 0x0000 0x4 0x0 +#define MX93_PAD_SD1_DATA2__GPIO3_IO12 0x0118 0x02C8 0x0000 0x5 0x0 +#define MX93_PAD_SD1_DATA2__CCMSRCGPCMIX_PMIC_READY 0x0118 0x02C8 0x0000 0x6 0x0 +#define MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x011C 0x02CC 0x0000 0x0 0x0 +#define MX93_PAD_SD1_DATA3__FLEXSPI1_A_SS1_B 0x011C 0x02CC 0x0000 0x1 0x0 +#define MX93_PAD_SD1_DATA3__FLEXIO1_FLEXIO13 0x011C 0x02CC 0x039C 0x4 0x1 +#define MX93_PAD_SD1_DATA3__GPIO3_IO13 0x011C 0x02CC 0x0000 0x5 0x0 +#define MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x0120 0x02D0 0x0000 0x0 0x0 +#define MX93_PAD_SD1_DATA4__FLEXSPI1_A_DATA04 0x0120 0x02D0 0x0000 0x1 0x0 +#define MX93_PAD_SD1_DATA4__FLEXIO1_FLEXIO14 0x0120 0x02D0 0x03A0 0x4 0x1 +#define MX93_PAD_SD1_DATA4__GPIO3_IO14 0x0120 0x02D0 0x0000 0x5 0x0 +#define MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x0124 0x02D4 0x0000 0x0 0x0 +#define MX93_PAD_SD1_DATA5__FLEXSPI1_A_DATA05 0x0124 0x02D4 0x0000 0x1 0x0 +#define MX93_PAD_SD1_DATA5__USDHC1_RESET_B 0x0124 0x02D4 0x0000 0x2 0x0 +#define MX93_PAD_SD1_DATA5__FLEXIO1_FLEXIO15 0x0124 0x02D4 0x03A4 0x4 0x1 +#define MX93_PAD_SD1_DATA5__GPIO3_IO15 0x0124 0x02D4 0x0000 0x5 0x0 +#define MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x0128 0x02D8 0x0000 0x0 0x0 +#define MX93_PAD_SD1_DATA6__FLEXSPI1_A_DATA06 0x0128 0x02D8 0x0000 0x1 0x0 +#define MX93_PAD_SD1_DATA6__USDHC1_CD_B 0x0128 0x02D8 0x0000 0x2 0x0 +#define MX93_PAD_SD1_DATA6__FLEXIO1_FLEXIO16 0x0128 0x02D8 0x03A8 0x4 0x1 +#define MX93_PAD_SD1_DATA6__GPIO3_IO16 0x0128 0x02D8 0x0000 0x5 0x0 +#define MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x012C 0x02DC 0x0000 0x0 0x0 +#define MX93_PAD_SD1_DATA7__FLEXSPI1_A_DATA07 0x012C 0x02DC 0x0000 0x1 0x0 +#define MX93_PAD_SD1_DATA7__USDHC1_WP 0x012C 0x02DC 0x0000 0x2 0x0 +#define MX93_PAD_SD1_DATA7__FLEXIO1_FLEXIO17 0x012C 0x02DC 0x03AC 0x4 0x1 +#define MX93_PAD_SD1_DATA7__GPIO3_IO17 0x012C 0x02DC 0x0000 0x5 0x0 +#define MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x0130 0x02E0 0x0000 0x0 0x0 +#define MX93_PAD_SD1_STROBE__FLEXSPI1_A_DQS 0x0130 0x02E0 0x0000 0x1 0x0 +#define MX93_PAD_SD1_STROBE__FLEXIO1_FLEXIO18 0x0130 0x02E0 0x03B0 0x4 0x1 +#define MX93_PAD_SD1_STROBE__GPIO3_IO18 0x0130 0x02E0 0x0000 0x5 0x0 +#define MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x0134 0x02E4 0x0000 0x0 0x0 +#define MX93_PAD_SD2_VSELECT__USDHC2_WP 0x0134 0x02E4 0x0000 0x1 0x0 +#define MX93_PAD_SD2_VSELECT__LPTMR2_ALT3 0x0134 0x02E4 0x0410 0x2 0x1 +#define MX93_PAD_SD2_VSELECT__FLEXIO1_FLEXIO19 0x0134 0x02E4 0x0000 0x4 0x0 +#define MX93_PAD_SD2_VSELECT__GPIO3_IO19 0x0134 0x02E4 0x0000 0x5 0x0 +#define MX93_PAD_SD2_VSELECT__CCMSRCGPCMIX_EXT_CLK1 0x0134 0x02E4 0x0368 0x6 0x0 +#define MX93_PAD_SD3_CLK__USDHC3_CLK 0x0138 0x02E8 0x0458 0x0 0x1 +#define MX93_PAD_SD3_CLK__FLEXSPI1_A_SCLK 0x0138 0x02E8 0x0000 0x1 0x0 +#define MX93_PAD_SD3_CLK__FLEXIO1_FLEXIO20 0x0138 0x02E8 0x03B4 0x4 0x1 +#define MX93_PAD_SD3_CLK__GPIO3_IO20 0x0138 0x02E8 0x0000 0x5 0x0 +#define MX93_PAD_SD3_CMD__USDHC3_CMD 0x013C 0x02EC 0x045C 0x0 0x1 +#define MX93_PAD_SD3_CMD__FLEXSPI1_A_SS0_B 0x013C 0x02EC 0x0000 0x1 0x0 +#define MX93_PAD_SD3_CMD__FLEXIO1_FLEXIO21 0x013C 0x02EC 0x0000 0x4 0x0 +#define MX93_PAD_SD3_CMD__GPIO3_IO21 0x013C 0x02EC 0x0000 0x5 0x0 +#define MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x0140 0x02F0 0x0460 0x0 0x1 +#define MX93_PAD_SD3_DATA0__FLEXSPI1_A_DATA00 0x0140 0x02F0 0x0000 0x1 0x0 +#define MX93_PAD_SD3_DATA0__FLEXIO1_FLEXIO22 0x0140 0x02F0 0x03B8 0x4 0x1 +#define MX93_PAD_SD3_DATA0__GPIO3_IO22 0x0140 0x02F0 0x0000 0x5 0x0 +#define MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x0144 0x02F4 0x0464 0x0 0x1 +#define MX93_PAD_SD3_DATA1__FLEXSPI1_A_DATA01 0x0144 0x02F4 0x0000 0x1 0x0 +#define MX93_PAD_SD3_DATA1__FLEXIO1_FLEXIO23 0x0144 0x02F4 0x03BC 0x4 0x1 +#define MX93_PAD_SD3_DATA1__GPIO3_IO23 0x0144 0x02F4 0x0000 0x5 0x0 +#define MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x0148 0x02F8 0x0468 0x0 0x1 +#define MX93_PAD_SD3_DATA2__FLEXSPI1_A_DATA02 0x0148 0x02F8 0x0000 0x1 0x0 +#define MX93_PAD_SD3_DATA2__FLEXIO1_FLEXIO24 0x0148 0x02F8 0x03C0 0x4 0x1 +#define MX93_PAD_SD3_DATA2__GPIO3_IO24 0x0148 0x02F8 0x0000 0x5 0x0 +#define MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x014C 0x02FC 0x046C 0x0 0x1 +#define MX93_PAD_SD3_DATA3__FLEXSPI1_A_DATA03 0x014C 0x02FC 0x0000 0x1 0x0 +#define MX93_PAD_SD3_DATA3__FLEXIO1_FLEXIO25 0x014C 0x02FC 0x03C4 0x4 0x1 +#define MX93_PAD_SD3_DATA3__GPIO3_IO25 0x014C 0x02FC 0x0000 0x5 0x0 +#define MX93_PAD_SD2_CD_B__USDHC2_CD_B 0x0150 0x0300 0x0000 0x0 0x0 +#define MX93_PAD_SD2_CD_B__ENET_QOS_1588_EVENT0_IN 0x0150 0x0300 0x0000 0x1 0x0 +#define MX93_PAD_SD2_CD_B__I3C2_SCL 0x0150 0x0300 0x03CC 0x2 0x1 +#define MX93_PAD_SD2_CD_B__FLEXIO1_FLEXIO00 0x0150 0x0300 0x036C 0x4 0x1 +#define MX93_PAD_SD2_CD_B__GPIO3_IO00 0x0150 0x0300 0x0000 0x5 0x0 +#define MX93_PAD_SD2_CLK__USDHC2_CLK 0x0154 0x0304 0x0000 0x0 0x0 +#define MX93_PAD_SD2_CLK__ENET_QOS_1588_EVENT0_OUT 0x0154 0x0304 0x0000 0x1 0x0 +#define MX93_PAD_SD2_CLK__I3C2_SDA 0x0154 0x0304 0x03D0 0x2 0x1 +#define MX93_PAD_SD2_CLK__FLEXIO1_FLEXIO01 0x0154 0x0304 0x0370 0x4 0x1 +#define MX93_PAD_SD2_CLK__GPIO3_IO01 0x0154 0x0304 0x0000 0x5 0x0 +#define MX93_PAD_SD2_CLK__CCMSRCGPCMIX_OBSERVE0 0x0154 0x0304 0x0000 0x6 0x0 +#define MX93_PAD_SD2_CMD__USDHC2_CMD 0x0158 0x0308 0x0000 0x0 0x0 +#define MX93_PAD_SD2_CMD__ENET1_1588_EVENT0_IN 0x0158 0x0308 0x0000 0x1 0x0 +#define MX93_PAD_SD2_CMD__I3C2_PUR 0x0158 0x0308 0x0000 0x2 0x0 +#define MX93_PAD_SD2_CMD__I3C2_PUR_B 0x0158 0x0308 0x0000 0x3 0x0 +#define MX93_PAD_SD2_CMD__FLEXIO1_FLEXIO02 0x0158 0x0308 0x0374 0x4 0x1 +#define MX93_PAD_SD2_CMD__GPIO3_IO02 0x0158 0x0308 0x0000 0x5 0x0 +#define MX93_PAD_SD2_CMD__CCMSRCGPCMIX_OBSERVE1 0x0158 0x0308 0x0000 0x6 0x0 +#define MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x015C 0x030C 0x0000 0x0 0x0 +#define MX93_PAD_SD2_DATA0__ENET1_1588_EVENT0_OUT 0x015C 0x030C 0x0000 0x1 0x0 +#define MX93_PAD_SD2_DATA0__CAN2_TX 0x015C 0x030C 0x0000 0x2 0x0 +#define MX93_PAD_SD2_DATA0__FLEXIO1_FLEXIO03 0x015C 0x030C 0x0378 0x4 0x1 +#define MX93_PAD_SD2_DATA0__GPIO3_IO03 0x015C 0x030C 0x0000 0x5 0x0 +#define MX93_PAD_SD2_DATA0__CCMSRCGPCMIX_OBSERVE2 0x015C 0x030C 0x0000 0x6 0x0 +#define MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x0160 0x0310 0x0000 0x0 0x0 +#define MX93_PAD_SD2_DATA1__ENET1_1588_EVENT1_IN 0x0160 0x0310 0x0000 0x1 0x0 +#define MX93_PAD_SD2_DATA1__CAN2_RX 0x0160 0x0310 0x0364 0x2 0x3 +#define MX93_PAD_SD2_DATA1__FLEXIO1_FLEXIO04 0x0160 0x0310 0x037C 0x4 0x1 +#define MX93_PAD_SD2_DATA1__GPIO3_IO04 0x0160 0x0310 0x0000 0x5 0x0 +#define MX93_PAD_SD2_DATA1__CCMSRCGPCMIX_WAIT 0x0160 0x0310 0x0000 0x6 0x0 +#define MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x0164 0x0314 0x0000 0x0 0x0 +#define MX93_PAD_SD2_DATA2__ENET1_1588_EVENT1_OUT 0x0164 0x0314 0x0000 0x1 0x0 +#define MX93_PAD_SD2_DATA2__MQS2_RIGHT 0x0164 0x0314 0x0000 0x2 0x0 +#define MX93_PAD_SD2_DATA2__FLEXIO1_FLEXIO05 0x0164 0x0314 0x0380 0x4 0x1 +#define MX93_PAD_SD2_DATA2__GPIO3_IO05 0x0164 0x0314 0x0000 0x5 0x0 +#define MX93_PAD_SD2_DATA2__CCMSRCGPCMIX_STOP 0x0164 0x0314 0x0000 0x6 0x0 +#define MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x0168 0x0318 0x0000 0x0 0x0 +#define MX93_PAD_SD2_DATA3__LPTMR2_ALT1 0x0168 0x0318 0x0408 0x1 0x1 +#define MX93_PAD_SD2_DATA3__MQS2_LEFT 0x0168 0x0318 0x0000 0x2 0x0 +#define MX93_PAD_SD2_DATA3__FLEXIO1_FLEXIO06 0x0168 0x0318 0x0384 0x4 0x1 +#define MX93_PAD_SD2_DATA3__GPIO3_IO06 0x0168 0x0318 0x0000 0x5 0x0 +#define MX93_PAD_SD2_DATA3__CCMSRCGPCMIX_EARLY_RESET 0x0168 0x0318 0x0000 0x6 0x0 +#define MX93_PAD_SD2_RESET_B__USDHC2_RESET_B 0x016C 0x031C 0x0000 0x0 0x0 +#define MX93_PAD_SD2_RESET_B__LPTMR2_ALT2 0x016C 0x031C 0x040C 0x1 0x1 +#define MX93_PAD_SD2_RESET_B__FLEXIO1_FLEXIO07 0x016C 0x031C 0x0388 0x4 0x1 +#define MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x016C 0x031C 0x0000 0x5 0x0 +#define MX93_PAD_SD2_RESET_B__CCMSRCGPCMIX_SYSTEM_RESET 0x016C 0x031C 0x0000 0x6 0x0 +#define MX93_PAD_I2C1_SCL__LPI2C1_SCL 0x0170 0x0320 0x0000 0x10 0x0 +#define MX93_PAD_I2C1_SCL__I3C1_SCL 0x0170 0x0320 0x0000 0x1 0x0 +#define MX93_PAD_I2C1_SCL__LPUART1_DCB_B 0x0170 0x0320 0x0000 0x2 0x0 +#define MX93_PAD_I2C1_SCL__TPM2_CH0 0x0170 0x0320 0x0000 0x3 0x0 +#define MX93_PAD_I2C1_SCL__GPIO1_IO00 0x0170 0x0320 0x0000 0x5 0x0 +#define MX93_PAD_I2C1_SDA__LPI2C1_SDA 0x0174 0x0324 0x0000 0x10 0x0 +#define MX93_PAD_I2C1_SDA__I3C1_SDA 0x0174 0x0324 0x0000 0x1 0x0 +#define MX93_PAD_I2C1_SDA__LPUART1_RIN_B 0x0174 0x0324 0x0000 0x2 0x0 +#define MX93_PAD_I2C1_SDA__TPM2_CH1 0x0174 0x0324 0x0000 0x3 0x0 +#define MX93_PAD_I2C1_SDA__GPIO1_IO01 0x0174 0x0324 0x0000 0x5 0x0 +#define MX93_PAD_I2C2_SCL__LPI2C2_SCL 0x0178 0x0328 0x0000 0x10 0x0 +#define MX93_PAD_I2C2_SCL__I3C1_PUR 0x0178 0x0328 0x0000 0x1 0x0 +#define MX93_PAD_I2C2_SCL__LPUART2_DCB_B 0x0178 0x0328 0x0000 0x2 0x0 +#define MX93_PAD_I2C2_SCL__TPM2_CH2 0x0178 0x0328 0x0000 0x3 0x0 +#define MX93_PAD_I2C2_SCL__SAI1_RX_SYNC 0x0178 0x0328 0x0000 0x4 0x0 +#define MX93_PAD_I2C2_SCL__GPIO1_IO02 0x0178 0x0328 0x0000 0x5 0x0 +#define MX93_PAD_I2C2_SCL__I3C1_PUR_B 0x0178 0x0328 0x0000 0x6 0x0 +#define MX93_PAD_I2C2_SDA__LPI2C2_SDA 0x017C 0x032C 0x0000 0x10 0x0 +#define MX93_PAD_I2C2_SDA__LPUART2_RIN_B 0x017C 0x032C 0x0000 0x2 0x0 +#define MX93_PAD_I2C2_SDA__TPM2_CH3 0x017C 0x032C 0x0000 0x3 0x0 +#define MX93_PAD_I2C2_SDA__SAI1_RX_BCLK 0x017C 0x032C 0x0000 0x4 0x0 +#define MX93_PAD_I2C2_SDA__GPIO1_IO03 0x017C 0x032C 0x0000 0x5 0x0 +#define MX93_PAD_UART1_RXD__LPUART1_RX 0x0180 0x0330 0x0000 0x0 0x0 +#define MX93_PAD_UART1_RXD__S400_UART_RX 0x0180 0x0330 0x0000 0x1 0x0 +#define MX93_PAD_UART1_RXD__LPSPI2_SIN 0x0180 0x0330 0x0000 0x2 0x0 +#define MX93_PAD_UART1_RXD__TPM1_CH0 0x0180 0x0330 0x0000 0x3 0x0 +#define MX93_PAD_UART1_RXD__GPIO1_IO04 0x0180 0x0330 0x0000 0x5 0x0 +#define MX93_PAD_UART1_TXD__LPUART1_TX 0x0184 0x0334 0x0000 0x0 0x0 +#define MX93_PAD_UART1_TXD__S400_UART_TX 0x0184 0x0334 0x0000 0x1 0x0 +#define MX93_PAD_UART1_TXD__LPSPI2_PCS0 0x0184 0x0334 0x0000 0x2 0x0 +#define MX93_PAD_UART1_TXD__TPM1_CH1 0x0184 0x0334 0x0000 0x3 0x0 +#define MX93_PAD_UART1_TXD__GPIO1_IO05 0x0184 0x0334 0x0000 0x5 0x0 +#define MX93_PAD_UART2_RXD__LPUART2_RX 0x0188 0x0338 0x0000 0x0 0x0 +#define MX93_PAD_UART2_RXD__LPUART1_CTS_B 0x0188 0x0338 0x0000 0x1 0x0 +#define MX93_PAD_UART2_RXD__LPSPI2_SOUT 0x0188 0x0338 0x0000 0x2 0x0 +#define MX93_PAD_UART2_RXD__TPM1_CH2 0x0188 0x0338 0x0000 0x3 0x0 +#define MX93_PAD_UART2_RXD__SAI1_MCLK 0x0188 0x0338 0x0448 0x4 0x0 +#define MX93_PAD_UART2_RXD__GPIO1_IO06 0x0188 0x0338 0x0000 0x5 0x0 +#define MX93_PAD_UART2_TXD__LPUART2_TX 0x018C 0x033C 0x0000 0x0 0x0 +#define MX93_PAD_UART2_TXD__LPUART1_RTS_B 0x018C 0x033C 0x0000 0x1 0x0 +#define MX93_PAD_UART2_TXD__LPSPI2_SCK 0x018C 0x033C 0x0000 0x2 0x0 +#define MX93_PAD_UART2_TXD__TPM1_CH3 0x018C 0x033C 0x0000 0x3 0x0 +#define MX93_PAD_UART2_TXD__GPIO1_IO07 0x018C 0x033C 0x0000 0x5 0x0 +#define MX93_PAD_PDM_CLK__PDM_CLK 0x0190 0x0340 0x0000 0x0 0x0 +#define MX93_PAD_PDM_CLK__MQS1_LEFT 0x0190 0x0340 0x0000 0x1 0x0 +#define MX93_PAD_PDM_CLK__LPTMR1_ALT1 0x0190 0x0340 0x0000 0x4 0x0 +#define MX93_PAD_PDM_CLK__GPIO1_IO08 0x0190 0x0340 0x0000 0x5 0x0 +#define MX93_PAD_PDM_CLK__CAN1_TX 0x0190 0x0340 0x0000 0x6 0x0 +#define MX93_PAD_PDM_BIT_STREAM0__PDM_BIT_STREAM00 0x0194 0x0344 0x0438 0x0 0x2 +#define MX93_PAD_PDM_BIT_STREAM0__MQS1_RIGHT 0x0194 0x0344 0x0000 0x1 0x0 +#define MX93_PAD_PDM_BIT_STREAM0__LPSPI1_PCS1 0x0194 0x0344 0x0000 0x2 0x0 +#define MX93_PAD_PDM_BIT_STREAM0__TPM1_EXTCLK 0x0194 0x0344 0x0000 0x3 0x0 +#define MX93_PAD_PDM_BIT_STREAM0__LPTMR1_ALT2 0x0194 0x0344 0x0000 0x4 0x0 +#define MX93_PAD_PDM_BIT_STREAM0__GPIO1_IO09 0x0194 0x0344 0x0000 0x5 0x0 +#define MX93_PAD_PDM_BIT_STREAM0__CAN1_RX 0x0194 0x0344 0x0360 0x6 0x0 +#define MX93_PAD_PDM_BIT_STREAM1__PDM_BIT_STREAM01 0x0198 0x0348 0x043C 0x0 0x2 +#define MX93_PAD_PDM_BIT_STREAM1__NMI_GLUE_NMI 0x0198 0x0348 0x0000 0x1 0x0 +#define MX93_PAD_PDM_BIT_STREAM1__LPSPI2_PCS1 0x0198 0x0348 0x0000 0x2 0x0 +#define MX93_PAD_PDM_BIT_STREAM1__TPM2_EXTCLK 0x0198 0x0348 0x0000 0x3 0x0 +#define MX93_PAD_PDM_BIT_STREAM1__LPTMR1_ALT3 0x0198 0x0348 0x0000 0x4 0x0 +#define MX93_PAD_PDM_BIT_STREAM1__GPIO1_IO10 0x0198 0x0348 0x0000 0x5 0x0 +#define MX93_PAD_PDM_BIT_STREAM1__CCMSRCGPCMIX_EXT_CLK1 0x0198 0x0348 0x0368 0x6 0x1 +#define MX93_PAD_SAI1_TXFS__SAI1_TX_SYNC 0x019C 0x034C 0x0000 0x0 0x0 +#define MX93_PAD_SAI1_TXFS__SAI1_TX_DATA01 0x019C 0x034C 0x0000 0x1 0x0 +#define MX93_PAD_SAI1_TXFS__LPSPI1_PCS0 0x019C 0x034C 0x0000 0x2 0x0 +#define MX93_PAD_SAI1_TXFS__LPUART2_DTR_B 0x019C 0x034C 0x0000 0x3 0x0 +#define MX93_PAD_SAI1_TXFS__MQS1_LEFT 0x019C 0x034C 0x0000 0x4 0x0 +#define MX93_PAD_SAI1_TXFS__GPIO1_IO11 0x019C 0x034C 0x0000 0x5 0x0 +#define MX93_PAD_SAI1_TXC__SAI1_TX_BCLK 0x01A0 0x0350 0x0000 0x0 0x0 +#define MX93_PAD_SAI1_TXC__LPUART2_CTS_B 0x01A0 0x0350 0x0000 0x1 0x0 +#define MX93_PAD_SAI1_TXC__LPSPI1_SIN 0x01A0 0x0350 0x0000 0x2 0x0 +#define MX93_PAD_SAI1_TXC__LPUART1_DSR_B 0x01A0 0x0350 0x0000 0x3 0x0 +#define MX93_PAD_SAI1_TXC__CAN1_RX 0x01A0 0x0350 0x0360 0x4 0x1 +#define MX93_PAD_SAI1_TXC__GPIO1_IO12 0x01A0 0x0350 0x0000 0x5 0x0 +#define MX93_PAD_SAI1_TXD0__SAI1_TX_DATA00 0x01A4 0x0354 0x0000 0x0 0x0 +#define MX93_PAD_SAI1_TXD0__LPUART2_RTS_B 0x01A4 0x0354 0x0000 0x1 0x0 +#define MX93_PAD_SAI1_TXD0__LPSPI1_SCK 0x01A4 0x0354 0x0000 0x2 0x0 +#define MX93_PAD_SAI1_TXD0__LPUART1_DTR_B 0x01A4 0x0354 0x0000 0x3 0x0 +#define MX93_PAD_SAI1_TXD0__CAN1_TX 0x01A4 0x0354 0x0000 0x4 0x0 +#define MX93_PAD_SAI1_TXD0__GPIO1_IO13 0x01A4 0x0354 0x0000 0x5 0x0 +#define MX93_PAD_SAI1_RXD0__SAI1_RX_DATA00 0x01A8 0x0358 0x0000 0x0 0x0 +#define MX93_PAD_SAI1_RXD0__SAI1_MCLK 0x01A8 0x0358 0x0448 0x1 0x1 +#define MX93_PAD_SAI1_RXD0__LPSPI1_SOUT 0x01A8 0x0358 0x0000 0x2 0x0 +#define MX93_PAD_SAI1_RXD0__LPUART2_DSR_B 0x01A8 0x0358 0x0000 0x3 0x0 +#define MX93_PAD_SAI1_RXD0__MQS1_RIGHT 0x01A8 0x0358 0x0000 0x4 0x0 +#define MX93_PAD_SAI1_RXD0__GPIO1_IO14 0x01A8 0x0358 0x0000 0x5 0x0 +#define MX93_PAD_WDOG_ANY__WDOG1_WDOG_ANY 0x01AC 0x035C 0x0000 0x0 0x0 +#define MX93_PAD_WDOG_ANY__GPIO1_IO15 0x01AC 0x035C 0x0000 0x5 0x0 + +#endif /* __DTS_IMX93_PINFUNC_H */ diff --git a/arch/arm64/boot/dts/freescale/imx93.dtsi b/arch/arm64/boot/dts/freescale/imx93.dtsi new file mode 100644 index 000000000000..f83a07c7c9b1 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx93.dtsi @@ -0,0 +1,334 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 NXP + */ + +#include <dt-bindings/clock/imx93-clock.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> + +#include "imx93-pinfunc.h" + +/ { + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + mmc0 = &usdhc1; + mmc1 = &usdhc2; + mmc2 = &usdhc3; + serial0 = &lpuart1; + serial1 = &lpuart2; + serial2 = &lpuart3; + serial3 = &lpuart4; + serial4 = &lpuart5; + serial5 = &lpuart6; + serial6 = &lpuart7; + serial7 = &lpuart8; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + A55_0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0>; + enable-method = "psci"; + #cooling-cells = <2>; + }; + + A55_1: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x100>; + enable-method = "psci"; + #cooling-cells = <2>; + }; + + }; + + osc_32k: clock-osc-32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "osc_32k"; + }; + + osc_24m: clock-osc-24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "osc_24m"; + }; + + clk_ext1: clock-ext1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <133000000>; + clock-output-names = "clk_ext1"; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; + clock-frequency = <24000000>; + arm,no-tick-in-suspend; + interrupt-parent = <&gic>; + }; + + gic: interrupt-controller@48000000 { + compatible = "arm,gic-v3"; + reg = <0 0x48000000 0 0x10000>, + <0 0x48040000 0 0xc0000>; + #interrupt-cells = <3>; + interrupt-controller; + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + }; + + soc@0 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x0 0x80000000>, + <0x28000000 0x0 0x28000000 0x10000000>; + + aips1: bus@44000000 { + compatible = "fsl,aips-bus", "simple-bus"; + reg = <0x44000000 0x800000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + mu1: mailbox@44230000 { + compatible = "fsl,imx93-mu", "fsl,imx8ulp-mu"; + reg = <0x44230000 0x10000>; + interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; + #mbox-cells = <2>; + status = "disabled"; + }; + + system_counter: timer@44290000 { + compatible = "nxp,sysctr-timer"; + reg = <0x44290000 0x30000>; + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&osc_24m>; + clock-names = "per"; + }; + + lpuart1: serial@44380000 { + compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart"; + reg = <0x44380000 0x1000>; + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPUART1_GATE>; + clock-names = "ipg"; + status = "disabled"; + }; + + lpuart2: serial@44390000 { + compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart"; + reg = <0x44390000 0x1000>; + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPUART2_GATE>; + clock-names = "ipg"; + status = "disabled"; + }; + + iomuxc: pinctrl@443c0000 { + compatible = "fsl,imx93-iomuxc"; + reg = <0x443c0000 0x10000>; + status = "okay"; + }; + + clk: clock-controller@44450000 { + compatible = "fsl,imx93-ccm"; + reg = <0x44450000 0x10000>; + #clock-cells = <1>; + clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>; + clock-names = "osc_32k", "osc_24m", "clk_ext1"; + status = "okay"; + }; + + anatop: anatop@44480000 { + compatible = "fsl,imx93-anatop", "syscon"; + reg = <0x44480000 0x10000>; + }; + }; + + aips2: bus@42000000 { + compatible = "fsl,aips-bus", "simple-bus"; + reg = <0x42000000 0x800000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + mu2: mailbox@42440000 { + compatible = "fsl,imx93-mu", "fsl,imx8ulp-mu"; + reg = <0x42440000 0x10000>; + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; + #mbox-cells = <2>; + status = "disabled"; + }; + + lpuart3: serial@42570000 { + compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart"; + reg = <0x42570000 0x1000>; + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPUART3_GATE>; + clock-names = "ipg"; + status = "disabled"; + }; + + lpuart4: serial@42580000 { + compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart"; + reg = <0x42580000 0x1000>; + interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPUART4_GATE>; + clock-names = "ipg"; + status = "disabled"; + }; + + lpuart5: serial@42590000 { + compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart"; + reg = <0x42590000 0x1000>; + interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPUART5_GATE>; + clock-names = "ipg"; + status = "disabled"; + }; + + lpuart6: serial@425a0000 { + compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart"; + reg = <0x425a0000 0x1000>; + interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPUART6_GATE>; + clock-names = "ipg"; + status = "disabled"; + }; + + lpuart7: serial@42690000 { + compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart"; + reg = <0x42690000 0x1000>; + interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPUART7_GATE>; + clock-names = "ipg"; + status = "disabled"; + }; + + lpuart8: serial@426a0000 { + compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart"; + reg = <0x426a0000 0x1000>; + interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPUART8_GATE>; + clock-names = "ipg"; + status = "disabled"; + }; + }; + + aips3: bus@42800000 { + compatible = "fsl,aips-bus", "simple-bus"; + reg = <0x42800000 0x800000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + usdhc1: mmc@42850000 { + compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc"; + reg = <0x42850000 0x10000>; + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_DUMMY>, + <&clk IMX93_CLK_DUMMY>, + <&clk IMX93_CLK_USDHC1_GATE>; + clock-names = "ipg", "ahb", "per"; + bus-width = <8>; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; + status = "disabled"; + }; + + usdhc2: mmc@42860000 { + compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc"; + reg = <0x42860000 0x10000>; + interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_DUMMY>, + <&clk IMX93_CLK_DUMMY>, + <&clk IMX93_CLK_USDHC2_GATE>; + clock-names = "ipg", "ahb", "per"; + bus-width = <4>; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; + status = "disabled"; + }; + + usdhc3: mmc@428b0000 { + compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc"; + reg = <0x428b0000 0x10000>; + interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_DUMMY>, + <&clk IMX93_CLK_DUMMY>, + <&clk IMX93_CLK_USDHC3_GATE>; + clock-names = "ipg", "ahb", "per"; + bus-width = <4>; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; + status = "disabled"; + }; + }; + + gpio2: gpio@43810080 { + compatible = "fsl,imx93-gpio", "fsl,imx7ulp-gpio"; + reg = <0x43810080 0x1000>, <0x43810040 0x40>; + gpio-controller; + #gpio-cells = <2>; + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 32 32>; + }; + + gpio3: gpio@43820080 { + compatible = "fsl,imx93-gpio", "fsl,imx7ulp-gpio"; + reg = <0x43820080 0x1000>, <0x43820040 0x40>; + gpio-controller; + #gpio-cells = <2>; + interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 64 32>; + }; + + gpio4: gpio@43830080 { + compatible = "fsl,imx93-gpio", "fsl,imx7ulp-gpio"; + reg = <0x43830080 0x1000>, <0x43830040 0x40>; + gpio-controller; + #gpio-cells = <2>; + interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 96 32>; + }; + + gpio1: gpio@47400080 { + compatible = "fsl,imx93-gpio", "fsl,imx7ulp-gpio"; + reg = <0x47400080 0x1000>, <0x47400040 0x40>; + gpio-controller; + #gpio-cells = <2>; + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 0 32>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/mba8mx.dtsi b/arch/arm64/boot/dts/freescale/mba8mx.dtsi index c2f0f1a1566c..104bdd4e437a 100644 --- a/arch/arm64/boot/dts/freescale/mba8mx.dtsi +++ b/arch/arm64/boot/dts/freescale/mba8mx.dtsi @@ -16,7 +16,6 @@ }; chosen { - // bootargs = "console=ttymxc2,115200 earlycon=ec_imx6q,0x30880000,115200"; stdout-path = &uart3; }; @@ -26,21 +25,21 @@ pinctrl-0 = <&pinctrl_gpiobutton>; autorepeat; - switch1 { + switch-1 { label = "switch1"; linux,code = <BTN_0>; gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; wakeup-source; }; - btn2: switch2 { + btn2: switch-2 { label = "switch2"; linux,code = <BTN_1>; gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; wakeup-source; }; - switch3 { + switch-3 { label = "switch3"; linux,code = <BTN_2>; gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; @@ -272,7 +271,6 @@ status = "okay"; }; -/* UART4 is assigned to Cortex-M4 */ &usdhc2 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; diff --git a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts index f68580dc87d8..0192a01bf852 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts +++ b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts @@ -49,9 +49,9 @@ ramoops@32000000 { compatible = "ramoops"; reg = <0x0 0x32000000 0x0 0x00100000>; - record-size = <0x00020000>; - console-size = <0x00020000>; - ftrace-size = <0x00020000>; + record-size = <0x00020000>; + console-size = <0x00020000>; + ftrace-size = <0x00020000>; }; }; @@ -63,9 +63,9 @@ compatible = "syscon-reboot-mode"; offset = <0x0>; - mode-normal = <0x77665501>; - mode-bootloader = <0x77665500>; - mode-recovery = <0x77665502>; + mode-normal = <0x77665501>; + mode-bootloader = <0x77665500>; + mode-recovery = <0x77665502>; }; }; @@ -74,7 +74,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pwr_key_pmx_func &pwr_key_cfg_func>; - power { + key-power { wakeup-source; gpios = <&gpio4 2 GPIO_ACTIVE_LOW>; label = "GPIO Power"; diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi index 6b3057a09251..8343d0cedde3 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi @@ -479,7 +479,7 @@ reg = <0x0 0xfdf00000 0x0 0x1000>; interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; dma-names = "rx", "tx"; - dmas = <&dma0 2 &dma0 3>; + dmas = <&dma0 2 &dma0 3>; clocks = <&crg_ctrl HI3660_CLK_GATE_UART1>, <&crg_ctrl HI3660_CLK_GATE_UART1>; clock-names = "uartclk", "apb_pclk"; @@ -493,7 +493,7 @@ reg = <0x0 0xfdf03000 0x0 0x1000>; interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; dma-names = "rx", "tx"; - dmas = <&dma0 4 &dma0 5>; + dmas = <&dma0 4 &dma0 5>; clocks = <&crg_ctrl HI3660_CLK_GATE_UART2>, <&crg_ctrl HI3660_PCLK>; clock-names = "uartclk", "apb_pclk"; @@ -519,7 +519,7 @@ reg = <0x0 0xfdf01000 0x0 0x1000>; interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; dma-names = "rx", "tx"; - dmas = <&dma0 6 &dma0 7>; + dmas = <&dma0 6 &dma0 7>; clocks = <&crg_ctrl HI3660_CLK_GATE_UART4>, <&crg_ctrl HI3660_CLK_GATE_UART4>; clock-names = "uartclk", "apb_pclk"; @@ -533,7 +533,7 @@ reg = <0x0 0xfdf05000 0x0 0x1000>; interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; dma-names = "rx", "tx"; - dmas = <&dma0 8 &dma0 9>; + dmas = <&dma0 8 &dma0 9>; clocks = <&crg_ctrl HI3660_CLK_GATE_UART5>, <&crg_ctrl HI3660_CLK_GATE_UART5>; clock-names = "uartclk", "apb_pclk"; diff --git a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi index 3125c3869c69..886b93c5893a 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi @@ -324,7 +324,7 @@ interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; #gpio-cells = <2>; - gpio-ranges = <&pmx0 0 13 4 &pmx0 7 17 1>; + gpio-ranges = <&pmx0 0 13 4 &pmx0 7 17 1>; interrupt-controller; #interrupt-cells = <2>; clocks = <&crg_ctrl HI3670_PCLK_GPIO3>; diff --git a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts index 3df2afb2f637..629e604aa281 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts +++ b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts @@ -54,9 +54,9 @@ ramoops@21f00000 { compatible = "ramoops"; reg = <0x0 0x21f00000 0x0 0x00100000>; - record-size = <0x00020000>; - console-size = <0x00020000>; - ftrace-size = <0x00020000>; + record-size = <0x00020000>; + console-size = <0x00020000>; + ftrace-size = <0x00020000>; }; /* global autoconfigured region for contiguous allocations */ @@ -76,9 +76,9 @@ compatible = "syscon-reboot-mode"; offset = <0x0>; - mode-normal = <0x77665501>; - mode-bootloader = <0x77665500>; - mode-recovery = <0x77665502>; + mode-normal = <0x77665501>; + mode-bootloader = <0x77665500>; + mode-recovery = <0x77665502>; }; }; diff --git a/arch/arm64/boot/dts/hisilicon/hip05-d02.dts b/arch/arm64/boot/dts/hisilicon/hip05-d02.dts index 40f3e00ac832..c4eaebbb448f 100644 --- a/arch/arm64/boot/dts/hisilicon/hip05-d02.dts +++ b/arch/arm64/boot/dts/hisilicon/hip05-d02.dts @@ -27,12 +27,10 @@ stdout-path = "serial0:115200n8"; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - pwrbutton { + pwr-button { label = "Power Button"; gpios = <&porta 8 GPIO_ACTIVE_LOW>; linux,code = <116>; diff --git a/arch/arm64/boot/dts/hisilicon/hip06.dtsi b/arch/arm64/boot/dts/hisilicon/hip06.dtsi index 70d7732dd348..2f8b03b0d365 100644 --- a/arch/arm64/boot/dts/hisilicon/hip06.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hip06.dtsi @@ -537,7 +537,7 @@ port@1 { reg = <1>; - serdes-syscon= <&serdes_ctrl>; + serdes-syscon = <&serdes_ctrl>; port-rst-offset = <1>; port-mode-offset = <1>; media-type = "fiber"; @@ -546,7 +546,7 @@ port@4 { reg = <4>; phy-handle = <&phy0>; - serdes-syscon= <&serdes_ctrl>; + serdes-syscon = <&serdes_ctrl>; port-rst-offset = <4>; port-mode-offset = <2>; media-type = "copper"; @@ -555,7 +555,7 @@ port@5 { reg = <5>; phy-handle = <&phy1>; - serdes-syscon= <&serdes_ctrl>; + serdes-syscon = <&serdes_ctrl>; port-rst-offset = <5>; port-mode-offset = <3>; media-type = "copper"; diff --git a/arch/arm64/boot/dts/hisilicon/hip07.dtsi b/arch/arm64/boot/dts/hisilicon/hip07.dtsi index 6baf6a686450..1a16662f8867 100644 --- a/arch/arm64/boot/dts/hisilicon/hip07.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hip07.dtsi @@ -1422,7 +1422,7 @@ port@1 { reg = <1>; - serdes-syscon= <&serdes_ctrl>; + serdes-syscon = <&serdes_ctrl>; cpld-syscon = <&dsa_cpld 0x4>; port-rst-offset = <1>; port-mode-offset = <1>; @@ -1433,7 +1433,7 @@ port@4 { reg = <4>; phy-handle = <&phy0>; - serdes-syscon= <&serdes_ctrl>; + serdes-syscon = <&serdes_ctrl>; port-rst-offset = <4>; port-mode-offset = <2>; mc-mac-mask = [ff f0 00 00 00 00]; @@ -1443,7 +1443,7 @@ port@5 { reg = <5>; phy-handle = <&phy1>; - serdes-syscon= <&serdes_ctrl>; + serdes-syscon = <&serdes_ctrl>; port-rst-offset = <5>; port-mode-offset = <3>; mc-mac-mask = [ff f0 00 00 00 00]; diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi index caccb0334ada..7bbec8aafa62 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi +++ b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi @@ -581,7 +581,7 @@ sdramedac { compatible = "altr,sdram-edac-s10"; altr,sdr-syscon = <&sdr>; - interrupts = <16 4>; + interrupts = <16 IRQ_TYPE_LEVEL_HIGH>; }; ocram-ecc@ff8cc000 { @@ -589,7 +589,7 @@ "altr,socfpga-a10-ocram-ecc"; reg = <0xff8cc000 0x100>; altr,ecc-parent = <&ocram>; - interrupts = <1 4>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; }; usb0-ecc@ff8c4000 { @@ -597,7 +597,7 @@ "altr,socfpga-usb-ecc"; reg = <0xff8c4000 0x100>; altr,ecc-parent = <&usb0>; - interrupts = <2 4>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; }; emac0-rx-ecc@ff8c0000 { @@ -605,7 +605,7 @@ "altr,socfpga-eth-mac-ecc"; reg = <0xff8c0000 0x100>; altr,ecc-parent = <&gmac0>; - interrupts = <4 4>; + interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; }; emac0-tx-ecc@ff8c0400 { @@ -613,7 +613,7 @@ "altr,socfpga-eth-mac-ecc"; reg = <0xff8c0400 0x100>; altr,ecc-parent = <&gmac0>; - interrupts = <5 4>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; }; sdmmca-ecc@ff8c8c00 { @@ -621,8 +621,8 @@ "altr,socfpga-sdmmc-ecc"; reg = <0xff8c8c00 0x100>; altr,ecc-parent = <&mmc>; - interrupts = <14 4>, - <15 4>; + interrupts = <14 IRQ_TYPE_LEVEL_HIGH>, + <15 IRQ_TYPE_LEVEL_HIGH>; }; }; diff --git a/arch/arm64/boot/dts/lg/lg1312.dtsi b/arch/arm64/boot/dts/lg/lg1312.dtsi index bec97480a960..78ae73d0cf36 100644 --- a/arch/arm64/boot/dts/lg/lg1312.dtsi +++ b/arch/arm64/boot/dts/lg/lg1312.dtsi @@ -52,7 +52,7 @@ }; psci { - compatible = "arm,psci-0.2", "arm,psci"; + compatible = "arm,psci-0.2", "arm,psci"; method = "smc"; cpu_suspend = <0x84000001>; cpu_off = <0x84000002>; @@ -150,7 +150,7 @@ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk_bus>; clock-names = "apb_pclk"; - status="disabled"; + status = "disabled"; }; uart1: serial@fe100000 { compatible = "arm,pl011", "arm,primecell"; @@ -158,7 +158,7 @@ interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk_bus>; clock-names = "apb_pclk"; - status="disabled"; + status = "disabled"; }; uart2: serial@fe200000 { compatible = "arm,pl011", "arm,primecell"; @@ -166,7 +166,7 @@ interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk_bus>; clock-names = "apb_pclk"; - status="disabled"; + status = "disabled"; }; spi0: spi@fe800000 { compatible = "arm,pl022", "arm,primecell"; @@ -197,7 +197,7 @@ reg = <0x0 0xfd400000 0x1000>; clocks = <&clk_bus>; clock-names = "apb_pclk"; - status="disabled"; + status = "disabled"; }; gpio1: gpio@fd410000 { #gpio-cells = <2>; @@ -206,7 +206,7 @@ reg = <0x0 0xfd410000 0x1000>; clocks = <&clk_bus>; clock-names = "apb_pclk"; - status="disabled"; + status = "disabled"; }; gpio2: gpio@fd420000 { #gpio-cells = <2>; @@ -215,7 +215,7 @@ reg = <0x0 0xfd420000 0x1000>; clocks = <&clk_bus>; clock-names = "apb_pclk"; - status="disabled"; + status = "disabled"; }; gpio3: gpio@fd430000 { #gpio-cells = <2>; @@ -232,7 +232,7 @@ reg = <0x0 0xfd440000 0x1000>; clocks = <&clk_bus>; clock-names = "apb_pclk"; - status="disabled"; + status = "disabled"; }; gpio5: gpio@fd450000 { #gpio-cells = <2>; @@ -241,7 +241,7 @@ reg = <0x0 0xfd450000 0x1000>; clocks = <&clk_bus>; clock-names = "apb_pclk"; - status="disabled"; + status = "disabled"; }; gpio6: gpio@fd460000 { #gpio-cells = <2>; @@ -250,7 +250,7 @@ reg = <0x0 0xfd460000 0x1000>; clocks = <&clk_bus>; clock-names = "apb_pclk"; - status="disabled"; + status = "disabled"; }; gpio7: gpio@fd470000 { #gpio-cells = <2>; @@ -259,7 +259,7 @@ reg = <0x0 0xfd470000 0x1000>; clocks = <&clk_bus>; clock-names = "apb_pclk"; - status="disabled"; + status = "disabled"; }; gpio8: gpio@fd480000 { #gpio-cells = <2>; @@ -268,7 +268,7 @@ reg = <0x0 0xfd480000 0x1000>; clocks = <&clk_bus>; clock-names = "apb_pclk"; - status="disabled"; + status = "disabled"; }; gpio9: gpio@fd490000 { #gpio-cells = <2>; @@ -277,7 +277,7 @@ reg = <0x0 0xfd490000 0x1000>; clocks = <&clk_bus>; clock-names = "apb_pclk"; - status="disabled"; + status = "disabled"; }; gpio10: gpio@fd4a0000 { #gpio-cells = <2>; @@ -286,7 +286,7 @@ reg = <0x0 0xfd4a0000 0x1000>; clocks = <&clk_bus>; clock-names = "apb_pclk"; - status="disabled"; + status = "disabled"; }; gpio11: gpio@fd4b0000 { #gpio-cells = <2>; @@ -303,7 +303,7 @@ reg = <0x0 0xfd4c0000 0x1000>; clocks = <&clk_bus>; clock-names = "apb_pclk"; - status="disabled"; + status = "disabled"; }; gpio13: gpio@fd4d0000 { #gpio-cells = <2>; @@ -312,7 +312,7 @@ reg = <0x0 0xfd4d0000 0x1000>; clocks = <&clk_bus>; clock-names = "apb_pclk"; - status="disabled"; + status = "disabled"; }; gpio14: gpio@fd4e0000 { #gpio-cells = <2>; @@ -321,7 +321,7 @@ reg = <0x0 0xfd4e0000 0x1000>; clocks = <&clk_bus>; clock-names = "apb_pclk"; - status="disabled"; + status = "disabled"; }; gpio15: gpio@fd4f0000 { #gpio-cells = <2>; @@ -330,7 +330,7 @@ reg = <0x0 0xfd4f0000 0x1000>; clocks = <&clk_bus>; clock-names = "apb_pclk"; - status="disabled"; + status = "disabled"; }; gpio16: gpio@fd500000 { #gpio-cells = <2>; @@ -339,7 +339,7 @@ reg = <0x0 0xfd500000 0x1000>; clocks = <&clk_bus>; clock-names = "apb_pclk"; - status="disabled"; + status = "disabled"; }; gpio17: gpio@fd510000 { #gpio-cells = <2>; diff --git a/arch/arm64/boot/dts/lg/lg1313.dtsi b/arch/arm64/boot/dts/lg/lg1313.dtsi index ada3d4dc6305..2173316573be 100644 --- a/arch/arm64/boot/dts/lg/lg1313.dtsi +++ b/arch/arm64/boot/dts/lg/lg1313.dtsi @@ -52,7 +52,7 @@ }; psci { - compatible = "arm,psci-0.2", "arm,psci"; + compatible = "arm,psci-0.2", "arm,psci"; method = "smc"; cpu_suspend = <0x84000001>; cpu_off = <0x84000002>; @@ -150,7 +150,7 @@ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk_bus>; clock-names = "apb_pclk"; - status="disabled"; + status = "disabled"; }; uart1: serial@fe100000 { compatible = "arm,pl011", "arm,primecell"; @@ -158,7 +158,7 @@ interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk_bus>; clock-names = "apb_pclk"; - status="disabled"; + status = "disabled"; }; uart2: serial@fe200000 { compatible = "arm,pl011", "arm,primecell"; @@ -166,7 +166,7 @@ interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk_bus>; clock-names = "apb_pclk"; - status="disabled"; + status = "disabled"; }; spi0: spi@fe800000 { compatible = "arm,pl022", "arm,primecell"; @@ -197,7 +197,7 @@ reg = <0x0 0xfd400000 0x1000>; clocks = <&clk_bus>; clock-names = "apb_pclk"; - status="disabled"; + status = "disabled"; }; gpio1: gpio@fd410000 { #gpio-cells = <2>; @@ -206,7 +206,7 @@ reg = <0x0 0xfd410000 0x1000>; clocks = <&clk_bus>; clock-names = "apb_pclk"; - status="disabled"; + status = "disabled"; }; gpio2: gpio@fd420000 { #gpio-cells = <2>; @@ -215,7 +215,7 @@ reg = <0x0 0xfd420000 0x1000>; clocks = <&clk_bus>; clock-names = "apb_pclk"; - status="disabled"; + status = "disabled"; }; gpio3: gpio@fd430000 { #gpio-cells = <2>; @@ -232,7 +232,7 @@ reg = <0x0 0xfd440000 0x1000>; clocks = <&clk_bus>; clock-names = "apb_pclk"; - status="disabled"; + status = "disabled"; }; gpio5: gpio@fd450000 { #gpio-cells = <2>; @@ -241,7 +241,7 @@ reg = <0x0 0xfd450000 0x1000>; clocks = <&clk_bus>; clock-names = "apb_pclk"; - status="disabled"; + status = "disabled"; }; gpio6: gpio@fd460000 { #gpio-cells = <2>; @@ -250,7 +250,7 @@ reg = <0x0 0xfd460000 0x1000>; clocks = <&clk_bus>; clock-names = "apb_pclk"; - status="disabled"; + status = "disabled"; }; gpio7: gpio@fd470000 { #gpio-cells = <2>; @@ -259,7 +259,7 @@ reg = <0x0 0xfd470000 0x1000>; clocks = <&clk_bus>; clock-names = "apb_pclk"; - status="disabled"; + status = "disabled"; }; gpio8: gpio@fd480000 { #gpio-cells = <2>; @@ -268,7 +268,7 @@ reg = <0x0 0xfd480000 0x1000>; clocks = <&clk_bus>; clock-names = "apb_pclk"; - status="disabled"; + status = "disabled"; }; gpio9: gpio@fd490000 { #gpio-cells = <2>; @@ -277,7 +277,7 @@ reg = <0x0 0xfd490000 0x1000>; clocks = <&clk_bus>; clock-names = "apb_pclk"; - status="disabled"; + status = "disabled"; }; gpio10: gpio@fd4a0000 { #gpio-cells = <2>; @@ -286,7 +286,7 @@ reg = <0x0 0xfd4a0000 0x1000>; clocks = <&clk_bus>; clock-names = "apb_pclk"; - status="disabled"; + status = "disabled"; }; gpio11: gpio@fd4b0000 { #gpio-cells = <2>; @@ -303,7 +303,7 @@ reg = <0x0 0xfd4c0000 0x1000>; clocks = <&clk_bus>; clock-names = "apb_pclk"; - status="disabled"; + status = "disabled"; }; gpio13: gpio@fd4d0000 { #gpio-cells = <2>; @@ -312,7 +312,7 @@ reg = <0x0 0xfd4d0000 0x1000>; clocks = <&clk_bus>; clock-names = "apb_pclk"; - status="disabled"; + status = "disabled"; }; gpio14: gpio@fd4e0000 { #gpio-cells = <2>; @@ -321,7 +321,7 @@ reg = <0x0 0xfd4e0000 0x1000>; clocks = <&clk_bus>; clock-names = "apb_pclk"; - status="disabled"; + status = "disabled"; }; gpio15: gpio@fd4f0000 { #gpio-cells = <2>; @@ -330,7 +330,7 @@ reg = <0x0 0xfd4f0000 0x1000>; clocks = <&clk_bus>; clock-names = "apb_pclk"; - status="disabled"; + status = "disabled"; }; gpio16: gpio@fd500000 { #gpio-cells = <2>; @@ -339,7 +339,7 @@ reg = <0x0 0xfd500000 0x1000>; clocks = <&clk_bus>; clock-names = "apb_pclk"; - status="disabled"; + status = "disabled"; }; gpio17: gpio@fd510000 { #gpio-cells = <2>; diff --git a/arch/arm64/boot/dts/marvell/Makefile b/arch/arm64/boot/dts/marvell/Makefile index 1c794cdcb8e6..b6d493e34dc5 100644 --- a/arch/arm64/boot/dts/marvell/Makefile +++ b/arch/arm64/boot/dts/marvell/Makefile @@ -24,3 +24,4 @@ dtb-$(CONFIG_ARCH_MVEBU) += cn9132-db.dtb dtb-$(CONFIG_ARCH_MVEBU) += cn9132-db-B.dtb dtb-$(CONFIG_ARCH_MVEBU) += cn9130-crb-A.dtb dtb-$(CONFIG_ARCH_MVEBU) += cn9130-crb-B.dtb +dtb-$(CONFIG_ARCH_MVEBU) += ac5-98dx35xx-rd.dtb diff --git a/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi b/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi new file mode 100644 index 000000000000..80b44c7df56a --- /dev/null +++ b/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi @@ -0,0 +1,291 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree For AC5. + * + * Copyright (C) 2021 Marvell + * Copyright (C) 2022 Allied Telesis Labs + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + model = "Marvell AC5 SoC"; + compatible = "marvell,ac5"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + core1 { + cpu = <&cpu1>; + }; + }; + }; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x0>; + enable-method = "psci"; + next-level-cache = <&l2>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x100>; + enable-method = "psci"; + next-level-cache = <&l2>; + }; + + l2: l2-cache { + compatible = "cache"; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>, + <GIC_PPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>, + <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <GIC_PPI 12 IRQ_TYPE_LEVEL_HIGH>; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + dma-ranges; + + internal-regs@7f000000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + /* 16M internal register @ 0x7f00_0000 */ + ranges = <0x0 0x0 0x7f000000 0x1000000>; + dma-coherent; + + uart0: serial@12000 { + compatible = "snps,dw-apb-uart"; + reg = <0x12000 0x100>; + reg-shift = <2>; + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + reg-io-width = <1>; + clocks = <&cnm_clock>; + status = "okay"; + }; + + mdio: mdio@22004 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "marvell,orion-mdio"; + reg = <0x22004 0x4>; + clocks = <&cnm_clock>; + }; + + i2c0: i2c@11000{ + compatible = "marvell,mv78230-i2c"; + reg = <0x11000 0x20>; + #address-cells = <1>; + #size-cells = <0>; + + clocks = <&cnm_clock>; + clock-names = "core"; + interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency=<100000>; + + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&i2c0_pins>; + pinctrl-1 = <&i2c0_gpio>; + scl_gpio = <&gpio0 26 GPIO_ACTIVE_HIGH>; + sda_gpio = <&gpio0 27 GPIO_ACTIVE_HIGH>; + status = "disabled"; + }; + + i2c1: i2c@11100{ + compatible = "marvell,mv78230-i2c"; + reg = <0x11100 0x20>; + #address-cells = <1>; + #size-cells = <0>; + + clocks = <&cnm_clock>; + clock-names = "core"; + interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency=<100000>; + + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&i2c1_pins>; + pinctrl-1 = <&i2c1_gpio>; + scl_gpio = <&gpio0 20 GPIO_ACTIVE_HIGH>; + sda_gpio = <&gpio0 21 GPIO_ACTIVE_HIGH>; + status = "disabled"; + }; + + gpio0: gpio@18100 { + compatible = "marvell,orion-gpio"; + reg = <0x18100 0x40>; + ngpios = <32>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl0 0 0 32>; + marvell,pwm-offset = <0x1f0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; + }; + + gpio1: gpio@18140 { + reg = <0x18140 0x40>; + compatible = "marvell,orion-gpio"; + ngpios = <14>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl0 0 32 14>; + marvell,pwm-offset = <0x1f0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + /* + * Dedicated section for devices behind 32bit controllers so we + * can configure specific DMA mapping for them + */ + behind-32bit-controller@7f000000 { + compatible = "simple-bus"; + #address-cells = <0x2>; + #size-cells = <0x2>; + ranges = <0x0 0x0 0x0 0x7f000000 0x0 0x1000000>; + /* Host phy ram starts at 0x200M */ + dma-ranges = <0x0 0x0 0x2 0x0 0x1 0x0>; + dma-coherent; + + eth0: ethernet@20000 { + compatible = "marvell,armada-ac5-neta"; + reg = <0x0 0x20000 0x0 0x4000>; + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cnm_clock>; + phy-mode = "sgmii"; + status = "disabled"; + }; + + eth1: ethernet@24000 { + compatible = "marvell,armada-ac5-neta"; + reg = <0x0 0x24000 0x0 0x4000>; + interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cnm_clock>; + phy-mode = "sgmii"; + status = "disabled"; + }; + + usb0: usb@80000 { + compatible = "marvell,orion-ehci"; + reg = <0x0 0x80000 0x0 0x500>; + interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + usb1: usb@a0000 { + compatible = "marvell,orion-ehci"; + reg = <0x0 0xa0000 0x0 0x500>; + interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + }; + + pinctrl0: pinctrl@80020100 { + compatible = "marvell,ac5-pinctrl"; + reg = <0 0x80020100 0 0x20>; + + i2c0_pins: i2c0-pins { + marvell,pins = "mpp26", "mpp27"; + marvell,function = "i2c0"; + }; + + i2c0_gpio: i2c0-gpio-pins { + marvell,pins = "mpp26", "mpp27"; + marvell,function = "gpio"; + }; + + i2c1_pins: i2c1-pins { + marvell,pins = "mpp20", "mpp21"; + marvell,function = "i2c1"; + }; + + i2c1_gpio: i2c1-gpio-pins { + marvell,pins = "mpp20", "mpp21"; + marvell,function = "i2c1"; + }; + }; + + spi0: spi@805a0000 { + compatible = "marvell,armada-3700-spi"; + reg = <0x0 0x805a0000 0x0 0x50>; + #address-cells = <0x1>; + #size-cells = <0x0>; + clocks = <&spi_clock>; + interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; + num-cs = <1>; + status = "disabled"; + }; + + spi1: spi@805a8000 { + compatible = "marvell,armada-3700-spi"; + reg = <0x0 0x805a8000 0x0 0x50>; + #address-cells = <0x1>; + #size-cells = <0x0>; + clocks = <&spi_clock>; + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; + num-cs = <1>; + status = "disabled"; + }; + + gic: interrupt-controller@80600000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x0 0x80600000 0x0 0x10000>, /* GICD */ + <0x0 0x80660000 0x0 0x40000>; /* GICR */ + interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + clocks { + cnm_clock: cnm-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <328000000>; + }; + + spi_clock: spi-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/marvell/ac5-98dx35xx-rd.dts b/arch/arm64/boot/dts/marvell/ac5-98dx35xx-rd.dts new file mode 100644 index 000000000000..f0ebdb84eec9 --- /dev/null +++ b/arch/arm64/boot/dts/marvell/ac5-98dx35xx-rd.dts @@ -0,0 +1,101 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree For RD-AC5X. + * + * Copyright (C) 2021 Marvell + * Copyright (C) 2022 Allied Telesis Labs + */ +/* + * Device Tree file for Marvell Alleycat 5X development board + * This board file supports the B configuration of the board + */ + +/dts-v1/; + +#include "ac5-98dx35xx.dtsi" + +/ { + model = "Marvell RD-AC5X Board"; + compatible = "marvell,rd-ac5x", "marvell,ac5x", "marvell,ac5"; + + aliases { + serial0 = &uart0; + spiflash0 = &spiflash0; + gpio0 = &gpio0; + gpio1 = &gpio1; + ethernet0 = ð0; + ethernet1 = ð1; + }; + + memory@0 { + device_type = "memory"; + reg = <0x2 0x00000000 0x0 0x40000000>; + }; + + usb1phy: usb-phy { + compatible = "usb-nop-xceiv"; + #phy-cells = <0>; + }; +}; + +&mdio { + phy0: ethernet-phy@0 { + reg = <0>; + }; +}; + +&i2c0 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; +}; + +ð0 { + status = "okay"; + phy-handle = <&phy0>; +}; + +/* USB0 is a host USB */ +&usb0 { + status = "okay"; +}; + +/* USB1 is a peripheral USB */ +&usb1 { + status = "okay"; + phys = <&usb1phy>; + phy-names = "usb-phy"; + dr_mode = "peripheral"; +}; + +&spi0 { + status = "okay"; + + spiflash0: flash@0 { + compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; + spi-tx-bus-width = <1>; /* 1-single, 2-dual, 4-quad */ + spi-rx-bus-width = <1>; /* 1-single, 2-dual, 4-quad */ + reg = <0>; + + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "spi_flash_part0"; + reg = <0x0 0x800000>; + }; + + parition@1 { + label = "spi_flash_part1"; + reg = <0x800000 0x700000>; + }; + + parition@2 { + label = "spi_flash_part2"; + reg = <0xF00000 0x100000>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/marvell/ac5-98dx35xx.dtsi b/arch/arm64/boot/dts/marvell/ac5-98dx35xx.dtsi new file mode 100644 index 000000000000..2ab72f854bea --- /dev/null +++ b/arch/arm64/boot/dts/marvell/ac5-98dx35xx.dtsi @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree For AC5X. + * + * Copyright (C) 2022 Allied Telesis Labs + */ + +#include "ac5-98dx25xx.dtsi" + +/ { + model = "Marvell AC5X SoC"; + compatible = "marvell,ac5x", "marvell,ac5"; +}; + +&cnm_clock { + clock-frequency = <325000000>; +}; diff --git a/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts b/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts index caf9c8529fca..de8d0cfa4cb4 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts +++ b/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts @@ -35,7 +35,7 @@ leds { compatible = "gpio-leds"; - red { + led { label = "mox:red:activity"; gpios = <&gpiosb 21 GPIO_ACTIVE_LOW>; linux,default-trigger = "default-on"; @@ -45,7 +45,7 @@ gpio-keys { compatible = "gpio-keys"; - reset { + key-reset { label = "reset"; linux,code = <KEY_RESTART>; gpios = <&gpiosb 20 GPIO_ACTIVE_LOW>; diff --git a/arch/arm64/boot/dts/marvell/armada-7040-mochabin.dts b/arch/arm64/boot/dts/marvell/armada-7040-mochabin.dts index 39a8e5e99d79..b9ba7c452a77 100644 --- a/arch/arm64/boot/dts/marvell/armada-7040-mochabin.dts +++ b/arch/arm64/boot/dts/marvell/armada-7040-mochabin.dts @@ -37,7 +37,7 @@ los-gpio = <&sfp_gpio 3 GPIO_ACTIVE_HIGH>; mod-def0-gpio = <&sfp_gpio 2 GPIO_ACTIVE_LOW>; tx-disable-gpio = <&sfp_gpio 1 GPIO_ACTIVE_HIGH>; - tx-fault-gpio = <&sfp_gpio 0 GPIO_ACTIVE_HIGH>; + tx-fault-gpio = <&sfp_gpio 0 GPIO_ACTIVE_HIGH>; }; /* SFP 1G */ @@ -47,7 +47,7 @@ los-gpio = <&sfp_gpio 7 GPIO_ACTIVE_HIGH>; mod-def0-gpio = <&sfp_gpio 6 GPIO_ACTIVE_LOW>; tx-disable-gpio = <&sfp_gpio 5 GPIO_ACTIVE_HIGH>; - tx-fault-gpio = <&sfp_gpio 4 GPIO_ACTIVE_HIGH>; + tx-fault-gpio = <&sfp_gpio 4 GPIO_ACTIVE_HIGH>; }; }; diff --git a/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts b/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts index 871f84b4a6ed..15f6ca4df121 100644 --- a/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts +++ b/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts @@ -94,7 +94,7 @@ pinctrl-0 = <&cp0_gpio_reset_pins &cp1_wps_button_pins>; pinctrl-names = "default"; - button_0 { + button-0 { /* The rear button */ label = "Rear Button"; gpios = <&cp0_gpio2 7 GPIO_ACTIVE_LOW>; @@ -102,7 +102,7 @@ linux,code = <BTN_0>; }; - button_1 { + button-1 { /* The wps button */ label = "WPS Button"; gpios = <&cp1_gpio1 30 GPIO_ACTIVE_LOW>; diff --git a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi index 779cf167c33e..c0389dd17340 100644 --- a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi @@ -68,7 +68,7 @@ los-gpio = <&cp1_gpio1 28 GPIO_ACTIVE_HIGH>; mod-def0-gpio = <&cp1_gpio1 27 GPIO_ACTIVE_LOW>; tx-disable-gpio = <&cp1_gpio1 29 GPIO_ACTIVE_HIGH>; - tx-fault-gpio = <&cp1_gpio1 26 GPIO_ACTIVE_HIGH>; + tx-fault-gpio = <&cp1_gpio1 26 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&cp1_sfpp0_pins>; maximum-power-milliwatt = <2000>; diff --git a/arch/arm64/boot/dts/marvell/armada-8040-puzzle-m801.dts b/arch/arm64/boot/dts/marvell/armada-8040-puzzle-m801.dts index 74bed79e4f5e..cf868e0bbb9c 100644 --- a/arch/arm64/boot/dts/marvell/armada-8040-puzzle-m801.dts +++ b/arch/arm64/boot/dts/marvell/armada-8040-puzzle-m801.dts @@ -70,7 +70,7 @@ los-gpio = <&sfpplus_gpio 11 GPIO_ACTIVE_HIGH>; mod-def0-gpio = <&sfpplus_gpio 10 GPIO_ACTIVE_LOW>; tx-disable-gpio = <&sfpplus_gpio 9 GPIO_ACTIVE_HIGH>; - tx-fault-gpio = <&sfpplus_gpio 8 GPIO_ACTIVE_HIGH>; + tx-fault-gpio = <&sfpplus_gpio 8 GPIO_ACTIVE_HIGH>; maximum-power-milliwatt = <3000>; }; @@ -80,7 +80,7 @@ los-gpio = <&sfpplus_gpio 3 GPIO_ACTIVE_HIGH>; mod-def0-gpio = <&sfpplus_gpio 2 GPIO_ACTIVE_LOW>; tx-disable-gpio = <&sfpplus_gpio 1 GPIO_ACTIVE_HIGH>; - tx-fault-gpio = <&sfpplus_gpio 0 GPIO_ACTIVE_HIGH>; + tx-fault-gpio = <&sfpplus_gpio 0 GPIO_ACTIVE_HIGH>; maximum-power-milliwatt = <3000>; }; diff --git a/arch/arm64/boot/dts/marvell/cn9130-db.dtsi b/arch/arm64/boot/dts/marvell/cn9130-db.dtsi index 7e20987253a3..f58402eb9536 100644 --- a/arch/arm64/boot/dts/marvell/cn9130-db.dtsi +++ b/arch/arm64/boot/dts/marvell/cn9130-db.dtsi @@ -404,7 +404,7 @@ &cp0_usb3_1 { status = "okay"; usb-phy = <&cp0_usb3_0_phy1>; - phys = <&cp0_utmi1>; + phys = <&cp0_utmi1>; phy-names = "utmi"; dr_mode = "host"; }; diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile index c7d4636a2cb7..af362a085a02 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -37,7 +37,12 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kodama-sku32.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku0.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku176.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-pumpkin.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-asurada-hayato-r1.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-asurada-spherion-r0.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-evb.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-cherry-tomato-r1.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-cherry-tomato-r2.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-cherry-tomato-r3.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-demo.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8516-pumpkin.dtb diff --git a/arch/arm64/boot/dts/mediatek/mt2712-evb.dts b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts index 11aa135aa0f3..9b1af9c80130 100644 --- a/arch/arm64/boot/dts/mediatek/mt2712-evb.dts +++ b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts @@ -106,7 +106,7 @@ }; ð { - phy-mode ="rgmii-rxid"; + phy-mode = "rgmii-rxid"; phy-handle = <ðernet_phy0>; mediatek,tx-delay-ps = <1530>; snps,reset-gpio = <&pio 87 GPIO_ACTIVE_LOW>; diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi index 623eb3beabf2..4797537cb368 100644 --- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi @@ -329,6 +329,7 @@ interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_LOW>; clocks = <&infracfg CLK_INFRA_M4U>; clock-names = "bclk"; + mediatek,infracfg = <&infracfg>; mediatek,larbs = <&larb0>, <&larb1>, <&larb2>, <&larb3>, <&larb6>; #iommu-cells = <1>; @@ -346,6 +347,7 @@ interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_LOW>; clocks = <&infracfg CLK_INFRA_M4U>; clock-names = "bclk"; + mediatek,infracfg = <&infracfg>; mediatek,larbs = <&larb4>, <&larb5>, <&larb7>; #iommu-cells = <1>; }; diff --git a/arch/arm64/boot/dts/mediatek/mt6795.dtsi b/arch/arm64/boot/dts/mediatek/mt6795.dtsi index c85659d0ff5d..d3bce9429e9b 100644 --- a/arch/arm64/boot/dts/mediatek/mt6795.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt6795.dtsi @@ -13,6 +13,7 @@ #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/pinctrl/mt6795-pinfunc.h> / { compatible = "mediatek,mt6795"; @@ -34,6 +35,8 @@ compatible = "arm,cortex-a53"; enable-method = "psci"; reg = <0x000>; + cci-control-port = <&cci_control2>; + next-level-cache = <&l2_0>; }; cpu1: cpu@1 { @@ -41,6 +44,8 @@ compatible = "arm,cortex-a53"; enable-method = "psci"; reg = <0x001>; + cci-control-port = <&cci_control2>; + next-level-cache = <&l2_0>; }; cpu2: cpu@2 { @@ -48,6 +53,8 @@ compatible = "arm,cortex-a53"; enable-method = "psci"; reg = <0x002>; + cci-control-port = <&cci_control2>; + next-level-cache = <&l2_0>; }; cpu3: cpu@3 { @@ -55,6 +62,8 @@ compatible = "arm,cortex-a53"; enable-method = "psci"; reg = <0x003>; + cci-control-port = <&cci_control2>; + next-level-cache = <&l2_0>; }; cpu4: cpu@100 { @@ -62,6 +71,8 @@ compatible = "arm,cortex-a53"; enable-method = "psci"; reg = <0x100>; + cci-control-port = <&cci_control1>; + next-level-cache = <&l2_1>; }; cpu5: cpu@101 { @@ -69,6 +80,8 @@ compatible = "arm,cortex-a53"; enable-method = "psci"; reg = <0x101>; + cci-control-port = <&cci_control1>; + next-level-cache = <&l2_1>; }; cpu6: cpu@102 { @@ -76,6 +89,8 @@ compatible = "arm,cortex-a53"; enable-method = "psci"; reg = <0x102>; + cci-control-port = <&cci_control1>; + next-level-cache = <&l2_1>; }; cpu7: cpu@103 { @@ -83,27 +98,88 @@ compatible = "arm,cortex-a53"; enable-method = "psci"; reg = <0x103>; + cci-control-port = <&cci_control1>; + next-level-cache = <&l2_1>; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + + core1 { + cpu = <&cpu1>; + }; + + core2 { + cpu = <&cpu2>; + }; + + core3 { + cpu = <&cpu3>; + }; + }; + + cluster1 { + core0 { + cpu = <&cpu4>; + }; + + core1 { + cpu = <&cpu5>; + }; + + core2 { + cpu = <&cpu6>; + }; + + core3 { + cpu = <&cpu7>; + }; + }; + }; + + l2_0: l2-cache0 { + compatible = "cache"; + cache-level = <2>; + }; + + l2_1: l2-cache1 { + compatible = "cache"; + cache-level = <2>; }; }; - system_clk: dummy13m { + clk26m: oscillator-26m { compatible = "fixed-clock"; - clock-frequency = <13000000>; #clock-cells = <0>; + clock-frequency = <26000000>; + clock-output-names = "clk26m"; }; - rtc_clk: dummy32k { + clk32k: oscillator-32k { compatible = "fixed-clock"; - clock-frequency = <32000>; #clock-cells = <0>; + clock-frequency = <32000>; + clock-output-names = "clk32k"; }; - uart_clk: dummy26m { + system_clk: dummy13m { compatible = "fixed-clock"; - clock-frequency = <26000000>; + clock-frequency = <13000000>; #clock-cells = <0>; }; + pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_LOW>, + <GIC_SPI 9 IRQ_TYPE_LEVEL_LOW>, + <GIC_SPI 10 IRQ_TYPE_LEVEL_LOW>, + <GIC_SPI 11 IRQ_TYPE_LEVEL_LOW>; + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + }; + timer { compatible = "arm,armv8-timer"; interrupt-parent = <&gic>; @@ -117,59 +193,133 @@ (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; }; - sysirq: intpol-controller@10200620 { - compatible = "mediatek,mt6795-sysirq", - "mediatek,mt6577-sysirq"; - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - reg = <0 0x10200620 0 0x20>; - }; + soc { + #address-cells = <2>; + #size-cells = <2>; + compatible = "simple-bus"; + ranges; - gic: interrupt-controller@10221000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - interrupt-controller; - reg = <0 0x10221000 0 0x1000>, - <0 0x10222000 0 0x2000>, - <0 0x10224000 0 0x2000>, - <0 0x10226000 0 0x2000>; - }; + pio: pinctrl@10005000 { + compatible = "mediatek,mt6795-pinctrl"; + reg = <0 0x10005000 0 0x1000>, <0 0x1000b000 0 0x1000>; + reg-names = "base", "eint"; + interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pio 0 0 196>; + interrupt-controller; + #interrupt-cells = <2>; + }; - uart0: serial@11002000 { - compatible = "mediatek,mt6795-uart", - "mediatek,mt6577-uart"; - reg = <0 0x11002000 0 0x400>; - interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>; - clocks = <&uart_clk>; - status = "disabled"; - }; + watchdog: watchdog@10007000 { + compatible = "mediatek,mt6795-wdt"; + reg = <0 0x10007000 0 0x100>; + interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_LOW>; + #reset-cells = <1>; + timeout-sec = <20>; + }; - uart1: serial@11003000 { - compatible = "mediatek,mt6795-uart", - "mediatek,mt6577-uart"; - reg = <0 0x11003000 0 0x400>; - interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>; - clocks = <&uart_clk>; - status = "disabled"; - }; + timer: timer@10008000 { + compatible = "mediatek,mt6795-timer", + "mediatek,mt6577-timer"; + reg = <0 0x10008000 0 0x1000>; + interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_LOW>; + clocks = <&system_clk>, <&clk32k>; + }; - uart2: serial@11004000 { - compatible = "mediatek,mt6795-uart", - "mediatek,mt6577-uart"; - reg = <0 0x11004000 0 0x400>; - interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>; - clocks = <&uart_clk>; - status = "disabled"; - }; + sysirq: intpol-controller@10200620 { + compatible = "mediatek,mt6795-sysirq", + "mediatek,mt6577-sysirq"; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + reg = <0 0x10200620 0 0x20>; + }; + + gic: interrupt-controller@10221000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + interrupt-controller; + reg = <0 0x10221000 0 0x1000>, + <0 0x10222000 0 0x2000>, + <0 0x10224000 0 0x2000>, + <0 0x10226000 0 0x2000>; + interrupts = <GIC_PPI 9 + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + }; + + cci: cci@10390000 { + compatible = "arm,cci-400"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0 0x10390000 0 0x1000>; + ranges = <0 0 0x10390000 0x10000>; - uart3: serial@11005000 { - compatible = "mediatek,mt6795-uart", - "mediatek,mt6577-uart"; - reg = <0 0x11005000 0 0x400>; - interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>; - clocks = <&uart_clk>; - status = "disabled"; + cci_control0: slave-if@1000 { + compatible = "arm,cci-400-ctrl-if"; + interface-type = "ace-lite"; + reg = <0x1000 0x1000>; + }; + + cci_control1: slave-if@4000 { + compatible = "arm,cci-400-ctrl-if"; + interface-type = "ace"; + reg = <0x4000 0x1000>; + }; + + cci_control2: slave-if@5000 { + compatible = "arm,cci-400-ctrl-if"; + interface-type = "ace"; + reg = <0x5000 0x1000>; + }; + + pmu@9000 { + compatible = "arm,cci-400-pmu,r1"; + reg = <0x9000 0x5000>; + interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + uart0: serial@11002000 { + compatible = "mediatek,mt6795-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11002000 0 0x400>; + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>; + clocks = <&clk26m>; + status = "disabled"; + }; + + uart1: serial@11003000 { + compatible = "mediatek,mt6795-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11003000 0 0x400>; + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>; + clocks = <&clk26m>; + status = "disabled"; + }; + + uart2: serial@11004000 { + compatible = "mediatek,mt6795-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11004000 0 0x400>; + interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>; + clocks = <&clk26m>; + status = "disabled"; + }; + + uart3: serial@11005000 { + compatible = "mediatek,mt6795-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11005000 0 0x400>; + interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>; + clocks = <&clk26m>; + status = "disabled"; + }; }; }; diff --git a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts index 2b9bf8dd14ec..d3f9eab2b784 100644 --- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts +++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts @@ -8,6 +8,7 @@ /dts-v1/; #include <dt-bindings/input/input.h> #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/leds/common.h> #include "mt7622.dtsi" #include "mt6380.dtsi" @@ -40,30 +41,32 @@ gpio-keys { compatible = "gpio-keys"; - factory { + factory-key { label = "factory"; linux,code = <BTN_0>; gpios = <&pio 0 GPIO_ACTIVE_HIGH>; }; - wps { + wps-key { label = "wps"; linux,code = <KEY_WPS_BUTTON>; - gpios = <&pio 102 GPIO_ACTIVE_HIGH>; + gpios = <&pio 102 GPIO_ACTIVE_LOW>; }; }; leds { compatible = "gpio-leds"; - green { + led-0 { label = "bpi-r64:pio:green"; + color = <LED_COLOR_ID_GREEN>; gpios = <&pio 89 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - red { + led-1 { label = "bpi-r64:pio:red"; + color = <LED_COLOR_ID_RED>; gpios = <&pio 88 GPIO_ACTIVE_HIGH>; default-state = "off"; }; @@ -336,14 +339,14 @@ i2c1_pins: i2c1-pins { mux { function = "i2c"; - groups = "i2c1_0"; + groups = "i2c1_0"; }; }; i2c2_pins: i2c2-pins { mux { function = "i2c"; - groups = "i2c2_0"; + groups = "i2c2_0"; }; }; @@ -366,14 +369,14 @@ irrx_pins: irrx-pins { mux { function = "ir"; - groups = "ir_1_rx"; + groups = "ir_1_rx"; }; }; irtx_pins: irtx-pins { mux { function = "ir"; - groups = "ir_1_tx"; + groups = "ir_1_tx"; }; }; diff --git a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts index 596c073d8b05..36722cabe626 100644 --- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts +++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts @@ -40,15 +40,14 @@ gpio-keys { compatible = "gpio-keys"; - poll-interval = <100>; - factory { + key-factory { label = "factory"; linux,code = <BTN_0>; gpios = <&pio 0 0>; }; - wps { + key-wps { label = "wps"; linux,code = <KEY_WPS_BUTTON>; gpios = <&pio 102 0>; @@ -298,14 +297,14 @@ i2c1_pins: i2c1-pins { mux { function = "i2c"; - groups = "i2c1_0"; + groups = "i2c1_0"; }; }; i2c2_pins: i2c2-pins { mux { function = "i2c"; - groups = "i2c2_0"; + groups = "i2c2_0"; }; }; @@ -328,14 +327,14 @@ irrx_pins: irrx-pins { mux { function = "ir"; - groups = "ir_1_rx"; + groups = "ir_1_rx"; }; }; irtx_pins: irtx-pins { mux { function = "ir"; - groups = "ir_1_tx"; + groups = "ir_1_tx"; }; }; diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi index dbcee8b4d8d8..146e18b5b1f4 100644 --- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi @@ -118,8 +118,8 @@ }; psci { - compatible = "arm,psci-0.2"; - method = "smc"; + compatible = "arm,psci-0.2"; + method = "smc"; }; pmu { @@ -616,9 +616,9 @@ afe: audio-controller { compatible = "mediatek,mt7622-audio"; - interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>, - <GIC_SPI 145 IRQ_TYPE_LEVEL_LOW>; - interrupt-names = "afe", "asys"; + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>, + <GIC_SPI 145 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "afe", "asys"; clocks = <&infracfg CLK_INFRA_AUDIO_PD>, <&topckgen CLK_TOP_AUD1_SEL>, diff --git a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi index d2636a0ed152..e3a407d03551 100644 --- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi @@ -57,8 +57,8 @@ }; psci { - compatible = "arm,psci-0.2"; - method = "smc"; + compatible = "arm,psci-0.2"; + method = "smc"; }; reserved-memory { diff --git a/arch/arm64/boot/dts/mediatek/mt8173-elm-hana-rev7.dts b/arch/arm64/boot/dts/mediatek/mt8173-elm-hana-rev7.dts index 44f6149c1307..28433b94f7c7 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173-elm-hana-rev7.dts +++ b/arch/arm64/boot/dts/mediatek/mt8173-elm-hana-rev7.dts @@ -21,7 +21,7 @@ }; &gpio_keys { - /delete-node/tablet_mode; - /delete-node/volume_down; - /delete-node/volume_up; + /delete-node/switch-tablet-mode; + /delete-node/switch-volume-down; + /delete-node/switch-volume-up; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi b/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi index 9c75fbb31f98..e21feb85d822 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi @@ -53,7 +53,7 @@ pinctrl-names = "default"; pinctrl-0 = <&gpio_keys_pins>; - lid { + switch-lid { label = "Lid"; gpios = <&pio 69 GPIO_ACTIVE_LOW>; linux,code = <SW_LID>; @@ -61,7 +61,7 @@ gpio-key,wakeup; }; - power { + switch-power { label = "Power"; gpios = <&pio 14 GPIO_ACTIVE_HIGH>; linux,code = <KEY_POWER>; @@ -69,7 +69,7 @@ gpio-key,wakeup; }; - tablet_mode { + switch-tablet-mode { label = "Tablet_mode"; gpios = <&pio 121 GPIO_ACTIVE_HIGH>; linux,code = <SW_TABLET_MODE>; @@ -77,13 +77,13 @@ gpio-key,wakeup; }; - volume_down { + switch-volume-down { label = "Volume_down"; gpios = <&pio 123 GPIO_ACTIVE_LOW>; linux,code = <KEY_VOLUMEDOWN>; }; - volume_up { + switch-volume-up { label = "Volume_up"; gpios = <&pio 124 GPIO_ACTIVE_LOW>; linux,code = <KEY_VOLUMEUP>; @@ -300,8 +300,8 @@ regulator-name = "VBUCKA"; regulator-min-microvolt = < 700000>; regulator-max-microvolt = <1310000>; - regulator-min-microamp = <2000000>; - regulator-max-microamp = <4400000>; + regulator-min-microamp = <2000000>; + regulator-max-microamp = <4400000>; regulator-ramp-delay = <10000>; regulator-always-on; regulator-allowed-modes = <DA9211_BUCK_MODE_SYNC @@ -312,8 +312,8 @@ regulator-name = "VBUCKB"; regulator-min-microvolt = < 700000>; regulator-max-microvolt = <1310000>; - regulator-min-microamp = <2000000>; - regulator-max-microamp = <3000000>; + regulator-min-microamp = <2000000>; + regulator-max-microamp = <3000000>; regulator-ramp-delay = <10000>; }; }; @@ -374,8 +374,8 @@ mmc-hs400-1_8v; cap-mmc-hw-reset; hs400-ds-delay = <0x14015>; - mediatek,hs200-cmd-int-delay=<30>; - mediatek,hs400-cmd-int-delay=<14>; + mediatek,hs200-cmd-int-delay = <30>; + mediatek,hs400-cmd-int-delay = <14>; mediatek,hs400-cmd-resp-sel-rising; vmmc-supply = <&mt6397_vemc_3v3_reg>; vqmmc-supply = <&mt6397_vio18_reg>; @@ -410,7 +410,7 @@ sd-uhs-sdr50; sd-uhs-sdr104; keep-power-in-suspend; - enable-sdio-wakeup; + wakeup-source; cap-sdio-irq; vmmc-supply = <&sdio_fixed_3v3>; vqmmc-supply = <&mt6397_vgp3_reg>; diff --git a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts index 4fa1e93302c7..0b5f154007be 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts +++ b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts @@ -122,8 +122,8 @@ regulator-name = "VBUCKA"; regulator-min-microvolt = < 700000>; regulator-max-microvolt = <1310000>; - regulator-min-microamp = <2000000>; - regulator-max-microamp = <4400000>; + regulator-min-microamp = <2000000>; + regulator-max-microamp = <4400000>; regulator-ramp-delay = <10000>; regulator-always-on; }; @@ -132,8 +132,8 @@ regulator-name = "VBUCKB"; regulator-min-microvolt = < 700000>; regulator-max-microvolt = <1310000>; - regulator-min-microamp = <2000000>; - regulator-max-microamp = <3000000>; + regulator-min-microamp = <2000000>; + regulator-max-microamp = <3000000>; regulator-ramp-delay = <10000>; }; }; @@ -148,8 +148,8 @@ bus-width = <8>; max-frequency = <50000000>; cap-mmc-highspeed; - mediatek,hs200-cmd-int-delay=<26>; - mediatek,hs400-cmd-int-delay=<14>; + mediatek,hs200-cmd-int-delay = <26>; + mediatek,hs400-cmd-int-delay = <14>; mediatek,hs400-cmd-resp-sel-rising; vmmc-supply = <&mt6397_vemc_3v3_reg>; vqmmc-supply = <&mt6397_vio18_reg>; diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi index 40d7b47fc52e..f35111724363 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi @@ -246,9 +246,9 @@ psci { compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci"; method = "smc"; - cpu_suspend = <0x84000001>; - cpu_off = <0x84000002>; - cpu_on = <0x84000003>; + cpu_suspend = <0x84000001>; + cpu_off = <0x84000002>; + cpu_on = <0x84000003>; }; clk26m: oscillator0 { @@ -588,6 +588,7 @@ interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>; clocks = <&infracfg CLK_INFRA_M4U>; clock-names = "bclk"; + mediatek,infracfg = <&infracfg>; mediatek,larbs = <&larb0>, <&larb1>, <&larb2>, <&larb3>, <&larb4>, <&larb5>; #iommu-cells = <1>; @@ -790,9 +791,12 @@ nor_flash: spi@1100d000 { compatible = "mediatek,mt8173-nor"; reg = <0 0x1100d000 0 0xe0>; + assigned-clocks = <&topckgen CLK_TOP_SPI_SEL>; + assigned-clock-parents = <&clk26m>; clocks = <&pericfg CLK_PERI_SPI>, - <&topckgen CLK_TOP_SPINFI_IFR_SEL>; - clock-names = "spi", "sf"; + <&topckgen CLK_TOP_SPINFI_IFR_SEL>, + <&pericfg CLK_PERI_NFI>; + clock-names = "spi", "sf", "axi"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1505,7 +1509,7 @@ vcodec_enc_vp8: vcodec@19002000 { compatible = "mediatek,mt8173-vcodec-enc-vp8"; - reg = <0 0x19002000 0 0x1000>; /* VENC_LT_SYS */ + reg = <0 0x19002000 0 0x1000>; /* VENC_LT_SYS */ interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>; iommus = <&iommu M4U_PORT_VENC_RCPU_SET2>, <&iommu M4U_PORT_VENC_REC_FRM_SET2>, diff --git a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts index f3fd3cca23e9..52dc4a50e34d 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts @@ -134,7 +134,7 @@ vmmc-supply = <&mt6358_vmch_reg>; vqmmc-supply = <&mt6358_vmc_reg>; keep-power-in-suspend; - enable-sdio-wakeup; + wakeup-source; non-removable; }; @@ -412,6 +412,42 @@ }; +&cci { + proc-supply = <&mt6358_vproc12_reg>; +}; + +&cpu0 { + proc-supply = <&mt6358_vproc12_reg>; +}; + +&cpu1 { + proc-supply = <&mt6358_vproc12_reg>; +}; + +&cpu2 { + proc-supply = <&mt6358_vproc12_reg>; +}; + +&cpu3 { + proc-supply = <&mt6358_vproc12_reg>; +}; + +&cpu4 { + proc-supply = <&mt6358_vproc11_reg>; +}; + +&cpu5 { + proc-supply = <&mt6358_vproc11_reg>; +}; + +&cpu6 { + proc-supply = <&mt6358_vproc11_reg>; +}; + +&cpu7 { + proc-supply = <&mt6358_vproc11_reg>; +}; + &uart0 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi index 2d7a193272ae..3ac83be53627 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi @@ -73,7 +73,7 @@ pinctrl-names = "default"; pinctrl-0 = <&volume_button_pins>; - volume_down { + button-volume-down { label = "Volume Down"; linux,code = <KEY_VOLUMEDOWN>; debounce-interval = <100>; @@ -81,7 +81,7 @@ gpios = <&pio 6 GPIO_ACTIVE_LOW>; }; - volume_up { + button-volume-up { label = "Volume Up"; linux,code = <KEY_VOLUMEUP>; debounce-interval = <100>; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dtsi index 28966a65391b..50a0dd36b5fb 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dtsi @@ -45,7 +45,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pen_eject>; - pen-insert { + switch-pen-insert { label = "Pen Insert"; /* Insert = low, eject = high */ gpios = <&pio 6 GPIO_ACTIVE_LOW>; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi index 8d5bf73a9099..b4b86bb1f1a7 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi @@ -144,7 +144,7 @@ pinctrl-names = "default"; pinctrl-0 = <&wifi_pins_wakeup>; - wowlan { + button-wowlan { label = "Wake on WiFi"; gpios = <&pio 113 GPIO_ACTIVE_HIGH>; linux,code = <KEY_WAKEUP>; @@ -230,6 +230,10 @@ status = "okay"; }; +&cci { + proc-supply = <&mt6358_vproc12_reg>; +}; + &cpu0 { proc-supply = <&mt6358_vproc12_reg>; }; @@ -276,6 +280,7 @@ avee-supply = <&ppvarp_lcd>; pp1800-supply = <&pp1800_lcd>; backlight = <&backlight_lcd0>; + rotation = <270>; port { panel_in: endpoint { remote-endpoint = <&dsi_out>; @@ -378,7 +383,7 @@ sd-uhs-sdr50; sd-uhs-sdr104; keep-power-in-suspend; - enable-sdio-wakeup; + wakeup-source; cap-sdio-irq; non-removable; no-mmc; @@ -817,6 +822,10 @@ }; }; +&mfg_async { + domain-supply = <&mt6358_vsram_gpu_reg>; +}; + &mfg { domain-supply = <&mt6358_vgpu_reg>; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts b/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts index afeb5cd37826..530e0c9ce0c9 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts @@ -159,7 +159,7 @@ vmmc-supply = <&mt6358_vmch_reg>; vqmmc-supply = <&mt6358_vmc_reg>; keep-power-in-suspend; - enable-sdio-wakeup; + wakeup-source; non-removable; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index 01e650251928..9d32871973a2 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -42,6 +42,252 @@ rdma1 = &rdma1; }; + cluster0_opp: opp-table-cluster0 { + compatible = "operating-points-v2"; + opp-shared; + opp0-793000000 { + opp-hz = /bits/ 64 <793000000>; + opp-microvolt = <650000>; + required-opps = <&opp2_00>; + }; + opp0-910000000 { + opp-hz = /bits/ 64 <910000000>; + opp-microvolt = <687500>; + required-opps = <&opp2_01>; + }; + opp0-1014000000 { + opp-hz = /bits/ 64 <1014000000>; + opp-microvolt = <718750>; + required-opps = <&opp2_02>; + }; + opp0-1131000000 { + opp-hz = /bits/ 64 <1131000000>; + opp-microvolt = <756250>; + required-opps = <&opp2_03>; + }; + opp0-1248000000 { + opp-hz = /bits/ 64 <1248000000>; + opp-microvolt = <800000>; + required-opps = <&opp2_04>; + }; + opp0-1326000000 { + opp-hz = /bits/ 64 <1326000000>; + opp-microvolt = <818750>; + required-opps = <&opp2_05>; + }; + opp0-1417000000 { + opp-hz = /bits/ 64 <1417000000>; + opp-microvolt = <850000>; + required-opps = <&opp2_06>; + }; + opp0-1508000000 { + opp-hz = /bits/ 64 <1508000000>; + opp-microvolt = <868750>; + required-opps = <&opp2_07>; + }; + opp0-1586000000 { + opp-hz = /bits/ 64 <1586000000>; + opp-microvolt = <893750>; + required-opps = <&opp2_08>; + }; + opp0-1625000000 { + opp-hz = /bits/ 64 <1625000000>; + opp-microvolt = <906250>; + required-opps = <&opp2_09>; + }; + opp0-1677000000 { + opp-hz = /bits/ 64 <1677000000>; + opp-microvolt = <931250>; + required-opps = <&opp2_10>; + }; + opp0-1716000000 { + opp-hz = /bits/ 64 <1716000000>; + opp-microvolt = <943750>; + required-opps = <&opp2_11>; + }; + opp0-1781000000 { + opp-hz = /bits/ 64 <1781000000>; + opp-microvolt = <975000>; + required-opps = <&opp2_12>; + }; + opp0-1846000000 { + opp-hz = /bits/ 64 <1846000000>; + opp-microvolt = <1000000>; + required-opps = <&opp2_13>; + }; + opp0-1924000000 { + opp-hz = /bits/ 64 <1924000000>; + opp-microvolt = <1025000>; + required-opps = <&opp2_14>; + }; + opp0-1989000000 { + opp-hz = /bits/ 64 <1989000000>; + opp-microvolt = <1050000>; + required-opps = <&opp2_15>; + }; }; + + cluster1_opp: opp-table-cluster1 { + compatible = "operating-points-v2"; + opp-shared; + opp1-793000000 { + opp-hz = /bits/ 64 <793000000>; + opp-microvolt = <700000>; + required-opps = <&opp2_00>; + }; + opp1-910000000 { + opp-hz = /bits/ 64 <910000000>; + opp-microvolt = <725000>; + required-opps = <&opp2_01>; + }; + opp1-1014000000 { + opp-hz = /bits/ 64 <1014000000>; + opp-microvolt = <750000>; + required-opps = <&opp2_02>; + }; + opp1-1131000000 { + opp-hz = /bits/ 64 <1131000000>; + opp-microvolt = <775000>; + required-opps = <&opp2_03>; + }; + opp1-1248000000 { + opp-hz = /bits/ 64 <1248000000>; + opp-microvolt = <800000>; + required-opps = <&opp2_04>; + }; + opp1-1326000000 { + opp-hz = /bits/ 64 <1326000000>; + opp-microvolt = <825000>; + required-opps = <&opp2_05>; + }; + opp1-1417000000 { + opp-hz = /bits/ 64 <1417000000>; + opp-microvolt = <850000>; + required-opps = <&opp2_06>; + }; + opp1-1508000000 { + opp-hz = /bits/ 64 <1508000000>; + opp-microvolt = <875000>; + required-opps = <&opp2_07>; + }; + opp1-1586000000 { + opp-hz = /bits/ 64 <1586000000>; + opp-microvolt = <900000>; + required-opps = <&opp2_08>; + }; + opp1-1625000000 { + opp-hz = /bits/ 64 <1625000000>; + opp-microvolt = <912500>; + required-opps = <&opp2_09>; + }; + opp1-1677000000 { + opp-hz = /bits/ 64 <1677000000>; + opp-microvolt = <931250>; + required-opps = <&opp2_10>; + }; + opp1-1716000000 { + opp-hz = /bits/ 64 <1716000000>; + opp-microvolt = <950000>; + required-opps = <&opp2_11>; + }; + opp1-1781000000 { + opp-hz = /bits/ 64 <1781000000>; + opp-microvolt = <975000>; + required-opps = <&opp2_12>; + }; + opp1-1846000000 { + opp-hz = /bits/ 64 <1846000000>; + opp-microvolt = <1000000>; + required-opps = <&opp2_13>; + }; + opp1-1924000000 { + opp-hz = /bits/ 64 <1924000000>; + opp-microvolt = <1025000>; + required-opps = <&opp2_14>; + }; + opp1-1989000000 { + opp-hz = /bits/ 64 <1989000000>; + opp-microvolt = <1050000>; + required-opps = <&opp2_15>; + }; + }; + + cci_opp: opp-table-cci { + compatible = "operating-points-v2"; + opp-shared; + opp2_00: opp-273000000 { + opp-hz = /bits/ 64 <273000000>; + opp-microvolt = <650000>; + }; + opp2_01: opp-338000000 { + opp-hz = /bits/ 64 <338000000>; + opp-microvolt = <687500>; + }; + opp2_02: opp-403000000 { + opp-hz = /bits/ 64 <403000000>; + opp-microvolt = <718750>; + }; + opp2_03: opp-463000000 { + opp-hz = /bits/ 64 <463000000>; + opp-microvolt = <756250>; + }; + opp2_04: opp-546000000 { + opp-hz = /bits/ 64 <546000000>; + opp-microvolt = <800000>; + }; + opp2_05: opp-624000000 { + opp-hz = /bits/ 64 <624000000>; + opp-microvolt = <818750>; + }; + opp2_06: opp-689000000 { + opp-hz = /bits/ 64 <689000000>; + opp-microvolt = <850000>; + }; + opp2_07: opp-767000000 { + opp-hz = /bits/ 64 <767000000>; + opp-microvolt = <868750>; + }; + opp2_08: opp-845000000 { + opp-hz = /bits/ 64 <845000000>; + opp-microvolt = <893750>; + }; + opp2_09: opp-871000000 { + opp-hz = /bits/ 64 <871000000>; + opp-microvolt = <906250>; + }; + opp2_10: opp-923000000 { + opp-hz = /bits/ 64 <923000000>; + opp-microvolt = <931250>; + }; + opp2_11: opp-962000000 { + opp-hz = /bits/ 64 <962000000>; + opp-microvolt = <943750>; + }; + opp2_12: opp-1027000000 { + opp-hz = /bits/ 64 <1027000000>; + opp-microvolt = <975000>; + }; + opp2_13: opp-1092000000 { + opp-hz = /bits/ 64 <1092000000>; + opp-microvolt = <1000000>; + }; + opp2_14: opp-1144000000 { + opp-hz = /bits/ 64 <1144000000>; + opp-microvolt = <1025000>; + }; + opp2_15: opp-1196000000 { + opp-hz = /bits/ 64 <1196000000>; + opp-microvolt = <1050000>; + }; + }; + + cci: cci { + compatible = "mediatek,mt8183-cci"; + clocks = <&mcucfg CLK_MCU_BUS_SEL>, + <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; + clock-names = "cci", "intermediate"; + operating-points-v2 = <&cci_opp>; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -85,8 +331,13 @@ enable-method = "psci"; capacity-dmips-mhz = <741>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>; + clocks = <&mcucfg CLK_MCU_MP0_SEL>, + <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; + clock-names = "cpu", "intermediate"; + operating-points-v2 = <&cluster0_opp>; dynamic-power-coefficient = <84>; #cooling-cells = <2>; + mediatek,cci = <&cci>; }; cpu1: cpu@1 { @@ -96,8 +347,13 @@ enable-method = "psci"; capacity-dmips-mhz = <741>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>; + clocks = <&mcucfg CLK_MCU_MP0_SEL>, + <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; + clock-names = "cpu", "intermediate"; + operating-points-v2 = <&cluster0_opp>; dynamic-power-coefficient = <84>; #cooling-cells = <2>; + mediatek,cci = <&cci>; }; cpu2: cpu@2 { @@ -107,8 +363,13 @@ enable-method = "psci"; capacity-dmips-mhz = <741>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>; + clocks = <&mcucfg CLK_MCU_MP0_SEL>, + <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; + clock-names = "cpu", "intermediate"; + operating-points-v2 = <&cluster0_opp>; dynamic-power-coefficient = <84>; #cooling-cells = <2>; + mediatek,cci = <&cci>; }; cpu3: cpu@3 { @@ -118,8 +379,13 @@ enable-method = "psci"; capacity-dmips-mhz = <741>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>; + clocks = <&mcucfg CLK_MCU_MP0_SEL>, + <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; + clock-names = "cpu", "intermediate"; + operating-points-v2 = <&cluster0_opp>; dynamic-power-coefficient = <84>; #cooling-cells = <2>; + mediatek,cci = <&cci>; }; cpu4: cpu@100 { @@ -129,8 +395,13 @@ enable-method = "psci"; capacity-dmips-mhz = <1024>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>; + clocks = <&mcucfg CLK_MCU_MP2_SEL>, + <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; + clock-names = "cpu", "intermediate"; + operating-points-v2 = <&cluster1_opp>; dynamic-power-coefficient = <211>; #cooling-cells = <2>; + mediatek,cci = <&cci>; }; cpu5: cpu@101 { @@ -140,8 +411,13 @@ enable-method = "psci"; capacity-dmips-mhz = <1024>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>; + clocks = <&mcucfg CLK_MCU_MP2_SEL>, + <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; + clock-names = "cpu", "intermediate"; + operating-points-v2 = <&cluster1_opp>; dynamic-power-coefficient = <211>; #cooling-cells = <2>; + mediatek,cci = <&cci>; }; cpu6: cpu@102 { @@ -151,8 +427,13 @@ enable-method = "psci"; capacity-dmips-mhz = <1024>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>; + clocks = <&mcucfg CLK_MCU_MP2_SEL>, + <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; + clock-names = "cpu", "intermediate"; + operating-points-v2 = <&cluster1_opp>; dynamic-power-coefficient = <211>; #cooling-cells = <2>; + mediatek,cci = <&cci>; }; cpu7: cpu@103 { @@ -162,8 +443,13 @@ enable-method = "psci"; capacity-dmips-mhz = <1024>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>; + clocks = <&mcucfg CLK_MCU_MP2_SEL>, + <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; + clock-names = "cpu", "intermediate"; + operating-points-v2 = <&cluster1_opp>; dynamic-power-coefficient = <211>; #cooling-cells = <2>; + mediatek,cci = <&cci>; }; idle-states { @@ -295,8 +581,8 @@ }; psci { - compatible = "arm,psci-1.0"; - method = "smc"; + compatible = "arm,psci-1.0"; + method = "smc"; }; clk26m: oscillator { @@ -321,7 +607,7 @@ compatible = "simple-bus"; ranges; - soc_data: soc_data@8000000 { + soc_data: efuse@8000000 { compatible = "mediatek,mt8183-efuse", "mediatek,efuse"; reg = <0 0x08000000 0 0x0010>; @@ -502,9 +788,9 @@ #power-domain-cells = <0>; }; - power-domain@MT8183_POWER_DOMAIN_MFG_ASYNC { + mfg_async: power-domain@MT8183_POWER_DOMAIN_MFG_ASYNC { reg = <MT8183_POWER_DOMAIN_MFG_ASYNC>; - clocks = <&topckgen CLK_TOP_MUX_MFG>; + clocks = <&topckgen CLK_TOP_MUX_MFG>; clock-names = "mfg"; #address-cells = <1>; #size-cells = <0>; @@ -807,6 +1093,18 @@ status = "disabled"; }; + svs: svs@1100b000 { + compatible = "mediatek,mt8183-svs"; + reg = <0 0x1100b000 0 0x1000>; + interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_LOW>; + clocks = <&infracfg CLK_INFRA_THERM>; + clock-names = "main"; + nvmem-cells = <&svs_calibration>, + <&thermal_calibration>; + nvmem-cell-names = "svs-calibration-data", + "t-calibration-data"; + }; + thermal: thermal@1100b000 { #thermal-sensor-cells = <1>; compatible = "mediatek,mt8183-thermal"; @@ -1150,7 +1448,7 @@ }; ssusb: usb@11201000 { - compatible ="mediatek,mt8183-mtu3", "mediatek,mtu3"; + compatible = "mediatek,mt8183-mtu3", "mediatek,mtu3"; reg = <0 0x11201000 0 0x2e00>, <0 0x11203e00 0 0x0100>; reg-names = "mac", "ippc"; @@ -1325,6 +1623,10 @@ mipi_tx_calibration: calib@190 { reg = <0x190 0xc>; }; + + svs_calibration: calib@580 { + reg = <0x580 0x64>; + }; }; u3phy: t-phy@11f40000 { @@ -1508,6 +1810,7 @@ power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; mediatek,gce-events = <CMDQ_EVENT_MUTEX_STREAM_DONE0>, <CMDQ_EVENT_MUTEX_STREAM_DONE1>; + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x6000 0x1000>; }; larb0: larb@14017000 { diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r1.dts b/arch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r1.dts new file mode 100644 index 000000000000..1e91491945f6 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r1.dts @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2020 Google LLC + */ +/dts-v1/; +#include "mt8192-asurada.dtsi" + +/ { + model = "Google Hayato rev1"; + compatible = "google,hayato-rev1", "google,hayato", "mediatek,mt8192"; +}; + +&keyboard_controller { + function-row-physmap = < + MATRIX_KEY(0x00, 0x02, 0) /* T1 */ + MATRIX_KEY(0x03, 0x02, 0) /* T2 */ + MATRIX_KEY(0x02, 0x02, 0) /* T3 */ + MATRIX_KEY(0x01, 0x02, 0) /* T4 */ + MATRIX_KEY(0x03, 0x04, 0) /* T5 */ + MATRIX_KEY(0x02, 0x04, 0) /* T6 */ + MATRIX_KEY(0x01, 0x04, 0) /* T7 */ + MATRIX_KEY(0x02, 0x09, 0) /* T8 */ + MATRIX_KEY(0x01, 0x09, 0) /* T9 */ + MATRIX_KEY(0x00, 0x04, 0) /* T10 */ + >; + linux,keymap = < + MATRIX_KEY(0x00, 0x02, KEY_BACK) + MATRIX_KEY(0x03, 0x02, KEY_FORWARD) + MATRIX_KEY(0x02, 0x02, KEY_REFRESH) + MATRIX_KEY(0x01, 0x02, KEY_FULL_SCREEN) + MATRIX_KEY(0x03, 0x04, KEY_SCALE) + MATRIX_KEY(0x02, 0x04, KEY_BRIGHTNESSDOWN) + MATRIX_KEY(0x01, 0x04, KEY_BRIGHTNESSUP) + MATRIX_KEY(0x02, 0x09, KEY_MUTE) + MATRIX_KEY(0x01, 0x09, KEY_VOLUMEDOWN) + MATRIX_KEY(0x00, 0x04, KEY_VOLUMEUP) + + CROS_STD_MAIN_KEYMAP + >; +}; + +&touchscreen { + compatible = "hid-over-i2c"; + post-power-on-delay-ms = <10>; + hid-descr-addr = <0x0001>; + vdd-supply = <&pp3300_u>; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts b/arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts new file mode 100644 index 000000000000..fa3d9573f37a --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts @@ -0,0 +1,62 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2021 Google LLC + */ +/dts-v1/; +#include "mt8192-asurada.dtsi" +#include <dt-bindings/leds/common.h> + +/ { + model = "Google Spherion (rev0 - 3)"; + compatible = "google,spherion-rev3", "google,spherion-rev2", + "google,spherion-rev1", "google,spherion-rev0", + "google,spherion", "mediatek,mt8192"; + + pwmleds { + compatible = "pwm-leds"; + + led { + function = LED_FUNCTION_KBD_BACKLIGHT; + color = <LED_COLOR_ID_WHITE>; + pwms = <&cros_ec_pwm 0>; + max-brightness = <1023>; + }; + }; +}; + +&cros_ec_pwm { + status = "okay"; +}; + +&keyboard_controller { + function-row-physmap = < + MATRIX_KEY(0x00, 0x02, 0) /* T1 */ + MATRIX_KEY(0x03, 0x02, 0) /* T2 */ + MATRIX_KEY(0x02, 0x02, 0) /* T3 */ + MATRIX_KEY(0x01, 0x02, 0) /* T4 */ + MATRIX_KEY(0x03, 0x04, 0) /* T5 */ + MATRIX_KEY(0x02, 0x04, 0) /* T6 */ + MATRIX_KEY(0x01, 0x04, 0) /* T7 */ + MATRIX_KEY(0x02, 0x09, 0) /* T8 */ + MATRIX_KEY(0x01, 0x09, 0) /* T9 */ + MATRIX_KEY(0x00, 0x04, 0) /* T10 */ + >; + linux,keymap = < + MATRIX_KEY(0x00, 0x02, KEY_BACK) + MATRIX_KEY(0x03, 0x02, KEY_REFRESH) + MATRIX_KEY(0x02, 0x02, KEY_FULL_SCREEN) + MATRIX_KEY(0x01, 0x02, KEY_SCALE) + MATRIX_KEY(0x03, 0x04, KEY_SYSRQ) + MATRIX_KEY(0x02, 0x04, KEY_BRIGHTNESSDOWN) + MATRIX_KEY(0x01, 0x04, KEY_BRIGHTNESSUP) + MATRIX_KEY(0x02, 0x09, KEY_MUTE) + MATRIX_KEY(0x01, 0x09, KEY_VOLUMEDOWN) + MATRIX_KEY(0x00, 0x04, KEY_VOLUMEUP) + + CROS_STD_MAIN_KEYMAP + >; +}; + +&touchscreen { + compatible = "elan,ekth3500"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi new file mode 100644 index 000000000000..4b314435f8fd --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi @@ -0,0 +1,959 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2020 MediaTek Inc. + * Author: Seiya Wang <seiya.wang@mediatek.com> + */ +/dts-v1/; +#include "mt8192.dtsi" +#include "mt6359.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/spmi/spmi.h> + +/ { + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0 0x80000000>; + }; + + /* system wide LDO 1.8V power rail */ + pp1800_ldo_g: regulator-1v8-g { + compatible = "regulator-fixed"; + regulator-name = "pp1800_ldo_g"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&pp3300_g>; + }; + + /* system wide switching 3.3V power rail */ + pp3300_g: regulator-3v3-g { + compatible = "regulator-fixed"; + regulator-name = "pp3300_g"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&ppvar_sys>; + }; + + /* system wide LDO 3.3V power rail */ + pp3300_ldo_z: regulator-3v3-z { + compatible = "regulator-fixed"; + regulator-name = "pp3300_ldo_z"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&ppvar_sys>; + }; + + /* separately switched 3.3V power rail */ + pp3300_u: regulator-3v3-u { + compatible = "regulator-fixed"; + regulator-name = "pp3300_u"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + /* enable pin wired to GPIO controlled by EC */ + vin-supply = <&pp3300_g>; + }; + + pp3300_wlan: regulator-3v3-wlan { + compatible = "regulator-fixed"; + regulator-name = "pp3300_wlan"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + pinctrl-names = "default"; + pinctrl-0 = <&pp3300_wlan_pins>; + enable-active-high; + gpio = <&pio 143 GPIO_ACTIVE_HIGH>; + }; + + /* system wide switching 5.0V power rail */ + pp5000_a: regulator-5v0-a { + compatible = "regulator-fixed"; + regulator-name = "pp5000_a"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&ppvar_sys>; + }; + + /* system wide semi-regulated power rail from battery or USB */ + ppvar_sys: regulator-var-sys { + compatible = "regulator-fixed"; + regulator-name = "ppvar_sys"; + regulator-always-on; + regulator-boot-on; + }; + + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + scp_mem_reserved: scp@50000000 { + compatible = "shared-dma-pool"; + reg = <0 0x50000000 0 0x2900000>; + no-map; + }; + + wifi_restricted_dma_region: wifi@c0000000 { + compatible = "restricted-dma-pool"; + reg = <0 0xc0000000 0 0x4000000>; + }; + }; +}; + +&i2c0 { + status = "okay"; + + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + + touchscreen: touchscreen@10 { + reg = <0x10>; + interrupts-extended = <&pio 21 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&touchscreen_pins>; + }; +}; + +&i2c1 { + status = "okay"; + + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; +}; + +&i2c2 { + status = "okay"; + + clock-frequency = <400000>; + clock-stretch-ns = <12600>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; + + trackpad@15 { + compatible = "elan,ekth3000"; + reg = <0x15>; + interrupts-extended = <&pio 15 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&trackpad_pins>; + vcc-supply = <&pp3300_u>; + wakeup-source; + }; +}; + +&i2c3 { + status = "okay"; + + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pins>; +}; + +&i2c7 { + status = "okay"; + + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c7_pins>; +}; + +&mmc0 { + status = "okay"; + + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc0_default_pins>; + pinctrl-1 = <&mmc0_uhs_pins>; + bus-width = <8>; + max-frequency = <200000000>; + vmmc-supply = <&mt6359_vemc_1_ldo_reg>; + vqmmc-supply = <&mt6359_vufs_ldo_reg>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + supports-cqe; + cap-mmc-hw-reset; + mmc-hs400-enhanced-strobe; + hs400-ds-delay = <0x12814>; + no-sdio; + no-sd; + non-removable; +}; + +&mmc1 { + status = "okay"; + + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc1_default_pins>; + pinctrl-1 = <&mmc1_uhs_pins>; + bus-width = <4>; + max-frequency = <200000000>; + cd-gpios = <&pio 17 GPIO_ACTIVE_LOW>; + vmmc-supply = <&mt6360_ldo5_reg>; + vqmmc-supply = <&mt6360_ldo3_reg>; + cap-sd-highspeed; + sd-uhs-sdr50; + sd-uhs-sdr104; + no-sdio; + no-mmc; +}; + +/* for CORE */ +&mt6359_vgpu11_buck_reg { + regulator-always-on; +}; + +&mt6359_vgpu11_sshub_buck_reg { + regulator-always-on; + regulator-min-microvolt = <575000>; + regulator-max-microvolt = <575000>; +}; + +&mt6359_vrf12_ldo_reg { + regulator-always-on; +}; + +&mt6359_vufs_ldo_reg { + regulator-always-on; +}; + +&mt6359codec { + mediatek,dmic-mode = <1>; /* one-wire */ + mediatek,mic-type-0 = <2>; /* DMIC */ + mediatek,mic-type-2 = <2>; /* DMIC */ +}; + +&nor_flash { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&nor_flash_pins>; + assigned-clocks = <&topckgen CLK_TOP_SFLASH_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6_D8>; + + flash@0 { + compatible = "winbond,w25q64jwm", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <52000000>; + spi-rx-bus-width = <2>; + spi-tx-bus-width = <2>; + }; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pcie_pins>; + + pcie0: pcie@0,0 { + device_type = "pci"; + reg = <0x0000 0 0 0 0>; + num-lanes = <1>; + bus-range = <0x1 0x1>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + + wifi: wifi@0,0 { + reg = <0x10000 0 0 0 0x100000>, + <0x10000 0 0x100000 0 0x100000>; + memory-region = <&wifi_restricted_dma_region>; + }; + }; +}; + +&pio { + /* 220 lines */ + gpio-line-names = "I2S_DP_LRCK", + "IS_DP_BCLK", + "I2S_DP_MCLK", + "I2S_DP_DATAOUT", + "SAR0_INT_ODL", + "EC_AP_INT_ODL", + "EDPBRDG_INT_ODL", + "DPBRDG_INT_ODL", + "DPBRDG_PWREN", + "DPBRDG_RST_ODL", + "I2S_HP_MCLK", + "I2S_HP_BCK", + "I2S_HP_LRCK", + "I2S_HP_DATAIN", + /* + * AP_FLASH_WP_L is crossystem ABI. Schematics + * call it AP_FLASH_WP_ODL. + */ + "AP_FLASH_WP_L", + "TRACKPAD_INT_ODL", + "EC_AP_HPD_OD", + "SD_CD_ODL", + "HP_INT_ODL_ALC", + "EN_PP1000_DPBRDG", + "AP_GPIO20", + "TOUCH_INT_L_1V8", + "UART_BT_WAKE_ODL", + "AP_GPIO23", + "AP_SPI_FLASH_CS_L", + "AP_SPI_FLASH_CLK", + "EN_PP3300_DPBRDG_DX", + "AP_SPI_FLASH_MOSI", + "AP_SPI_FLASH_MISO", + "I2S_HP_DATAOUT", + "AP_GPIO30", + "I2S_SPKR_MCLK", + "I2S_SPKR_BCLK", + "I2S_SPKR_LRCK", + "I2S_SPKR_DATAIN", + "I2S_SPKR_DATAOUT", + "AP_SPI_H1_TPM_CLK", + "AP_SPI_H1_TPM_CS_L", + "AP_SPI_H1_TPM_MISO", + "AP_SPI_H1_TPM_MOSI", + "BL_PWM", + "EDPBRDG_PWREN", + "EDPBRDG_RST_ODL", + "EN_PP3300_HUB", + "HUB_RST_L", + "", + "", + "", + "", + "", + "", + "SD_CLK", + "SD_CMD", + "SD_DATA3", + "SD_DATA0", + "SD_DATA2", + "SD_DATA1", + "", + "", + "", + "", + "", + "", + "PCIE_WAKE_ODL", + "PCIE_RST_L", + "PCIE_CLKREQ_ODL", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "SPMI_SCL", + "SPMI_SDA", + "AP_GOOD", + "UART_DBG_TX_AP_RX", + "UART_AP_TX_DBG_RX", + "UART_AP_TX_BT_RX", + "UART_BT_TX_AP_RX", + "MIPI_DPI_D0_R", + "MIPI_DPI_D1_R", + "MIPI_DPI_D2_R", + "MIPI_DPI_D3_R", + "MIPI_DPI_D4_R", + "MIPI_DPI_D5_R", + "MIPI_DPI_D6_R", + "MIPI_DPI_D7_R", + "MIPI_DPI_D8_R", + "MIPI_DPI_D9_R", + "MIPI_DPI_D10_R", + "", + "", + "MIPI_DPI_DE_R", + "MIPI_DPI_D11_R", + "MIPI_DPI_VSYNC_R", + "MIPI_DPI_CLK_R", + "MIPI_DPI_HSYNC_R", + "PCM_BT_DATAIN", + "PCM_BT_SYNC", + "PCM_BT_DATAOUT", + "PCM_BT_CLK", + "AP_I2C_AUDIO_SCL", + "AP_I2C_AUDIO_SDA", + "SCP_I2C_SCL", + "SCP_I2C_SDA", + "AP_I2C_WLAN_SCL", + "AP_I2C_WLAN_SDA", + "AP_I2C_DPBRDG_SCL", + "AP_I2C_DPBRDG_SDA", + "EN_PP1800_DPBRDG_DX", + "EN_PP3300_EDP_DX", + "EN_PP1800_EDPBRDG_DX", + "EN_PP1000_EDPBRDG", + "SCP_JTAG0_TDO", + "SCP_JTAG0_TDI", + "SCP_JTAG0_TMS", + "SCP_JTAG0_TCK", + "SCP_JTAG0_TRSTN", + "EN_PP3000_VMC_PMU", + "EN_PP3300_DISPLAY_DX", + "TOUCH_RST_L_1V8", + "TOUCH_REPORT_DISABLE", + "", + "", + "AP_I2C_TRACKPAD_SCL_1V8", + "AP_I2C_TRACKPAD_SDA_1V8", + "EN_PP3300_WLAN", + "BT_KILL_L", + "WIFI_KILL_L", + "SET_VMC_VOLT_AT_1V8", + "EN_SPK", + "AP_WARM_RST_REQ", + "", + "", + "EN_PP3000_SD_S3", + "AP_EDP_BKLTEN", + "", + "", + "", + "AP_SPI_EC_CLK", + "AP_SPI_EC_CS_L", + "AP_SPI_EC_MISO", + "AP_SPI_EC_MOSI", + "AP_I2C_EDPBRDG_SCL", + "AP_I2C_EDPBRDG_SDA", + "MT6315_PROC_INT", + "MT6315_GPU_INT", + "UART_SERVO_TX_SCP_RX", + "UART_SCP_TX_SERVO_RX", + "BT_RTS_AP_CTS", + "AP_RTS_BT_CTS", + "UART_AP_WAKE_BT_ODL", + "WLAN_ALERT_ODL", + "EC_IN_RW_ODL", + "H1_AP_INT_ODL", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "MSDC0_CMD", + "MSDC0_DAT0", + "MSDC0_DAT2", + "MSDC0_DAT4", + "MSDC0_DAT6", + "MSDC0_DAT1", + "MSDC0_DAT5", + "MSDC0_DAT7", + "MSDC0_DSL", + "MSDC0_CLK", + "MSDC0_DAT3", + "MSDC0_RST_L", + "SCP_VREQ_VAO", + "AUD_DAT_MOSI2", + "AUD_NLE_MOSI1", + "AUD_NLE_MOSI0", + "AUD_DAT_MISO2", + "AP_I2C_SAR_SDA", + "AP_I2C_SAR_SCL", + "AP_I2C_PWR_SCL", + "AP_I2C_PWR_SDA", + "AP_I2C_TS_SCL_1V8", + "AP_I2C_TS_SDA_1V8", + "SRCLKENA0", + "SRCLKENA1", + "AP_EC_WATCHDOG_L", + "PWRAP_SPI0_MI", + "PWRAP_SPI0_CSN", + "PWRAP_SPI0_MO", + "PWRAP_SPI0_CK", + "AP_RTC_CLK32K", + "AUD_CLK_MOSI", + "AUD_SYNC_MOSI", + "AUD_DAT_MOSI0", + "AUD_DAT_MOSI1", + "AUD_DAT_MISO0", + "AUD_DAT_MISO1"; + + cr50_int: cr50-irq-default-pins { + pins-gsc-ap-int-odl { + pinmux = <PINMUX_GPIO171__FUNC_GPIO171>; + input-enable; + }; + }; + + cros_ec_int: cros-ec-irq-default-pins { + pins-ec-ap-int-odl { + pinmux = <PINMUX_GPIO5__FUNC_GPIO5>; + input-enable; + bias-pull-up; + }; + }; + + i2c0_pins: i2c0-default-pins { + pins-bus { + pinmux = <PINMUX_GPIO204__FUNC_SCL0>, + <PINMUX_GPIO205__FUNC_SDA0>; + bias-pull-up = <MTK_PULL_SET_RSEL_011>; + drive-strength-microamp = <1000>; + }; + }; + + i2c1_pins: i2c1-default-pins { + pins-bus { + pinmux = <PINMUX_GPIO118__FUNC_SCL1>, + <PINMUX_GPIO119__FUNC_SDA1>; + bias-pull-up = <MTK_PULL_SET_RSEL_011>; + drive-strength-microamp = <1000>; + }; + }; + + i2c2_pins: i2c2-default-pins { + pins-bus { + pinmux = <PINMUX_GPIO141__FUNC_SCL2>, + <PINMUX_GPIO142__FUNC_SDA2>; + bias-pull-up = <MTK_PULL_SET_RSEL_011>; + }; + }; + + i2c3_pins: i2c3-default-pins { + pins-bus { + pinmux = <PINMUX_GPIO160__FUNC_SCL3>, + <PINMUX_GPIO161__FUNC_SDA3>; + bias-disable; + drive-strength-microamp = <1000>; + }; + }; + + i2c7_pins: i2c7-default-pins { + pins-bus { + pinmux = <PINMUX_GPIO124__FUNC_SCL7>, + <PINMUX_GPIO125__FUNC_SDA7>; + bias-disable; + drive-strength-microamp = <1000>; + }; + }; + + mmc0_default_pins: mmc0-default-pins { + pins-cmd-dat { + pinmux = <PINMUX_GPIO184__FUNC_MSDC0_DAT0>, + <PINMUX_GPIO188__FUNC_MSDC0_DAT1>, + <PINMUX_GPIO185__FUNC_MSDC0_DAT2>, + <PINMUX_GPIO193__FUNC_MSDC0_DAT3>, + <PINMUX_GPIO186__FUNC_MSDC0_DAT4>, + <PINMUX_GPIO189__FUNC_MSDC0_DAT5>, + <PINMUX_GPIO187__FUNC_MSDC0_DAT6>, + <PINMUX_GPIO190__FUNC_MSDC0_DAT7>, + <PINMUX_GPIO183__FUNC_MSDC0_CMD>; + input-enable; + drive-strength = <8>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + }; + + pins-clk { + pinmux = <PINMUX_GPIO192__FUNC_MSDC0_CLK>; + drive-strength = <8>; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; + }; + + pins-rst { + pinmux = <PINMUX_GPIO194__FUNC_MSDC0_RSTB>; + drive-strength = <8>; + bias-pull-down = <MTK_PUPD_SET_R1R0_01>; + }; + }; + + mmc0_uhs_pins: mmc0-uhs-pins { + pins-cmd-dat { + pinmux = <PINMUX_GPIO184__FUNC_MSDC0_DAT0>, + <PINMUX_GPIO188__FUNC_MSDC0_DAT1>, + <PINMUX_GPIO185__FUNC_MSDC0_DAT2>, + <PINMUX_GPIO193__FUNC_MSDC0_DAT3>, + <PINMUX_GPIO186__FUNC_MSDC0_DAT4>, + <PINMUX_GPIO189__FUNC_MSDC0_DAT5>, + <PINMUX_GPIO187__FUNC_MSDC0_DAT6>, + <PINMUX_GPIO190__FUNC_MSDC0_DAT7>, + <PINMUX_GPIO183__FUNC_MSDC0_CMD>; + input-enable; + drive-strength = <10>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + }; + + pins-clk { + pinmux = <PINMUX_GPIO192__FUNC_MSDC0_CLK>; + drive-strength = <10>; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; + }; + + pins-rst { + pinmux = <PINMUX_GPIO194__FUNC_MSDC0_RSTB>; + drive-strength = <8>; + bias-pull-down = <MTK_PUPD_SET_R1R0_01>; + }; + + pins-ds { + pinmux = <PINMUX_GPIO191__FUNC_MSDC0_DSL>; + drive-strength = <10>; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; + }; + }; + + mmc1_default_pins: mmc1-default-pins { + pins-cmd-dat { + pinmux = <PINMUX_GPIO54__FUNC_MSDC1_DAT0>, + <PINMUX_GPIO56__FUNC_MSDC1_DAT1>, + <PINMUX_GPIO55__FUNC_MSDC1_DAT2>, + <PINMUX_GPIO53__FUNC_MSDC1_DAT3>, + <PINMUX_GPIO52__FUNC_MSDC1_CMD>; + input-enable; + drive-strength = <8>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + }; + + pins-clk { + pinmux = <PINMUX_GPIO51__FUNC_MSDC1_CLK>; + drive-strength = <8>; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; + }; + + pins-insert { + pinmux = <PINMUX_GPIO17__FUNC_GPIO17>; + input-enable; + bias-pull-up; + }; + }; + + mmc1_uhs_pins: mmc1-uhs-pins { + pins-cmd-dat { + pinmux = <PINMUX_GPIO54__FUNC_MSDC1_DAT0>, + <PINMUX_GPIO56__FUNC_MSDC1_DAT1>, + <PINMUX_GPIO55__FUNC_MSDC1_DAT2>, + <PINMUX_GPIO53__FUNC_MSDC1_DAT3>, + <PINMUX_GPIO52__FUNC_MSDC1_CMD>; + input-enable; + drive-strength = <8>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + }; + + pins-clk { + pinmux = <PINMUX_GPIO51__FUNC_MSDC1_CLK>; + input-enable; + drive-strength = <8>; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; + }; + }; + + nor_flash_pins: nor-flash-default-pins { + pins-cs-io1 { + pinmux = <PINMUX_GPIO24__FUNC_SPINOR_CS>, + <PINMUX_GPIO28__FUNC_SPINOR_IO1>; + input-enable; + bias-pull-up; + drive-strength = <10>; + }; + + pins-io0 { + pinmux = <PINMUX_GPIO27__FUNC_SPINOR_IO0>; + bias-pull-up; + drive-strength = <10>; + }; + + pins-clk { + pinmux = <PINMUX_GPIO25__FUNC_SPINOR_CK>; + input-enable; + bias-pull-up; + drive-strength = <10>; + }; + }; + + pcie_pins: pcie-default-pins { + pins-pcie-wake { + pinmux = <PINMUX_GPIO63__FUNC_PCIE_WAKE_N>; + bias-pull-up; + }; + + pins-pcie-pereset { + pinmux = <PINMUX_GPIO64__FUNC_PCIE_PERESET_N>; + }; + + pins-pcie-clkreq { + pinmux = <PINMUX_GPIO65__FUNC_PCIE_CLKREQ_N>; + bias-pull-up; + }; + + pins-wifi-kill { + pinmux = <PINMUX_GPIO145__FUNC_GPIO145>; /* WIFI_KILL_L */ + output-high; + }; + }; + + pp3300_wlan_pins: pp3300-wlan-pins { + pins-pcie-en-pp3300-wlan { + pinmux = <PINMUX_GPIO143__FUNC_GPIO143>; + output-high; + }; + }; + + scp_pins: scp-pins { + pins-vreq-vao { + pinmux = <PINMUX_GPIO195__FUNC_SCP_VREQ_VAO>; + }; + }; + + spi1_pins: spi1-default-pins { + pins-cs-mosi-clk { + pinmux = <PINMUX_GPIO157__FUNC_SPI1_A_CSB>, + <PINMUX_GPIO159__FUNC_SPI1_A_MO>, + <PINMUX_GPIO156__FUNC_SPI1_A_CLK>; + bias-disable; + }; + + pins-miso { + pinmux = <PINMUX_GPIO158__FUNC_SPI1_A_MI>; + bias-pull-down; + }; + }; + + spi5_pins: spi5-default-pins { + pins-bus { + pinmux = <PINMUX_GPIO38__FUNC_SPI5_A_MI>, + <PINMUX_GPIO37__FUNC_GPIO37>, + <PINMUX_GPIO39__FUNC_SPI5_A_MO>, + <PINMUX_GPIO36__FUNC_SPI5_A_CLK>; + bias-disable; + }; + }; + + trackpad_pins: trackpad-default-pins { + pins-int-n { + pinmux = <PINMUX_GPIO15__FUNC_GPIO15>; + input-enable; + bias-pull-up = <MTK_PUPD_SET_R1R0_11>; + }; + }; + + touchscreen_pins: touchscreen-default-pins { + pins-irq { + pinmux = <PINMUX_GPIO21__FUNC_GPIO21>; + input-enable; + bias-pull-up; + }; + + pins-reset { + pinmux = <PINMUX_GPIO137__FUNC_GPIO137>; + output-high; + }; + + pins-report-sw { + pinmux = <PINMUX_GPIO138__FUNC_GPIO138>; + output-low; + }; + }; +}; + +&pmic { + interrupts-extended = <&pio 214 IRQ_TYPE_LEVEL_HIGH>; +}; + +&scp { + status = "okay"; + + firmware-name = "mediatek/mt8192/scp.img"; + memory-region = <&scp_mem_reserved>; + pinctrl-names = "default"; + pinctrl-0 = <&scp_pins>; + + cros-ec { + compatible = "google,cros-ec-rpmsg"; + mediatek,rpmsg-name = "cros-ec-rpmsg"; + }; +}; + +&spi1 { + status = "okay"; + + mediatek,pad-select = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&spi1_pins>; + + cros_ec: ec@0 { + compatible = "google,cros-ec-spi"; + reg = <0>; + interrupts-extended = <&pio 5 IRQ_TYPE_LEVEL_LOW>; + spi-max-frequency = <3000000>; + pinctrl-names = "default"; + pinctrl-0 = <&cros_ec_int>; + + #address-cells = <1>; + #size-cells = <0>; + + base_detection: cbas { + compatible = "google,cros-cbas"; + }; + + cros_ec_pwm: pwm { + compatible = "google,cros-ec-pwm"; + #pwm-cells = <1>; + + status = "disabled"; + }; + + i2c_tunnel: i2c-tunnel { + compatible = "google,cros-ec-i2c-tunnel"; + google,remote-bus = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mt6360_ldo3_reg: regulator@0 { + compatible = "google,cros-ec-regulator"; + reg = <0>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + mt6360_ldo5_reg: regulator@1 { + compatible = "google,cros-ec-regulator"; + reg = <1>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + typec { + compatible = "google,cros-ec-typec"; + #address-cells = <1>; + #size-cells = <0>; + + usb_c0: connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + label = "left"; + power-role = "dual"; + data-role = "host"; + try-power-role = "source"; + }; + + usb_c1: connector@1 { + compatible = "usb-c-connector"; + reg = <1>; + label = "right"; + power-role = "dual"; + data-role = "host"; + try-power-role = "source"; + }; + }; + }; +}; + +&spi5 { + status = "okay"; + + cs-gpios = <&pio 37 GPIO_ACTIVE_LOW>; + mediatek,pad-select = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&spi5_pins>; + + cr50@0 { + compatible = "google,cr50"; + reg = <0>; + interrupts-extended = <&pio 171 IRQ_TYPE_EDGE_RISING>; + spi-max-frequency = <1000000>; + pinctrl-names = "default"; + pinctrl-0 = <&cr50_int>; + }; +}; + +&spmi { + #address-cells = <2>; + #size-cells = <0>; + + mt6315_6: pmic@6 { + compatible = "mediatek,mt6315-regulator"; + reg = <0x6 SPMI_USID>; + + regulators { + mt6315_6_vbuck1: vbuck1 { + regulator-compatible = "vbuck1"; + regulator-name = "Vbcpu"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1193750>; + regulator-enable-ramp-delay = <256>; + regulator-allowed-modes = <0 1 2>; + regulator-always-on; + }; + + mt6315_6_vbuck3: vbuck3 { + regulator-compatible = "vbuck3"; + regulator-name = "Vlcpu"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1193750>; + regulator-enable-ramp-delay = <256>; + regulator-allowed-modes = <0 1 2>; + regulator-always-on; + }; + }; + }; + + mt6315_7: pmic@7 { + compatible = "mediatek,mt6315-regulator"; + reg = <0x7 SPMI_USID>; + + regulators { + mt6315_7_vbuck1: vbuck1 { + regulator-compatible = "vbuck1"; + regulator-name = "Vgpu"; + regulator-min-microvolt = <606250>; + regulator-max-microvolt = <1193750>; + regulator-enable-ramp-delay = <256>; + regulator-allowed-modes = <0 1 2>; + }; + }; + }; +}; + +&uart0 { + status = "okay"; +}; + +&xhci { + status = "okay"; + + wakeup-source; + vusb33-supply = <&pp3300_g>; + vbus-supply = <&pp5000_a>; +}; + +#include <arm/cros-ec-keyboard.dtsi> +#include <arm/cros-ec-sbs.dtsi> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index 733aec2e7f77..cbae5a5ee4a0 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -43,7 +43,7 @@ reg = <0x000>; enable-method = "psci"; clock-frequency = <1701000000>; - cpu-idle-states = <&cpuoff_l &clusteroff_l>; + cpu-idle-states = <&cpu_sleep_l &cluster_sleep_l>; next-level-cache = <&l2_0>; capacity-dmips-mhz = <530>; }; @@ -54,7 +54,7 @@ reg = <0x100>; enable-method = "psci"; clock-frequency = <1701000000>; - cpu-idle-states = <&cpuoff_l &clusteroff_l>; + cpu-idle-states = <&cpu_sleep_l &cluster_sleep_l>; next-level-cache = <&l2_0>; capacity-dmips-mhz = <530>; }; @@ -65,7 +65,7 @@ reg = <0x200>; enable-method = "psci"; clock-frequency = <1701000000>; - cpu-idle-states = <&cpuoff_l &clusteroff_l>; + cpu-idle-states = <&cpu_sleep_l &cluster_sleep_l>; next-level-cache = <&l2_0>; capacity-dmips-mhz = <530>; }; @@ -76,7 +76,7 @@ reg = <0x300>; enable-method = "psci"; clock-frequency = <1701000000>; - cpu-idle-states = <&cpuoff_l &clusteroff_l>; + cpu-idle-states = <&cpu_sleep_l &cluster_sleep_l>; next-level-cache = <&l2_0>; capacity-dmips-mhz = <530>; }; @@ -87,7 +87,7 @@ reg = <0x400>; enable-method = "psci"; clock-frequency = <2171000000>; - cpu-idle-states = <&cpuoff_b &clusteroff_b>; + cpu-idle-states = <&cpu_sleep_b &cluster_sleep_b>; next-level-cache = <&l2_1>; capacity-dmips-mhz = <1024>; }; @@ -98,7 +98,7 @@ reg = <0x500>; enable-method = "psci"; clock-frequency = <2171000000>; - cpu-idle-states = <&cpuoff_b &clusteroff_b>; + cpu-idle-states = <&cpu_sleep_b &cluster_sleep_b>; next-level-cache = <&l2_1>; capacity-dmips-mhz = <1024>; }; @@ -109,7 +109,7 @@ reg = <0x600>; enable-method = "psci"; clock-frequency = <2171000000>; - cpu-idle-states = <&cpuoff_b &clusteroff_b>; + cpu-idle-states = <&cpu_sleep_b &cluster_sleep_b>; next-level-cache = <&l2_1>; capacity-dmips-mhz = <1024>; }; @@ -120,7 +120,7 @@ reg = <0x700>; enable-method = "psci"; clock-frequency = <2171000000>; - cpu-idle-states = <&cpuoff_b &clusteroff_b>; + cpu-idle-states = <&cpu_sleep_b &cluster_sleep_b>; next-level-cache = <&l2_1>; capacity-dmips-mhz = <1024>; }; @@ -172,8 +172,8 @@ }; idle-states { - entry-method = "arm,psci"; - cpuoff_l: cpuoff_l { + entry-method = "psci"; + cpu_sleep_l: cpu-sleep-l { compatible = "arm,idle-state"; arm,psci-suspend-param = <0x00010001>; local-timer-stop; @@ -181,7 +181,7 @@ exit-latency-us = <140>; min-residency-us = <780>; }; - cpuoff_b: cpuoff_b { + cpu_sleep_b: cpu-sleep-b { compatible = "arm,idle-state"; arm,psci-suspend-param = <0x00010001>; local-timer-stop; @@ -189,7 +189,7 @@ exit-latency-us = <145>; min-residency-us = <720>; }; - clusteroff_l: clusteroff_l { + cluster_sleep_l: cluster-sleep-l { compatible = "arm,idle-state"; arm,psci-suspend-param = <0x01010002>; local-timer-stop; @@ -197,7 +197,7 @@ exit-latency-us = <155>; min-residency-us = <860>; }; - clusteroff_b: clusteroff_b { + cluster_sleep_b: cluster-sleep-b { compatible = "arm,idle-state"; arm,psci-suspend-param = <0x01010002>; local-timer-stop; @@ -271,6 +271,7 @@ compatible = "mediatek,mt8192-infracfg", "syscon"; reg = <0 0x10001000 0 0x1000>; #clock-cells = <1>; + #reset-cells = <1>; }; pericfg: syscon@10003000 { @@ -911,7 +912,7 @@ }; efuse: efuse@11c10000 { - compatible = "mediatek,efuse"; + compatible = "mediatek,mt8192-efuse", "mediatek,efuse"; reg = <0 0x11c10000 0 0x1000>; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r1.dts b/arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r1.dts new file mode 100644 index 000000000000..3348ba69ff6c --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r1.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2021 MediaTek Inc. + */ +/dts-v1/; +#include "mt8195-cherry.dtsi" + +/ { + model = "Acer Tomato (rev1) board"; + compatible = "google,tomato-rev1", "google,tomato", "mediatek,mt8195"; +}; + +&ts_10 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r2.dts b/arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r2.dts new file mode 100644 index 000000000000..4669e9d917f8 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r2.dts @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2021 MediaTek Inc. + */ +/dts-v1/; +#include "mt8195-cherry.dtsi" + +/ { + model = "Acer Tomato (rev2) board"; + compatible = "google,tomato-rev2", "google,tomato", "mediatek,mt8195"; +}; + +&pio_default { + pins-low-power-hdmi-disable { + pinmux = <PINMUX_GPIO31__FUNC_GPIO31>, + <PINMUX_GPIO32__FUNC_GPIO32>, + <PINMUX_GPIO33__FUNC_GPIO33>, + <PINMUX_GPIO34__FUNC_GPIO34>, + <PINMUX_GPIO35__FUNC_GPIO35>; + input-enable; + bias-pull-down; + }; + + pins-low-power-pcie0-disable { + pinmux = <PINMUX_GPIO19__FUNC_GPIO19>, + <PINMUX_GPIO20__FUNC_GPIO20>, + <PINMUX_GPIO21__FUNC_GPIO21>; + input-enable; + bias-pull-down; + }; +}; + +&ts_10 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r3.dts b/arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r3.dts new file mode 100644 index 000000000000..5021edd02f7c --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r3.dts @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2021 MediaTek Inc. + */ +/dts-v1/; +#include "mt8195-cherry.dtsi" + +/ { + model = "Acer Tomato (rev3 - 4) board"; + compatible = "google,tomato-rev4", "google,tomato-rev3", + "google,tomato", "mediatek,mt8195"; +}; + +&pio_default { + pins-low-power-hdmi-disable { + pinmux = <PINMUX_GPIO31__FUNC_GPIO31>, + <PINMUX_GPIO32__FUNC_GPIO32>, + <PINMUX_GPIO33__FUNC_GPIO33>, + <PINMUX_GPIO34__FUNC_GPIO34>, + <PINMUX_GPIO35__FUNC_GPIO35>; + input-enable; + bias-pull-down; + }; + + pins-low-power-pcie0-disable { + pinmux = <PINMUX_GPIO19__FUNC_GPIO19>, + <PINMUX_GPIO20__FUNC_GPIO20>, + <PINMUX_GPIO21__FUNC_GPIO21>; + input-enable; + bias-pull-down; + }; +}; + +&ts_10 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi new file mode 100644 index 000000000000..fcc600674339 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi @@ -0,0 +1,702 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2021 MediaTek Inc. + */ + +#include <dt-bindings/gpio/gpio.h> +#include "mt8195.dtsi" +#include "mt6359.dtsi" + +/ { + aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + i2c7 = &i2c7; + mmc0 = &mmc0; + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0 0x80000000>; + }; + + /* system wide LDO 3.3V power rail */ + pp3300_z5: regulator-pp3300-ldo-z5 { + compatible = "regulator-fixed"; + regulator-name = "pp3300_ldo_z5"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&ppvar_sys>; + }; + + /* separately switched 3.3V power rail */ + pp3300_s3: regulator-pp3300-s3 { + compatible = "regulator-fixed"; + regulator-name = "pp3300_s3"; + /* automatically sequenced by PMIC EXT_PMIC_EN2 */ + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&pp3300_z2>; + }; + + /* system wide 3.3V power rail */ + pp3300_z2: regulator-pp3300-z2 { + compatible = "regulator-fixed"; + regulator-name = "pp3300_z2"; + /* EN pin tied to pp4200_z2, which is controlled by EC */ + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&ppvar_sys>; + }; + + /* system wide 4.2V power rail */ + pp4200_z2: regulator-pp4200-z2 { + compatible = "regulator-fixed"; + regulator-name = "pp4200_z2"; + /* controlled by EC */ + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <4200000>; + regulator-max-microvolt = <4200000>; + vin-supply = <&ppvar_sys>; + }; + + /* system wide switching 5.0V power rail */ + pp5000_s5: regulator-pp5000-s5 { + compatible = "regulator-fixed"; + regulator-name = "pp5000_s5"; + /* controlled by EC */ + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&ppvar_sys>; + }; + + /* system wide semi-regulated power rail from battery or USB */ + ppvar_sys: regulator-ppvar-sys { + compatible = "regulator-fixed"; + regulator-name = "ppvar_sys"; + regulator-always-on; + regulator-boot-on; + }; + + usb_vbus: regulator-5v0-usb-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + }; +}; + +&i2c0 { + status = "okay"; + + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; +}; + +&i2c1 { + status = "okay"; + + clock-frequency = <400000>; + i2c-scl-internal-delay-ns = <12500>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; +}; + +&i2c2 { + status = "okay"; + + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; +}; + +&i2c3 { + status = "okay"; + + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pins>; +}; + +&i2c4 { + status = "okay"; + + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_pins>; + + ts_10: touchscreen@10 { + compatible = "hid-over-i2c"; + reg = <0x10>; + hid-descr-addr = <0x0001>; + interrupts-extended = <&pio 92 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&touchscreen_pins>; + post-power-on-delay-ms = <10>; + vdd-supply = <&pp3300_s3>; + status = "disabled"; + }; +}; + +&i2c5 { + status = "okay"; + + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c5_pins>; +}; + +&i2c7 { + status = "okay"; + + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c7_pins>; + + pmic@34 { + #interrupt-cells = <1>; + compatible = "mediatek,mt6360"; + reg = <0x34>; + interrupt-controller; + interrupts-extended = <&pio 130 IRQ_TYPE_EDGE_FALLING>; + interrupt-names = "IRQB"; + pinctrl-names = "default"; + pinctrl-0 = <&subpmic_default>; + wakeup-source; + }; +}; + +&mmc0 { + status = "okay"; + + bus-width = <8>; + cap-mmc-highspeed; + cap-mmc-hw-reset; + hs400-ds-delay = <0x14c11>; + max-frequency = <200000000>; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + no-sdio; + no-sd; + non-removable; + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc0_pins_default>; + pinctrl-1 = <&mmc0_pins_uhs>; + vmmc-supply = <&mt6359_vemc_1_ldo_reg>; + vqmmc-supply = <&mt6359_vufs_ldo_reg>; +}; + +/* for CPU-L */ +&mt6359_vcore_buck_reg { + regulator-always-on; +}; + +/* for CORE */ +&mt6359_vgpu11_buck_reg { + regulator-always-on; +}; + +&mt6359_vgpu11_sshub_buck_reg { + regulator-always-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <550000>; +}; + +/* for CORE SRAM */ +&mt6359_vpu_buck_reg { + regulator-always-on; +}; + +&mt6359_vrf12_ldo_reg { + regulator-always-on; +}; + +/* for GPU SRAM */ +&mt6359_vsram_others_ldo_reg { + regulator-always-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; +}; + +&mt6359_vufs_ldo_reg { + regulator-always-on; +}; + +&nor_flash { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&nor_pins_default>; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <52000000>; + spi-rx-bus-width = <2>; + spi-tx-bus-width = <2>; + }; +}; + +&pio { + mediatek,rsel-resistance-in-si-unit; + pinctrl-names = "default"; + pinctrl-0 = <&pio_default>; + + /* 144 lines */ + gpio-line-names = + "I2S_SPKR_MCLK", + "I2S_SPKR_DATAIN", + "I2S_SPKR_LRCK", + "I2S_SPKR_BCLK", + "EC_AP_INT_ODL", + /* + * AP_FLASH_WP_L is crossystem ABI. Schematics + * call it AP_FLASH_WP_ODL. + */ + "AP_FLASH_WP_L", + "TCHPAD_INT_ODL", + "EDP_HPD_1V8", + "AP_I2C_CAM_SDA", + "AP_I2C_CAM_SCL", + "AP_I2C_TCHPAD_SDA_1V8", + "AP_I2C_TCHPAD_SCL_1V8", + "AP_I2C_AUD_SDA", + "AP_I2C_AUD_SCL", + "AP_I2C_TPM_SDA_1V8", + "AP_I2C_TPM_SCL_1V8", + "AP_I2C_TCHSCR_SDA_1V8", + "AP_I2C_TCHSCR_SCL_1V8", + "EC_AP_HPD_OD", + "", + "PCIE_NVME_RST_L", + "PCIE_NVME_CLKREQ_ODL", + "PCIE_RST_1V8_L", + "PCIE_CLKREQ_1V8_ODL", + "PCIE_WAKE_1V8_ODL", + "CLK_24M_CAM0", + "CAM1_SEN_EN", + "AP_I2C_PWR_SCL_1V8", + "AP_I2C_PWR_SDA_1V8", + "AP_I2C_MISC_SCL", + "AP_I2C_MISC_SDA", + "EN_PP5000_HDMI_X", + "AP_HDMITX_HTPLG", + "", + "AP_HDMITX_SCL_1V8", + "AP_HDMITX_SDA_1V8", + "AP_RTC_CLK32K", + "AP_EC_WATCHDOG_L", + "SRCLKENA0", + "SRCLKENA1", + "PWRAP_SPI0_CS_L", + "PWRAP_SPI0_CK", + "PWRAP_SPI0_MOSI", + "PWRAP_SPI0_MISO", + "SPMI_SCL", + "SPMI_SDA", + "", + "", + "", + "I2S_HP_DATAIN", + "I2S_HP_MCLK", + "I2S_HP_BCK", + "I2S_HP_LRCK", + "I2S_HP_DATAOUT", + "SD_CD_ODL", + "EN_PP3300_DISP_X", + "TCHSCR_RST_1V8_L", + "TCHSCR_REPORT_DISABLE", + "EN_PP3300_WLAN_X", + "BT_KILL_1V8_L", + "I2S_SPKR_DATAOUT", + "WIFI_KILL_1V8_L", + "BEEP_ON", + "SCP_I2C_SENSOR_SCL_1V8", + "SCP_I2C_SENSOR_SDA_1V8", + "", + "", + "", + "", + "AUD_CLK_MOSI", + "AUD_SYNC_MOSI", + "AUD_DAT_MOSI0", + "AUD_DAT_MOSI1", + "AUD_DAT_MISO0", + "AUD_DAT_MISO1", + "AUD_DAT_MISO2", + "SCP_VREQ_VAO", + "AP_SPI_GSC_TPM_CLK", + "AP_SPI_GSC_TPM_MOSI", + "AP_SPI_GSC_TPM_CS_L", + "AP_SPI_GSC_TPM_MISO", + "EN_PP1000_CAM_X", + "AP_EDP_BKLTEN", + "", + "USB3_HUB_RST_L", + "", + "WLAN_ALERT_ODL", + "EC_IN_RW_ODL", + "GSC_AP_INT_ODL", + "HP_INT_ODL", + "CAM0_RST_L", + "CAM1_RST_L", + "TCHSCR_INT_1V8_L", + "CAM1_DET_L", + "RST_ALC1011_L", + "", + "", + "BL_PWM_1V8", + "UART_AP_TX_DBG_RX", + "UART_DBG_TX_AP_RX", + "EN_SPKR", + "AP_EC_WARM_RST_REQ", + "UART_SCP_TX_DBGCON_RX", + "UART_DBGCON_TX_SCP_RX", + "", + "", + "KPCOL0", + "", + "MT6315_GPU_INT", + "MT6315_PROC_BC_INT", + "SD_CMD", + "SD_CLK", + "SD_DAT0", + "SD_DAT1", + "SD_DAT2", + "SD_DAT3", + "EMMC_DAT7", + "EMMC_DAT6", + "EMMC_DAT5", + "EMMC_DAT4", + "EMMC_RSTB", + "EMMC_CMD", + "EMMC_CLK", + "EMMC_DAT3", + "EMMC_DAT2", + "EMMC_DAT1", + "EMMC_DAT0", + "EMMC_DSL", + "", + "", + "MT6360_INT_ODL", + "SCP_JTAG0_TRSTN", + "AP_SPI_EC_CS_L", + "AP_SPI_EC_CLK", + "AP_SPI_EC_MOSI", + "AP_SPI_EC_MISO", + "SCP_JTAG0_TMS", + "SCP_JTAG0_TCK", + "SCP_JTAG0_TDO", + "SCP_JTAG0_TDI", + "AP_SPI_FLASH_CS_L", + "AP_SPI_FLASH_CLK", + "AP_SPI_FLASH_MOSI", + "AP_SPI_FLASH_MISO"; + + i2c0_pins: i2c0-default-pins { + pins-bus { + pinmux = <PINMUX_GPIO8__FUNC_SDA0>, + <PINMUX_GPIO9__FUNC_SCL0>; + bias-disable; + drive-strength-microamp = <1000>; + }; + }; + + i2c1_pins: i2c1-default-pins { + pins-bus { + pinmux = <PINMUX_GPIO10__FUNC_SDA1>, + <PINMUX_GPIO11__FUNC_SCL1>; + bias-pull-up = <1000>; + drive-strength-microamp = <1000>; + }; + }; + + i2c2_pins: i2c2-default-pins { + pins-bus { + pinmux = <PINMUX_GPIO12__FUNC_SDA2>, + <PINMUX_GPIO13__FUNC_SCL2>; + bias-disable; + drive-strength-microamp = <1000>; + }; + }; + + i2c3_pins: i2c3-default-pins { + pins-bus { + pinmux = <PINMUX_GPIO14__FUNC_SDA3>, + <PINMUX_GPIO15__FUNC_SCL3>; + bias-pull-up = <1000>; + drive-strength-microamp = <1000>; + }; + }; + + i2c4_pins: i2c4-default-pins { + pins-bus { + pinmux = <PINMUX_GPIO16__FUNC_SDA4>, + <PINMUX_GPIO17__FUNC_SCL4>; + bias-pull-up = <1000>; + drive-strength = <4>; + }; + }; + + i2c5_pins: i2c5-default-pins { + pins-bus { + pinmux = <PINMUX_GPIO29__FUNC_SCL5>, + <PINMUX_GPIO30__FUNC_SDA5>; + bias-disable; + drive-strength-microamp = <1000>; + }; + }; + + i2c7_pins: i2c7-default-pins { + pins-bus { + pinmux = <PINMUX_GPIO27__FUNC_SCL7>, + <PINMUX_GPIO28__FUNC_SDA7>; + bias-disable; + }; + }; + + mmc0_pins_default: mmc0-default-pins { + pins-cmd-dat { + pinmux = <PINMUX_GPIO126__FUNC_MSDC0_DAT0>, + <PINMUX_GPIO125__FUNC_MSDC0_DAT1>, + <PINMUX_GPIO124__FUNC_MSDC0_DAT2>, + <PINMUX_GPIO123__FUNC_MSDC0_DAT3>, + <PINMUX_GPIO119__FUNC_MSDC0_DAT4>, + <PINMUX_GPIO118__FUNC_MSDC0_DAT5>, + <PINMUX_GPIO117__FUNC_MSDC0_DAT6>, + <PINMUX_GPIO116__FUNC_MSDC0_DAT7>, + <PINMUX_GPIO121__FUNC_MSDC0_CMD>; + input-enable; + drive-strength = <6>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + }; + + pins-clk { + pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>; + drive-strength = <6>; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; + }; + + pins-rst { + pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>; + drive-strength = <6>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + }; + }; + + mmc0_pins_uhs: mmc0-uhs-pins { + pins-cmd-dat { + pinmux = <PINMUX_GPIO126__FUNC_MSDC0_DAT0>, + <PINMUX_GPIO125__FUNC_MSDC0_DAT1>, + <PINMUX_GPIO124__FUNC_MSDC0_DAT2>, + <PINMUX_GPIO123__FUNC_MSDC0_DAT3>, + <PINMUX_GPIO119__FUNC_MSDC0_DAT4>, + <PINMUX_GPIO118__FUNC_MSDC0_DAT5>, + <PINMUX_GPIO117__FUNC_MSDC0_DAT6>, + <PINMUX_GPIO116__FUNC_MSDC0_DAT7>, + <PINMUX_GPIO121__FUNC_MSDC0_CMD>; + input-enable; + drive-strength = <8>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + }; + + pins-clk { + pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>; + drive-strength = <8>; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; + }; + + pins-ds { + pinmux = <PINMUX_GPIO127__FUNC_MSDC0_DSL>; + drive-strength = <8>; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; + }; + + pins-rst { + pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>; + drive-strength = <8>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + }; + }; + + nor_pins_default: nor-default-pins { + pins-ck-io { + pinmux = <PINMUX_GPIO142__FUNC_SPINOR_IO0>, + <PINMUX_GPIO141__FUNC_SPINOR_CK>, + <PINMUX_GPIO143__FUNC_SPINOR_IO1>; + drive-strength = <6>; + bias-pull-down; + }; + + pins-cs { + pinmux = <PINMUX_GPIO140__FUNC_SPINOR_CS>; + drive-strength = <6>; + bias-pull-up; + }; + }; + + pio_default: pio-default-pins { + pins-wifi-enable { + pinmux = <PINMUX_GPIO58__FUNC_GPIO58>; + output-high; + drive-strength = <14>; + }; + + pins-low-power-pd { + pinmux = <PINMUX_GPIO25__FUNC_GPIO25>, + <PINMUX_GPIO26__FUNC_GPIO26>, + <PINMUX_GPIO46__FUNC_GPIO46>, + <PINMUX_GPIO47__FUNC_GPIO47>, + <PINMUX_GPIO48__FUNC_GPIO48>, + <PINMUX_GPIO65__FUNC_GPIO65>, + <PINMUX_GPIO66__FUNC_GPIO66>, + <PINMUX_GPIO67__FUNC_GPIO67>, + <PINMUX_GPIO68__FUNC_GPIO68>, + <PINMUX_GPIO128__FUNC_GPIO128>, + <PINMUX_GPIO129__FUNC_GPIO129>; + input-enable; + bias-pull-down; + }; + + pins-low-power-pupd { + pinmux = <PINMUX_GPIO77__FUNC_GPIO77>, + <PINMUX_GPIO78__FUNC_GPIO78>, + <PINMUX_GPIO79__FUNC_GPIO79>, + <PINMUX_GPIO80__FUNC_GPIO80>, + <PINMUX_GPIO83__FUNC_GPIO83>, + <PINMUX_GPIO85__FUNC_GPIO85>, + <PINMUX_GPIO90__FUNC_GPIO90>, + <PINMUX_GPIO91__FUNC_GPIO91>, + <PINMUX_GPIO93__FUNC_GPIO93>, + <PINMUX_GPIO94__FUNC_GPIO94>, + <PINMUX_GPIO95__FUNC_GPIO95>, + <PINMUX_GPIO96__FUNC_GPIO96>, + <PINMUX_GPIO104__FUNC_GPIO104>, + <PINMUX_GPIO105__FUNC_GPIO105>, + <PINMUX_GPIO107__FUNC_GPIO107>; + input-enable; + bias-pull-down = <MTK_PUPD_SET_R1R0_01>; + }; + }; + + spi0_pins: spi0-default-pins { + pins-cs-mosi-clk { + pinmux = <PINMUX_GPIO132__FUNC_SPIM0_CSB>, + <PINMUX_GPIO134__FUNC_SPIM0_MO>, + <PINMUX_GPIO133__FUNC_SPIM0_CLK>; + bias-disable; + }; + + pins-miso { + pinmux = <PINMUX_GPIO135__FUNC_SPIM0_MI>; + bias-pull-down; + }; + }; + + subpmic_default: subpmic-default-pins { + subpmic_pin_irq: pins-subpmic-int-n { + pinmux = <PINMUX_GPIO130__FUNC_GPIO130>; + input-enable; + bias-pull-up; + }; + }; + + touchscreen_pins: touchscreen-default-pins { + pins-int-n { + pinmux = <PINMUX_GPIO92__FUNC_GPIO92>; + input-enable; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + }; + pins-rst { + pinmux = <PINMUX_GPIO56__FUNC_GPIO56>; + output-high; + }; + pins-report-sw { + pinmux = <PINMUX_GPIO57__FUNC_GPIO57>; + output-low; + }; + }; +}; + +&pmic { + interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>; +}; + +&spi0 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins>; + mediatek,pad-select = <0>; +}; + +&u3phy0 { + status = "okay"; +}; + +&u3phy1 { + status = "okay"; +}; + +&u3phy2 { + status = "okay"; +}; + +&u3phy3 { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&xhci0 { + status = "okay"; + + vusb33-supply = <&mt6359_vusb_ldo_reg>; + vbus-supply = <&usb_vbus>; +}; + +&xhci1 { + status = "okay"; + + vusb33-supply = <&mt6359_vusb_ldo_reg>; + vbus-supply = <&usb_vbus>; +}; + +&xhci2 { + status = "okay"; + + vusb33-supply = <&mt6359_vusb_ldo_reg>; + vbus-supply = <&usb_vbus>; +}; + +&xhci3 { + status = "okay"; + + /* MT7921's USB Bluetooth has issues with USB2 LPM */ + usb2-lpm-disable; + vusb33-supply = <&mt6359_vusb_ldo_reg>; + vbus-supply = <&usb_vbus>; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8195-evb.dts b/arch/arm64/boot/dts/mediatek/mt8195-evb.dts index db25a515e420..690dc7717f2c 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195-evb.dts +++ b/arch/arm64/boot/dts/mediatek/mt8195-evb.dts @@ -139,19 +139,19 @@ }; &u3phy0 { - status="okay"; + status = "okay"; }; &u3phy1 { - status="okay"; + status = "okay"; }; &u3phy2 { - status="okay"; + status = "okay"; }; &u3phy3 { - status="okay"; + status = "okay"; }; &uart0 { diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index b57e620c2c72..066c14989708 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -10,7 +10,6 @@ #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/phy/phy.h> #include <dt-bindings/pinctrl/mt8195-pinfunc.h> -#include <dt-bindings/reset/ti-syscon.h> / { compatible = "mediatek,mt8195"; @@ -295,17 +294,7 @@ compatible = "mediatek,mt8195-infracfg_ao", "syscon", "simple-mfd"; reg = <0 0x10001000 0 0x1000>; #clock-cells = <1>; - - infracfg_rst: reset-controller { - compatible = "ti,syscon-reset"; - #reset-cells = <1>; - ti,reset-bits = < - 0x140 18 0x144 18 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* pcie */ - 0x120 0 0x124 0 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* thermal */ - 0x730 10 0x734 10 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* thermal */ - 0x150 5 0x154 5 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* svs gpu */ - >; - }; + #reset-cells = <1>; }; pericfg: syscon@10003000 { @@ -573,6 +562,8 @@ <&apmixedsys CLK_APMIXED_USB1PLL>, <&infracfg_ao CLK_INFRA_AO_SSUSB_XHCI>; clock-names = "sys_ck", "ref_ck", "mcu_ck", "xhci_ck"; + mediatek,syscon-wakeup = <&pericfg 0x400 103>; + wakeup-source; status = "disabled"; }; @@ -636,6 +627,8 @@ <&apmixedsys CLK_APMIXED_USB1PLL>, <&pericfg_ao CLK_PERI_AO_SSUSB_1P_XHCI>; clock-names = "sys_ck", "ref_ck", "mcu_ck","xhci_ck"; + mediatek,syscon-wakeup = <&pericfg 0x400 104>; + wakeup-source; status = "disabled"; }; @@ -655,6 +648,8 @@ <&topckgen CLK_TOP_SSUSB_P2_REF>, <&pericfg_ao CLK_PERI_AO_SSUSB_2P_XHCI>; clock-names = "sys_ck", "ref_ck", "xhci_ck"; + mediatek,syscon-wakeup = <&pericfg 0x400 105>; + wakeup-source; status = "disabled"; }; @@ -674,6 +669,8 @@ <&topckgen CLK_TOP_SSUSB_P3_REF>, <&pericfg_ao CLK_PERI_AO_SSUSB_3P_XHCI>; clock-names = "sys_ck", "ref_ck", "xhci_ck"; + mediatek,syscon-wakeup = <&pericfg 0x400 106>; + wakeup-source; status = "disabled"; }; @@ -691,6 +688,53 @@ status = "disabled"; }; + efuse: efuse@11c10000 { + compatible = "mediatek,mt8195-efuse", "mediatek,efuse"; + reg = <0 0x11c10000 0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + u3_tx_imp_p0: usb3-tx-imp@184,1 { + reg = <0x184 0x1>; + bits = <0 5>; + }; + u3_rx_imp_p0: usb3-rx-imp@184,2 { + reg = <0x184 0x2>; + bits = <5 5>; + }; + u3_intr_p0: usb3-intr@185 { + reg = <0x185 0x1>; + bits = <2 6>; + }; + comb_tx_imp_p1: usb3-tx-imp@186,1 { + reg = <0x186 0x1>; + bits = <0 5>; + }; + comb_rx_imp_p1: usb3-rx-imp@186,2 { + reg = <0x186 0x2>; + bits = <5 5>; + }; + comb_intr_p1: usb3-intr@187 { + reg = <0x187 0x1>; + bits = <2 6>; + }; + u2_intr_p0: usb2-intr-p0@188,1 { + reg = <0x188 0x1>; + bits = <0 5>; + }; + u2_intr_p1: usb2-intr-p1@188,2 { + reg = <0x188 0x2>; + bits = <5 5>; + }; + u2_intr_p2: usb2-intr-p2@189,1 { + reg = <0x189 0x1>; + bits = <2 5>; + }; + u2_intr_p3: usb2-intr-p3@189,2 { + reg = <0x189 0x2>; + bits = <7 5>; + }; + }; + u3phy2: t-phy@11c40000 { compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3"; #address-cells = <1>; @@ -873,6 +917,10 @@ clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M>, <&topckgen CLK_TOP_SSUSB_PHY_P1_REF>; clock-names = "ref", "da_ref"; + nvmem-cells = <&comb_intr_p1>, + <&comb_rx_imp_p1>, + <&comb_tx_imp_p1>; + nvmem-cell-names = "intr", "rx_imp", "tx_imp"; #phy-cells = <1>; }; }; @@ -897,6 +945,10 @@ clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M>, <&topckgen CLK_TOP_SSUSB_PHY_REF>; clock-names = "ref", "da_ref"; + nvmem-cells = <&u3_intr_p0>, + <&u3_rx_imp_p0>, + <&u3_tx_imp_p0>; + nvmem-cell-names = "intr", "rx_imp", "tx_imp"; #phy-cells = <1>; }; }; diff --git a/arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi b/arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi index 7a717f926929..8ee1529683a3 100644 --- a/arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi +++ b/arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi @@ -28,7 +28,7 @@ pinctrl-names = "default"; pinctrl-0 = <&gpio_keys_default>; - volume-up { + key-volume-up { gpios = <&pio 42 GPIO_ACTIVE_LOW>; label = "volume_up"; linux,code = <115>; @@ -36,7 +36,7 @@ debounce-interval = <15>; }; - volume-down { + key-volume-down { gpios = <&pio 43 GPIO_ACTIVE_LOW>; label = "volume_down"; linux,code = <114>; diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi b/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi index 699256f1b9d8..bf12be5e8d84 100644 --- a/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi @@ -546,164 +546,164 @@ &axi { sfp_eth12: sfp-eth12 { - compatible = "sff,sfp"; - i2c-bus = <&i2c_sfp1>; + compatible = "sff,sfp"; + i2c-bus = <&i2c_sfp1>; tx-disable-gpios = <&sgpio_out2 11 1 GPIO_ACTIVE_LOW>; - los-gpios = <&sgpio_in2 11 1 GPIO_ACTIVE_HIGH>; - mod-def0-gpios = <&sgpio_in2 11 2 GPIO_ACTIVE_LOW>; - tx-fault-gpios = <&sgpio_in2 12 0 GPIO_ACTIVE_HIGH>; + los-gpios = <&sgpio_in2 11 1 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&sgpio_in2 11 2 GPIO_ACTIVE_LOW>; + tx-fault-gpios = <&sgpio_in2 12 0 GPIO_ACTIVE_HIGH>; }; sfp_eth13: sfp-eth13 { - compatible = "sff,sfp"; - i2c-bus = <&i2c_sfp2>; + compatible = "sff,sfp"; + i2c-bus = <&i2c_sfp2>; tx-disable-gpios = <&sgpio_out2 12 1 GPIO_ACTIVE_LOW>; - los-gpios = <&sgpio_in2 12 1 GPIO_ACTIVE_HIGH>; - mod-def0-gpios = <&sgpio_in2 12 2 GPIO_ACTIVE_LOW>; - tx-fault-gpios = <&sgpio_in2 13 0 GPIO_ACTIVE_HIGH>; + los-gpios = <&sgpio_in2 12 1 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&sgpio_in2 12 2 GPIO_ACTIVE_LOW>; + tx-fault-gpios = <&sgpio_in2 13 0 GPIO_ACTIVE_HIGH>; }; sfp_eth14: sfp-eth14 { - compatible = "sff,sfp"; - i2c-bus = <&i2c_sfp3>; + compatible = "sff,sfp"; + i2c-bus = <&i2c_sfp3>; tx-disable-gpios = <&sgpio_out2 13 1 GPIO_ACTIVE_LOW>; - los-gpios = <&sgpio_in2 13 1 GPIO_ACTIVE_HIGH>; - mod-def0-gpios = <&sgpio_in2 13 2 GPIO_ACTIVE_LOW>; - tx-fault-gpios = <&sgpio_in2 14 0 GPIO_ACTIVE_HIGH>; + los-gpios = <&sgpio_in2 13 1 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&sgpio_in2 13 2 GPIO_ACTIVE_LOW>; + tx-fault-gpios = <&sgpio_in2 14 0 GPIO_ACTIVE_HIGH>; }; sfp_eth15: sfp-eth15 { - compatible = "sff,sfp"; - i2c-bus = <&i2c_sfp4>; + compatible = "sff,sfp"; + i2c-bus = <&i2c_sfp4>; tx-disable-gpios = <&sgpio_out2 14 1 GPIO_ACTIVE_LOW>; - los-gpios = <&sgpio_in2 14 1 GPIO_ACTIVE_HIGH>; - mod-def0-gpios = <&sgpio_in2 14 2 GPIO_ACTIVE_LOW>; - tx-fault-gpios = <&sgpio_in2 15 0 GPIO_ACTIVE_HIGH>; + los-gpios = <&sgpio_in2 14 1 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&sgpio_in2 14 2 GPIO_ACTIVE_LOW>; + tx-fault-gpios = <&sgpio_in2 15 0 GPIO_ACTIVE_HIGH>; }; sfp_eth48: sfp-eth48 { - compatible = "sff,sfp"; - i2c-bus = <&i2c_sfp5>; + compatible = "sff,sfp"; + i2c-bus = <&i2c_sfp5>; tx-disable-gpios = <&sgpio_out2 15 1 GPIO_ACTIVE_LOW>; - los-gpios = <&sgpio_in2 15 1 GPIO_ACTIVE_HIGH>; - mod-def0-gpios = <&sgpio_in2 15 2 GPIO_ACTIVE_LOW>; - tx-fault-gpios = <&sgpio_in2 16 0 GPIO_ACTIVE_HIGH>; + los-gpios = <&sgpio_in2 15 1 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&sgpio_in2 15 2 GPIO_ACTIVE_LOW>; + tx-fault-gpios = <&sgpio_in2 16 0 GPIO_ACTIVE_HIGH>; }; sfp_eth49: sfp-eth49 { - compatible = "sff,sfp"; - i2c-bus = <&i2c_sfp6>; + compatible = "sff,sfp"; + i2c-bus = <&i2c_sfp6>; tx-disable-gpios = <&sgpio_out2 16 1 GPIO_ACTIVE_LOW>; - los-gpios = <&sgpio_in2 16 1 GPIO_ACTIVE_HIGH>; - mod-def0-gpios = <&sgpio_in2 16 2 GPIO_ACTIVE_LOW>; - tx-fault-gpios = <&sgpio_in2 17 0 GPIO_ACTIVE_HIGH>; + los-gpios = <&sgpio_in2 16 1 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&sgpio_in2 16 2 GPIO_ACTIVE_LOW>; + tx-fault-gpios = <&sgpio_in2 17 0 GPIO_ACTIVE_HIGH>; }; sfp_eth50: sfp-eth50 { - compatible = "sff,sfp"; - i2c-bus = <&i2c_sfp7>; + compatible = "sff,sfp"; + i2c-bus = <&i2c_sfp7>; tx-disable-gpios = <&sgpio_out2 17 1 GPIO_ACTIVE_LOW>; - los-gpios = <&sgpio_in2 17 1 GPIO_ACTIVE_HIGH>; - mod-def0-gpios = <&sgpio_in2 17 2 GPIO_ACTIVE_LOW>; - tx-fault-gpios = <&sgpio_in2 18 0 GPIO_ACTIVE_HIGH>; + los-gpios = <&sgpio_in2 17 1 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&sgpio_in2 17 2 GPIO_ACTIVE_LOW>; + tx-fault-gpios = <&sgpio_in2 18 0 GPIO_ACTIVE_HIGH>; }; sfp_eth51: sfp-eth51 { - compatible = "sff,sfp"; - i2c-bus = <&i2c_sfp8>; + compatible = "sff,sfp"; + i2c-bus = <&i2c_sfp8>; tx-disable-gpios = <&sgpio_out2 18 1 GPIO_ACTIVE_LOW>; - los-gpios = <&sgpio_in2 18 1 GPIO_ACTIVE_HIGH>; - mod-def0-gpios = <&sgpio_in2 18 2 GPIO_ACTIVE_LOW>; - tx-fault-gpios = <&sgpio_in2 19 0 GPIO_ACTIVE_HIGH>; + los-gpios = <&sgpio_in2 18 1 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&sgpio_in2 18 2 GPIO_ACTIVE_LOW>; + tx-fault-gpios = <&sgpio_in2 19 0 GPIO_ACTIVE_HIGH>; }; sfp_eth52: sfp-eth52 { - compatible = "sff,sfp"; - i2c-bus = <&i2c_sfp9>; + compatible = "sff,sfp"; + i2c-bus = <&i2c_sfp9>; tx-disable-gpios = <&sgpio_out2 19 1 GPIO_ACTIVE_LOW>; - los-gpios = <&sgpio_in2 19 1 GPIO_ACTIVE_HIGH>; - mod-def0-gpios = <&sgpio_in2 19 2 GPIO_ACTIVE_LOW>; - tx-fault-gpios = <&sgpio_in2 20 0 GPIO_ACTIVE_HIGH>; + los-gpios = <&sgpio_in2 19 1 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&sgpio_in2 19 2 GPIO_ACTIVE_LOW>; + tx-fault-gpios = <&sgpio_in2 20 0 GPIO_ACTIVE_HIGH>; }; sfp_eth53: sfp-eth53 { - compatible = "sff,sfp"; - i2c-bus = <&i2c_sfp10>; + compatible = "sff,sfp"; + i2c-bus = <&i2c_sfp10>; tx-disable-gpios = <&sgpio_out2 20 1 GPIO_ACTIVE_LOW>; - los-gpios = <&sgpio_in2 20 1 GPIO_ACTIVE_HIGH>; - mod-def0-gpios = <&sgpio_in2 20 2 GPIO_ACTIVE_LOW>; - tx-fault-gpios = <&sgpio_in2 21 0 GPIO_ACTIVE_HIGH>; + los-gpios = <&sgpio_in2 20 1 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&sgpio_in2 20 2 GPIO_ACTIVE_LOW>; + tx-fault-gpios = <&sgpio_in2 21 0 GPIO_ACTIVE_HIGH>; }; sfp_eth54: sfp-eth54 { - compatible = "sff,sfp"; - i2c-bus = <&i2c_sfp11>; + compatible = "sff,sfp"; + i2c-bus = <&i2c_sfp11>; tx-disable-gpios = <&sgpio_out2 21 1 GPIO_ACTIVE_LOW>; - los-gpios = <&sgpio_in2 21 1 GPIO_ACTIVE_HIGH>; - mod-def0-gpios = <&sgpio_in2 21 2 GPIO_ACTIVE_LOW>; - tx-fault-gpios = <&sgpio_in2 22 0 GPIO_ACTIVE_HIGH>; + los-gpios = <&sgpio_in2 21 1 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&sgpio_in2 21 2 GPIO_ACTIVE_LOW>; + tx-fault-gpios = <&sgpio_in2 22 0 GPIO_ACTIVE_HIGH>; }; sfp_eth55: sfp-eth55 { - compatible = "sff,sfp"; - i2c-bus = <&i2c_sfp12>; + compatible = "sff,sfp"; + i2c-bus = <&i2c_sfp12>; tx-disable-gpios = <&sgpio_out2 22 1 GPIO_ACTIVE_LOW>; - los-gpios = <&sgpio_in2 22 1 GPIO_ACTIVE_HIGH>; - mod-def0-gpios = <&sgpio_in2 22 2 GPIO_ACTIVE_LOW>; - tx-fault-gpios = <&sgpio_in2 23 0 GPIO_ACTIVE_HIGH>; + los-gpios = <&sgpio_in2 22 1 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&sgpio_in2 22 2 GPIO_ACTIVE_LOW>; + tx-fault-gpios = <&sgpio_in2 23 0 GPIO_ACTIVE_HIGH>; }; sfp_eth56: sfp-eth56 { - compatible = "sff,sfp"; - i2c-bus = <&i2c_sfp13>; + compatible = "sff,sfp"; + i2c-bus = <&i2c_sfp13>; tx-disable-gpios = <&sgpio_out2 23 1 GPIO_ACTIVE_LOW>; - los-gpios = <&sgpio_in2 23 1 GPIO_ACTIVE_HIGH>; - mod-def0-gpios = <&sgpio_in2 23 2 GPIO_ACTIVE_LOW>; - tx-fault-gpios = <&sgpio_in2 24 0 GPIO_ACTIVE_HIGH>; + los-gpios = <&sgpio_in2 23 1 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&sgpio_in2 23 2 GPIO_ACTIVE_LOW>; + tx-fault-gpios = <&sgpio_in2 24 0 GPIO_ACTIVE_HIGH>; }; sfp_eth57: sfp-eth57 { - compatible = "sff,sfp"; - i2c-bus = <&i2c_sfp14>; + compatible = "sff,sfp"; + i2c-bus = <&i2c_sfp14>; tx-disable-gpios = <&sgpio_out2 24 1 GPIO_ACTIVE_LOW>; - los-gpios = <&sgpio_in2 24 1 GPIO_ACTIVE_HIGH>; - mod-def0-gpios = <&sgpio_in2 24 2 GPIO_ACTIVE_LOW>; - tx-fault-gpios = <&sgpio_in2 25 0 GPIO_ACTIVE_HIGH>; + los-gpios = <&sgpio_in2 24 1 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&sgpio_in2 24 2 GPIO_ACTIVE_LOW>; + tx-fault-gpios = <&sgpio_in2 25 0 GPIO_ACTIVE_HIGH>; }; sfp_eth58: sfp-eth58 { - compatible = "sff,sfp"; - i2c-bus = <&i2c_sfp15>; + compatible = "sff,sfp"; + i2c-bus = <&i2c_sfp15>; tx-disable-gpios = <&sgpio_out2 25 1 GPIO_ACTIVE_LOW>; - los-gpios = <&sgpio_in2 25 1 GPIO_ACTIVE_HIGH>; - mod-def0-gpios = <&sgpio_in2 25 2 GPIO_ACTIVE_LOW>; - tx-fault-gpios = <&sgpio_in2 26 0 GPIO_ACTIVE_HIGH>; + los-gpios = <&sgpio_in2 25 1 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&sgpio_in2 25 2 GPIO_ACTIVE_LOW>; + tx-fault-gpios = <&sgpio_in2 26 0 GPIO_ACTIVE_HIGH>; }; sfp_eth59: sfp-eth59 { - compatible = "sff,sfp"; - i2c-bus = <&i2c_sfp16>; + compatible = "sff,sfp"; + i2c-bus = <&i2c_sfp16>; tx-disable-gpios = <&sgpio_out2 26 1 GPIO_ACTIVE_LOW>; - los-gpios = <&sgpio_in2 26 1 GPIO_ACTIVE_HIGH>; - mod-def0-gpios = <&sgpio_in2 26 2 GPIO_ACTIVE_LOW>; - tx-fault-gpios = <&sgpio_in2 27 0 GPIO_ACTIVE_HIGH>; + los-gpios = <&sgpio_in2 26 1 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&sgpio_in2 26 2 GPIO_ACTIVE_LOW>; + tx-fault-gpios = <&sgpio_in2 27 0 GPIO_ACTIVE_HIGH>; }; sfp_eth60: sfp-eth60 { - compatible = "sff,sfp"; - i2c-bus = <&i2c_sfp17>; + compatible = "sff,sfp"; + i2c-bus = <&i2c_sfp17>; tx-disable-gpios = <&sgpio_out2 27 1 GPIO_ACTIVE_LOW>; - los-gpios = <&sgpio_in2 27 1 GPIO_ACTIVE_HIGH>; - mod-def0-gpios = <&sgpio_in2 27 2 GPIO_ACTIVE_LOW>; - tx-fault-gpios = <&sgpio_in2 28 0 GPIO_ACTIVE_HIGH>; + los-gpios = <&sgpio_in2 27 1 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&sgpio_in2 27 2 GPIO_ACTIVE_LOW>; + tx-fault-gpios = <&sgpio_in2 28 0 GPIO_ACTIVE_HIGH>; }; sfp_eth61: sfp-eth61 { - compatible = "sff,sfp"; - i2c-bus = <&i2c_sfp18>; + compatible = "sff,sfp"; + i2c-bus = <&i2c_sfp18>; tx-disable-gpios = <&sgpio_out2 28 1 GPIO_ACTIVE_LOW>; - los-gpios = <&sgpio_in2 28 1 GPIO_ACTIVE_HIGH>; - mod-def0-gpios = <&sgpio_in2 28 2 GPIO_ACTIVE_LOW>; - tx-fault-gpios = <&sgpio_in2 29 0 GPIO_ACTIVE_HIGH>; + los-gpios = <&sgpio_in2 28 1 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&sgpio_in2 28 2 GPIO_ACTIVE_LOW>; + tx-fault-gpios = <&sgpio_in2 29 0 GPIO_ACTIVE_HIGH>; }; sfp_eth62: sfp-eth62 { - compatible = "sff,sfp"; - i2c-bus = <&i2c_sfp19>; + compatible = "sff,sfp"; + i2c-bus = <&i2c_sfp19>; tx-disable-gpios = <&sgpio_out2 29 1 GPIO_ACTIVE_LOW>; - los-gpios = <&sgpio_in2 29 1 GPIO_ACTIVE_HIGH>; - mod-def0-gpios = <&sgpio_in2 29 2 GPIO_ACTIVE_LOW>; - tx-fault-gpios = <&sgpio_in2 30 0 GPIO_ACTIVE_HIGH>; + los-gpios = <&sgpio_in2 29 1 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&sgpio_in2 29 2 GPIO_ACTIVE_LOW>; + tx-fault-gpios = <&sgpio_in2 30 0 GPIO_ACTIVE_HIGH>; }; sfp_eth63: sfp-eth63 { - compatible = "sff,sfp"; - i2c-bus = <&i2c_sfp20>; + compatible = "sff,sfp"; + i2c-bus = <&i2c_sfp20>; tx-disable-gpios = <&sgpio_out2 30 1 GPIO_ACTIVE_LOW>; - los-gpios = <&sgpio_in2 30 1 GPIO_ACTIVE_HIGH>; - mod-def0-gpios = <&sgpio_in2 30 2 GPIO_ACTIVE_LOW>; - tx-fault-gpios = <&sgpio_in2 31 0 GPIO_ACTIVE_HIGH>; + los-gpios = <&sgpio_in2 30 1 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&sgpio_in2 30 2 GPIO_ACTIVE_LOW>; + tx-fault-gpios = <&sgpio_in2 31 0 GPIO_ACTIVE_HIGH>; }; }; diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi b/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi index d10a9172b529..ec90bda7ed6a 100644 --- a/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi @@ -170,40 +170,40 @@ &axi { sfp_eth60: sfp-eth60 { - compatible = "sff,sfp"; - i2c-bus = <&i2c_sfp1>; - tx-disable-gpios = <&sgpio_out2 28 0 GPIO_ACTIVE_LOW>; + compatible = "sff,sfp"; + i2c-bus = <&i2c_sfp1>; + tx-disable-gpios = <&sgpio_out2 28 0 GPIO_ACTIVE_LOW>; rate-select0-gpios = <&sgpio_out2 28 1 GPIO_ACTIVE_HIGH>; - los-gpios = <&sgpio_in2 28 0 GPIO_ACTIVE_HIGH>; - mod-def0-gpios = <&sgpio_in2 28 1 GPIO_ACTIVE_LOW>; - tx-fault-gpios = <&sgpio_in2 28 2 GPIO_ACTIVE_HIGH>; + los-gpios = <&sgpio_in2 28 0 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&sgpio_in2 28 1 GPIO_ACTIVE_LOW>; + tx-fault-gpios = <&sgpio_in2 28 2 GPIO_ACTIVE_HIGH>; }; sfp_eth61: sfp-eth61 { - compatible = "sff,sfp"; - i2c-bus = <&i2c_sfp2>; - tx-disable-gpios = <&sgpio_out2 29 0 GPIO_ACTIVE_LOW>; + compatible = "sff,sfp"; + i2c-bus = <&i2c_sfp2>; + tx-disable-gpios = <&sgpio_out2 29 0 GPIO_ACTIVE_LOW>; rate-select0-gpios = <&sgpio_out2 29 1 GPIO_ACTIVE_HIGH>; - los-gpios = <&sgpio_in2 29 0 GPIO_ACTIVE_HIGH>; - mod-def0-gpios = <&sgpio_in2 29 1 GPIO_ACTIVE_LOW>; - tx-fault-gpios = <&sgpio_in2 29 2 GPIO_ACTIVE_HIGH>; + los-gpios = <&sgpio_in2 29 0 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&sgpio_in2 29 1 GPIO_ACTIVE_LOW>; + tx-fault-gpios = <&sgpio_in2 29 2 GPIO_ACTIVE_HIGH>; }; sfp_eth62: sfp-eth62 { - compatible = "sff,sfp"; - i2c-bus = <&i2c_sfp3>; - tx-disable-gpios = <&sgpio_out2 30 0 GPIO_ACTIVE_LOW>; + compatible = "sff,sfp"; + i2c-bus = <&i2c_sfp3>; + tx-disable-gpios = <&sgpio_out2 30 0 GPIO_ACTIVE_LOW>; rate-select0-gpios = <&sgpio_out2 30 1 GPIO_ACTIVE_HIGH>; - los-gpios = <&sgpio_in2 30 0 GPIO_ACTIVE_HIGH>; - mod-def0-gpios = <&sgpio_in2 30 1 GPIO_ACTIVE_LOW>; - tx-fault-gpios = <&sgpio_in2 30 2 GPIO_ACTIVE_HIGH>; + los-gpios = <&sgpio_in2 30 0 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&sgpio_in2 30 1 GPIO_ACTIVE_LOW>; + tx-fault-gpios = <&sgpio_in2 30 2 GPIO_ACTIVE_HIGH>; }; sfp_eth63: sfp-eth63 { - compatible = "sff,sfp"; - i2c-bus = <&i2c_sfp4>; - tx-disable-gpios = <&sgpio_out2 31 0 GPIO_ACTIVE_LOW>; + compatible = "sff,sfp"; + i2c-bus = <&i2c_sfp4>; + tx-disable-gpios = <&sgpio_out2 31 0 GPIO_ACTIVE_LOW>; rate-select0-gpios = <&sgpio_out2 31 1 GPIO_ACTIVE_HIGH>; - los-gpios = <&sgpio_in2 31 0 GPIO_ACTIVE_HIGH>; - mod-def0-gpios = <&sgpio_in2 31 1 GPIO_ACTIVE_LOW>; - tx-fault-gpios = <&sgpio_in2 31 2 GPIO_ACTIVE_HIGH>; + los-gpios = <&sgpio_in2 31 0 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&sgpio_in2 31 1 GPIO_ACTIVE_LOW>; + tx-fault-gpios = <&sgpio_in2 31 2 GPIO_ACTIVE_HIGH>; }; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts b/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts index f16acb4cabaa..d461da0b8049 100644 --- a/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts +++ b/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts @@ -1030,7 +1030,7 @@ gpio-keys { compatible = "gpio-keys"; - lid { + switch-lid { label = "Lid"; gpios = <&gpio TEGRA_GPIO(R, 4) GPIO_ACTIVE_LOW>; linux,input-type = <5>; @@ -1039,7 +1039,7 @@ wakeup-source; }; - power { + key-power { label = "Power"; gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; linux,code = <KEY_POWER>; diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts index 70737a09a9b8..47cf2013afcc 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts @@ -915,6 +915,22 @@ remote-endpoint = <&asrc_in7_ep>; }; }; + + xbar_ope1_in_port: port@70 { + reg = <0x70>; + + xbar_ope1_in_ep: endpoint { + remote-endpoint = <&ope1_cif_in_ep>; + }; + }; + + port@71 { + reg = <0x71>; + + xbar_ope1_out_ep: endpoint { + remote-endpoint = <&ope1_cif_out_ep>; + }; + }; }; admaif@290f000 { @@ -1911,6 +1927,31 @@ }; }; + processing-engine@2908000 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0x0>; + + ope1_cif_in_ep: endpoint { + remote-endpoint = <&xbar_ope1_in_ep>; + }; + }; + + ope1_out_port: port@1 { + reg = <0x1>; + + ope1_cif_out_ep: endpoint { + remote-endpoint = <&xbar_ope1_out_ep>; + }; + }; + }; + }; + amixer@290bb00 { status = "okay"; @@ -2437,7 +2478,7 @@ gpio-keys { compatible = "gpio-keys"; - power { + key-power { label = "Power"; gpios = <&gpio_aon TEGRA186_AON_GPIO(FF, 0) GPIO_ACTIVE_LOW>; @@ -2448,7 +2489,7 @@ wakeup-source; }; - volume-up { + key-volume-up { label = "Volume Up"; gpios = <&gpio_aon TEGRA186_AON_GPIO(FF, 1) GPIO_ACTIVE_LOW>; @@ -2457,7 +2498,7 @@ debounce-interval = <10>; }; - volume-down { + key-volume-down { label = "Volume Down"; gpios = <&gpio_aon TEGRA186_AON_GPIO(FF, 2) GPIO_ACTIVE_LOW>; @@ -2552,6 +2593,7 @@ <&xbar_asrc_in3_port>, <&xbar_asrc_in4_port>, <&xbar_asrc_in5_port>, <&xbar_asrc_in6_port>, <&xbar_asrc_in7_port>, + <&xbar_ope1_in_port>, /* HW accelerators */ <&sfc1_out_port>, <&sfc2_out_port>, <&sfc3_out_port>, <&sfc4_out_port>, @@ -2571,6 +2613,7 @@ <&mixer_out5_port>, <&asrc_out1_port>, <&asrc_out2_port>, <&asrc_out3_port>, <&asrc_out4_port>, <&asrc_out5_port>, <&asrc_out6_port>, + <&ope1_out_port>, /* I/O */ <&i2s1_port>, <&i2s2_port>, <&i2s3_port>, <&i2s4_port>, <&i2s5_port>, <&i2s6_port>, <&dmic1_port>, <&dmic2_port>, diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dts b/arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dts index 7e9aad9ff177..3e83a4d52eb1 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dts +++ b/arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dts @@ -360,7 +360,7 @@ gpio-keys { compatible = "gpio-keys"; - power { + key-power { label = "Power"; gpios = <&gpio_aon TEGRA186_AON_GPIO(FF, 0) GPIO_ACTIVE_LOW>; @@ -371,7 +371,7 @@ wakeup-source; }; - volume-up { + key-volume-up { label = "Volume Up"; gpios = <&gpio_aon TEGRA186_AON_GPIO(FF, 1) GPIO_ACTIVE_LOW>; @@ -380,7 +380,7 @@ debounce-interval = <10>; }; - volume-down { + key-volume-down { label = "Volume Down"; gpios = <&gpio_aon TEGRA186_AON_GPIO(FF, 2) GPIO_ACTIVE_LOW>; diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index 0e9afc3e2f26..59a10fb184f8 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -509,6 +509,29 @@ status = "disabled"; }; + tegra_ope1: processing-engine@2908000 { + compatible = "nvidia,tegra186-ope", + "nvidia,tegra210-ope"; + reg = <0x2908000 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + sound-name-prefix = "OPE1"; + status = "disabled"; + + equalizer@2908100 { + compatible = "nvidia,tegra186-peq", + "nvidia,tegra210-peq"; + reg = <0x2908100 0x100>; + }; + + dynamic-range-compressor@2908200 { + compatible = "nvidia,tegra186-mbdrc", + "nvidia,tegra210-mbdrc"; + reg = <0x2908200 0x200>; + }; + }; + tegra_amixer: amixer@290bb00 { compatible = "nvidia,tegra186-amixer", "nvidia,tegra210-amixer"; @@ -576,7 +599,7 @@ <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; + status = "okay"; }; uarta: serial@3100000 { @@ -1461,6 +1484,17 @@ iommus = <&smmu TEGRA186_SID_HOST1X>; + /* Context isolation domains */ + iommu-map = < + 0 &smmu TEGRA186_SID_HOST1X_CTX0 1 + 1 &smmu TEGRA186_SID_HOST1X_CTX1 1 + 2 &smmu TEGRA186_SID_HOST1X_CTX2 1 + 3 &smmu TEGRA186_SID_HOST1X_CTX3 1 + 4 &smmu TEGRA186_SID_HOST1X_CTX4 1 + 5 &smmu TEGRA186_SID_HOST1X_CTX5 1 + 6 &smmu TEGRA186_SID_HOST1X_CTX6 1 + 7 &smmu TEGRA186_SID_HOST1X_CTX7 1>; + dpaux1: dpaux@15040000 { compatible = "nvidia,tegra186-dpaux"; reg = <0x15040000 0x10000>; @@ -1820,6 +1854,7 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x0 0x30000000 0x50000>; + no-memory-wc; cpu_bpmp_tx: sram@4e000 { reg = <0x4e000 0x1000>; diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi index a7d7cfd66379..b0f9393dd39c 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi @@ -75,7 +75,7 @@ /* SDMMC1 (SD/MMC) */ mmc@3400000 { - cd-gpios = <&gpio TEGRA194_MAIN_GPIO(A, 0) GPIO_ACTIVE_LOW>; + cd-gpios = <&gpio TEGRA194_MAIN_GPIO(G, 7) GPIO_ACTIVE_LOW>; }; /* SDMMC4 (eMMC) */ diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts index bce518ace6a0..bc1041d11f6d 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts @@ -868,6 +868,22 @@ remote-endpoint = <&asrc_in7_ep>; }; }; + + xbar_ope1_in_port: port@70 { + reg = <0x70>; + + xbar_ope1_in_ep: endpoint { + remote-endpoint = <&ope1_cif_in_ep>; + }; + }; + + port@71 { + reg = <0x71>; + + xbar_ope1_out_ep: endpoint { + remote-endpoint = <&ope1_cif_out_ep>; + }; + }; }; admaif@290f000 { @@ -1710,6 +1726,31 @@ }; }; + processing-engine@2908000 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0x0>; + + ope1_cif_in_ep: endpoint { + remote-endpoint = <&xbar_ope1_in_ep>; + }; + }; + + ope1_out_port: port@1 { + reg = <0x1>; + + ope1_cif_out_ep: endpoint { + remote-endpoint = <&xbar_ope1_out_ep>; + }; + }; + }; + }; + amixer@290bb00 { status = "okay"; @@ -2217,7 +2258,7 @@ gpio-keys { compatible = "gpio-keys"; - force-recovery { + key-force-recovery { label = "Force Recovery"; gpios = <&gpio TEGRA194_MAIN_GPIO(G, 0) GPIO_ACTIVE_LOW>; @@ -2226,7 +2267,7 @@ debounce-interval = <10>; }; - power { + key-power { label = "Power"; gpios = <&gpio_aon TEGRA194_AON_GPIO(EE, 4) GPIO_ACTIVE_LOW>; @@ -2273,6 +2314,7 @@ <&xbar_asrc_in3_port>, <&xbar_asrc_in4_port>, <&xbar_asrc_in5_port>, <&xbar_asrc_in6_port>, <&xbar_asrc_in7_port>, + <&xbar_ope1_in_port>, /* HW accelerators */ <&sfc1_out_port>, <&sfc2_out_port>, <&sfc3_out_port>, <&sfc4_out_port>, @@ -2291,6 +2333,7 @@ <&mixer_out4_port>, <&mixer_out5_port>, <&asrc_out1_port>, <&asrc_out2_port>, <&asrc_out3_port>, <&asrc_out4_port>, <&asrc_out5_port>, <&asrc_out6_port>, + <&ope1_out_port>, /* BE I/O Ports */ <&i2s1_port>, <&i2s2_port>, <&i2s4_port>, <&i2s6_port>, <&dmic3_port>; diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi b/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi index 7acc32dd290a..273a1ef716b6 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi @@ -878,6 +878,22 @@ remote-endpoint = <&asrc_in7_ep>; }; }; + + xbar_ope1_in_port: port@70 { + reg = <0x70>; + + xbar_ope1_in_ep: endpoint { + remote-endpoint = <&ope1_cif_in_ep>; + }; + }; + + port@71 { + reg = <0x71>; + + xbar_ope1_out_ep: endpoint { + remote-endpoint = <&ope1_cif_out_ep>; + }; + }; }; admaif@290f000 { @@ -1770,6 +1786,31 @@ }; }; + processing-engine@2908000 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0x0>; + + ope1_cif_in_ep: endpoint { + remote-endpoint = <&xbar_ope1_in_ep>; + }; + }; + + ope1_out_port: port@1 { + reg = <0x1>; + + ope1_cif_out_ep: endpoint { + remote-endpoint = <&xbar_ope1_out_ep>; + }; + }; + }; + }; + amixer@290bb00 { status = "okay"; @@ -2221,7 +2262,7 @@ gpio-keys { compatible = "gpio-keys"; - force-recovery { + key-force-recovery { label = "Force Recovery"; gpios = <&gpio TEGRA194_MAIN_GPIO(G, 0) GPIO_ACTIVE_LOW>; @@ -2230,7 +2271,7 @@ debounce-interval = <10>; }; - power { + key-power { label = "Power"; gpios = <&gpio_aon TEGRA194_AON_GPIO(EE, 4) GPIO_ACTIVE_LOW>; @@ -2323,6 +2364,7 @@ <&xbar_asrc_in3_port>, <&xbar_asrc_in4_port>, <&xbar_asrc_in5_port>, <&xbar_asrc_in6_port>, <&xbar_asrc_in7_port>, + <&xbar_ope1_in_port>, /* HW accelerators */ <&sfc1_out_port>, <&sfc2_out_port>, <&sfc3_out_port>, <&sfc4_out_port>, @@ -2342,6 +2384,7 @@ <&mixer_out5_port>, <&asrc_out1_port>, <&asrc_out2_port>, <&asrc_out3_port>, <&asrc_out4_port>, <&asrc_out5_port>, <&asrc_out6_port>, + <&ope1_out_port>, /* BE I/O Ports */ <&i2s3_port>, <&i2s5_port>, <&dmic1_port>, <&dmic2_port>, <&dmic4_port>, diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index d1f8248c00f4..d0ed55e5c860 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -23,7 +23,7 @@ #size-cells = <1>; ranges = <0x0 0x0 0x0 0x40000000>; - misc@100000 { + apbmisc: misc@100000 { compatible = "nvidia,tegra194-misc"; reg = <0x00100000 0xf000>, <0x0010f000 0x1000>; @@ -88,6 +88,27 @@ gpio-controller; }; + cbb-noc@2300000 { + compatible = "nvidia,tegra194-cbb-noc"; + reg = <0x02300000 0x1000>; + interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; + nvidia,axi2apb = <&axi2apb>; + nvidia,apbmisc = <&apbmisc>; + status = "okay"; + }; + + axi2apb: axi2apb@2390000 { + compatible = "nvidia,tegra194-axi2apb"; + reg = <0x2390000 0x1000>, + <0x23a0000 0x1000>, + <0x23b0000 0x1000>, + <0x23c0000 0x1000>, + <0x23d0000 0x1000>, + <0x23e0000 0x1000>; + status = "okay"; + }; + ethernet@2490000 { compatible = "nvidia,tegra194-eqos", "nvidia,tegra186-eqos", @@ -562,6 +583,29 @@ status = "disabled"; }; + tegra_ope1: processing-engine@2908000 { + compatible = "nvidia,tegra194-ope", + "nvidia,tegra210-ope"; + reg = <0x2908000 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + sound-name-prefix = "OPE1"; + status = "disabled"; + + equalizer@2908100 { + compatible = "nvidia,tegra194-peq", + "nvidia,tegra210-peq"; + reg = <0x2908100 0x100>; + }; + + dynamic-range-compressor@2908200 { + compatible = "nvidia,tegra194-mbdrc", + "nvidia,tegra210-mbdrc"; + reg = <0x2908200 0x200>; + }; + }; + tegra_amixer: amixer@290bb00 { compatible = "nvidia,tegra194-amixer", "nvidia,tegra210-amixer"; @@ -675,6 +719,22 @@ }; }; + timer@3010000 { + compatible = "nvidia,tegra186-timer"; + reg = <0x03010000 0x000e0000>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; + status = "okay"; + }; + uarta: serial@3100000 { compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; reg = <0x03100000 0x40>; @@ -1460,6 +1520,26 @@ #phy-cells = <0>; }; + sce-noc@b600000 { + compatible = "nvidia,tegra194-sce-noc"; + reg = <0xb600000 0x1000>; + interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; + nvidia,axi2apb = <&axi2apb>; + nvidia,apbmisc = <&apbmisc>; + status = "okay"; + }; + + rce-noc@be00000 { + compatible = "nvidia,tegra194-rce-noc"; + reg = <0xbe00000 0x1000>; + interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; + nvidia,axi2apb = <&axi2apb>; + nvidia,apbmisc = <&apbmisc>; + status = "okay"; + }; + hsp_aon: hsp@c150000 { compatible = "nvidia,tegra194-hsp"; reg = <0x0c150000 0x90000>; @@ -1594,6 +1674,25 @@ }; + aon-noc@c600000 { + compatible = "nvidia,tegra194-aon-noc"; + reg = <0xc600000 0x1000>; + interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; + nvidia,apbmisc = <&apbmisc>; + status = "okay"; + }; + + bpmp-noc@d600000 { + compatible = "nvidia,tegra194-bpmp-noc"; + reg = <0xd600000 0x1000>; + interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; + nvidia,axi2apb = <&axi2apb>; + nvidia,apbmisc = <&apbmisc>; + status = "okay"; + }; + iommu@10000000 { compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500"; reg = <0x10000000 0x800000>; @@ -1769,6 +1868,17 @@ interconnect-names = "dma-mem"; iommus = <&smmu TEGRA194_SID_HOST1X>; + /* Context isolation domains */ + iommu-map = < + 0 &smmu TEGRA194_SID_HOST1X_CTX0 1 + 1 &smmu TEGRA194_SID_HOST1X_CTX1 1 + 2 &smmu TEGRA194_SID_HOST1X_CTX2 1 + 3 &smmu TEGRA194_SID_HOST1X_CTX3 1 + 4 &smmu TEGRA194_SID_HOST1X_CTX4 1 + 5 &smmu TEGRA194_SID_HOST1X_CTX5 1 + 6 &smmu TEGRA194_SID_HOST1X_CTX6 1 + 7 &smmu TEGRA194_SID_HOST1X_CTX7 1>; + nvdec@15140000 { compatible = "nvidia,tegra194-nvdec"; reg = <0x15140000 0x00040000>; @@ -2684,6 +2794,7 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x0 0x40000000 0x50000>; + no-memory-wc; cpu_bpmp_tx: sram@4e000 { reg = <0x4e000 0x1000>; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts b/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts index 328fbfec4ee8..1e26ca91a944 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts @@ -682,6 +682,56 @@ }; }; + processing-engine@702d8000 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0x0>; + + ope1_cif_in_ep: endpoint { + remote-endpoint = <&xbar_ope1_in_ep>; + }; + }; + + ope1_out_port: port@1 { + reg = <0x1>; + + ope1_cif_out_ep: endpoint { + remote-endpoint = <&xbar_ope1_out_ep>; + }; + }; + }; + }; + + processing-engine@702d8400 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0x0>; + + ope2_cif_in_ep: endpoint { + remote-endpoint = <&xbar_ope2_in_ep>; + }; + }; + + ope2_out_port: port@1 { + reg = <0x1>; + + ope2_cif_out_ep: endpoint { + remote-endpoint = <&xbar_ope2_out_ep>; + }; + }; + }; + }; + amixer@702dbb00 { status = "okay"; @@ -1251,6 +1301,38 @@ remote-endpoint = <&mixer_out5_ep>; }; }; + + xbar_ope1_in_port: port@41 { + reg = <0x41>; + + xbar_ope1_in_ep: endpoint { + remote-endpoint = <&ope1_cif_in_ep>; + }; + }; + + port@42 { + reg = <0x42>; + + xbar_ope1_out_ep: endpoint { + remote-endpoint = <&ope1_cif_out_ep>; + }; + }; + + xbar_ope2_in_port: port@43 { + reg = <0x43>; + + xbar_ope2_in_ep: endpoint { + remote-endpoint = <&ope2_cif_in_ep>; + }; + }; + + port@44 { + reg = <0x44>; + + xbar_ope2_out_ep: endpoint { + remote-endpoint = <&ope2_cif_out_ep>; + }; + }; }; }; }; @@ -1281,6 +1363,7 @@ <&xbar_mixer_in5_port>, <&xbar_mixer_in6_port>, <&xbar_mixer_in7_port>, <&xbar_mixer_in8_port>, <&xbar_mixer_in9_port>, <&xbar_mixer_in10_port>, + <&xbar_ope1_in_port>, <&xbar_ope2_in_port>, /* HW accelerators */ <&sfc1_out_port>, <&sfc2_out_port>, <&sfc3_out_port>, <&sfc4_out_port>, @@ -1293,6 +1376,7 @@ <&mixer_out1_port>, <&mixer_out2_port>, <&mixer_out3_port>, <&mixer_out4_port>, <&mixer_out5_port>, + <&ope1_out_port>, <&ope2_out_port>, /* I/O DAP Ports */ <&i2s1_port>, <&i2s2_port>, <&i2s3_port>, <&i2s4_port>, <&i2s5_port>, <&dmic1_port>, <&dmic2_port>, <&dmic3_port>; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi index 4b43b89a9651..a44c56c1e56e 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi @@ -1530,20 +1530,20 @@ compatible = "gpio-keys"; label = "gpio-keys"; - power { + key-power { label = "Power"; gpios = <&gpio TEGRA_GPIO(X, 5) GPIO_ACTIVE_LOW>; linux,code = <KEY_POWER>; wakeup-source; }; - volume_down { + key-volume-down { label = "Volume Down"; gpios = <&gpio TEGRA_GPIO(Y, 0) GPIO_ACTIVE_LOW>; linux,code = <KEY_VOLUMEDOWN>; }; - volume_up { + key-volume-up { label = "Volume Up"; gpios = <&gpio TEGRA_GPIO(X, 6) GPIO_ACTIVE_LOW>; linux,code = <KEY_VOLUMEUP>; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi index 10347b6e6e84..8e657b10569d 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi @@ -1596,7 +1596,7 @@ compatible = "gpio-keys"; status = "okay"; - power { + key-power { debounce-interval = <30>; gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_LOW>; label = "Power"; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts index 746bd52ea3f7..37678c337a34 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts @@ -1074,6 +1074,56 @@ }; }; + processing-engine@702d8000 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0x0>; + + ope1_cif_in_ep: endpoint { + remote-endpoint = <&xbar_ope1_in_ep>; + }; + }; + + ope1_out_port: port@1 { + reg = <0x1>; + + ope1_cif_out_ep: endpoint { + remote-endpoint = <&xbar_ope1_out_ep>; + }; + }; + }; + }; + + processing-engine@702d8400 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0x0>; + + ope2_cif_in_ep: endpoint { + remote-endpoint = <&xbar_ope2_in_ep>; + }; + }; + + ope2_out_port: port@1 { + reg = <0x1>; + + ope2_cif_out_ep: endpoint { + remote-endpoint = <&xbar_ope2_out_ep>; + }; + }; + }; + }; + amixer@702dbb00 { status = "okay"; @@ -1611,6 +1661,38 @@ remote-endpoint = <&mixer_out5_ep>; }; }; + + xbar_ope1_in_port: port@41 { + reg = <0x41>; + + xbar_ope1_in_ep: endpoint { + remote-endpoint = <&ope1_cif_in_ep>; + }; + }; + + port@42 { + reg = <0x42>; + + xbar_ope1_out_ep: endpoint { + remote-endpoint = <&ope1_cif_out_ep>; + }; + }; + + xbar_ope2_in_port: port@43 { + reg = <0x43>; + + xbar_ope2_in_ep: endpoint { + remote-endpoint = <&ope2_cif_in_ep>; + }; + }; + + port@44 { + reg = <0x44>; + + xbar_ope2_out_ep: endpoint { + remote-endpoint = <&ope2_cif_out_ep>; + }; + }; }; }; }; @@ -1720,7 +1802,7 @@ gpio-keys { compatible = "gpio-keys"; - power { + key-power { label = "Power"; gpios = <&gpio TEGRA_GPIO(X, 5) GPIO_ACTIVE_LOW>; linux,input-type = <EV_KEY>; @@ -1730,7 +1812,7 @@ wakeup-source; }; - force-recovery { + key-force-recovery { label = "Force Recovery"; gpios = <&gpio TEGRA_GPIO(X, 6) GPIO_ACTIVE_LOW>; linux,input-type = <EV_KEY>; @@ -1884,6 +1966,7 @@ <&xbar_mixer_in5_port>, <&xbar_mixer_in6_port>, <&xbar_mixer_in7_port>, <&xbar_mixer_in8_port>, <&xbar_mixer_in9_port>, <&xbar_mixer_in10_port>, + <&xbar_ope1_in_port>, <&xbar_ope2_in_port>, /* HW accelerators */ <&sfc1_out_port>, <&sfc2_out_port>, <&sfc3_out_port>, <&sfc4_out_port>, @@ -1896,6 +1979,7 @@ <&mixer_out1_port>, <&mixer_out2_port>, <&mixer_out3_port>, <&mixer_out4_port>, <&mixer_out5_port>, + <&ope1_out_port>, <&ope2_out_port>, /* I/O DAP Ports */ <&i2s3_port>, <&i2s4_port>, <&dmic1_port>, <&dmic2_port>; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts index a263d51882ee..5f3a1c56b2eb 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts @@ -1756,7 +1756,7 @@ gpio-keys { compatible = "gpio-keys"; - power { + key-power { label = "Power"; gpios = <&gpio TEGRA_GPIO(X, 5) GPIO_ACTIVE_LOW>; linux,code = <KEY_POWER>; @@ -1764,7 +1764,7 @@ wakeup-source; }; - lid { + switch-lid { label = "Lid"; gpios = <&gpio TEGRA_GPIO(B, 4) GPIO_ACTIVE_LOW>; linux,input-type = <EV_SW>; @@ -1772,7 +1772,7 @@ wakeup-source; }; - tablet_mode { + switch-tablet-mode { label = "Tablet Mode"; gpios = <&gpio TEGRA_GPIO(Z, 2) GPIO_ACTIVE_HIGH>; linux,input-type = <EV_SW>; @@ -1780,13 +1780,13 @@ wakeup-source; }; - volume_down { + key-volume-down { label = "Volume Down"; gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_LOW>; linux,code = <KEY_VOLUMEDOWN>; }; - volume_up { + key-volume-up { label = "Volume Up"; gpios = <&gpio TEGRA_GPIO(M, 4) GPIO_ACTIVE_LOW>; linux,code = <KEY_VOLUMEUP>; diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index 4f0e51f1a343..724e87450605 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -1055,7 +1055,7 @@ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; resets = <&tegra_car 142>; reset-names = "padctl"; - nvidia,pmc = <&tegra_pmc>; + nvidia,pmc = <&tegra_pmc>; status = "disabled"; @@ -1723,6 +1723,46 @@ status = "disabled"; }; + tegra_ope1: processing-engine@702d8000 { + compatible = "nvidia,tegra210-ope"; + reg = <0x702d8000 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + sound-name-prefix = "OPE1"; + status = "disabled"; + + equalizer@702d8100 { + compatible = "nvidia,tegra210-peq"; + reg = <0x702d8100 0x100>; + }; + + dynamic-range-compressor@702d8200 { + compatible = "nvidia,tegra210-mbdrc"; + reg = <0x702d8200 0x200>; + }; + }; + + tegra_ope2: processing-engine@702d8400 { + compatible = "nvidia,tegra210-ope"; + reg = <0x702d8400 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + sound-name-prefix = "OPE2"; + status = "disabled"; + + equalizer@702d8500 { + compatible = "nvidia,tegra210-peq"; + reg = <0x702d8500 0x100>; + }; + + dynamic-range-compressor@702d8600 { + compatible = "nvidia,tegra210-mbdrc"; + reg = <0x702d8600 0x200>; + }; + }; + tegra_amixer: amixer@702dbb00 { compatible = "nvidia,tegra210-amixer"; reg = <0x702dbb00 0x800>; diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts index eaf1994abb04..02a10bb38562 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts @@ -867,6 +867,22 @@ remote-endpoint = <&asrc_in7_ep>; }; }; + + xbar_ope1_in_port: port@70 { + reg = <0x70>; + + xbar_ope1_in_ep: endpoint { + remote-endpoint = <&ope1_cif_in_ep>; + }; + }; + + port@71 { + reg = <0x71>; + + xbar_ope1_out_ep: endpoint { + remote-endpoint = <&ope1_cif_out_ep>; + }; + }; }; i2s@2901000 { @@ -1490,6 +1506,31 @@ }; }; + processing-engine@2908000 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0x0>; + + ope1_cif_in_ep: endpoint { + remote-endpoint = <&xbar_ope1_in_ep>; + }; + }; + + ope1_out_port: port@1 { + reg = <0x1>; + + ope1_cif_out_ep: endpoint { + remote-endpoint = <&xbar_ope1_out_ep>; + }; + }; + }; + }; + mvc@290a000 { status = "okay"; @@ -1980,14 +2021,14 @@ compatible = "gpio-keys"; status = "okay"; - force-recovery { + key-force-recovery { label = "Force Recovery"; gpios = <&gpio TEGRA234_MAIN_GPIO(G, 0) GPIO_ACTIVE_LOW>; linux,input-type = <EV_KEY>; linux,code = <BTN_1>; }; - power-key { + key-power { label = "Power"; gpios = <&gpio_aon TEGRA234_AON_GPIO(EE, 4) GPIO_ACTIVE_LOW>; linux,input-type = <EV_KEY>; @@ -1996,7 +2037,7 @@ wakeup-source; }; - suspend { + key-suspend { label = "Suspend"; gpios = <&gpio TEGRA234_MAIN_GPIO(G, 2) GPIO_ACTIVE_LOW>; linux,input-type = <EV_KEY>; @@ -2044,6 +2085,7 @@ <&xbar_asrc_in3_port>, <&xbar_asrc_in4_port>, <&xbar_asrc_in5_port>, <&xbar_asrc_in6_port>, <&xbar_asrc_in7_port>, + <&xbar_ope1_in_port>, /* HW accelerators */ <&sfc1_out_port>, <&sfc2_out_port>, <&sfc3_out_port>, <&sfc4_out_port>, @@ -2062,6 +2104,7 @@ <&mix_out4_port>, <&mix_out5_port>, <&asrc_out1_port>, <&asrc_out2_port>, <&asrc_out3_port>, <&asrc_out4_port>, <&asrc_out5_port>, <&asrc_out6_port>, + <&ope1_out_port>, /* BE I/O Ports */ <&i2s1_port>, <&i2s2_port>, <&i2s4_port>, <&i2s6_port>, <&dmic3_port>; diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index cb3af539e477..81a0f599685f 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -21,6 +21,49 @@ ranges = <0x0 0x0 0x0 0x40000000>; + gpcdma: dma-controller@2600000 { + compatible = "nvidia,tegra234-gpcdma", + "nvidia,tegra194-gpcdma", + "nvidia,tegra186-gpcdma"; + reg = <0x2600000 0x210000>; + resets = <&bpmp TEGRA234_RESET_GPCDMA>; + reset-names = "gpcdma"; + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; + iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; + dma-coherent; + }; + aconnect@2900000 { compatible = "nvidia,tegra234-aconnect", "nvidia,tegra210-aconnect"; @@ -304,6 +347,29 @@ status = "disabled"; }; + tegra_ope1: processing-engine@2908000 { + compatible = "nvidia,tegra234-ope", + "nvidia,tegra210-ope"; + reg = <0x2908000 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + sound-name-prefix = "OPE1"; + status = "disabled"; + + equalizer@2908100 { + compatible = "nvidia,tegra234-peq", + "nvidia,tegra210-peq"; + reg = <0x2908100 0x100>; + }; + + dynamic-range-compressor@2908200 { + compatible = "nvidia,tegra234-mbdrc", + "nvidia,tegra210-mbdrc"; + reg = <0x2908200 0x200>; + }; + }; + tegra_mvc1: mvc@290a000 { compatible = "nvidia,tegra234-mvc", "nvidia,tegra210-mvc"; @@ -454,6 +520,74 @@ status = "okay"; }; + timer@2080000 { + compatible = "nvidia,tegra234-timer"; + reg = <0x02080000 0x00121000>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; + status = "okay"; + }; + + host1x@13e00000 { + compatible = "nvidia,tegra234-host1x"; + reg = <0x13e00000 0x10000>, + <0x13e10000 0x10000>, + <0x13e40000 0x10000>; + reg-names = "common", "hypervisor", "vm"; + interrupts = <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "syncpt0", "syncpt1", "syncpt2", "syncpt3", "syncpt4", + "syncpt5", "syncpt6", "syncpt7", "host1x"; + clocks = <&bpmp TEGRA234_CLK_HOST1X>; + clock-names = "host1x"; + + #address-cells = <1>; + #size-cells = <1>; + + ranges = <0x15000000 0x15000000 0x01000000>; + interconnects = <&mc TEGRA234_MEMORY_CLIENT_HOST1XDMAR &emc>; + interconnect-names = "dma-mem"; + iommus = <&smmu_niso1 TEGRA234_SID_HOST1X>; + + vic@15340000 { + compatible = "nvidia,tegra234-vic"; + reg = <0x15340000 0x00040000>; + interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&bpmp TEGRA234_CLK_VIC>; + clock-names = "vic"; + resets = <&bpmp TEGRA234_RESET_VIC>; + reset-names = "vic"; + + power-domains = <&bpmp TEGRA234_POWER_DOMAIN_VIC>; + interconnects = <&mc TEGRA234_MEMORY_CLIENT_VICSRD &emc>, + <&mc TEGRA234_MEMORY_CLIENT_VICSWR &emc>; + interconnect-names = "dma-mem", "write"; + iommus = <&smmu_niso1 TEGRA234_SID_VIC>; + dma-coherent; + }; + }; + gpio: gpio@2200000 { compatible = "nvidia,tegra234-gpio"; reg-names = "security", "gpio"; @@ -933,6 +1067,20 @@ status = "okay"; }; + sce-fabric@b600000 { + compatible = "nvidia,tegra234-sce-fabric"; + reg = <0xb600000 0x40000>; + interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; + status = "okay"; + }; + + rce-fabric@be00000 { + compatible = "nvidia,tegra234-rce-fabric"; + reg = <0xbe00000 0x40000>; + interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; + status = "okay"; + }; + hsp_aon: hsp@c150000 { compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp"; reg = <0x0c150000 0x90000>; @@ -1017,6 +1165,27 @@ interrupt-controller; }; + aon-fabric@c600000 { + compatible = "nvidia,tegra234-aon-fabric"; + reg = <0xc600000 0x40000>; + interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; + status = "okay"; + }; + + bpmp-fabric@d600000 { + compatible = "nvidia,tegra234-bpmp-fabric"; + reg = <0xd600000 0x40000>; + interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; + status = "okay"; + }; + + dce-fabric@de00000 { + compatible = "nvidia,tegra234-sce-fabric"; + reg = <0xde00000 0x40000>; + interrupts = <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>; + status = "okay"; + }; + gic: interrupt-controller@f400000 { compatible = "arm,gic-v3"; reg = <0x0f400000 0x010000>, /* GICD */ @@ -1310,6 +1479,13 @@ nvidia,memory-controller = <&mc>; status = "okay"; }; + + cbb-fabric@13a00000 { + compatible = "nvidia,tegra234-cbb-fabric"; + reg = <0x13a00000 0x400000>; + interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; + status = "okay"; + }; }; ccplex@e000000 { @@ -1325,6 +1501,7 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x0 0x40000000 0x80000>; + no-memory-wc; cpu_bpmp_tx: sram@70000 { reg = <0x70000 0x1000>; diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 2f8aec2cc6db..1d86a33de528 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -30,13 +30,11 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8994-sony-xperia-kitakami-satsuki.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8994-sony-xperia-kitakami-sumire.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8994-sony-xperia-kitakami-suzuran.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8996-mtp.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8996-pmi8996-sony-xperia-tone-dora.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8996-pmi8996-sony-xperia-tone-kagura.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8996-pmi8996-sony-xperia-tone-keyaki.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8996-sony-xperia-tone-dora.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8996-sony-xperia-tone-kagura.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8996-sony-xperia-tone-keyaki.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8996-xiaomi-gemini.dtb +dtb-$(CONFIG_ARCH_QCOM) += msm8996-xiaomi-natrium.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8996-xiaomi-scorpio.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8998-asus-novago-tp370ql.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8998-fxtec-pro1.dtb @@ -52,6 +50,7 @@ dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-1000.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-4000.dtb dtb-$(CONFIG_ARCH_QCOM) += qrb5165-rb5.dtb dtb-$(CONFIG_ARCH_QCOM) += sa8155p-adp.dtb +dtb-$(CONFIG_ARCH_QCOM) += sa8295p-adp.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-idp.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-r1.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-r1-lte.dtb @@ -60,6 +59,8 @@ dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-r3-lte.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-homestar-r2.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-homestar-r3.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-homestar-r4.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-kingoftown-r0.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-kingoftown-r1.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r0.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r1.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r1-kb.dtb @@ -75,12 +76,28 @@ dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-limozeen-r9.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-limozeen-nots-r4.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-limozeen-nots-r5.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-limozeen-nots-r9.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-mrbland-rev0-auo.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-mrbland-rev0-boe.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-mrbland-rev1-auo.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-mrbland-rev1-boe.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pazquel-lte-parade.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pazquel-lte-ti.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pazquel-parade.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pazquel-ti.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pompom-r1.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pompom-r1-lte.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pompom-r2.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pompom-r2-lte.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pompom-r3.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pompom-r3-lte.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-quackingstick-r0.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-quackingstick-r0-lte.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-wormdingler-rev0-boe.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-wormdingler-rev0-inx.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-wormdingler-rev1-boe.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-wormdingler-rev1-inx.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-wormdingler-rev1-inx-rt5682s.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-wormdingler-rev1-boe-rt5682s.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-r1.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-r1-lte.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-crd.dtb @@ -89,6 +106,9 @@ dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-villager-r0.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7280-idp.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7280-idp2.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7280-crd-r3.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc8280xp-crd.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc8280xp-lenovo-thinkpad-x13s.dtb +dtb-$(CONFIG_ARCH_QCOM) += sda660-inforce-ifc6560.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm630-sony-xperia-ganges-kirin.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm630-sony-xperia-nile-discovery.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm630-sony-xperia-nile-pioneer.dtb @@ -100,6 +120,8 @@ dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r1.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r2.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r3.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-db845c.dtb +dtb-$(CONFIG_ARCH_QCOM) += sdm845-lg-judyln.dtb +dtb-$(CONFIG_ARCH_QCOM) += sdm845-lg-judyp.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-oneplus-enchilada.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-oneplus-fajita.dtb @@ -107,6 +129,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sdm845-sony-xperia-tama-akari.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-sony-xperia-tama-akatsuki.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-sony-xperia-tama-apollo.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-xiaomi-beryllium.dtb +dtb-$(CONFIG_ARCH_QCOM) += sdm845-xiaomi-polaris.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-shift-axolotl.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm850-lenovo-yoga-c630.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm850-samsung-w737.dtb diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dts b/arch/arm64/boot/dts/qcom/apq8016-sbc.dts index 7c1eab605c15..1b613098fb4a 100644 --- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dts +++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dts @@ -8,6 +8,7 @@ #include "msm8916-pm8916.dtsi" #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> #include <dt-bindings/pinctrl/qcom,pmic-gpio.h> #include <dt-bindings/pinctrl/qcom,pmic-mpp.h> #include <dt-bindings/sound/apq8016-lpass.h> @@ -20,11 +21,11 @@ serial0 = &blsp1_uart2; serial1 = &blsp1_uart1; usid0 = &pm8916_0; - i2c0 = &blsp_i2c2; - i2c1 = &blsp_i2c6; - i2c3 = &blsp_i2c4; - spi0 = &blsp_spi5; - spi1 = &blsp_spi3; + i2c0 = &blsp_i2c2; + i2c1 = &blsp_i2c6; + i2c3 = &blsp_i2c4; + spi0 = &blsp_spi5; + spi1 = &blsp_spi3; }; chosen { @@ -92,14 +93,12 @@ gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; autorepeat; pinctrl-names = "default"; pinctrl-0 = <&msm_key_volp_n_default>; - button@0 { + button { label = "Volume Up"; linux,code = <KEY_VOLUMEUP>; gpios = <&msmgpio 107 GPIO_ACTIVE_LOW>; @@ -116,6 +115,8 @@ led@1 { label = "apq8016-sbc:green:user1"; + function = LED_FUNCTION_HEARTBEAT; + color = <LED_COLOR_ID_GREEN>; gpios = <&msmgpio 21 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; default-state = "off"; @@ -123,6 +124,8 @@ led@2 { label = "apq8016-sbc:green:user2"; + function = LED_FUNCTION_DISK_ACTIVITY; + color = <LED_COLOR_ID_GREEN>; gpios = <&msmgpio 120 GPIO_ACTIVE_HIGH>; linux,default-trigger = "mmc0"; default-state = "off"; @@ -130,6 +133,8 @@ led@3 { label = "apq8016-sbc:green:user3"; + function = LED_FUNCTION_DISK_ACTIVITY; + color = <LED_COLOR_ID_GREEN>; gpios = <&pm8916_gpios 1 GPIO_ACTIVE_HIGH>; linux,default-trigger = "mmc1"; default-state = "off"; @@ -137,6 +142,7 @@ led@4 { label = "apq8016-sbc:green:user4"; + color = <LED_COLOR_ID_GREEN>; gpios = <&pm8916_gpios 2 GPIO_ACTIVE_HIGH>; linux,default-trigger = "none"; panic-indicator; @@ -145,6 +151,8 @@ led@5 { label = "apq8016-sbc:yellow:wlan"; + function = LED_FUNCTION_WLAN; + color = <LED_COLOR_ID_YELLOW>; gpios = <&pm8916_mpps 2 GPIO_ACTIVE_HIGH>; linux,default-trigger = "phy0tx"; default-state = "off"; @@ -152,6 +160,8 @@ led@6 { label = "apq8016-sbc:blue:bt"; + function = LED_FUNCTION_BLUETOOTH; + color = <LED_COLOR_ID_BLUE>; gpios = <&pm8916_mpps 3 GPIO_ACTIVE_HIGH>; linux,default-trigger = "bluetooth-power"; default-state = "off"; @@ -773,7 +783,7 @@ "USB_HUB_RESET_N_PM", "USB_SW_SEL_PM"; - usb_hub_reset_pm: usb-hub-reset-pm { + usb_hub_reset_pm: usb-hub-reset-pm-state { pins = "gpio3"; function = PMIC_GPIO_FUNC_NORMAL; @@ -781,14 +791,14 @@ output-high; }; - usb_hub_reset_pm_device: usb-hub-reset-pm-device { + usb_hub_reset_pm_device: usb-hub-reset-pm-device-state { pins = "gpio3"; function = PMIC_GPIO_FUNC_NORMAL; output-low; }; - usb_sw_sel_pm: usb-sw-sel-pm { + usb_sw_sel_pm: usb-sw-sel-pm-state { pins = "gpio4"; function = PMIC_GPIO_FUNC_NORMAL; @@ -797,7 +807,7 @@ output-high; }; - usb_sw_sel_pm_device: usb-sw-sel-pm-device { + usb_sw_sel_pm_device: usb-sw-sel-pm-device-state { pins = "gpio4"; function = PMIC_GPIO_FUNC_NORMAL; @@ -806,7 +816,7 @@ output-low; }; - pm8916_gpios_leds: pm8916-gpios-leds { + pm8916_gpios_leds: pm8916-gpios-leds-state { pins = "gpio1", "gpio2"; function = PMIC_GPIO_FUNC_NORMAL; diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c.dts b/arch/arm64/boot/dts/qcom/apq8096-db820c.dts index 49afbb1a066a..c1cb1ba5173c 100644 --- a/arch/arm64/boot/dts/qcom/apq8096-db820c.dts +++ b/arch/arm64/boot/dts/qcom/apq8096-db820c.dts @@ -10,6 +10,7 @@ #include "pmi8994.dtsi" #include <dt-bindings/input/input.h> #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/leds/common.h> #include <dt-bindings/pinctrl/qcom,pmic-gpio.h> #include <dt-bindings/sound/qcom,q6afe.h> #include <dt-bindings/sound/qcom,q6asm.h> @@ -49,11 +50,11 @@ serial0 = &blsp2_uart2; serial1 = &blsp2_uart3; serial2 = &blsp1_uart2; - i2c0 = &blsp1_i2c3; - i2c1 = &blsp2_i2c1; - i2c2 = &blsp2_i2c1; - spi0 = &blsp1_spi1; - spi1 = &blsp2_spi6; + i2c0 = &blsp1_i2c3; + i2c1 = &blsp2_i2c1; + i2c2 = &blsp2_i2c1; + spi0 = &blsp1_spi1; + spi1 = &blsp2_spi6; }; chosen { @@ -82,16 +83,14 @@ }; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; autorepeat; pinctrl-names = "default"; pinctrl-0 = <&volume_up_gpio>; - button@0 { + button { label = "Volume Up"; linux,code = <KEY_VOLUMEUP>; gpios = <&pm8994_gpios 2 GPIO_ACTIVE_LOW>; @@ -555,15 +554,16 @@ pinctrl-names = "default"; pinctrl-0 = <&ls_exp_gpio_f &bt_en_gpios>; - ls_exp_gpio_f: pm8994_gpio5 { + ls_exp_gpio_f: pm8994-gpio5-state { pinconf { pins = "gpio5"; + function = PMIC_GPIO_FUNC_NORMAL; output-low; power-source = <2>; // PM8994_GPIO_S4, 1.8V }; }; - bt_en_gpios: bt_en_gpios { + bt_en_gpios: bt-en-pios-state { pinconf { pins = "gpio19"; function = PMIC_GPIO_FUNC_NORMAL; @@ -574,7 +574,7 @@ }; }; - wlan_en_gpios: wlan_en_gpios { + wlan_en_gpios: wlan-en-gpios-state { pinconf { pins = "gpio8"; function = PMIC_GPIO_FUNC_NORMAL; @@ -585,7 +585,7 @@ }; }; - audio_mclk: clk_div1 { + audio_mclk: clk-div1-state { pinconf { pins = "gpio15"; function = "func1"; @@ -593,7 +593,7 @@ }; }; - volume_up_gpio: pm8996_gpio2 { + volume_up_gpio: pm8996-gpio2-state { pinconf { pins = "gpio2"; function = "normal"; @@ -605,7 +605,7 @@ }; }; - divclk4_pin_a: divclk4 { + divclk4_pin_a: divclk4-state { pinconf { pins = "gpio18"; function = PMIC_GPIO_FUNC_FUNC2; @@ -615,7 +615,7 @@ }; }; - usb3_vbus_det_gpio: pm8996_gpio22 { + usb3_vbus_det_gpio: pm8996-gpio22-state { pinconf { pins = "gpio22"; function = PMIC_GPIO_FUNC_NORMAL; @@ -671,7 +671,7 @@ "NC", "NC"; - usb2_vbus_det_gpio: pmi8996_gpio6 { + usb2_vbus_det_gpio: pmi8996-gpio6-state { pinconf { pins = "gpio6"; function = PMIC_GPIO_FUNC_NORMAL; @@ -683,6 +683,61 @@ }; }; +&pmi8994_lpg { + qcom,power-source = <1>; + + pinctrl-names = "default"; + pinctrl-0 = <&pmi8994_mpp2_userled4>; + + qcom,dtest = <0 0>, + <0 0>, + <0 0>, + <4 1>; + + status = "okay"; + + led@1 { + reg = <1>; + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_HEARTBEAT; + function-enumerator = <1>; + + linux,default-trigger = "heartbeat"; + default-state = "on"; + }; + + led@2 { + reg = <2>; + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_HEARTBEAT; + function-enumerator = <0>; + }; + + led@3 { + reg = <3>; + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_HEARTBEAT; + function-enumerator = <2>; + }; + + led@4 { + reg = <4>; + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_HEARTBEAT; + function-enumerator = <3>; + }; +}; + +&pmi8994_mpps { + pmi8994_mpp2_userled4: mpp2-userled4-state { + pins = "mpp2"; + function = "sink"; + + output-low; + qcom,dtest = <4>; + }; +}; + &pmi8994_spmi_regulators { vdd_s2-supply = <&vph_pwr>; @@ -957,7 +1012,7 @@ &sound { compatible = "qcom,apq8096-sndcard"; model = "DB820c"; - audio-routing = "RX_BIAS", "MCLK", + audio-routing = "RX_BIAS", "MCLK", "MM_DL1", "MultiMedia1 Playback", "MM_DL2", "MultiMedia2 Playback", "MultiMedia3 Capture", "MM_UL3"; diff --git a/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts index 821cb7c0c183..1ba2eca33c7b 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts +++ b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts @@ -29,13 +29,13 @@ status = "okay"; }; -&i2c_1 { +&blsp1_i2c3 { pinctrl-0 = <&i2c_1_pins>; pinctrl-names = "default"; status = "okay"; }; -&spi_0 { +&blsp1_spi1 { cs-select = <0>; status = "okay"; @@ -43,7 +43,7 @@ #address-cells = <1>; #size-cells = <1>; reg = <0>; - compatible = "n25q128a11"; + compatible = "micron,n25q128a11", "jedec,spi-nor"; spi-max-frequency = <50000000>; }; }; diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi index c89499e366d3..aaad7d9059f6 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi @@ -87,7 +87,7 @@ }; }; - cpu_opp_table: cpu_opp_table { + cpu_opp_table: opp-table-cpu { compatible = "operating-points-v2"; opp-shared; @@ -125,7 +125,7 @@ firmware { scm { - compatible = "qcom,scm"; + compatible = "qcom,scm-ipq6018", "qcom,scm"; }; }; @@ -282,7 +282,7 @@ status = "disabled"; }; - spi_0: spi@78b5000 { + blsp1_spi1: spi@78b5000 { compatible = "qcom,spi-qup-v2.2.1"; #address-cells = <1>; #size-cells = <0>; @@ -297,7 +297,7 @@ status = "disabled"; }; - spi_1: spi@78b6000 { + blsp1_spi2: spi@78b6000 { compatible = "qcom,spi-qup-v2.2.1"; #address-cells = <1>; #size-cells = <0>; @@ -312,7 +312,7 @@ status = "disabled"; }; - i2c_0: i2c@78b6000 { + blsp1_i2c2: i2c@78b6000 { compatible = "qcom,i2c-qup-v2.2.1"; #address-cells = <1>; #size-cells = <0>; @@ -321,13 +321,13 @@ clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; - clock-frequency = <400000>; + clock-frequency = <400000>; dmas = <&blsp_dma 14>, <&blsp_dma 15>; dma-names = "tx", "rx"; status = "disabled"; }; - i2c_1: i2c@78b7000 { /* BLSP1 QUP2 */ + blsp1_i2c3: i2c@78b7000 { compatible = "qcom,i2c-qup-v2.2.1"; #address-cells = <1>; #size-cells = <0>; @@ -336,7 +336,7 @@ clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; - clock-frequency = <400000>; + clock-frequency = <400000>; dmas = <&blsp_dma 16>, <&blsp_dma 17>; dma-names = "tx", "rx"; status = "disabled"; @@ -525,9 +525,9 @@ }; timer@b120000 { - #address-cells = <2>; - #size-cells = <2>; - ranges; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0x10000000>; compatible = "arm,armv7-timer-mem"; reg = <0x0 0x0b120000 0x0 0x1000>; @@ -535,49 +535,49 @@ frame-number = <0>; interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x0 0x0b121000 0x0 0x1000>, - <0x0 0x0b122000 0x0 0x1000>; + reg = <0x0b121000 0x1000>, + <0x0b122000 0x1000>; }; frame@b123000 { frame-number = <1>; interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x0 0xb123000 0x0 0x1000>; + reg = <0x0b123000 0x1000>; status = "disabled"; }; frame@b124000 { frame-number = <2>; interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x0 0x0b124000 0x0 0x1000>; + reg = <0x0b124000 0x1000>; status = "disabled"; }; frame@b125000 { frame-number = <3>; interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x0 0x0b125000 0x0 0x1000>; + reg = <0x0b125000 0x1000>; status = "disabled"; }; frame@b126000 { frame-number = <4>; interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x0 0x0b126000 0x0 0x1000>; + reg = <0x0b126000 0x1000>; status = "disabled"; }; frame@b127000 { frame-number = <5>; interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x0 0x0b127000 0x0 0x1000>; + reg = <0x0b127000 0x1000>; status = "disabled"; }; frame@b128000 { frame-number = <6>; interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x0 0x0b128000 0x0 0x1000>; + reg = <0x0b128000 0x1000>; status = "disabled"; }; }; @@ -621,6 +621,7 @@ glink-edge { interrupts = <GIC_SPI 321 IRQ_TYPE_EDGE_RISING>; + label = "rtr"; qcom,remote-pid = <1>; mboxes = <&apcs_glb 8>; @@ -710,7 +711,7 @@ <0x0 0x00078800 0x0 0x1F8>, /* PCS */ <0x0 0x00078600 0x0 0x044>; /* PCS misc */ #phy-cells = <0>; - #clock-cells = <1>; + #clock-cells = <0>; clocks = <&gcc GCC_USB0_PIPE_CLK>; clock-names = "pipe0"; clock-output-names = "gcc_usb0_pipe_clk_src"; diff --git a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts index de20cb98acd3..81dc3a0bcd7d 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts +++ b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts @@ -5,11 +5,8 @@ #include "ipq8074.dtsi" / { - #address-cells = <0x2>; - #size-cells = <0x2>; model = "Qualcomm Technologies, Inc. IPQ8074-HK01"; compatible = "qcom,ipq8074-hk01", "qcom,ipq8074"; - interrupt-parent = <&intc>; aliases { serial0 = &blsp1_uart5; diff --git a/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi b/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi index ce86d9b10d69..40415d988e4a 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi @@ -7,11 +7,6 @@ #include "ipq8074.dtsi" / { - #address-cells = <0x2>; - #size-cells = <0x2>; - - interrupt-parent = <&intc>; - aliases { serial0 = &blsp1_uart5; }; diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index 4c38b15c6fd4..d53675fc1595 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -7,8 +7,12 @@ #include <dt-bindings/clock/qcom,gcc-ipq8074.h> / { + #address-cells = <2>; + #size-cells = <2>; + model = "Qualcomm Technologies, Inc. IPQ8074"; compatible = "qcom,ipq8074"; + interrupt-parent = <&intc>; clocks { sleep_clk: sleep_clk { @@ -119,7 +123,7 @@ <&xo>; clock-names = "aux", "cfg_ahb", "ref"; - resets = <&gcc GCC_USB1_PHY_BCR>, + resets = <&gcc GCC_USB1_PHY_BCR>, <&gcc GCC_USB3PHY_1_PHY_BCR>; reset-names = "phy","common"; status = "disabled"; @@ -130,7 +134,7 @@ <0x00058800 0x1f8>, /* PCS */ <0x00058600 0x044>; /* PCS misc*/ #phy-cells = <0>; - #clock-cells = <1>; + #clock-cells = <0>; clocks = <&gcc GCC_USB1_PIPE_CLK>; clock-names = "pipe0"; clock-output-names = "gcc_usb1_pipe_clk_src"; @@ -162,7 +166,7 @@ <&xo>; clock-names = "aux", "cfg_ahb", "ref"; - resets = <&gcc GCC_USB0_PHY_BCR>, + resets = <&gcc GCC_USB0_PHY_BCR>, <&gcc GCC_USB3PHY_0_PHY_BCR>; reset-names = "phy","common"; status = "disabled"; @@ -173,7 +177,7 @@ <0x00078800 0x1f8>, /* PCS */ <0x00078600 0x044>; /* PCS misc*/ #phy-cells = <0>; - #clock-cells = <1>; + #clock-cells = <0>; clocks = <&gcc GCC_USB0_PIPE_CLK>; clock-names = "pipe0"; clock-output-names = "gcc_usb0_pipe_clk_src"; @@ -347,6 +351,7 @@ compatible = "qcom,gcc-ipq8074"; reg = <0x01800000 0x80000>; #clock-cells = <0x1>; + #power-domain-cells = <1>; #reset-cells = <0x1>; }; @@ -375,7 +380,7 @@ cell-index = <0>; }; - sdhc_1: sdhci@7824900 { + sdhc_1: mmc@7824900 { compatible = "qcom,sdhci-msm-v4"; reg = <0x7824900 0x500>, <0x7824000 0x800>; reg-names = "hc_mem", "core_mem"; @@ -384,10 +389,11 @@ <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "hc_irq", "pwr_irq"; - clocks = <&xo>, - <&gcc GCC_SDCC1_AHB_CLK>, - <&gcc GCC_SDCC1_APPS_CLK>; - clock-names = "xo", "iface", "core"; + clocks = <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, + <&xo>; + clock-names = "iface", "core", "xo"; + resets = <&gcc GCC_SDCC1_BCR>; max-frequency = <384000000>; mmc-ddr-1_8v; mmc-hs200-1_8v; @@ -534,7 +540,7 @@ status = "disabled"; }; - qpic_nand: nand@79b0000 { + qpic_nand: nand-controller@79b0000 { compatible = "qcom,ipq8074-nand"; reg = <0x079b0000 0x10000>; #address-cells = <1>; @@ -575,6 +581,8 @@ <133330000>, <19200000>; + power-domains = <&gcc USB0_GDSC>; + resets = <&gcc GCC_USB0_BCR>; status = "disabled"; @@ -615,6 +623,8 @@ <133330000>, <19200000>; + power-domains = <&gcc USB1_GDSC>; + resets = <&gcc GCC_USB1_BCR>; status = "disabled"; @@ -648,14 +658,6 @@ }; }; - timer { - compatible = "arm,armv8-timer"; - interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; - }; - watchdog: watchdog@b017000 { compatible = "qcom,kpss-wdt"; reg = <0xb017000 0x1000>; @@ -664,6 +666,14 @@ timeout-sec = <30>; }; + apcs_glb: mailbox@b111000 { + compatible = "qcom,ipq8074-apcs-apps-global"; + reg = <0x0b111000 0x6000>; + + #clock-cells = <1>; + #mbox-cells = <1>; + }; + timer@b120000 { #address-cells = <1>; #size-cells = <1>; @@ -847,4 +857,12 @@ status = "disabled"; }; }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; + }; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916-alcatel-idol347.dts b/arch/arm64/boot/dts/qcom/msm8916-alcatel-idol347.dts index 265e539e7e99..3dc9619fde6e 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-alcatel-idol347.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-alcatel-idol347.dts @@ -27,7 +27,7 @@ label = "GPIO Buttons"; - volume-up { + button-volume-up { label = "Volume Up"; gpios = <&msmgpio 107 GPIO_ACTIVE_LOW>; linux,code = <KEY_VOLUMEUP>; diff --git a/arch/arm64/boot/dts/qcom/msm8916-asus-z00l.dts b/arch/arm64/boot/dts/qcom/msm8916-asus-z00l.dts index d4d33dd3584a..dd92070a1211 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-asus-z00l.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-asus-z00l.dts @@ -28,14 +28,14 @@ label = "GPIO Buttons"; - volume-up { + button-volume-up { label = "Volume Up"; gpios = <&msmgpio 107 GPIO_ACTIVE_LOW>; linux,code = <KEY_VOLUMEUP>; debounce-interval = <15>; }; - volume-down { + button-volume-down { label = "Volume Down"; gpios = <&msmgpio 117 GPIO_ACTIVE_LOW>; linux,code = <KEY_VOLUMEDOWN>; diff --git a/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts b/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts index 00488afb413d..9e470c67274e 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts @@ -39,7 +39,7 @@ label = "GPIO Buttons"; - volume-up { + button-volume-up { label = "Volume Up"; gpios = <&msmgpio 107 GPIO_ACTIVE_LOW>; linux,code = <KEY_VOLUMEUP>; diff --git a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts index b3836dde8a54..d85e7f7c0835 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts @@ -39,7 +39,7 @@ label = "GPIO Buttons"; - volume-up { + button-volume-up { label = "Volume Up"; gpios = <&msmgpio 107 GPIO_ACTIVE_LOW>; linux,code = <KEY_VOLUMEUP>; diff --git a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8910.dts b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8910.dts index f9ce123471d4..b4812f093b17 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8910.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8910.dts @@ -28,7 +28,7 @@ label = "GPIO Buttons"; - volume-up { + button-volume-up { label = "Volume Up"; gpios = <&msmgpio 107 GPIO_ACTIVE_LOW>; linux,code = <KEY_VOLUMEUP>; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi index 9b4b7de7cec2..10f6509a8709 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi @@ -31,13 +31,13 @@ label = "GPIO Buttons"; - volume-up { + button-volume-up { label = "Volume Up"; gpios = <&msmgpio 107 GPIO_ACTIVE_LOW>; linux,code = <KEY_VOLUMEUP>; }; - home { + button-home { label = "Home"; gpios = <&msmgpio 109 GPIO_ACTIVE_LOW>; linux,code = <KEY_HOMEPAGE>; @@ -52,7 +52,7 @@ label = "GPIO Hall Effect Sensor"; - hall-sensor { + event-hall-sensor { label = "Hall Effect Sensor"; gpios = <&msmgpio 52 GPIO_ACTIVE_LOW>; linux,input-type = <EV_SW>; @@ -460,10 +460,18 @@ drive-strength = <2>; bias-disable; }; + + ts_int_default: ts-int-default { + pins = "gpio13"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; }; &pm8916_gpios { - nfc_clk_req: nfc-clk-req { + nfc_clk_req: nfc-clk-req-state { pins = "gpio2"; function = "func1"; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-a3u-eur.dts b/arch/arm64/boot/dts/qcom/msm8916-samsung-a3u-eur.dts index 4ba11b020f9b..bc198a2eea25 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-a3u-eur.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-a3u-eur.dts @@ -128,12 +128,4 @@ drive-strength = <2>; bias-disable; }; - - ts_int_default: ts-int-default { - pins = "gpio13"; - function = "gpio"; - - drive-strength = <2>; - bias-disable; - }; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-a5u-eur.dts b/arch/arm64/boot/dts/qcom/msm8916-samsung-a5u-eur.dts index d978c9ac179d..7f2ab1891d91 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-a5u-eur.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-a5u-eur.dts @@ -69,12 +69,4 @@ drive-strength = <2>; bias-disable; }; - - ts_int_default: ts-int-default { - pins = "gpio13"; - function = "gpio"; - - drive-strength = <2>; - bias-disable; - }; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-j5.dts b/arch/arm64/boot/dts/qcom/msm8916-samsung-j5.dts index 6c408d61de75..eabeed18cfaa 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-j5.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-j5.dts @@ -34,13 +34,13 @@ label = "GPIO Buttons"; - volume-up { + button-volume-up { label = "Volume Up"; gpios = <&msmgpio 107 GPIO_ACTIVE_LOW>; linux,code = <KEY_VOLUMEUP>; }; - home-key { + button-home { label = "Home Key"; gpios = <&msmgpio 109 GPIO_ACTIVE_LOW>; linux,code = <KEY_HOMEPAGE>; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts b/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts index 58dfbfff4c7d..439e89cf7878 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts @@ -49,13 +49,13 @@ label = "GPIO Buttons"; - volume-up { + button-volume-up { label = "Volume Up"; gpios = <&msmgpio 107 GPIO_ACTIVE_LOW>; linux,code = <KEY_VOLUMEUP>; }; - home { + button-home { label = "Home"; gpios = <&msmgpio 109 GPIO_ACTIVE_LOW>; linux,code = <KEY_HOMEPAGE>; @@ -70,7 +70,7 @@ label = "GPIO Hall Effect Sensor"; - hall-sensor { + event-hall-sensor { label = "Hall Effect Sensor"; gpios = <&msmgpio 52 GPIO_ACTIVE_LOW>; linux,input-type = <EV_SW>; diff --git a/arch/arm64/boot/dts/qcom/msm8916-wingtech-wt88047.dts b/arch/arm64/boot/dts/qcom/msm8916-wingtech-wt88047.dts index 69a44c6f57fc..84a352dcf9a2 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-wingtech-wt88047.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-wingtech-wt88047.dts @@ -29,7 +29,7 @@ label = "GPIO Buttons"; - volume-up { + button-volume-up { label = "Volume Up"; gpios = <&msmgpio 107 GPIO_ACTIVE_LOW>; linux,code = <KEY_VOLUMEUP>; diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 05472510e29d..48bc2e09128d 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -216,7 +216,7 @@ }; }; - cpu_opp_table: cpu-opp-table { + cpu_opp_table: opp-table-cpu { compatible = "operating-points-v2"; opp-shared; @@ -301,6 +301,8 @@ rpmcc: clock-controller { compatible = "qcom,rpmcc-msm8916", "qcom,rpmcc"; #clock-cells = <1>; + clocks = <&xo_board>; + clock-names = "xo"; }; rpmpd: power-controller { @@ -436,7 +438,7 @@ }; qfprom: qfprom@5c000 { - compatible = "qcom,qfprom"; + compatible = "qcom,msm8916-qfprom", "qcom,qfprom"; reg = <0x0005c000 0x1000>; #address-cells = <1>; #size-cells = <1>; @@ -1464,7 +1466,7 @@ #sound-dai-cells = <1>; }; - sdhc_1: sdhci@7824000 { + sdhc_1: mmc@7824000 { compatible = "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4"; reg = <0x07824900 0x11c>, <0x07824000 0x800>; reg-names = "hc_mem", "core_mem"; @@ -1472,17 +1474,17 @@ interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "hc_irq", "pwr_irq"; - clocks = <&gcc GCC_SDCC1_APPS_CLK>, - <&gcc GCC_SDCC1_AHB_CLK>, + clocks = <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, <&xo_board>; - clock-names = "core", "iface", "xo"; + clock-names = "iface", "core", "xo"; mmc-ddr-1_8v; bus-width = <8>; non-removable; status = "disabled"; }; - sdhc_2: sdhci@7864000 { + sdhc_2: mmc@7864000 { compatible = "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4"; reg = <0x07864900 0x11c>, <0x07864000 0x800>; reg-names = "hc_mem", "core_mem"; @@ -1490,10 +1492,10 @@ interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "hc_irq", "pwr_irq"; - clocks = <&gcc GCC_SDCC2_APPS_CLK>, - <&gcc GCC_SDCC2_AHB_CLK>, + clocks = <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, <&xo_board>; - clock-names = "core", "iface", "xo"; + clock-names = "iface", "core", "xo"; bus-width = <4>; status = "disabled"; }; @@ -1788,8 +1790,8 @@ <&rpmpd MSM8916_VDDMX>; power-domain-names = "cx", "mx"; - qcom,state = <&wcnss_smp2p_out 0>; - qcom,state-names = "stop"; + qcom,smem-states = <&wcnss_smp2p_out 0>; + qcom,smem-state-names = "stop"; pinctrl-names = "default"; pinctrl-0 = <&wcnss_pin_a>; @@ -1858,6 +1860,8 @@ compatible = "qcom,msm8916-a53pll"; reg = <0x0b016000 0x40>; #clock-cells = <0>; + clocks = <&xo_board>; + clock-names = "xo"; }; timer@b020000 { diff --git a/arch/arm64/boot/dts/qcom/msm8953.dtsi b/arch/arm64/boot/dts/qcom/msm8953.dtsi index ffc3ec2cd3bc..8416a45ca4fd 100644 --- a/arch/arm64/boot/dts/qcom/msm8953.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8953.dtsi @@ -215,7 +215,7 @@ firmware { scm: scm { - compatible = "qcom,scm-msm8953"; + compatible = "qcom,scm-msm8953", "qcom,scm"; clocks = <&gcc GCC_CRYPTO_CLK>, <&gcc GCC_CRYPTO_AXI_CLK>, <&gcc GCC_CRYPTO_AHB_CLK>; @@ -795,7 +795,7 @@ }; }; - sdhc_1: sdhci@7824900 { + sdhc_1: mmc@7824900 { compatible = "qcom,msm8953-sdhci", "qcom,sdhci-msm-v4"; reg = <0x7824900 0x500>, <0x7824000 0x800>; @@ -855,7 +855,7 @@ }; }; - sdhc_2: sdhci@7864900 { + sdhc_2: mmc@7864900 { compatible = "qcom,msm8953-sdhci", "qcom,sdhci-msm-v4"; reg = <0x7864900 0x500>, <0x7864000 0x800>; diff --git a/arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts b/arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts index afa91ca9a3dc..cbe11c060df9 100644 --- a/arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts +++ b/arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts @@ -51,13 +51,11 @@ }; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; autorepeat; - button@0 { + button { label = "Volume Up"; gpios = <&pm8994_gpios 3 GPIO_ACTIVE_LOW>; linux,input-type = <1>; diff --git a/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi b/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi index cc038f9b641f..61ec905025b0 100644 --- a/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi @@ -64,7 +64,7 @@ compatible = "gpio-keys"; autorepeat; - volupkey { + volup-key { label = "Volume Up"; gpios = <&pm8994_gpios 3 GPIO_ACTIVE_LOW>; linux,input-type = <1>; @@ -73,7 +73,7 @@ debounce-interval = <15>; }; - camsnapkey { + camsnap-key { label = "Camera Snapshot"; gpios = <&pm8994_gpios 4 GPIO_ACTIVE_LOW>; linux,input-type = <1>; @@ -82,7 +82,7 @@ debounce-interval = <15>; }; - camfocuskey { + camfocus-key { label = "Camera Focus"; gpios = <&pm8994_gpios 5 GPIO_ACTIVE_LOW>; linux,input-type = <1>; @@ -100,7 +100,7 @@ label = "GPIO Hall Effect Sensor"; - hall-front-sensor { + event-hall-front-sensor { label = "Hall Effect Front Sensor"; gpios = <&tlmm 42 GPIO_ACTIVE_HIGH>; linux,input-type = <EV_SW>; @@ -108,7 +108,7 @@ linux,can-disable; }; - hall-back-sensor { + event-hall-back-sensor { label = "Hall Effect Back Sensor"; gpios = <&tlmm 75 GPIO_ACTIVE_HIGH>; linux,input-type = <EV_SW>; @@ -470,7 +470,7 @@ }; &pm8994_gpios { - bt_en_gpios: bt_en_gpios { + bt_en_gpios: bt-en-gpios-state { pinconf { pins = "gpio19"; function = PMIC_GPIO_FUNC_NORMAL; @@ -481,7 +481,7 @@ }; }; - divclk4_pin_a: divclk4 { + divclk4_pin_a: divclk4-state { pinconf { pins = "gpio18"; function = PMIC_GPIO_FUNC_FUNC2; @@ -519,21 +519,24 @@ * TODO: remove once a driver is available * TODO: add VBUS GPIO 5 */ - hd3ss460_pol: pol_low { + hd3ss460_pol: pol-low-state { pins = "gpio8"; - drive-strength = <3>; + function = PMIC_GPIO_FUNC_NORMAL; + qcom,drive-strength = <3>; bias-pull-down; }; - hd3ss460_amsel: amsel_high { + hd3ss460_amsel: amsel-high-state { pins = "gpio9"; - drive-strength = <1>; + function = PMIC_GPIO_FUNC_NORMAL; + qcom,drive-strength = <1>; bias-pull-up; }; - hd3ss460_en: en_high { + hd3ss460_en: en-high-state { pins = "gpio10"; - drive-strength = <1>; + function = PMIC_GPIO_FUNC_NORMAL; + qcom,drive-strength = <1>; bias-pull-up; }; }; diff --git a/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi b/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi index e5a45af0bd12..f430d797196f 100644 --- a/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi @@ -27,13 +27,11 @@ /* Kitakami firmware doesn't support PSCI */ /delete-node/ psci; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; autorepeat; - button@0 { + button-0 { label = "Volume Down"; gpios = <&pm8994_gpios 2 GPIO_ACTIVE_LOW>; linux,input-type = <1>; @@ -42,7 +40,7 @@ debounce-interval = <15>; }; - button@1 { + button-1 { label = "Volume Up"; gpios = <&pm8994_gpios 3 GPIO_ACTIVE_LOW>; linux,input-type = <1>; @@ -51,7 +49,7 @@ debounce-interval = <15>; }; - button@2 { + button-2 { label = "Camera Snapshot"; gpios = <&pm8994_gpios 4 GPIO_ACTIVE_LOW>; linux,input-type = <1>; @@ -60,7 +58,7 @@ debounce-interval = <15>; }; - button@3 { + button-3 { label = "Camera Focus"; gpios = <&pm8994_gpios 5 GPIO_ACTIVE_LOW>; linux,input-type = <1>; diff --git a/arch/arm64/boot/dts/qcom/msm8994.dtsi b/arch/arm64/boot/dts/qcom/msm8994.dtsi index 1ac2913b182c..8bc6c070e306 100644 --- a/arch/arm64/boot/dts/qcom/msm8994.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994.dtsi @@ -461,7 +461,7 @@ }; }; - sdhc1: sdhci@f9824900 { + sdhc1: mmc@f9824900 { compatible = "qcom,msm8994-sdhci", "qcom,sdhci-msm-v4"; reg = <0xf9824900 0x1a0>, <0xf9824000 0x800>; reg-names = "hc_mem", "core_mem"; @@ -470,10 +470,10 @@ <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "hc_irq", "pwr_irq"; - clocks = <&gcc GCC_SDCC1_APPS_CLK>, - <&gcc GCC_SDCC1_AHB_CLK>, + clocks = <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, <&xo_board>; - clock-names = "core", "iface", "xo"; + clock-names = "iface", "core", "xo"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>; @@ -484,7 +484,7 @@ status = "disabled"; }; - sdhc2: sdhci@f98a4900 { + sdhc2: mmc@f98a4900 { compatible = "qcom,msm8994-sdhci", "qcom,sdhci-msm-v4"; reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; reg-names = "hc_mem", "core_mem"; @@ -493,10 +493,10 @@ <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "hc_irq", "pwr_irq"; - clocks = <&gcc GCC_SDCC2_APPS_CLK>, - <&gcc GCC_SDCC2_AHB_CLK>, - <&xo_board>; - clock-names = "core", "iface", "xo"; + clocks = <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, + <&xo_board>; + clock-names = "iface", "core", "xo"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>; @@ -1069,11 +1069,12 @@ <600000000>; }; - ocmem: ocmem@fdd00000 { + ocmem: sram@fdd00000 { compatible = "qcom,msm8974-ocmem"; reg = <0xfdd00000 0x2000>, <0xfec00000 0x200000>; reg-names = "ctrl", "mem"; + ranges = <0 0xfec00000 0x200000>; clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>, <&mmcc OCMEMCX_OCMEMNOC_CLK>; clock-names = "core", "iface"; diff --git a/arch/arm64/boot/dts/qcom/msm8996-pmi8996-sony-xperia-tone-dora.dts b/arch/arm64/boot/dts/qcom/msm8996-pmi8996-sony-xperia-tone-dora.dts deleted file mode 100644 index b018693600a5..000000000000 --- a/arch/arm64/boot/dts/qcom/msm8996-pmi8996-sony-xperia-tone-dora.dts +++ /dev/null @@ -1,11 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org> - */ - -#include "msm8996-sony-xperia-tone-dora.dts" -#include "pmi8996.dtsi" - -/ { - model = "Sony Xperia X Performance (PMI8996)"; -}; diff --git a/arch/arm64/boot/dts/qcom/msm8996-pmi8996-sony-xperia-tone-kagura.dts b/arch/arm64/boot/dts/qcom/msm8996-pmi8996-sony-xperia-tone-kagura.dts deleted file mode 100644 index 842ea3cf557e..000000000000 --- a/arch/arm64/boot/dts/qcom/msm8996-pmi8996-sony-xperia-tone-kagura.dts +++ /dev/null @@ -1,11 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org> - */ - -#include "msm8996-sony-xperia-tone-kagura.dts" -#include "pmi8996.dtsi" - -/ { - model = "Sony Xperia XZ (PMI8996)"; -}; diff --git a/arch/arm64/boot/dts/qcom/msm8996-pmi8996-sony-xperia-tone-keyaki.dts b/arch/arm64/boot/dts/qcom/msm8996-pmi8996-sony-xperia-tone-keyaki.dts deleted file mode 100644 index b3f9062da4b0..000000000000 --- a/arch/arm64/boot/dts/qcom/msm8996-pmi8996-sony-xperia-tone-keyaki.dts +++ /dev/null @@ -1,11 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org> - */ - -#include "msm8996-sony-xperia-tone-keyaki.dts" -#include "pmi8996.dtsi" - -/ { - model = "Sony Xperia XZs (PMI8996)"; -}; diff --git a/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi b/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi index ca3c633f5a45..e165b5e890a0 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi @@ -8,6 +8,7 @@ #include "msm8996.dtsi" #include "pm8994.dtsi" #include "pmi8994.dtsi" +#include "pmi8996.dtsi" #include <dt-bindings/input/input.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/pinctrl/qcom,pmic-gpio.h> @@ -20,7 +21,6 @@ / { qcom,msm-id = <246 0x30001>; /* MSM8996 V3.1 (Final) */ - qcom,pmic-id = <0x20009 0x2000a 0 0>; /* PM8994 + PMI8994 */ qcom,board-id = <8 0>; chosen { @@ -42,11 +42,6 @@ ecc-size = <16>; }; - cont_splash_mem: memory@83401000 { - reg = <0 0x83401000 0 0x23ff000>; - no-map; - }; - adsp_mem: adsp@8ea00000 { reg = <0x0 0x8ea00000 0x0 0x1a00000>; no-map; @@ -247,14 +242,14 @@ * probably a reason for it, and just to be on the safe side, we follow suit. */ pm8994_gpios_defaults: pm8994-gpios-default-state { - pm8994-gpio1-nc { + pm8994-gpio1-nc-pins { pins = "gpio1"; function = PMIC_GPIO_FUNC_NORMAL; drive-push-pull; bias-high-impedance; }; - vol-down-n { + vol-down-n-pins { pins = "gpio2"; function = PMIC_GPIO_FUNC_NORMAL; drive-push-pull; @@ -264,7 +259,7 @@ power-source = <PM8994_GPIO_S4>; }; - vol-up-n { + vol-up-n-pins { pins = "gpio3"; function = PMIC_GPIO_FUNC_NORMAL; drive-push-pull; @@ -273,7 +268,7 @@ power-source = <PM8994_GPIO_S4>; }; - camera-snapshot-n { + camera-snapshot-n-pins { pins = "gpio4"; function = PMIC_GPIO_FUNC_NORMAL; drive-push-pull; @@ -283,7 +278,7 @@ power-source = <PM8994_GPIO_S4>; }; - camera-focus-n { + camera-focus-n-pins { pins = "gpio5"; function = PMIC_GPIO_FUNC_NORMAL; drive-push-pull; @@ -293,7 +288,7 @@ power-source = <PM8994_GPIO_S4>; }; - pm8994-gpio6-nc { + pm8994-gpio6-nc-pins { pins = "gpio6"; function = PMIC_GPIO_FUNC_NORMAL; drive-push-pull; @@ -301,7 +296,7 @@ power-source = <PM8994_GPIO_VPH>; }; - nfc-download { + nfc-download-pins { pins = "gpio7"; function = PMIC_GPIO_FUNC_NORMAL; output-low; @@ -311,7 +306,7 @@ power-source = <PM8994_GPIO_S4>; }; - pm8994-gpio8-nc { + pm8994-gpio8-nc-pins { pins = "gpio8"; function = PMIC_GPIO_FUNC_NORMAL; output-low; @@ -321,7 +316,7 @@ power-source = <PM8994_GPIO_VPH>; }; - pm8994-gpio9-nc { + pm8994-gpio9-nc-pins { pins = "gpio9"; function = PMIC_GPIO_FUNC_NORMAL; output-high; @@ -331,7 +326,7 @@ power-source = <PM8994_GPIO_VPH>; }; - nfc-clock { + nfc-clock-pins { pins = "gpio10"; function = PMIC_GPIO_FUNC_NORMAL; input-enable; @@ -341,7 +336,7 @@ power-source = <PM8994_GPIO_S4>; }; - pm8994-gpio11-nc { + pm8994-gpio11-nc-pins { pins = "gpio11"; function = PMIC_GPIO_FUNC_NORMAL; drive-push-pull; @@ -349,7 +344,7 @@ power-source = <PM8994_GPIO_VPH>; }; - pm8994-gpio12-nc { + pm8994-gpio12-nc-pins { pins = "gpio12"; function = PMIC_GPIO_FUNC_NORMAL; drive-push-pull; @@ -357,7 +352,7 @@ power-source = <PM8994_GPIO_VPH>; }; - ear-enable { + ear-enable-pins { pins = "gpio13"; function = PMIC_GPIO_FUNC_NORMAL; output-high; @@ -367,7 +362,7 @@ power-source = <PM8994_GPIO_S4>; }; - pm8994-gpio14-nc { + pm8994-gpio14-nc-pins { pins = "gpio14"; function = PMIC_GPIO_FUNC_NORMAL; drive-push-pull; @@ -377,7 +372,7 @@ power-source = <PM8994_GPIO_VPH>; }; - pm-divclk1-gpio { + pm-divclk1-gpio-pins { pins = "gpio15"; function = "func1"; output-high; @@ -387,13 +382,13 @@ power-source = <PM8994_GPIO_VPH>; }; - pmi-clk-gpio { + pmi-clk-gpio-pins { pins = "gpio16"; function = PMIC_GPIO_FUNC_NORMAL; drive-push-pull; }; - pm8994-gpio17-nc { + pm8994-gpio17-nc-pins { pins = "gpio17"; function = PMIC_GPIO_FUNC_NORMAL; drive-push-pull; @@ -401,7 +396,7 @@ power-source = <PM8994_GPIO_VPH>; }; - rome-sleep { + rome-sleep-pins { pins = "gpio18"; function = PMIC_GPIO_FUNC_FUNC2; output-low; @@ -411,7 +406,7 @@ power-source = <PM8994_GPIO_S4>; }; - pm8994-gpio19-nc { + pm8994-gpio19-nc-pins { pins = "gpio19"; function = PMIC_GPIO_FUNC_NORMAL; output-low; @@ -421,7 +416,7 @@ power-source = <PM8994_GPIO_VPH>; }; - pm8994-gpio22-nc { + pm8994-gpio22-nc-pins { pins = "gpio22"; function = PMIC_GPIO_FUNC_NORMAL; drive-push-pull; @@ -446,34 +441,34 @@ "RF_ID"; pm8994_mpps_defaults: pm8994-mpps-default-state { - lcd-id_adc-mpp { + lcd-id_adc-mpp-pins { pins = "mpp2"; function = "analog"; input-enable; qcom,amux-route = <PMIC_MPP_AMUX_ROUTE_CH6>; }; - pm-mpp4-nc { + pm-mpp4-nc-pins { pins = "mpp4"; function = "digital"; bias-high-impedance; power-source = <PM8994_GPIO_VPH>; }; - flash-therm-mpp { + flash-therm-mpp-pins { pins = "mpp5"; function = "analog"; input-enable; qcom,amux-route = <PMIC_MPP_AMUX_ROUTE_CH5>; }; - mpp6-nc { + mpp6-nc-pins { pins = "mpp6"; function = "digital"; bias-high-impedance; }; - rf-id-mpp { + rf-id-mpp-pins { pins = "mpp8"; function = "analog"; input-enable; @@ -504,7 +499,7 @@ "NC"; pmi8994_gpios_defaults: pmi8994-gpios-default-state { - vib-ldo-en-gpio { + vib-ldo-en-gpio-pins { pins = "gpio1"; function = PMIC_GPIO_FUNC_NORMAL; drive-push-pull; @@ -513,7 +508,7 @@ power-source = <PM8994_GPIO_S4>; }; - pmi-gpio2-nc { + pmi-gpio2-nc-pins { pins = "gpio2"; function = PMIC_GPIO_FUNC_NORMAL; drive-push-pull; @@ -523,7 +518,7 @@ power-source = <PM8994_GPIO_VPH>; }; - pmi-gpio3-nc { + pmi-gpio3-nc-pins { pins = "gpio3"; function = PMIC_GPIO_FUNC_NORMAL; drive-push-pull; @@ -533,7 +528,7 @@ power-source = <PM8994_GPIO_VPH>; }; - pmi-gpio4-nc { + pmi-gpio4-nc-pins { pins = "gpio4"; function = PMIC_GPIO_FUNC_NORMAL; drive-push-pull; @@ -542,7 +537,7 @@ power-source = <PM8994_GPIO_S4>; }; - pmi-gpio5-nc { + pmi-gpio5-nc-pins { pins = "gpio5"; function = PMIC_GPIO_FUNC_NORMAL; drive-push-pull; @@ -551,7 +546,7 @@ power-source = <PM8994_GPIO_S4>; }; - pmi-gpio6-nc { + pmi-gpio6-nc-pins { pins = "gpio6"; function = PMIC_GPIO_FUNC_NORMAL; drive-push-pull; @@ -560,7 +555,7 @@ power-source = <PM8994_GPIO_S4>; }; - pmi-gpio7-nc { + pmi-gpio7-nc-pins { pins = "gpio7"; function = PMIC_GPIO_FUNC_NORMAL; drive-push-pull; @@ -569,7 +564,7 @@ power-source = <PM8994_GPIO_S4>; }; - pmi-gpio8-nc { + pmi-gpio8-nc-pins { pins = "gpio8"; function = PMIC_GPIO_FUNC_NORMAL; drive-push-pull; @@ -578,13 +573,13 @@ power-source = <PM8994_GPIO_S4>; }; - usb-switch-sel { + usb-switch-sel-pins { pins = "gpio9"; function = PMIC_GPIO_FUNC_NORMAL; drive-push-pull; }; - pmi-gpio10-nc { + pmi-gpio10-nc-pins { pins = "gpio10"; function = PMIC_GPIO_FUNC_NORMAL; output-low; diff --git a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi index a7090befc16f..627649979891 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi @@ -38,10 +38,10 @@ }; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; - vol_up { + key-vol-up { label = "Volume Up"; gpios = <&pm8994_gpios 2 GPIO_ACTIVE_LOW>; linux,code = <KEY_VOLUMEUP>; @@ -49,7 +49,7 @@ debounce-interval = <15>; }; - dome { + key-dome { label = "Home"; gpios = <&tlmm 34 GPIO_ACTIVE_LOW>; linux,code = <KEY_HOME>; @@ -608,7 +608,7 @@ }; &pm8994_gpios { - wlan_en_default: wlan-en-default { + wlan_en_default: wlan-en-state { pins = "gpio8"; function = PMIC_GPIO_FUNC_NORMAL; output-low; @@ -617,7 +617,7 @@ bias-disable; }; - rome_enable_default: rome-enable-default { + rome_enable_default: rome-enable-state { pins = "gpio9"; function = PMIC_GPIO_FUNC_NORMAL; output-high; @@ -625,7 +625,7 @@ power-source = <PM8994_GPIO_VPH>; }; - divclk1_default: divclk1_default { + divclk1_default: divclk1-state { pins = "gpio15"; function = PMIC_GPIO_FUNC_FUNC1; bias-disable; @@ -633,7 +633,7 @@ qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>; }; - divclk4_pin_a: divclk4 { + divclk4_pin_a: divclk4-state { pins = "gpio18"; function = PMIC_GPIO_FUNC_FUNC2; bias-disable; diff --git a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dts b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dts index 22978d06f85b..25f30ec277c1 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dts +++ b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dts @@ -156,7 +156,7 @@ &sound { compatible = "qcom,apq8096-sndcard"; model = "gemini"; - audio-routing = "RX_BIAS", "MCLK", + audio-routing = "RX_BIAS", "MCLK", "MM_DL1", "MultiMedia1 Playback", "MM_DL2", "MultiMedia2 Playback", "MultiMedia3 Capture", "MM_UL3"; @@ -257,7 +257,7 @@ "UIM_BATT_ALARM", /* GPIO_21 */ "NC"; /* GPIO_22 */ - divclk2_pin_a: divclk2 { + divclk2_pin_a: divclk2-state { pins = "gpio16"; function = PMIC_GPIO_FUNC_FUNC2; bias-disable; diff --git a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-natrium.dts b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-natrium.dts new file mode 100644 index 000000000000..ff4673ee9e81 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-natrium.dts @@ -0,0 +1,414 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022, Alec Su <ae40515@yahoo.com.tw> + */ + +/dts-v1/; + +#include "msm8996-xiaomi-common.dtsi" +#include "pmi8996.dtsi" +#include <dt-bindings/sound/qcom,q6afe.h> +#include <dt-bindings/sound/qcom,q6asm.h> + +/ { + model = "Xiaomi Mi 5s Plus"; + compatible = "xiaomi,natrium", "qcom,msm8996"; + chassis-type = "handset"; + qcom,msm-id = <305 0x10000>; + qcom,board-id = <47 0>; +}; + +&adsp_pil { + firmware-name = "qcom/msm8996/natrium/adsp.mbn"; +}; + +&blsp2_i2c6 { + touchscreen@20 { + compatible = "syna,rmi4-i2c"; + reg = <0x20>; + interrupt-parent = <&tlmm>; + interrupts = <125 IRQ_TYPE_LEVEL_LOW>; + vdd-supply = <&vdd_3v2_tp>; + syna,reset-delay-ms = <200>; + syna,startup-delay-ms = <5>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&touchscreen_default>; + pinctrl-1 = <&touchscreen_sleep>; + }; +}; + +&dsi0 { + status = "okay"; + + vdda-supply = <&vreg_l2a_1p25>; + vcca-supply = <&vreg_l28a_0p925>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&mdss_dsi_default &mdss_te_default>; + pinctrl-1 = <&mdss_dsi_sleep &mdss_te_sleep>; + + panel: panel@0 { + compatible = "jdi,fhd-r63452"; + reg = <0>; + reset-gpios = <&tlmm 8 GPIO_ACTIVE_LOW>; + backlight = <&pmi8994_wled>; + + port { + panel_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + }; +}; + +&dsi0_out { + remote-endpoint = <&panel_in>; +}; + +&gpu { + zap-shader { + firmware-name = "qcom/msm8996/natrium/a530_zap.mbn"; + }; +}; + +&mss_pil { + firmware-name = "qcom/msm8996/natrium/mba.mbn", + "qcom/msm8996/natrium/modem.mbn"; +}; + +&pmi8994_wled { + status = "okay"; + + qcom,enabled-strings = <0 1>; + qcom,switching-freq = <600>; +}; + +&q6asmdai { + dai@0 { + reg = <0>; + }; + + dai@1 { + reg = <1>; + }; + + dai@2 { + reg = <2>; + }; +}; + +&slpi_pil { + firmware-name = "qcom/msm8996/natrium/slpi.mbn"; +}; + +&sound { + compatible = "qcom,apq8096-sndcard"; + model = "natrium"; + audio-routing = "RX_BIAS", "MCLK"; + + mm1-dai-link { + link-name = "MultiMedia1"; + cpu { + sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA1>; + }; + }; + + mm2-dai-link { + link-name = "MultiMedia2"; + cpu { + sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA2>; + }; + }; + + mm3-dai-link { + link-name = "MultiMedia3"; + cpu { + sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA3>; + }; + }; + + slim-dai-link { + link-name = "SLIM Playback"; + cpu { + sound-dai = <&q6afedai SLIMBUS_6_RX>; + }; + + platform { + sound-dai = <&q6routing>; + }; + + codec { + sound-dai = <&wcd9335 6>; + }; + }; + + slimcap-dai-link { + link-name = "SLIM Capture"; + cpu { + sound-dai = <&q6afedai SLIMBUS_0_TX>; + }; + + platform { + sound-dai = <&q6routing>; + }; + + codec { + sound-dai = <&wcd9335 1>; + }; + }; +}; + +&venus { + firmware-name = "qcom/msm8996/natrium/venus.mbn"; +}; + +&rpm_requests { + pm8994-regulators { + vreg_l3a_0p875: l3 { + regulator-name = "vreg_l3a_0p875"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1300000>; + }; + vreg_l11a_1p1: l11 { + regulator-name = "vreg_l11a_1p1"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + }; + vreg_l17a_2p8: l17 { + regulator-name = "vreg_l17a_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + vreg_l18a_2p8: l18 { + regulator-name = "vreg_l18a_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + vreg_l29a_2p8: l29 { + regulator-name = "vreg_l29a_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + }; +}; + +&pm8994_gpios { + gpio-line-names = + "NC", /* GPIO_1 */ + "VOL_UP_N", /* GPIO_2 */ + "SPKR_ID", /* GPIO_3 */ + "PWM_HAPTICS", /* GPIO_4 */ + "INFARED_DRV", /* GPIO_5 */ + "NC", /* GPIO_6 */ + "KEYPAD_LED_EN_A", /* GPIO_7 */ + "WL_EN", /* GPIO_8 */ + "3P3_ENABLE", /* GPIO_9 */ + "NC", /* GPIO_10 */ + "NC", /* GPIO_11 */ + "NC", /* GPIO_12 */ + "NC", /* GPIO_13 */ + "NC", /* GPIO_14 */ + "DIVCLK1_CDC", /* GPIO_15 */ + "DIVCLK2_HAPTICS", /* GPIO_16 */ + "NC", /* GPIO_17 */ + "32KHz_CLK_IN", /* GPIO_18 */ + "BT_EN", /* GPIO_19 */ + "PMIC_SLB", /* GPIO_20 */ + "UIM_BATT_ALARM", /* GPIO_21 */ + "NC"; /* GPIO_22 */ +}; + +&pm8994_mpps { + gpio-line-names = + "NC", /* MPP_1 */ + "CCI_TIMER1", /* MPP_2 */ + "PMIC_SLB", /* MPP_3 */ + "EXT_FET_WLED_PWR_EN_N",/* MPP_4 */ + "NC", /* MPP_5 */ + "NC", /* MPP_6 */ + "NC", /* MPP_7 */ + "NC"; /* MPP_8 */ +}; + +&pmi8994_gpios { + gpio-line-names = + "NC", /* GPIO_1 */ + "SPKR_PA_EN", /* GPIO_2 */ + "NC", /* GPIO_3 */ + "NC", /* GPIO_4 */ + "NC", /* GPIO_5 */ + "NC", /* GPIO_6 */ + "NC", /* GPIO_7 */ + "NC", /* GPIO_8 */ + "NC", /* GPIO_9 */ + "NC"; /* GPIO_10 */ +}; + +&tlmm { + gpio-line-names = + "ESE_SPI_MOSI", /* GPIO_0 */ + "ESE_SPI_MISO", /* GPIO_1 */ + "NC", /* GPIO_2 */ + "ESE_SPI_CLK", /* GPIO_3 */ + "MSM_UART_TX", /* GPIO_4 */ + "MSM_UART_RX", /* GPIO_5 */ + "NFC_I2C_SDA", /* GPIO_6 */ + "NFC_I2C_SCL", /* GPIO_7 */ + "LCD0_RESET_N", /* GPIO_8 */ + "NFC_IRQ", /* GPIO_9 */ + "LCD_TE", /* GPIO_10 */ + "LCD_ID_DET1", /* GPIO_11 */ + "NFC_DISABLE", /* GPIO_12 */ + "CAM_MCLK0", /* GPIO_13 */ + "CAM_MCLK1", /* GPIO_14 */ + "CAM_MCLK2", /* GPIO_15 */ + "ESE_PWR_REQ", /* GPIO_16 */ + "CCI_I2C_SDA0", /* GPIO_17 */ + "CCI_I2C_SCL0", /* GPIO_18 */ + "CCI_I2C_SDA1", /* GPIO_19 */ + "CCI_I2C_SCL1", /* GPIO_20 */ + "NFC_DWL_REQ", /* GPIO_21 */ + "CCI_TIMER1", /* GPIO_22 */ + "WEBCAM1_RESET_N", /* GPIO_23 */ + "ESE_IRQ", /* GPIO_24 */ + "NC", /* GPIO_25 */ + "WEBCAM1_STANDBY", /* GPIO_26 */ + "NC", /* GPIO_27 */ + "NC", /* GPIO_28 */ + "NC", /* GPIO_29 */ + "CAM_VDD_1P2_EN_2", /* GPIO_30 */ + "CAM_RESET_0", /* GPIO_31 */ + "CAM_RESET_1", /* GPIO_32 */ + "NC", /* GPIO_33 */ + "NC", /* GPIO_34 */ + "PCI_E0_RST_N", /* GPIO_35 */ + "PCI_E0_CLKREQ_N", /* GPIO_36 */ + "PCI_E0_WAKE", /* GPIO_37 */ + "CHARGER_INT", /* GPIO_38 */ + "CHARGER_RESET", /* GPIO_39 */ + "NC", /* GPIO_40 */ + "QCA_UART_TXD", /* GPIO_41 */ + "QCA_UART_RXD", /* GPIO_42 */ + "QCA_UART_CTS", /* GPIO_43 */ + "QCA_UART_RTS", /* GPIO_44 */ + "MAWC_UART_TX", /* GPIO_45 */ + "MAWC_UART_RX", /* GPIO_46 */ + "NC", /* GPIO_47 */ + "NC", /* GPIO_48 */ + "NC", /* GPIO_49 */ + "FP_SPI_RST", /* GPIO_50 */ + "TYPEC_I2C_SDA", /* GPIO_51 */ + "TYPEC_I2C_SCL", /* GPIO_52 */ + "CODEC_INT2_N", /* GPIO_53 */ + "CODEC_INT1_N", /* GPIO_54 */ + "APPS_I2C7_SDA", /* GPIO_55 */ + "APPS_I2C7_SCL", /* GPIO_56 */ + "FORCE_USB_BOOT", /* GPIO_57 */ + "NC", /* GPIO_58 */ + "NC", /* GPIO_59 */ + "NC", /* GPIO_60 */ + "NC", /* GPIO_61 */ + "ESE_RSTN", /* GPIO_62 */ + "TYPEC_INT", /* GPIO_63 */ + "CODEC_RESET_N", /* GPIO_64 */ + "PCM_CLK", /* GPIO_65 */ + "PCM_SYNC", /* GPIO_66 */ + "PCM_DIN", /* GPIO_67 */ + "PCM_DOUT", /* GPIO_68 */ + "CDC_44K1_CLK", /* GPIO_69 */ + "SLIMBUS_CLK", /* GPIO_70 */ + "SLIMBUS_DATA0", /* GPIO_71 */ + "SLIMBUS_DATA1", /* GPIO_72 */ + "LDO_5V_IN_EN", /* GPIO_73 */ + "TYPEC_EN_N", /* GPIO_74 */ + "NC", /* GPIO_75 */ + "NC", /* GPIO_76 */ + "NC", /* GPIO_77 */ + "NC", /* GPIO_78 */ + "NC", /* GPIO_79 */ + "SENSOR_RESET_N", /* GPIO_80 */ + "FP_SPI_MOSI", /* GPIO_81 */ + "FP_SPI_MISO", /* GPIO_82 */ + "FP_SPI_CS_N", /* GPIO_83 */ + "FP_SPI_CLK", /* GPIO_84 */ + "NC", /* GPIO_85 */ + "CAM_VDD_1P2_EN", /* GPIO_86 */ + "MSM_TS_I2C_SDA", /* GPIO_87 */ + "MSM_TS_I2C_SCL", /* GPIO_88 */ + "TS_RESOUT_N", /* GPIO_89 */ + "ESE_SPI_CS_N", /* GPIO_90 */ + "NC", /* GPIO_91 */ + "CAM2_AVDD_EN", /* GPIO_92 */ + "CAM2_VCM_EN", /* GPIO_93 */ + "NC", /* GPIO_94 */ + "NC", /* GPIO_95 */ + "NC", /* GPIO_96 */ + "GRFC_0", /* GPIO_97 */ + "GRFC_1", /* GPIO_98 */ + "NC", /* GPIO_99 */ + "GRFC_3", /* GPIO_100 */ + "GRFC_4", /* GPIO_101 */ + "GRFC_5", /* GPIO_102 */ + "NC", /* GPIO_103 */ + "GRFC_7", /* GPIO_104 */ + "UIM2_DATA", /* GPIO_105 */ + "UIM2_CLK", /* GPIO_106 */ + "UIM2_RESET", /* GPIO_107 */ + "UIM2_PRESENT", /* GPIO_108 */ + "UIM1_DATA", /* GPIO_109 */ + "UIM1_CLK", /* GPIO_110 */ + "UIM1_RESET", /* GPIO_111 */ + "UIM1_PRESENT", /* GPIO_112 */ + "UIM_BATT_ALARM", /* GPIO_113 */ + "GRFC_8", /* GPIO_114 */ + "GRFC_9", /* GPIO_115 */ + "TX_GTR_THRES", /* GPIO_116 */ + "ACCEL_INT", /* GPIO_117 */ + "GYRO_INT", /* GPIO_118 */ + "COMPASS_INT", /* GPIO_119 */ + "PROXIMITY_INT_N", /* GPIO_120 */ + "FP_IRQ", /* GPIO_121 */ + "P_SENSE", /* GPIO_122 */ + "HALL_INTR2", /* GPIO_123 */ + "HALL_INTR1", /* GPIO_124 */ + "TS_INT_N", /* GPIO_125 */ + "NC", /* GPIO_126 */ + "GRFC_11", /* GPIO_127 */ + "NC", /* GPIO_128 */ + "EXT_GPS_LNA_EN", /* GPIO_129 */ + "NC", /* GPIO_130 */ + "LCD_ID_DET2", /* GPIO_131 */ + "LCD_TE2", /* GPIO_132 */ + "GRFC_14", /* GPIO_133 */ + "GSM_TX2_PHASE_D", /* GPIO_134 */ + "NC", /* GPIO_135 */ + "GRFC_15", /* GPIO_136 */ + "RFFE3_DATA", /* GPIO_137 */ + "RFFE3_CLK", /* GPIO_138 */ + "NC", /* GPIO_139 */ + "NC", /* GPIO_140 */ + "RFFE5_DATA", /* GPIO_141 */ + "RFFE5_CLK", /* GPIO_142 */ + "NC", /* GPIO_143 */ + "COEX_UART_TX", /* GPIO_144 */ + "COEX_UART_RX", /* GPIO_145 */ + "RFFE2_DATA", /* GPIO_146 */ + "RFFE2_CLK", /* GPIO_147 */ + "RFFE1_DATA", /* GPIO_148 */ + "RFFE1_CLK"; /* GPIO_149 */ + + touchscreen_default: touchscreen-default { + pins = "gpio89", "gpio125"; + function = "gpio"; + drive-strength = <10>; + bias-pull-up; + }; + + touchscreen_sleep: touchscreen-sleep { + pins = "gpio89", "gpio125"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-scorpio.dts b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-scorpio.dts index 1e2dd6763ad1..30a9e4bed4af 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-scorpio.dts +++ b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-scorpio.dts @@ -137,7 +137,7 @@ &sound { compatible = "qcom,apq8096-sndcard"; model = "scorpio"; - audio-routing = "RX_BIAS", "MCLK"; + audio-routing = "RX_BIAS", "MCLK"; mm1-dai-link { link-name = "MultiMedia1"; diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 9932186f7ceb..742eac4ce9b3 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -6,6 +6,7 @@ #include <dt-bindings/clock/qcom,gcc-msm8996.h> #include <dt-bindings/clock/qcom,mmcc-msm8996.h> #include <dt-bindings/clock/qcom,rpmcc.h> +#include <dt-bindings/interconnect/qcom,msm8996.h> #include <dt-bindings/power/qcom-rpmpd.h> #include <dt-bindings/soc/qcom,apr.h> #include <dt-bindings/thermal/thermal.h> @@ -357,7 +358,7 @@ firmware { scm { - compatible = "qcom,scm-msm8996"; + compatible = "qcom,scm-msm8996", "qcom,scm"; qcom,dload-mode = <&tcsr 0x13000>; }; }; @@ -463,6 +464,8 @@ rpmcc: qcom,rpmcc { compatible = "qcom,rpmcc-msm8996", "qcom,rpmcc"; #clock-cells = <1>; + clocks = <&xo_board>; + clock-names = "xo"; }; rpmpd: power-controller { @@ -585,12 +588,12 @@ ranges = <0 0 0 0xffffffff>; compatible = "simple-bus"; - pcie_phy: phy@34000 { + pcie_phy: phy-wrapper@34000 { compatible = "qcom,msm8996-qmp-pcie-phy"; reg = <0x00034000 0x488>; #address-cells = <1>; #size-cells = <1>; - ranges; + ranges = <0x0 0x00034000 0x4000>; clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, <&gcc GCC_PCIE_PHY_CFG_AHB_CLK>, @@ -601,46 +604,55 @@ <&gcc GCC_PCIE_PHY_COM_BCR>, <&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>; reset-names = "phy", "common", "cfg"; + status = "disabled"; - pciephy_0: phy@35000 { - reg = <0x00035000 0x130>, - <0x00035200 0x200>, - <0x00035400 0x1dc>; - #phy-cells = <0>; + pciephy_0: phy@1000 { + reg = <0x1000 0x130>, + <0x1200 0x200>, + <0x1400 0x1dc>; - #clock-cells = <1>; - clock-output-names = "pcie_0_pipe_clk_src"; clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; clock-names = "pipe0"; resets = <&gcc GCC_PCIE_0_PHY_BCR>; reset-names = "lane0"; - }; - pciephy_1: phy@36000 { - reg = <0x00036000 0x130>, - <0x00036200 0x200>, - <0x00036400 0x1dc>; + #clock-cells = <0>; + clock-output-names = "pcie_0_pipe_clk_src"; + #phy-cells = <0>; + }; + + pciephy_1: phy@2000 { + reg = <0x2000 0x130>, + <0x2200 0x200>, + <0x2400 0x1dc>; - clock-output-names = "pcie_1_pipe_clk_src"; clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; clock-names = "pipe1"; resets = <&gcc GCC_PCIE_1_PHY_BCR>; reset-names = "lane1"; - }; - pciephy_2: phy@37000 { - reg = <0x00037000 0x130>, - <0x00037200 0x200>, - <0x00037400 0x1dc>; + #clock-cells = <0>; + clock-output-names = "pcie_1_pipe_clk_src"; + #phy-cells = <0>; + }; + + pciephy_2: phy@3000 { + reg = <0x3000 0x130>, + <0x3200 0x200>, + <0x3400 0x1dc>; - clock-output-names = "pcie_2_pipe_clk_src"; clocks = <&gcc GCC_PCIE_2_PIPE_CLK>; clock-names = "pipe2"; resets = <&gcc GCC_PCIE_2_PHY_BCR>; reset-names = "lane2"; + + #clock-cells = <0>; + clock-output-names = "pcie_2_pipe_clk_src"; + + #phy-cells = <0>; }; }; @@ -650,7 +662,7 @@ }; qfprom@74000 { - compatible = "qcom,qfprom"; + compatible = "qcom,msm8996-qfprom", "qcom,qfprom"; reg = <0x00074000 0x8ff>; #address-cells = <1>; #size-cells = <1>; @@ -687,8 +699,31 @@ clocks = <&rpmcc RPM_SMD_BB_CLK1>, <&rpmcc RPM_SMD_LN_BB_CLK>, - <&sleep_clk>; - clock-names = "cxo", "cxo2", "sleep_clk"; + <&sleep_clk>, + <&pciephy_0>, + <&pciephy_1>, + <&pciephy_2>, + <&ssusb_phy_0>, + <0>, <0>, <0>; + clock-names = "cxo", + "cxo2", + "sleep_clk", + "pcie_0_pipe_clk_src", + "pcie_1_pipe_clk_src", + "pcie_2_pipe_clk_src", + "usb3_phy_pipe_clk_src", + "ufs_rx_symbol_0_clk_src", + "ufs_rx_symbol_1_clk_src", + "ufs_tx_symbol_0_clk_src"; + }; + + bimc: interconnect@408000 { + compatible = "qcom,msm8996-bimc"; + reg = <0x00408000 0x5a000>; + #interconnect-cells = <1>; + clock-names = "bus", "bus_a"; + clocks = <&rpmcc RPM_SMD_BIMC_CLK>, + <&rpmcc RPM_SMD_BIMC_A_CLK>; }; tsens0: thermal-sensor@4a9000 { @@ -735,6 +770,74 @@ dma-names = "rx", "tx"; }; + cnoc: interconnect@500000 { + compatible = "qcom,msm8996-cnoc"; + reg = <0x00500000 0x1000>; + #interconnect-cells = <1>; + clock-names = "bus", "bus_a"; + clocks = <&rpmcc RPM_SMD_CNOC_CLK>, + <&rpmcc RPM_SMD_CNOC_A_CLK>; + }; + + snoc: interconnect@524000 { + compatible = "qcom,msm8996-snoc"; + reg = <0x00524000 0x1c000>; + #interconnect-cells = <1>; + clock-names = "bus", "bus_a"; + clocks = <&rpmcc RPM_SMD_SNOC_CLK>, + <&rpmcc RPM_SMD_SNOC_A_CLK>; + }; + + a0noc: interconnect@543000 { + compatible = "qcom,msm8996-a0noc"; + reg = <0x00543000 0x6000>; + #interconnect-cells = <1>; + clock-names = "aggre0_snoc_axi", + "aggre0_cnoc_ahb", + "aggre0_noc_mpu_cfg"; + clocks = <&gcc GCC_AGGRE0_SNOC_AXI_CLK>, + <&gcc GCC_AGGRE0_CNOC_AHB_CLK>, + <&gcc GCC_AGGRE0_NOC_MPU_CFG_AHB_CLK>; + power-domains = <&gcc AGGRE0_NOC_GDSC>; + }; + + a1noc: interconnect@562000 { + compatible = "qcom,msm8996-a1noc"; + reg = <0x00562000 0x5000>; + #interconnect-cells = <1>; + clock-names = "bus", "bus_a"; + clocks = <&rpmcc RPM_SMD_AGGR1_NOC_CLK>, + <&rpmcc RPM_SMD_AGGR1_NOC_A_CLK>; + }; + + a2noc: interconnect@583000 { + compatible = "qcom,msm8996-a2noc"; + reg = <0x00583000 0x7000>; + #interconnect-cells = <1>; + clock-names = "bus", "bus_a"; + clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>, + <&rpmcc RPM_SMD_AGGR2_NOC_A_CLK>; + }; + + mnoc: interconnect@5a4000 { + compatible = "qcom,msm8996-mnoc"; + reg = <0x005a4000 0x1c000>; + #interconnect-cells = <1>; + clock-names = "bus", "bus_a", "iface"; + clocks = <&rpmcc RPM_SMD_MMAXI_CLK>, + <&rpmcc RPM_SMD_MMAXI_A_CLK>, + <&mmcc AHB_CLK_SRC>; + }; + + pnoc: interconnect@5c0000 { + compatible = "qcom,msm8996-pnoc"; + reg = <0x005c0000 0x3000>; + #interconnect-cells = <1>; + clock-names = "bus", "bus_a"; + clocks = <&rpmcc RPM_SMD_PCNOC_CLK>, + <&rpmcc RPM_SMD_PCNOC_A_CLK>; + }; + tcsr_mutex_regs: syscon@740000 { compatible = "syscon"; reg = <0x00740000 0x40000>; @@ -751,6 +854,22 @@ #reset-cells = <1>; #power-domain-cells = <1>; reg = <0x008c0000 0x40000>; + clocks = <&xo_board>, + <&gcc GCC_MMSS_NOC_CFG_AHB_CLK>, + <&gcc GPLL0>, + <&dsi0_phy 1>, + <&dsi0_phy 0>, + <0>, + <0>, + <0>; + clock-names = "xo", + "gcc_mmss_noc_cfg_ahb_clk", + "gpll0", + "dsi0pll", + "dsi0pllbyte", + "dsi1pll", + "dsi1pllbyte", + "hdmipll"; assigned-clocks = <&mmcc MMPLL9_PLL>, <&mmcc MMPLL1_PLL>, <&mmcc MMPLL3_PLL>, @@ -779,8 +898,9 @@ interrupt-controller; #interrupt-cells = <1>; - clocks = <&mmcc MDSS_AHB_CLK>; - clock-names = "iface"; + clocks = <&mmcc MDSS_AHB_CLK>, + <&mmcc MDSS_MDP_CLK>; + clock-names = "iface", "core"; #address-cells = <1>; #size-cells = <1>; @@ -814,6 +934,11 @@ assigned-clock-rates = <300000000>, <19200000>; + interconnects = <&mnoc MASTER_MDP_PORT0 &bimc SLAVE_EBI_CH0>, + <&mnoc MASTER_MDP_PORT1 &bimc SLAVE_EBI_CH0>, + <&mnoc MASTER_ROTATOR &bimc SLAVE_EBI_CH0>; + interconnect-names = "mdp0-mem", "mdp1-mem", "rotator-mem"; + ports { #address-cells = <1>; #size-cells = <0>; @@ -831,6 +956,13 @@ remote-endpoint = <&dsi0_in>; }; }; + + port@2 { + reg = <2>; + mdp5_intf2_out: endpoint { + remote-endpoint = <&dsi1_in>; + }; + }; }; }; @@ -856,6 +988,8 @@ "core_mmss", "pixel", "core"; + assigned-clocks = <&mmcc BYTE0_CLK_SRC>, <&mmcc PCLK0_CLK_SRC>; + assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>; phys = <&dsi0_phy>; phy-names = "dsi"; @@ -900,6 +1034,74 @@ status = "disabled"; }; + dsi1: dsi@996000 { + compatible = "qcom,mdss-dsi-ctrl"; + reg = <0x00996000 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4>; + + clocks = <&mmcc MDSS_MDP_CLK>, + <&mmcc MDSS_BYTE1_CLK>, + <&mmcc MDSS_AHB_CLK>, + <&mmcc MDSS_AXI_CLK>, + <&mmcc MMSS_MISC_AHB_CLK>, + <&mmcc MDSS_PCLK1_CLK>, + <&mmcc MDSS_ESC1_CLK>; + clock-names = "mdp_core", + "byte", + "iface", + "bus", + "core_mmss", + "pixel", + "core"; + assigned-clocks = <&mmcc BYTE1_CLK_SRC>, <&mmcc PCLK1_CLK_SRC>; + assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>; + + phys = <&dsi1_phy>; + phy-names = "dsi"; + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi1_in: endpoint { + remote-endpoint = <&mdp5_intf2_out>; + }; + }; + + port@1 { + reg = <1>; + dsi1_out: endpoint { + }; + }; + }; + }; + + dsi1_phy: dsi-phy@996400 { + compatible = "qcom,dsi-phy-14nm"; + reg = <0x00996400 0x100>, + <0x00996500 0x300>, + <0x00996800 0x188>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_BB_CLK1>; + clock-names = "iface", "ref"; + status = "disabled"; + }; + hdmi: hdmi-tx@9a0000 { compatible = "qcom,hdmi-tx-8996"; reg = <0x009a0000 0x50c>, @@ -925,7 +1127,6 @@ "extp"; phys = <&hdmi_phy>; - phy-names = "hdmi_phy"; #sound-dai-cells = <1>; status = "disabled"; @@ -988,6 +1189,9 @@ "mem", "mem_iface"; + interconnects = <&bimc MASTER_GRAPHICS_3D &bimc SLAVE_EBI_CH0>; + interconnect-names = "gfx-mem"; + power-domains = <&mmcc GPU_GX_GDSC>; iommus = <&adreno_smmu 0>; @@ -1001,7 +1205,7 @@ #cooling-cells = <2>; gpu_opp_table: opp-table { - compatible ="operating-points-v2"; + compatible = "operating-points-v2"; /* * 624Mhz and 560Mhz are only available on speed @@ -1623,7 +1827,7 @@ <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, <&gcc GCC_PCIE_0_SLV_AXI_CLK>; - clock-names = "pipe", + clock-names = "pipe", "aux", "cfg", "bus_master", @@ -1637,7 +1841,7 @@ bus-range = <0x00 0xff>; num-lanes = <1>; - status = "disabled"; + status = "disabled"; reg = <0x00608000 0x2000>, <0x0d000000 0xf1d>, @@ -1677,7 +1881,7 @@ <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, <&gcc GCC_PCIE_1_SLV_AXI_CLK>; - clock-names = "pipe", + clock-names = "pipe", "aux", "cfg", "bus_master", @@ -1727,7 +1931,7 @@ <&gcc GCC_PCIE_2_MSTR_AXI_CLK>, <&gcc GCC_PCIE_2_SLV_AXI_CLK>; - clock-names = "pipe", + clock-names = "pipe", "aux", "cfg", "bus_master", @@ -2013,6 +2217,9 @@ <&mmcc VIDEO_AXI_CLK>, <&mmcc VIDEO_MAXI_CLK>; clock-names = "core", "iface", "bus", "mbus"; + interconnects = <&mnoc MASTER_VIDEO_P0 &bimc SLAVE_EBI_CH0>, + <&bimc MASTER_AMPSS_M0 &mnoc SLAVE_VENUS_CFG>; + interconnect-names = "video-mem", "cpu-cfg"; iommus = <&venus_smmu 0x00>, <&venus_smmu 0x01>, <&venus_smmu 0x0a>, @@ -2732,6 +2939,10 @@ <&gcc GCC_USB30_MASTER_CLK>; assigned-clock-rates = <19200000>, <120000000>; + interconnects = <&a2noc MASTER_USB3 &bimc SLAVE_EBI_CH0>, + <&bimc MASTER_AMPSS_M0 &snoc SLAVE_USB3>; + interconnect-names = "usb-ddr", "apps-usb"; + power-domains = <&gcc USB30_GDSC>; status = "disabled"; @@ -2769,7 +2980,7 @@ <0x07410600 0x1a8>; #phy-cells = <0>; - #clock-cells = <1>; + #clock-cells = <0>; clock-output-names = "usb3_phy_pipe_clk_src"; clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>; clock-names = "pipe0"; @@ -2804,7 +3015,7 @@ status = "disabled"; }; - sdhc1: sdhci@7464900 { + sdhc1: mmc@7464900 { compatible = "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4"; reg = <0x07464900 0x11c>, <0x07464000 0x800>; reg-names = "hc_mem", "core_mem"; @@ -2817,6 +3028,7 @@ clocks = <&gcc GCC_SDCC1_AHB_CLK>, <&gcc GCC_SDCC1_APPS_CLK>, <&rpmcc RPM_SMD_BB_CLK1>; + resets = <&gcc GCC_SDCC1_BCR>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&sdc1_state_on>; @@ -2827,7 +3039,7 @@ status = "disabled"; }; - sdhc2: sdhci@74a4900 { + sdhc2: mmc@74a4900 { compatible = "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4"; reg = <0x074a4900 0x314>, <0x074a4000 0x800>; reg-names = "hc_mem", "core_mem"; @@ -2840,6 +3052,7 @@ clocks = <&gcc GCC_SDCC2_AHB_CLK>, <&gcc GCC_SDCC2_APPS_CLK>, <&rpmcc RPM_SMD_BB_CLK1>; + resets = <&gcc GCC_SDCC2_BCR>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&sdc2_state_on>; @@ -3084,7 +3297,7 @@ compatible = "qcom,bam-v1.7.0"; qcom,controlled-remotely; reg = <0x09184000 0x32000>; - num-channels = <31>; + num-channels = <31>; interrupts = <0 164 IRQ_TYPE_LEVEL_HIGH>; #dma-cells = <1>; qcom,ee = <1>; @@ -3096,7 +3309,7 @@ reg = <0x091c0000 0x2C000>; reg-names = "ctrl"; interrupts = <0 163 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&slimbam 3>, <&slimbam 4>, + dmas = <&slimbam 3>, <&slimbam 4>, <&slimbam 5>, <&slimbam 6>; dma-names = "rx", "tx", "tx2", "rx2"; #address-cells = <1>; @@ -3108,7 +3321,7 @@ tasha_ifd: tas-ifd { compatible = "slim217,1a0"; - reg = <0 0>; + reg = <0 0>; }; wcd9335: codec@1{ @@ -3116,17 +3329,17 @@ pinctrl-names = "default"; compatible = "slim217,1a0"; - reg = <1 0>; + reg = <1 0>; interrupt-parent = <&tlmm>; interrupts = <54 IRQ_TYPE_LEVEL_HIGH>, <53 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "intr1", "intr2"; + interrupt-names = "intr1", "intr2"; interrupt-controller; #interrupt-cells = <1>; reset-gpios = <&tlmm 64 0>; - slim-ifc-dev = <&tasha_ifd>; + slim-ifc-dev = <&tasha_ifd>; #sound-dai-cells = <1>; }; diff --git a/arch/arm64/boot/dts/qcom/msm8998-asus-novago-tp370ql.dts b/arch/arm64/boot/dts/qcom/msm8998-asus-novago-tp370ql.dts index e204b7050441..102f3e9a79a1 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-asus-novago-tp370ql.dts +++ b/arch/arm64/boot/dts/qcom/msm8998-asus-novago-tp370ql.dts @@ -16,20 +16,22 @@ touchpad@15 { compatible = "hid-over-i2c"; - interrupt-parent = <&tlmm>; - interrupts = <0x7b IRQ_TYPE_LEVEL_LOW>; reg = <0x15>; - hid-descr-addr = <0x0001>; - pinctrl-names = "default"; pinctrl-0 = <&touchpad>; + + interrupt-parent = <&tlmm>; + interrupts = <123 IRQ_TYPE_LEVEL_LOW>; + + hid-descr-addr = <0x0001>; }; keyboard@3a { compatible = "hid-over-i2c"; - interrupt-parent = <&tlmm>; - interrupts = <0x25 IRQ_TYPE_LEVEL_LOW>; reg = <0x3a>; + interrupt-parent = <&tlmm>; + interrupts = <37 IRQ_TYPE_LEVEL_LOW>; + hid-descr-addr = <0x0001>; }; }; @@ -37,12 +39,3 @@ &sdhc2 { cd-gpios = <&tlmm 95 GPIO_ACTIVE_HIGH>; }; - -&tlmm { - touchpad: touchpad { - config { - pins = "gpio123"; - bias-pull-up; - }; - }; -}; diff --git a/arch/arm64/boot/dts/qcom/msm8998-clamshell.dtsi b/arch/arm64/boot/dts/qcom/msm8998-clamshell.dtsi index b3b352530d76..7928b8197474 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-clamshell.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998-clamshell.dtsi @@ -8,13 +8,10 @@ */ #include "msm8998.dtsi" -#include "pm8998.dtsi" #include "pm8005.dtsi" +#include "pm8998.dtsi" / { - chosen { - }; - vph_pwr: vph-pwr-regulator { compatible = "regulator-fixed"; regulator-name = "vph_pwr"; @@ -37,6 +34,28 @@ }; }; +&blsp1_uart3_on { + rx { + /delete-property/ bias-disable; + /* + * Configure a pull-up on 45 (RX). This is needed to + * avoid garbage data when the TX pin of the Bluetooth + * module is in tri-state (module powered off or not + * driving the signal yet). + */ + bias-pull-up; + }; + + cts { + /delete-property/ bias-disable; + /* + * Configure a pull-down on 47 (CTS) to match the pull + * of the Bluetooth module. + */ + bias-pull-down; + }; +}; + /* * The laptop FW does not appear to support the retention state as it is * not advertised as enabled in ACPI, and enabling it in DT can cause boot @@ -74,6 +93,20 @@ cpu-idle-states = <&BIG_CPU_SLEEP_1>; }; +/* + * If EFIFB is used, enabling MMCC will cause important MMSS clocks to be cleaned + * up, because as far as Linux is concerned - they are unused. Disable it by default + * on clamshell devices, as it will break them, unless either simplefb is configured to + * hold a vote for these clocks, or panels are brought up properly, using drm/msm. + */ +&mmcc { + status = "disabled"; +}; + +&mmss_smmu { + status = "disabled"; +}; + &pcie0 { status = "okay"; }; @@ -82,20 +115,16 @@ status = "okay"; }; -&pm8005_lsid1 { - pm8005-regulators { - compatible = "qcom,pm8005-regulators"; +&pm8005_regulators { + vdd_s1-supply = <&vph_pwr>; - vdd_s1-supply = <&vph_pwr>; + pm8005_s1: s1 { /* VDD_GFX supply */ + regulator-min-microvolt = <524000>; + regulator-max-microvolt = <1100000>; + regulator-enable-ramp-delay = <500>; - pm8005_s1: s1 { /* VDD_GFX supply */ - regulator-min-microvolt = <524000>; - regulator-max-microvolt = <1100000>; - regulator-enable-ramp-delay = <500>; - - /* hack until we rig up the gpu consumer */ - regulator-always-on; - }; + /* hack until we rig up the gpu consumer */ + regulator-always-on; }; }; @@ -143,127 +172,156 @@ regulator-min-microvolt = <1352000>; regulator-max-microvolt = <1352000>; }; + vreg_s4a_1p8: s4 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-allow-set-load; }; + vreg_s5a_2p04: s5 { regulator-min-microvolt = <1904000>; regulator-max-microvolt = <2040000>; }; + vreg_s7a_1p025: s7 { regulator-min-microvolt = <900000>; regulator-max-microvolt = <1028000>; }; + vreg_l1a_0p875: l1 { regulator-min-microvolt = <880000>; regulator-max-microvolt = <880000>; regulator-allow-set-load; }; + vreg_l2a_1p2: l2 { regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; regulator-allow-set-load; }; + vreg_l3a_1p0: l3 { regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; }; + vreg_l5a_0p8: l5 { regulator-min-microvolt = <800000>; regulator-max-microvolt = <800000>; }; + vreg_l6a_1p8: l6 { regulator-min-microvolt = <1808000>; regulator-max-microvolt = <1808000>; }; + vreg_l7a_1p8: l7 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-allow-set-load; }; + vreg_l8a_1p2: l8 { regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; }; + vreg_l9a_1p8: l9 { regulator-min-microvolt = <1808000>; regulator-max-microvolt = <2960000>; }; + vreg_l10a_1p8: l10 { regulator-min-microvolt = <1808000>; regulator-max-microvolt = <2960000>; }; + vreg_l11a_1p0: l11 { regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; }; + vreg_l12a_1p8: l12 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; + vreg_l13a_2p95: l13 { regulator-min-microvolt = <1808000>; regulator-max-microvolt = <2960000>; }; + vreg_l14a_1p88: l14 { regulator-min-microvolt = <1880000>; regulator-max-microvolt = <1880000>; }; + vreg_l15a_1p8: l15 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; + vreg_l16a_2p7: l16 { regulator-min-microvolt = <2704000>; regulator-max-microvolt = <2704000>; }; + vreg_l17a_1p3: l17 { regulator-min-microvolt = <1304000>; regulator-max-microvolt = <1304000>; regulator-allow-set-load; }; + vreg_l18a_2p7: l18 { regulator-min-microvolt = <2704000>; regulator-max-microvolt = <2704000>; }; + vreg_l19a_3p0: l19 { regulator-min-microvolt = <3008000>; regulator-max-microvolt = <3008000>; }; + vreg_l20a_2p95: l20 { regulator-min-microvolt = <2960000>; regulator-max-microvolt = <2960000>; regulator-allow-set-load; }; + vreg_l21a_2p95: l21 { regulator-min-microvolt = <2960000>; regulator-max-microvolt = <2960000>; regulator-allow-set-load; regulator-system-load = <800000>; }; + vreg_l22a_2p85: l22 { regulator-min-microvolt = <2864000>; regulator-max-microvolt = <2864000>; }; + vreg_l23a_3p3: l23 { regulator-min-microvolt = <3312000>; regulator-max-microvolt = <3312000>; }; + vreg_l24a_3p075: l24 { regulator-min-microvolt = <3088000>; regulator-max-microvolt = <3088000>; }; + vreg_l25a_3p3: l25 { regulator-min-microvolt = <3104000>; regulator-max-microvolt = <3312000>; regulator-allow-set-load; }; + vreg_l26a_1p2: l26 { regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; }; + vreg_l28_3p0: l28 { regulator-min-microvolt = <3008000>; regulator-max-microvolt = <3008000>; @@ -278,7 +336,6 @@ regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; - }; }; @@ -286,17 +343,6 @@ status = "okay"; }; -&tlmm { - gpio-reserved-ranges = <0 4>, <81 4>; - - touchpad: touchpad { - config { - pins = "gpio123"; - bias-pull-up; /* pull up */ - }; - }; -}; - &sdhc2 { status = "okay"; @@ -304,8 +350,17 @@ vqmmc-supply = <&vreg_l13a_2p95>; pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; - pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; + pinctrl-0 = <&sdc2_on &sdc2_cd>; + pinctrl-1 = <&sdc2_off &sdc2_cd>; +}; + +&tlmm { + gpio-reserved-ranges = <0 4>, <81 4>; + + touchpad: touchpad-pin { + pins = "gpio123"; + bias-pull-up; + }; }; &ufshc { @@ -341,26 +396,3 @@ vdd-1.3-rfa-supply = <&vreg_l17a_1p3>; vdd-3.3-ch0-supply = <&vreg_l25a_3p3>; }; - -/* PINCTRL - board-specific pinctrl */ -&blsp1_uart3_on { - rx { - /delete-property/ bias-disable; - /* - * Configure a pull-up on 45 (RX). This is needed to - * avoid garbage data when the TX pin of the Bluetooth - * module is in tri-state (module powered off or not - * driving the signal yet). - */ - bias-pull-up; - }; - - cts { - /delete-property/ bias-disable; - /* - * Configure a pull-down on 47 (CTS) to match the pull - * of the Bluetooth module. - */ - bias-pull-down; - }; -}; diff --git a/arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts b/arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts index dc5b9b274df3..429ba57e20f7 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts +++ b/arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts @@ -6,11 +6,13 @@ /dts-v1/; -#include "msm8998-mtp.dtsi" - #include <dt-bindings/input/input.h> #include <dt-bindings/leds/common.h> #include <dt-bindings/pinctrl/qcom,pmic-gpio.h> +#include "msm8998.dtsi" +#include "pm8005.dtsi" +#include "pm8998.dtsi" +#include "pmi8998.dtsi" / { model = "F(x)tec Pro1 (QX1000)"; @@ -18,6 +20,11 @@ chassis-type = "handset"; qcom,board-id = <0x02000b 0x10>; + aliases { + serial0 = &blsp2_uart1; + serial1 = &blsp1_uart3; + }; + /* * Until we hook up type-c detection, we * have to stick with this. But it works. @@ -33,7 +40,7 @@ pinctrl-names = "default"; pinctrl-0 = <&hall_sensor1_default>; - hall-sensor1 { + event-hall-sensor1 { label = "Keyboard Hall Sensor"; gpios = <&tlmm 124 GPIO_ACTIVE_HIGH>; debounce-interval = <15>; @@ -49,7 +56,7 @@ pinctrl-names = "default"; pinctrl-0 = <&gpio_kb_pins_extra>; - home { + key-home { label = "Home"; gpios = <&tlmm 21 GPIO_ACTIVE_LOW>; linux,code = <KEY_HOMEPAGE>; @@ -57,7 +64,7 @@ linux,can-disable; }; - super-l { + key-super-l { label = "Super Left"; gpios = <&tlmm 32 GPIO_ACTIVE_LOW>; linux,code = <KEY_FN>; @@ -65,7 +72,7 @@ linux,can-disable; }; - super-r { + key-super-r { label = "Super Right"; gpios = <&tlmm 33 GPIO_ACTIVE_LOW>; linux,code = <KEY_FN>; @@ -73,7 +80,7 @@ linux,can-disable; }; - shift { + key-shift { label = "Shift"; gpios = <&tlmm 114 GPIO_ACTIVE_LOW>; linux,code = <KEY_RIGHTSHIFT>; @@ -81,7 +88,7 @@ linux,can-disable; }; - ctrl { + key-ctrl { label = "Ctrl"; gpios = <&tlmm 128 GPIO_ACTIVE_LOW>; linux,code = <KEY_LEFTCTRL>; @@ -89,7 +96,7 @@ linux,can-disable; }; - alt { + key-alt { label = "Alt"; gpios = <&tlmm 129 GPIO_ACTIVE_LOW>; linux,code = <KEY_LEFTALT>; @@ -101,12 +108,10 @@ gpio-keys { compatible = "gpio-keys"; label = "Side buttons"; - #address-cells = <1>; - #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&vol_up_pin_a>, <&cam_focus_pin_a>, <&cam_snapshot_pin_a>; - vol-up { + button-vol-up { label = "Volume Up"; gpios = <&pm8998_gpio 6 GPIO_ACTIVE_LOW>; linux,input-type = <EV_KEY>; @@ -115,7 +120,7 @@ debounce-interval = <15>; }; - camera-snapshot { + button-camera-snapshot { label = "Camera Snapshot"; gpios = <&pm8998_gpio 7 GPIO_ACTIVE_LOW>; linux,input-type = <EV_KEY>; @@ -123,7 +128,7 @@ debounce-interval = <15>; }; - camera-focus { + button-camera-focus { label = "Camera Focus"; gpios = <&pm8998_gpio 8 GPIO_ACTIVE_LOW>; linux,input-type = <EV_KEY>; @@ -135,7 +140,7 @@ keyboard-leds { compatible = "gpio-leds"; - backlight { + led-0 { color = <LED_COLOR_ID_WHITE>; default-state = "off"; function = LED_FUNCTION_KBD_BACKLIGHT; @@ -144,7 +149,7 @@ retain-state-suspended; }; - caps-lock { + led-1 { color = <LED_COLOR_ID_YELLOW>; default-state = "off"; function = LED_FUNCTION_CAPSLOCK; @@ -187,10 +192,57 @@ pinctrl-0 = <&ts_vio_default>; regulator-always-on; }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-always-on; + regulator-boot-on; + }; +}; + +&blsp1_uart3 { + status = "okay"; + + bluetooth { + compatible = "qcom,wcn3990-bt"; + + vddio-supply = <&vreg_s4a_1p8>; + vddxo-supply = <&vreg_l7a_1p8>; + vddrf-supply = <&vreg_l17a_1p3>; + vddch0-supply = <&vreg_l25a_3p3>; + max-speed = <3200000>; + }; +}; + +&blsp1_uart3_on { + rx { + /delete-property/ bias-disable; + /* + * Configure a pull-up on 45 (RX). This is needed to + * avoid garbage data when the TX pin of the Bluetooth + * module is in tri-state (module powered off or not + * driving the signal yet). + */ + bias-pull-up; + }; + + cts { + /delete-property/ bias-disable; + /* + * Configure a pull-down on 47 (CTS) to match the pull + * of the Bluetooth module. + */ + bias-pull-down; + }; +}; + +&blsp2_uart1 { + status = "okay"; }; &blsp2_i2c1 { - status = "ok"; + status = "okay"; touchscreen@14 { compatible = "goodix,gt9286"; @@ -205,16 +257,93 @@ }; }; -&mmcc { - status = "ok"; +&etf { + status = "okay"; +}; + +&etm1 { + status = "okay"; +}; + +&etm2 { + status = "okay"; +}; + +&etm3 { + status = "okay"; +}; + +&etm4 { + status = "okay"; +}; + +&etm5 { + status = "okay"; +}; + +&etm6 { + status = "okay"; +}; + +&etm7 { + status = "okay"; +}; + +&etm8 { + status = "okay"; +}; + +&etr { + status = "okay"; }; -&mmss_smmu { - status = "ok"; +&funnel1 { + status = "okay"; +}; + +&funnel2 { + status = "okay"; +}; + +&funnel3 { + status = "okay"; +}; + +&funnel4 { + // FIXME: Figure out why clock late_initcall crashes the board with + // this enabled. + // status = "okay"; +}; + +&funnel5 { + // FIXME: Figure out why clock late_initcall crashes the board with + // this enabled. + // status = "okay"; +}; + +&pcie0 { + status = "okay"; +}; + +&pcie_phy { + status = "okay"; +}; + +&pm8005_regulators { + vdd_s1-supply = <&vph_pwr>; + + pm8005_s1: s1 { /* VDD_GFX supply */ + regulator-min-microvolt = <524000>; + regulator-max-microvolt = <1100000>; + regulator-enable-ramp-delay = <500>; + + /* Hack until we rig up the gpu consumer */ + regulator-always-on; + }; }; &pm8998_gpio { - vol_up_pin_a: vol-up-active { + vol_up_pin_a: vol-up-active-state { pins = "gpio6"; function = "normal"; bias-pull-up; @@ -222,7 +351,7 @@ qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>; }; - cam_focus_pin_a: cam-focus-btn-active { + cam_focus_pin_a: cam-focus-btn-active-state { pins = "gpio7"; function = "normal"; bias-pull-up; @@ -230,7 +359,7 @@ qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>; }; - cam_snapshot_pin_a: cam-snapshot-btn-active { + cam_snapshot_pin_a: cam-snapshot-btn-active-state { pins = "gpio8"; function = "normal"; bias-pull-up; @@ -249,6 +378,240 @@ }; }; +&qusb2phy { + status = "okay"; + + vdda-pll-supply = <&vreg_l12a_1p8>; + vdda-phy-dpdm-supply = <&vreg_l24a_3p075>; +}; + +&replicator1 { + status = "okay"; +}; + +&rpm_requests { + pm8998-regulators { + compatible = "qcom,rpm-pm8998-regulators"; + + vdd_s1-supply = <&vph_pwr>; + vdd_s2-supply = <&vph_pwr>; + vdd_s3-supply = <&vph_pwr>; + vdd_s4-supply = <&vph_pwr>; + vdd_s5-supply = <&vph_pwr>; + vdd_s6-supply = <&vph_pwr>; + vdd_s7-supply = <&vph_pwr>; + vdd_s8-supply = <&vph_pwr>; + vdd_s9-supply = <&vph_pwr>; + vdd_s10-supply = <&vph_pwr>; + vdd_s11-supply = <&vph_pwr>; + vdd_s12-supply = <&vph_pwr>; + vdd_s13-supply = <&vph_pwr>; + vdd_l1_l27-supply = <&vreg_s7a_1p025>; + vdd_l2_l8_l17-supply = <&vreg_s3a_1p35>; + vdd_l3_l11-supply = <&vreg_s7a_1p025>; + vdd_l4_l5-supply = <&vreg_s7a_1p025>; + vdd_l6-supply = <&vreg_s5a_2p04>; + vdd_l7_l12_l14_l15-supply = <&vreg_s5a_2p04>; + vdd_l9-supply = <&vreg_bob>; + vdd_l10_l23_l25-supply = <&vreg_bob>; + vdd_l13_l19_l21-supply = <&vreg_bob>; + vdd_l16_l28-supply = <&vreg_bob>; + vdd_l18_l22-supply = <&vreg_bob>; + vdd_l20_l24-supply = <&vreg_bob>; + vdd_l26-supply = <&vreg_s3a_1p35>; + vdd_lvs1_lvs2-supply = <&vreg_s4a_1p8>; + + vreg_s3a_1p35: s3 { + regulator-min-microvolt = <1352000>; + regulator-max-microvolt = <1352000>; + }; + + vreg_s4a_1p8: s4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-allow-set-load; + }; + + vreg_s5a_2p04: s5 { + regulator-min-microvolt = <1904000>; + regulator-max-microvolt = <2040000>; + }; + + vreg_s7a_1p025: s7 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1028000>; + }; + + vreg_l1a_0p875: l1 { + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + }; + + vreg_l2a_1p2: l2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + vreg_l3a_1p0: l3 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + }; + + vreg_l5a_0p8: l5 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + }; + + vreg_l6a_1p8: l6 { + regulator-min-microvolt = <1808000>; + regulator-max-microvolt = <1808000>; + }; + + vreg_l7a_1p8: l7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vreg_l8a_1p2: l8 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + vreg_l9a_1p8: l9 { + regulator-min-microvolt = <1808000>; + regulator-max-microvolt = <2960000>; + }; + + vreg_l10a_1p8: l10 { + regulator-min-microvolt = <1808000>; + regulator-max-microvolt = <2960000>; + }; + + vreg_l11a_1p0: l11 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + }; + + vreg_l12a_1p8: l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vreg_l13a_2p95: l13 { + regulator-min-microvolt = <1808000>; + regulator-max-microvolt = <2960000>; + }; + + vreg_l14a_1p88: l14 { + regulator-min-microvolt = <1880000>; + regulator-max-microvolt = <1880000>; + }; + + vreg_l15a_1p8: l15 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vreg_l16a_2p7: l16 { + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <2704000>; + }; + + vreg_l17a_1p3: l17 { + regulator-min-microvolt = <1304000>; + regulator-max-microvolt = <1304000>; + }; + + vreg_l18a_2p7: l18 { + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <2704000>; + }; + + vreg_l19a_3p0: l19 { + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3008000>; + }; + + vreg_l20a_2p95: l20 { + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <2960000>; + regulator-allow-set-load; + }; + + vreg_l21a_2p95: l21 { + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <2960000>; + regulator-system-load = <800000>; + regulator-allow-set-load; + }; + + vreg_l22a_2p85: l22 { + regulator-min-microvolt = <2864000>; + regulator-max-microvolt = <2864000>; + }; + + vreg_l23a_3p3: l23 { + regulator-min-microvolt = <3312000>; + regulator-max-microvolt = <3312000>; + }; + + vreg_l24a_3p075: l24 { + regulator-min-microvolt = <3088000>; + regulator-max-microvolt = <3088000>; + }; + + vreg_l25a_3p3: l25 { + regulator-min-microvolt = <3104000>; + regulator-max-microvolt = <3312000>; + }; + + vreg_l26a_1p2: l26 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-allow-set-load; + }; + + vreg_l28_3p0: l28 { + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3008000>; + }; + + vreg_lvs1a_1p8: lvs1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vreg_lvs2a_1p8: lvs2 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + }; + + pmi8998-regulators { + compatible = "qcom,rpm-pmi8998-regulators"; + + vdd_bob-supply = <&vph_pwr>; + + vreg_bob: bob { + regulator-min-microvolt = <3312000>; + regulator-max-microvolt = <3600000>; + }; + }; +}; + +&remoteproc_adsp { + status = "okay"; +}; + +&remoteproc_mss { + status = "okay"; +}; + +&remoteproc_slpi { + status = "okay"; +}; + &tlmm { gpio-reserved-ranges = <0 4>; @@ -297,12 +660,41 @@ }; }; +&sdhc2 { + status = "okay"; + cd-gpios = <&tlmm 95 GPIO_ACTIVE_LOW>; + + vmmc-supply = <&vreg_l21a_2p95>; + vqmmc-supply = <&vreg_l13a_2p95>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_on &sdc2_cd>; + pinctrl-1 = <&sdc2_off &sdc2_cd>; +}; + +&stm { + status = "okay"; +}; + &ufshc { - status = "ok"; + status = "okay"; + vcc-supply = <&vreg_l20a_2p95>; + vccq-supply = <&vreg_l26a_1p2>; + vccq2-supply = <&vreg_s4a_1p8>; + vcc-max-microamp = <750000>; + vccq-max-microamp = <560000>; + vccq2-max-microamp = <750000>; }; &ufsphy { - status = "ok"; + status = "okay"; + vdda-phy-supply = <&vreg_l1a_0p875>; + vdda-pll-supply = <&vreg_l2a_1p2>; + vddp-ref-clk-supply = <&vreg_l26a_1p2>; +}; + +&usb3 { + status = "okay"; }; &usb3_dwc3 { @@ -310,8 +702,24 @@ extcon = <&extcon_usb>; }; +&usb3phy { + status = "okay"; + + vdda-phy-supply = <&vreg_l1a_0p875>; + vdda-pll-supply = <&vreg_l2a_1p2>; +}; + /* GT9286 analog supply */ &vreg_l28_3p0 { regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; }; + +&wifi { + status = "okay"; + + vdd-0.8-cx-mx-supply = <&vreg_l5a_0p8>; + vdd-1.8-xo-supply = <&vreg_l7a_1p8>; + vdd-1.3-rfa-supply = <&vreg_l17a_1p3>; + vdd-3.3-ch0-supply = <&vreg_l25a_3p3>; +}; diff --git a/arch/arm64/boot/dts/qcom/msm8998-hp-envy-x2.dts b/arch/arm64/boot/dts/qcom/msm8998-hp-envy-x2.dts index 1eb406b43fd7..38389c6a3f68 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-hp-envy-x2.dts +++ b/arch/arm64/boot/dts/qcom/msm8998-hp-envy-x2.dts @@ -16,13 +16,14 @@ keyboard@3a { compatible = "hid-over-i2c"; - interrupt-parent = <&tlmm>; - interrupts = <0x79 IRQ_TYPE_LEVEL_LOW>; reg = <0x3a>; - hid-descr-addr = <0x0001>; - pinctrl-names = "default"; pinctrl-0 = <&touchpad>; + + interrupt-parent = <&tlmm>; + interrupts = <121 IRQ_TYPE_LEVEL_LOW>; + + hid-descr-addr = <0x0001>; }; }; diff --git a/arch/arm64/boot/dts/qcom/msm8998-lenovo-miix-630.dts b/arch/arm64/boot/dts/qcom/msm8998-lenovo-miix-630.dts index f55f6f3e3e5d..cf81c33a9d7e 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-lenovo-miix-630.dts +++ b/arch/arm64/boot/dts/qcom/msm8998-lenovo-miix-630.dts @@ -16,13 +16,14 @@ keyboard@3a { compatible = "hid-over-i2c"; - interrupt-parent = <&tlmm>; - interrupts = <0x79 IRQ_TYPE_LEVEL_LOW>; reg = <0x3a>; - hid-descr-addr = <0x0001>; - pinctrl-names = "default"; pinctrl-0 = <&touchpad>; + + interrupt-parent = <&tlmm>; + interrupts = <121 IRQ_TYPE_LEVEL_LOW>; + + hid-descr-addr = <0x0001>; }; }; diff --git a/arch/arm64/boot/dts/qcom/msm8998-mtp.dts b/arch/arm64/boot/dts/qcom/msm8998-mtp.dts index 66540d2ca13b..a3ca58100aee 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-mtp.dts +++ b/arch/arm64/boot/dts/qcom/msm8998-mtp.dts @@ -3,11 +3,450 @@ /dts-v1/; -#include "msm8998-mtp.dtsi" +#include "msm8998.dtsi" +#include "pm8005.dtsi" +#include "pm8998.dtsi" +#include "pmi8998.dtsi" / { model = "Qualcomm Technologies, Inc. MSM8998 v1 MTP"; - compatible = "qcom,msm8998-mtp"; + compatible = "qcom,msm8998-mtp", "qcom,msm8998"; qcom,board-id = <8 0>; + + aliases { + serial0 = &blsp2_uart1; + serial1 = &blsp1_uart3; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-always-on; + regulator-boot-on; + }; +}; + +&blsp1_uart3 { + status = "okay"; + + bluetooth { + compatible = "qcom,wcn3990-bt"; + + vddio-supply = <&vreg_s4a_1p8>; + vddxo-supply = <&vreg_l7a_1p8>; + vddrf-supply = <&vreg_l17a_1p3>; + vddch0-supply = <&vreg_l25a_3p3>; + max-speed = <3200000>; + }; +}; + +&blsp1_uart3_on { + rx { + /delete-property/ bias-disable; + /* + * Configure a pull-up on 45 (RX). This is needed to + * avoid garbage data when the TX pin of the Bluetooth + * module is in tri-state (module powered off or not + * driving the signal yet). + */ + bias-pull-up; + }; + + cts { + /delete-property/ bias-disable; + /* + * Configure a pull-down on 47 (CTS) to match the pull + * of the Bluetooth module. + */ + bias-pull-down; + }; +}; + +&blsp2_uart1 { + status = "okay"; +}; + +&etf { + status = "okay"; +}; + +&etm1 { + status = "okay"; +}; + +&etm2 { + status = "okay"; +}; + +&etm3 { + status = "okay"; +}; + +&etm4 { + status = "okay"; +}; + +&etm5 { + status = "okay"; +}; + +&etm6 { + status = "okay"; +}; + +&etm7 { + status = "okay"; +}; + +&etm8 { + status = "okay"; +}; + +&etr { + status = "okay"; +}; + +&funnel1 { + status = "okay"; +}; + +&funnel2 { + status = "okay"; +}; + +&funnel3 { + status = "okay"; +}; + +&funnel4 { + // FIXME: Figure out why clock late_initcall crashes the board with + // this enabled. + // status = "okay"; +}; + +&funnel5 { + // FIXME: Figure out why clock late_initcall crashes the board with + // this enabled. + // status = "okay"; +}; + +&pcie0 { + status = "okay"; +}; + +&pcie_phy { + status = "okay"; +}; + +&pm8005_regulators { + vdd_s1-supply = <&vph_pwr>; + + pm8005_s1: s1 { /* VDD_GFX supply */ + regulator-min-microvolt = <524000>; + regulator-max-microvolt = <1100000>; + regulator-enable-ramp-delay = <500>; + + /* Hack until we rig up the gpu consumer */ + regulator-always-on; + }; +}; + +&qusb2phy { + status = "okay"; + + vdda-pll-supply = <&vreg_l12a_1p8>; + vdda-phy-dpdm-supply = <&vreg_l24a_3p075>; +}; + +&replicator1 { + status = "okay"; +}; + +&rpm_requests { + pm8998-regulators { + compatible = "qcom,rpm-pm8998-regulators"; + + vdd_s1-supply = <&vph_pwr>; + vdd_s2-supply = <&vph_pwr>; + vdd_s3-supply = <&vph_pwr>; + vdd_s4-supply = <&vph_pwr>; + vdd_s5-supply = <&vph_pwr>; + vdd_s6-supply = <&vph_pwr>; + vdd_s7-supply = <&vph_pwr>; + vdd_s8-supply = <&vph_pwr>; + vdd_s9-supply = <&vph_pwr>; + vdd_s10-supply = <&vph_pwr>; + vdd_s11-supply = <&vph_pwr>; + vdd_s12-supply = <&vph_pwr>; + vdd_s13-supply = <&vph_pwr>; + vdd_l1_l27-supply = <&vreg_s7a_1p025>; + vdd_l2_l8_l17-supply = <&vreg_s3a_1p35>; + vdd_l3_l11-supply = <&vreg_s7a_1p025>; + vdd_l4_l5-supply = <&vreg_s7a_1p025>; + vdd_l6-supply = <&vreg_s5a_2p04>; + vdd_l7_l12_l14_l15-supply = <&vreg_s5a_2p04>; + vdd_l9-supply = <&vreg_bob>; + vdd_l10_l23_l25-supply = <&vreg_bob>; + vdd_l13_l19_l21-supply = <&vreg_bob>; + vdd_l16_l28-supply = <&vreg_bob>; + vdd_l18_l22-supply = <&vreg_bob>; + vdd_l20_l24-supply = <&vreg_bob>; + vdd_l26-supply = <&vreg_s3a_1p35>; + vdd_lvs1_lvs2-supply = <&vreg_s4a_1p8>; + + vreg_s3a_1p35: s3 { + regulator-min-microvolt = <1352000>; + regulator-max-microvolt = <1352000>; + }; + + vreg_s4a_1p8: s4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-allow-set-load; + }; + + vreg_s5a_2p04: s5 { + regulator-min-microvolt = <1904000>; + regulator-max-microvolt = <2040000>; + }; + + vreg_s7a_1p025: s7 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1028000>; + }; + + vreg_l1a_0p875: l1 { + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + }; + + vreg_l2a_1p2: l2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + vreg_l3a_1p0: l3 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + }; + + vreg_l5a_0p8: l5 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + }; + + vreg_l6a_1p8: l6 { + regulator-min-microvolt = <1808000>; + regulator-max-microvolt = <1808000>; + }; + + vreg_l7a_1p8: l7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vreg_l8a_1p2: l8 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + vreg_l9a_1p8: l9 { + regulator-min-microvolt = <1808000>; + regulator-max-microvolt = <2960000>; + }; + + vreg_l10a_1p8: l10 { + regulator-min-microvolt = <1808000>; + regulator-max-microvolt = <2960000>; + }; + + vreg_l11a_1p0: l11 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + }; + + vreg_l12a_1p8: l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vreg_l13a_2p95: l13 { + regulator-min-microvolt = <1808000>; + regulator-max-microvolt = <2960000>; + }; + + vreg_l14a_1p88: l14 { + regulator-min-microvolt = <1880000>; + regulator-max-microvolt = <1880000>; + }; + + vreg_l15a_1p8: l15 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vreg_l16a_2p7: l16 { + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <2704000>; + }; + + vreg_l17a_1p3: l17 { + regulator-min-microvolt = <1304000>; + regulator-max-microvolt = <1304000>; + }; + + vreg_l18a_2p7: l18 { + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <2704000>; + }; + + vreg_l19a_3p0: l19 { + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3008000>; + }; + + vreg_l20a_2p95: l20 { + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <2960000>; + regulator-allow-set-load; + }; + + vreg_l21a_2p95: l21 { + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <2960000>; + regulator-system-load = <800000>; + regulator-allow-set-load; + }; + + vreg_l22a_2p85: l22 { + regulator-min-microvolt = <2864000>; + regulator-max-microvolt = <2864000>; + }; + + vreg_l23a_3p3: l23 { + regulator-min-microvolt = <3312000>; + regulator-max-microvolt = <3312000>; + }; + + vreg_l24a_3p075: l24 { + regulator-min-microvolt = <3088000>; + regulator-max-microvolt = <3088000>; + }; + + vreg_l25a_3p3: l25 { + regulator-min-microvolt = <3104000>; + regulator-max-microvolt = <3312000>; + }; + + vreg_l26a_1p2: l26 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-allow-set-load; + }; + + vreg_l28_3p0: l28 { + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3008000>; + }; + + vreg_lvs1a_1p8: lvs1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vreg_lvs2a_1p8: lvs2 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + }; + + pmi8998-regulators { + compatible = "qcom,rpm-pmi8998-regulators"; + + vdd_bob-supply = <&vph_pwr>; + + vreg_bob: bob { + regulator-min-microvolt = <3312000>; + regulator-max-microvolt = <3600000>; + }; + }; +}; + +&remoteproc_adsp { + status = "okay"; +}; + +&remoteproc_mss { + status = "okay"; +}; + +&remoteproc_slpi { + status = "okay"; +}; + +&tlmm { + gpio-reserved-ranges = <0 4>, <81 4>; +}; + +&sdhc2 { + status = "okay"; + cd-gpios = <&tlmm 95 GPIO_ACTIVE_LOW>; + + vmmc-supply = <&vreg_l21a_2p95>; + vqmmc-supply = <&vreg_l13a_2p95>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_on &sdc2_cd>; + pinctrl-1 = <&sdc2_off &sdc2_cd>; +}; + +&stm { + status = "okay"; +}; + +&ufshc { + status = "okay"; + vcc-supply = <&vreg_l20a_2p95>; + vccq-supply = <&vreg_l26a_1p2>; + vccq2-supply = <&vreg_s4a_1p8>; + vcc-max-microamp = <750000>; + vccq-max-microamp = <560000>; + vccq2-max-microamp = <750000>; +}; + +&ufsphy { + status = "okay"; + vdda-phy-supply = <&vreg_l1a_0p875>; + vdda-pll-supply = <&vreg_l2a_1p2>; + vddp-ref-clk-supply = <&vreg_l26a_1p2>; +}; + +&usb3 { + status = "okay"; +}; + +&usb3_dwc3 { + dr_mode = "host"; /* Force to host until we have Type-C hooked up */ +}; + +&usb3phy { + status = "okay"; + + vdda-phy-supply = <&vreg_l1a_0p875>; + vdda-pll-supply = <&vreg_l2a_1p2>; +}; + +&wifi { + status = "okay"; + + vdd-0.8-cx-mx-supply = <&vreg_l5a_0p8>; + vdd-1.8-xo-supply = <&vreg_l7a_1p8>; + vdd-1.3-rfa-supply = <&vreg_l17a_1p3>; + vdd-3.3-ch0-supply = <&vreg_l25a_3p3>; }; diff --git a/arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi b/arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi deleted file mode 100644 index af67c641df4e..000000000000 --- a/arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi +++ /dev/null @@ -1,421 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* Copyright (c) 2016, The Linux Foundation. All rights reserved. */ - -#include "msm8998.dtsi" -#include "pm8998.dtsi" -#include "pmi8998.dtsi" -#include "pm8005.dtsi" - -/ { - aliases { - serial0 = &blsp2_uart1; - serial1 = &blsp1_uart3; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - vph_pwr: vph-pwr-regulator { - compatible = "regulator-fixed"; - regulator-name = "vph_pwr"; - regulator-always-on; - regulator-boot-on; - }; -}; - -&blsp1_uart3 { - status = "okay"; - - bluetooth { - compatible = "qcom,wcn3990-bt"; - - vddio-supply = <&vreg_s4a_1p8>; - vddxo-supply = <&vreg_l7a_1p8>; - vddrf-supply = <&vreg_l17a_1p3>; - vddch0-supply = <&vreg_l25a_3p3>; - max-speed = <3200000>; - }; -}; - -&blsp2_uart1 { - status = "okay"; -}; - -&etf { - status = "okay"; -}; - -&etm1 { - status = "okay"; -}; - -&etm2 { - status = "okay"; -}; - -&etm3 { - status = "okay"; -}; - -&etm4 { - status = "okay"; -}; - -&etm5 { - status = "okay"; -}; - -&etm6 { - status = "okay"; -}; - -&etm7 { - status = "okay"; -}; - -&etm8 { - status = "okay"; -}; - -&etr { - status = "okay"; -}; - -&funnel1 { - status = "okay"; -}; - -&funnel2 { - status = "okay"; -}; - -&funnel3 { - status = "okay"; -}; - -&funnel4 { - // FIXME: Figure out why clock late_initcall crashes the board with - // this enabled. - // status = "okay"; -}; - -&funnel5 { - // FIXME: Figure out why clock late_initcall crashes the board with - // this enabled. - // status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; - -&pcie_phy { - status = "okay"; -}; - -&pm8005_lsid1 { - pm8005-regulators { - compatible = "qcom,pm8005-regulators"; - - vdd_s1-supply = <&vph_pwr>; - - pm8005_s1: s1 { /* VDD_GFX supply */ - regulator-min-microvolt = <524000>; - regulator-max-microvolt = <1100000>; - regulator-enable-ramp-delay = <500>; - - /* hack until we rig up the gpu consumer */ - regulator-always-on; - }; - }; -}; - -&qusb2phy { - status = "okay"; - - vdda-pll-supply = <&vreg_l12a_1p8>; - vdda-phy-dpdm-supply = <&vreg_l24a_3p075>; -}; - -&replicator1 { - status = "okay"; -}; - -&rpm_requests { - pm8998-regulators { - compatible = "qcom,rpm-pm8998-regulators"; - - vdd_s1-supply = <&vph_pwr>; - vdd_s2-supply = <&vph_pwr>; - vdd_s3-supply = <&vph_pwr>; - vdd_s4-supply = <&vph_pwr>; - vdd_s5-supply = <&vph_pwr>; - vdd_s6-supply = <&vph_pwr>; - vdd_s7-supply = <&vph_pwr>; - vdd_s8-supply = <&vph_pwr>; - vdd_s9-supply = <&vph_pwr>; - vdd_s10-supply = <&vph_pwr>; - vdd_s11-supply = <&vph_pwr>; - vdd_s12-supply = <&vph_pwr>; - vdd_s13-supply = <&vph_pwr>; - vdd_l1_l27-supply = <&vreg_s7a_1p025>; - vdd_l2_l8_l17-supply = <&vreg_s3a_1p35>; - vdd_l3_l11-supply = <&vreg_s7a_1p025>; - vdd_l4_l5-supply = <&vreg_s7a_1p025>; - vdd_l6-supply = <&vreg_s5a_2p04>; - vdd_l7_l12_l14_l15-supply = <&vreg_s5a_2p04>; - vdd_l9-supply = <&vreg_bob>; - vdd_l10_l23_l25-supply = <&vreg_bob>; - vdd_l13_l19_l21-supply = <&vreg_bob>; - vdd_l16_l28-supply = <&vreg_bob>; - vdd_l18_l22-supply = <&vreg_bob>; - vdd_l20_l24-supply = <&vreg_bob>; - vdd_l26-supply = <&vreg_s3a_1p35>; - vdd_lvs1_lvs2-supply = <&vreg_s4a_1p8>; - - vreg_s3a_1p35: s3 { - regulator-min-microvolt = <1352000>; - regulator-max-microvolt = <1352000>; - }; - vreg_s4a_1p8: s4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-allow-set-load; - }; - vreg_s5a_2p04: s5 { - regulator-min-microvolt = <1904000>; - regulator-max-microvolt = <2040000>; - }; - vreg_s7a_1p025: s7 { - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1028000>; - }; - vreg_l1a_0p875: l1 { - regulator-min-microvolt = <880000>; - regulator-max-microvolt = <880000>; - }; - vreg_l2a_1p2: l2 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - vreg_l3a_1p0: l3 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - }; - vreg_l5a_0p8: l5 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <800000>; - }; - vreg_l6a_1p8: l6 { - regulator-min-microvolt = <1808000>; - regulator-max-microvolt = <1808000>; - }; - vreg_l7a_1p8: l7 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - vreg_l8a_1p2: l8 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - vreg_l9a_1p8: l9 { - regulator-min-microvolt = <1808000>; - regulator-max-microvolt = <2960000>; - }; - vreg_l10a_1p8: l10 { - regulator-min-microvolt = <1808000>; - regulator-max-microvolt = <2960000>; - }; - vreg_l11a_1p0: l11 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - }; - vreg_l12a_1p8: l12 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - vreg_l13a_2p95: l13 { - regulator-min-microvolt = <1808000>; - regulator-max-microvolt = <2960000>; - }; - vreg_l14a_1p88: l14 { - regulator-min-microvolt = <1880000>; - regulator-max-microvolt = <1880000>; - }; - vreg_l15a_1p8: l15 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - vreg_l16a_2p7: l16 { - regulator-min-microvolt = <2704000>; - regulator-max-microvolt = <2704000>; - }; - vreg_l17a_1p3: l17 { - regulator-min-microvolt = <1304000>; - regulator-max-microvolt = <1304000>; - }; - vreg_l18a_2p7: l18 { - regulator-min-microvolt = <2704000>; - regulator-max-microvolt = <2704000>; - }; - vreg_l19a_3p0: l19 { - regulator-min-microvolt = <3008000>; - regulator-max-microvolt = <3008000>; - }; - vreg_l20a_2p95: l20 { - regulator-min-microvolt = <2960000>; - regulator-max-microvolt = <2960000>; - regulator-allow-set-load; - }; - vreg_l21a_2p95: l21 { - regulator-min-microvolt = <2960000>; - regulator-max-microvolt = <2960000>; - regulator-allow-set-load; - regulator-system-load = <800000>; - }; - vreg_l22a_2p85: l22 { - regulator-min-microvolt = <2864000>; - regulator-max-microvolt = <2864000>; - }; - vreg_l23a_3p3: l23 { - regulator-min-microvolt = <3312000>; - regulator-max-microvolt = <3312000>; - }; - vreg_l24a_3p075: l24 { - regulator-min-microvolt = <3088000>; - regulator-max-microvolt = <3088000>; - }; - vreg_l25a_3p3: l25 { - regulator-min-microvolt = <3104000>; - regulator-max-microvolt = <3312000>; - }; - vreg_l26a_1p2: l26 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-allow-set-load; - }; - vreg_l28_3p0: l28 { - regulator-min-microvolt = <3008000>; - regulator-max-microvolt = <3008000>; - }; - - vreg_lvs1a_1p8: lvs1 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vreg_lvs2a_1p8: lvs2 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - }; - - pmi8998-regulators { - compatible = "qcom,rpm-pmi8998-regulators"; - - vdd_bob-supply = <&vph_pwr>; - - vreg_bob: bob { - regulator-min-microvolt = <3312000>; - regulator-max-microvolt = <3600000>; - }; - }; -}; - -&remoteproc_adsp { - status = "okay"; -}; - -&remoteproc_mss { - status = "okay"; -}; - -&remoteproc_slpi { - status = "okay"; -}; - -&tlmm { - gpio-reserved-ranges = <0 4>, <81 4>; -}; - -&sdhc2 { - status = "okay"; - cd-gpios = <&tlmm 95 GPIO_ACTIVE_LOW>; - - vmmc-supply = <&vreg_l21a_2p95>; - vqmmc-supply = <&vreg_l13a_2p95>; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; - pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; -}; - -&stm { - status = "okay"; -}; - -&ufshc { - status = "okay"; - vcc-supply = <&vreg_l20a_2p95>; - vccq-supply = <&vreg_l26a_1p2>; - vccq2-supply = <&vreg_s4a_1p8>; - vcc-max-microamp = <750000>; - vccq-max-microamp = <560000>; - vccq2-max-microamp = <750000>; -}; - -&ufsphy { - status = "okay"; - vdda-phy-supply = <&vreg_l1a_0p875>; - vdda-pll-supply = <&vreg_l2a_1p2>; - vddp-ref-clk-supply = <&vreg_l26a_1p2>; -}; - -&usb3 { - status = "okay"; -}; - -&usb3_dwc3 { - dr_mode = "host"; /* Force to host until we have Type-C hooked up */ -}; - -&usb3phy { - status = "okay"; - - vdda-phy-supply = <&vreg_l1a_0p875>; - vdda-pll-supply = <&vreg_l2a_1p2>; -}; - -&wifi { - status = "okay"; - - vdd-0.8-cx-mx-supply = <&vreg_l5a_0p8>; - vdd-1.8-xo-supply = <&vreg_l7a_1p8>; - vdd-1.3-rfa-supply = <&vreg_l17a_1p3>; - vdd-3.3-ch0-supply = <&vreg_l25a_3p3>; -}; - -/* PINCTRL - board-specific pinctrl */ -&blsp1_uart3_on { - rx { - /delete-property/ bias-disable; - /* - * Configure a pull-up on 45 (RX). This is needed to - * avoid garbage data when the TX pin of the Bluetooth - * module is in tri-state (module powered off or not - * driving the signal yet). - */ - bias-pull-up; - }; - - cts { - /delete-property/ bias-disable; - /* - * Configure a pull-down on 47 (CTS) to match the pull - * of the Bluetooth module. - */ - bias-pull-down; - }; -}; diff --git a/arch/arm64/boot/dts/qcom/msm8998-oneplus-cheeseburger.dts b/arch/arm64/boot/dts/qcom/msm8998-oneplus-cheeseburger.dts index 9563eb62db88..ef2a88a64d32 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-oneplus-cheeseburger.dts +++ b/arch/arm64/boot/dts/qcom/msm8998-oneplus-cheeseburger.dts @@ -32,7 +32,7 @@ }; &pmi8998_gpio { - button_backlight_default: button-backlight-default { + button_backlight_default: button-backlight-state { pinconf { pins = "gpio5"; function = "normal"; diff --git a/arch/arm64/boot/dts/qcom/msm8998-oneplus-common.dtsi b/arch/arm64/boot/dts/qcom/msm8998-oneplus-common.dtsi index dbaea360bffc..62bda23791bb 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-oneplus-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998-oneplus-common.dtsi @@ -11,9 +11,9 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/pinctrl/qcom,pmic-gpio.h> #include "msm8998.dtsi" +#include "pm8005.dtsi" #include "pm8998.dtsi" #include "pmi8998.dtsi" -#include "pm8005.dtsi" / { /* Required for bootloader to select correct board */ @@ -32,6 +32,19 @@ height = <1920>; stride = <(1080 * 4)>; format = "a8r8g8b8"; + /* + * That's a lot of clocks, but it's necessary due + * to unused clk cleanup & no panel driver yet.. + */ + clocks = <&mmcc MDSS_AHB_CLK>, + <&mmcc MDSS_AXI_CLK>, + <&mmcc MDSS_VSYNC_CLK>, + <&mmcc MDSS_MDP_CLK>, + <&mmcc MDSS_BYTE0_CLK>, + <&mmcc MDSS_BYTE0_INTF_CLK>, + <&mmcc MDSS_PCLK0_CLK>, + <&mmcc MDSS_ESC0_CLK>; + power-domains = <&mmcc MDSS_GDSC>; }; }; @@ -77,7 +90,7 @@ pinctrl-names = "default"; pinctrl-0 = <&vol_keys_default>; - vol-down { + button-vol-down { label = "Volume down"; gpios = <&pm8998_gpio 5 GPIO_ACTIVE_LOW>; linux,code = <KEY_VOLUMEDOWN>; @@ -85,7 +98,7 @@ wakeup-source; }; - vol-up { + button-vol-up { label = "Volume up"; gpios = <&pm8998_gpio 6 GPIO_ACTIVE_LOW>; linux,code = <KEY_VOLUMEUP>; @@ -101,7 +114,7 @@ pinctrl-names = "default"; pinctrl-0 = <&hall_sensor_default>; - hall-sensor { + event-hall-sensor { label = "Hall Effect Sensor"; gpios = <&tlmm 124 GPIO_ACTIVE_LOW>; linux,input-type = <EV_SW>; @@ -245,32 +258,24 @@ status = "okay"; }; -&pm8005_lsid1 { - pm8005-regulators { - compatible = "qcom,pm8005-regulators"; - - vdd_s1-supply = <&vph_pwr>; - - pm8005_s1: s1 { /* VDD_GFX supply */ - regulator-min-microvolt = <524000>; - regulator-max-microvolt = <1100000>; - regulator-enable-ramp-delay = <500>; - - /* hack until we rig up the gpu consumer */ - regulator-always-on; - }; +&pm8005_regulators { + /* VDD_GFX supply */ + pm8005_s1: s1 { + regulator-min-microvolt = <524000>; + regulator-max-microvolt = <1100000>; + regulator-enable-ramp-delay = <500>; + /* Hack until we rig up the gpu consumer */ + regulator-always-on; }; }; &pm8998_gpio { - vol_keys_default: vol-keys-default { - pinconf { - pins = "gpio5", "gpio6"; - function = "normal"; - bias-pull-up; - input-enable; - qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>; - }; + vol_keys_default: vol-keys-state { + pins = "gpio5", "gpio6"; + function = "normal"; + bias-pull-up; + input-enable; + qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>; }; }; @@ -318,91 +323,113 @@ regulator-min-microvolt = <1352000>; regulator-max-microvolt = <1352000>; }; + vreg_s4a_1p8: s4 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-allow-set-load; }; + vreg_s5a_2p04: s5 { regulator-min-microvolt = <1904000>; regulator-max-microvolt = <2040000>; }; + vreg_s7a_1p025: s7 { regulator-min-microvolt = <900000>; regulator-max-microvolt = <1028000>; }; + vreg_l1a_0p875: l1 { regulator-min-microvolt = <880000>; regulator-max-microvolt = <880000>; }; + vreg_l2a_1p2: l2 { regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; }; + vreg_l3a_1p0: l3 { regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; }; + vreg_l5a_0p8: l5 { regulator-min-microvolt = <800000>; regulator-max-microvolt = <800000>; }; + vreg_l6a_1p8: l6 { regulator-min-microvolt = <1808000>; regulator-max-microvolt = <1808000>; }; + vreg_l7a_1p8: l7 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; + vreg_l8a_1p2: l8 { regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; }; + vreg_l9a_1p8: l9 { regulator-min-microvolt = <1808000>; regulator-max-microvolt = <2960000>; }; + vreg_l10a_1p8: l10 { regulator-min-microvolt = <1808000>; regulator-max-microvolt = <2960000>; }; + vreg_l11a_1p0: l11 { regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; }; + vreg_l12a_1p8: l12 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; + vreg_l13a_2p95: l13 { regulator-min-microvolt = <1808000>; regulator-max-microvolt = <2960000>; }; + vreg_l14a_1p88: l14 { regulator-min-microvolt = <1880000>; regulator-max-microvolt = <1880000>; }; + vreg_l15a_1p8: l15 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; + vreg_l16a_2p7: l16 { regulator-min-microvolt = <2704000>; regulator-max-microvolt = <2704000>; }; + vreg_l17a_1p3: l17 { regulator-min-microvolt = <1304000>; regulator-max-microvolt = <1304000>; }; + vreg_l18a_2p7: l18 { regulator-min-microvolt = <2704000>; regulator-max-microvolt = <2704000>; }; + vreg_l19a_3p0: l19 { regulator-min-microvolt = <3008000>; regulator-max-microvolt = <3008000>; }; + vreg_l20a_2p95: l20 { regulator-min-microvolt = <2960000>; regulator-max-microvolt = <2960000>; @@ -411,34 +438,41 @@ vreg_l21a_2p95: l21 { regulator-min-microvolt = <2960000>; regulator-max-microvolt = <2960000>; - regulator-allow-set-load; regulator-system-load = <800000>; + regulator-allow-set-load; }; + vreg_l22a_2p85: l22 { regulator-min-microvolt = <2864000>; regulator-max-microvolt = <2864000>; }; + vreg_l23a_3p3: l23 { regulator-min-microvolt = <3312000>; regulator-max-microvolt = <3312000>; }; + vreg_l24a_3p075: l24 { regulator-min-microvolt = <3088000>; regulator-max-microvolt = <3088000>; }; + vreg_l25a_3p3: l25 { regulator-min-microvolt = <3104000>; regulator-max-microvolt = <3312000>; }; + vreg_l26a_1p2: l26 { regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; regulator-allow-set-load; }; + vreg_l28_3p0: l28 { regulator-min-microvolt = <3008000>; regulator-max-microvolt = <3008000>; }; + vreg_lvs1a_1p8: lvs1 { }; vreg_lvs2a_1p8: lvs2 { }; }; diff --git a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino-lilac.dts b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino-lilac.dts index caacb7c28402..fcaefc1b1e2f 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino-lilac.dts +++ b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino-lilac.dts @@ -29,3 +29,7 @@ regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; }; + +&vreg_lvs1a_1p8 { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino-maple.dts b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino-maple.dts index 978495a8a6b9..20fe0394a3c1 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino-maple.dts +++ b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino-maple.dts @@ -38,7 +38,7 @@ }; &pmi8998_gpio { - disp_dvdd_en: disp-dvdd-en-active { + disp_dvdd_en: disp-dvdd-en-active-state { pins = "gpio10"; function = "normal"; bias-disable; diff --git a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino-poplar.dts b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino-poplar.dts index 4a1f98a21031..c21333aa73c2 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino-poplar.dts +++ b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino-poplar.dts @@ -26,11 +26,13 @@ }; &vreg_l18a_2p85 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; + /* Note: Round-down from 2850000 to be a multiple of PLDO step-size 8000 */ + regulator-min-microvolt = <2848000>; + regulator-max-microvolt = <2848000>; }; &vreg_l22a_2p85 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; + /* Note: Round-down from 2700000 to be a multiple of PLDO step-size 8000 */ + regulator-min-microvolt = <2696000>; + regulator-max-microvolt = <2696000>; }; diff --git a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi index 47488a1aecae..d08639082247 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi @@ -5,15 +5,13 @@ * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org> */ +#include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/pinctrl/qcom,pmic-gpio.h> #include "msm8998.dtsi" #include "pm8005.dtsi" #include "pm8998.dtsi" #include "pmi8998.dtsi" -#include <dt-bindings/input/input.h> -#include <dt-bindings/leds/common.h> -#include <dt-bindings/pinctrl/qcom,pmic-gpio.h> -#include <dt-bindings/sound/qcom,q6afe.h> -#include <dt-bindings/sound/qcom,q6asm.h> / { /* required for bootloader to select correct board */ @@ -21,8 +19,6 @@ qcom,board-id = <8 0>; clocks { - compatible = "simple-bus"; - div1_mclk: divclk1 { compatible = "gpio-gate-clock"; pinctrl-0 = <&audio_mclk_pin>; @@ -91,13 +87,21 @@ regulator-boot-on; }; + extcon_usb: extcon-usb { + compatible = "linux,extcon-usb-gpio"; + id-gpio = <&tlmm 38 GPIO_ACTIVE_HIGH>; + vbus-gpio = <&tlmm 128 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_extcon_active &usb_vbus_active>; + }; + gpio-keys { compatible = "gpio-keys"; label = "Side buttons"; pinctrl-names = "default"; pinctrl-0 = <&vol_down_pin_a>, <&cam_focus_pin_a>, <&cam_snapshot_pin_a>; - vol-down { + button-vol-down { label = "Volume Down"; gpios = <&pm8998_gpio 5 GPIO_ACTIVE_LOW>; linux,input-type = <EV_KEY>; @@ -106,7 +110,7 @@ debounce-interval = <15>; }; - camera-snapshot { + button-camera-snapshot { label = "Camera Snapshot"; gpios = <&pm8998_gpio 7 GPIO_ACTIVE_LOW>; linux,input-type = <EV_KEY>; @@ -114,7 +118,7 @@ debounce-interval = <15>; }; - camera-focus { + button-camera-focus { label = "Camera Focus"; gpios = <&pm8998_gpio 8 GPIO_ACTIVE_LOW>; linux,input-type = <EV_KEY>; @@ -129,7 +133,7 @@ pinctrl-names = "default"; pinctrl-0 = <&hall_sensor0_default>; - hall-sensor0 { + event-hall-sensor0 { label = "Cover Hall Sensor"; gpios = <&tlmm 124 GPIO_ACTIVE_LOW>; linux,input-type = <EV_SW>; @@ -245,6 +249,24 @@ status = "okay"; }; +&blsp2_i2c2 { + status = "okay"; + + proximity@29 { + compatible = "st,vl53l0x"; + reg = <0x29>; + + interrupt-parent = <&tlmm>; + interrupts = <22 IRQ_TYPE_EDGE_FALLING>; + + reset-gpios = <&tlmm 27 GPIO_ACTIVE_LOW>; + vdd-supply = <&cam_vio_vreg>; + + pinctrl-names = "default"; + pinctrl-0 = <&tof_int &tof_reset>; + }; +}; + &ibb { regulator-min-microamp = <800000>; regulator-max-microamp = <800000>; @@ -270,32 +292,19 @@ regulator-soft-start; }; -&mmcc { - status = "ok"; -}; - -&mmss_smmu { - status = "ok"; -}; - -&pm8005_lsid1 { - pm8005-regulators { - compatible = "qcom,pm8005-regulators"; - - vdd_s1-supply = <&vph_pwr>; - - /* VDD_GFX supply */ - pm8005_s1: s1 { - regulator-min-microvolt = <524000>; - regulator-max-microvolt = <1088000>; - regulator-enable-ramp-delay = <500>; - regulator-always-on; - }; +&pm8005_regulators { + /* VDD_GFX supply */ + pm8005_s1: s1 { + regulator-min-microvolt = <524000>; + regulator-max-microvolt = <1088000>; + regulator-enable-ramp-delay = <500>; + /* Hack until we rig up the gpu consumer */ + regulator-always-on; }; }; &pm8998_gpio { - vol_down_pin_a: vol-down-active { + vol_down_pin_a: vol-down-active-state { pins = "gpio5"; function = PMIC_GPIO_FUNC_NORMAL; bias-pull-up; @@ -303,7 +312,7 @@ qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>; }; - cam_focus_pin_a: cam-focus-btn-active { + cam_focus_pin_a: cam-focus-btn-active-state { pins = "gpio7"; function = PMIC_GPIO_FUNC_NORMAL; bias-pull-up; @@ -311,7 +320,7 @@ qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>; }; - cam_snapshot_pin_a: cam-snapshot-btn-active { + cam_snapshot_pin_a: cam-snapshot-btn-active-state { pins = "gpio8"; function = PMIC_GPIO_FUNC_NORMAL; bias-pull-up; @@ -319,7 +328,7 @@ qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>; }; - audio_mclk_pin: audio-mclk-pin-active { + audio_mclk_pin: audio-mclk-pin-active-state { pins = "gpio13"; function = "func2"; power-source = <0>; @@ -327,7 +336,7 @@ }; &pmi8998_gpio { - cam_vio_default: cam-vio-active { + cam_vio_default: cam-vio-active-state { pins = "gpio1"; function = PMIC_GPIO_FUNC_NORMAL; bias-disable; @@ -337,7 +346,7 @@ power-source = <1>; }; - vib_default: vib-en { + vib_default: vib-en-state { pins = "gpio5"; function = PMIC_GPIO_FUNC_NORMAL; bias-disable; @@ -549,8 +558,8 @@ vqmmc-supply = <&vreg_l13a_2p95>; pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; - pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; + pinctrl-0 = <&sdc2_on &sdc2_cd>; + pinctrl-1 = <&sdc2_off &sdc2_cd>; }; &tlmm { @@ -606,6 +615,14 @@ drive-strength = <2>; }; + tof_int: tof-int { + pins = "gpio22"; + function = "gpio"; + bias-pull-up; + drive-strength = <2>; + input-enable; + }; + cam1_vdig_default: cam1-vdig-default { pins = "gpio25"; function = "gpio"; @@ -613,6 +630,20 @@ drive-strength = <2>; }; + usb_extcon_active: usb-extcon-active { + pins = "gpio38"; + function = "gpio"; + bias-disable; + drive-strength = <16>; + }; + + tof_reset: tof-reset { + pins = "gpio27"; + function = "gpio"; + bias-disable; + drive-strength = <2>; + }; + hall_sensor0_default: acc-cover-open { pins = "gpio124"; function = "gpio"; @@ -628,6 +659,14 @@ bias-pull-up; }; + usb_vbus_active: usb-vbus-active { + pins = "gpio128"; + function = "gpio"; + bias-disable; + drive-strength = <2>; + output-low; + }; + ts_vddio_en: ts-vddio-en-default { pins = "gpio133"; function = "gpio"; @@ -658,6 +697,7 @@ &usb3_dwc3 { /* Force to peripheral until we have Type-C hooked up */ dr_mode = "peripheral"; + extcon = <&extcon_usb>; }; &usb3phy { diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index 758c45bbbe78..02d21bff2198 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -838,7 +838,7 @@ }; qfprom: qfprom@784000 { - compatible = "qcom,qfprom"; + compatible = "qcom,msm8998-qfprom", "qcom,qfprom"; reg = <0x00784000 0x621c>; #address-cells = <1>; #size-cells = <1>; @@ -929,7 +929,7 @@ interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "msi"; interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 0 135 IRQ_TYPE_LEVEL_HIGH>, + interrupt-map = <0 0 0 1 &intc 0 0 135 IRQ_TYPE_LEVEL_HIGH>, <0 0 0 2 &intc 0 0 136 IRQ_TYPE_LEVEL_HIGH>, <0 0 0 3 &intc 0 0 138 IRQ_TYPE_LEVEL_HIGH>, <0 0 0 4 &intc 0 0 139 IRQ_TYPE_LEVEL_HIGH>; @@ -1057,85 +1057,58 @@ reg = <0x03400000 0xc00000>; interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; - #gpio-cells = <0x2>; + #gpio-cells = <2>; interrupt-controller; - #interrupt-cells = <0x2>; + #interrupt-cells = <2>; - sdc2_clk_on: sdc2_clk_on { - config { + sdc2_on: sdc2-on { + clk { pins = "sdc2_clk"; - bias-disable; drive-strength = <16>; - }; - }; - - sdc2_clk_off: sdc2_clk_off { - config { - pins = "sdc2_clk"; bias-disable; - drive-strength = <2>; }; - }; - sdc2_cmd_on: sdc2_cmd_on { - config { + cmd { pins = "sdc2_cmd"; - bias-pull-up; drive-strength = <10>; - }; - }; - - sdc2_cmd_off: sdc2_cmd_off { - config { - pins = "sdc2_cmd"; bias-pull-up; - drive-strength = <2>; }; - }; - sdc2_data_on: sdc2_data_on { - config { + data { pins = "sdc2_data"; - bias-pull-up; drive-strength = <10>; + bias-pull-up; }; }; - sdc2_data_off: sdc2_data_off { - config { - pins = "sdc2_data"; - bias-pull-up; + sdc2_off: sdc2-off { + clk { + pins = "sdc2_clk"; drive-strength = <2>; + bias-disable; }; - }; - sdc2_cd_on: sdc2_cd_on { - mux { - pins = "gpio95"; - function = "gpio"; + cmd { + pins = "sdc2_cmd"; + drive-strength = <2>; + bias-pull-up; }; - config { - pins = "gpio95"; - bias-pull-up; + data { + pins = "sdc2_data"; drive-strength = <2>; + bias-pull-up; }; }; - sdc2_cd_off: sdc2_cd_off { - mux { - pins = "gpio95"; - function = "gpio"; - }; - - config { - pins = "gpio95"; - bias-pull-up; - drive-strength = <2>; - }; + sdc2_cd: sdc2-cd { + pins = "gpio95"; + function = "gpio"; + bias-pull-up; + drive-strength = <2>; }; - blsp1_uart3_on: blsp1_uart3_on { + blsp1_uart3_on: blsp1-uart3-on { tx { pins = "gpio45"; function = "blsp_uart3_a"; @@ -1416,7 +1389,7 @@ status = "disabled"; gpu_opp_table: opp-table { - compatible = "operating-points-v2"; + compatible = "operating-points-v2"; opp-710000097 { opp-hz = /bits/ 64 <710000097>; opp-level = <RPM_SMD_LEVEL_TURBO>; @@ -2080,7 +2053,7 @@ <0xc010600 0x128>, <0xc010800 0x200>; #phy-cells = <0>; - #clock-cells = <1>; + #clock-cells = <0>; clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>; clock-names = "pipe0"; clock-output-names = "usb3_phy_pipe_clk_src"; @@ -2102,7 +2075,7 @@ nvmem-cells = <&qusb2_hstx_trim>; }; - sdhc2: sdhci@c0a4900 { + sdhc2: mmc@c0a4900 { compatible = "qcom,sdhci-msm-v4"; reg = <0x0c0a4900 0x314>, <0x0c0a4000 0x800>; reg-names = "hc_mem", "core_mem"; @@ -2415,7 +2388,6 @@ #reset-cells = <1>; #power-domain-cells = <1>; reg = <0xc8c0000 0x40000>; - status = "disabled"; clock-names = "xo", "gpll0", @@ -2450,7 +2422,6 @@ <&mmcc BIMC_SMMU_AXI_CLK>; clock-names = "iface-mm", "iface-smmu", "bus-mm", "bus-smmu"; - status = "disabled"; #global-interrupts = <0>; interrupts = diff --git a/arch/arm64/boot/dts/qcom/pm6350.dtsi b/arch/arm64/boot/dts/qcom/pm6350.dtsi index c5d85064562b..ecf9b9919182 100644 --- a/arch/arm64/boot/dts/qcom/pm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/pm6350.dtsi @@ -36,9 +36,10 @@ }; pm6350_gpios: gpios@c000 { - compatible = "qcom,pm6350-gpio"; + compatible = "qcom,pm6350-gpio", "qcom,spmi-gpio"; reg = <0xc000>; gpio-controller; + gpio-ranges = <&pm6350_gpios 0 0 9>; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; diff --git a/arch/arm64/boot/dts/qcom/pm660.dtsi b/arch/arm64/boot/dts/qcom/pm660.dtsi index c482663aad56..d0eefbb51663 100644 --- a/arch/arm64/boot/dts/qcom/pm660.dtsi +++ b/arch/arm64/boot/dts/qcom/pm660.dtsi @@ -171,7 +171,7 @@ }; pm660_gpios: gpios@c000 { - compatible = "qcom,pm660-gpio"; + compatible = "qcom,pm660-gpio", "qcom,spmi-gpio"; reg = <0xc000>; gpio-controller; gpio-ranges = <&pm660_gpios 0 0 13>; diff --git a/arch/arm64/boot/dts/qcom/pm660l.dtsi b/arch/arm64/boot/dts/qcom/pm660l.dtsi index cfef42353611..c7945470ffee 100644 --- a/arch/arm64/boot/dts/qcom/pm660l.dtsi +++ b/arch/arm64/boot/dts/qcom/pm660l.dtsi @@ -65,9 +65,15 @@ #address-cells = <1>; #size-cells = <0>; + pm660l_lpg: lpg@b100 { + compatible = "qcom,pm660l-lpg"; + + status = "disabled"; + }; + pm660l_wled: leds@d800 { compatible = "qcom,pm660l-wled"; - reg = <0xd800 0xd900>; + reg = <0xd800>, <0xd900>; interrupts = <0x3 0xd8 0x1 IRQ_TYPE_EDGE_RISING>; interrupt-names = "ovp"; label = "backlight"; diff --git a/arch/arm64/boot/dts/qcom/pm8005.dtsi b/arch/arm64/boot/dts/qcom/pm8005.dtsi index 3f97607d8baa..50fb6c753bf8 100644 --- a/arch/arm64/boot/dts/qcom/pm8005.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8005.dtsi @@ -28,5 +28,9 @@ reg = <0x5 SPMI_USID>; #address-cells = <1>; #size-cells = <0>; + + pm8005_regulators: regulators { + compatible = "qcom,pm8005-regulators"; + }; }; }; diff --git a/arch/arm64/boot/dts/qcom/pm8009.dtsi b/arch/arm64/boot/dts/qcom/pm8009.dtsi index b126d7e7e4fb..0c2c424be0ea 100644 --- a/arch/arm64/boot/dts/qcom/pm8009.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8009.dtsi @@ -19,9 +19,10 @@ }; pm8009_gpios: gpio@c000 { - compatible = "qcom,pm8005-gpio"; + compatible = "qcom,pm8005-gpio", "qcom,spmi-gpio"; reg = <0xc000>; gpio-controller; + gpio-ranges = <&pm8009_gpios 0 0 4>; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; diff --git a/arch/arm64/boot/dts/qcom/pm8150.dtsi b/arch/arm64/boot/dts/qcom/pm8150.dtsi index 0df76f7b1cc1..fd8434215924 100644 --- a/arch/arm64/boot/dts/qcom/pm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8150.dtsi @@ -127,9 +127,10 @@ }; pm8150_gpios: gpio@c000 { - compatible = "qcom,pm8150-gpio"; + compatible = "qcom,pm8150-gpio", "qcom,spmi-gpio"; reg = <0xc000>; gpio-controller; + gpio-ranges = <&pm8150_gpios 0 0 10>; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; diff --git a/arch/arm64/boot/dts/qcom/pm8150b.dtsi b/arch/arm64/boot/dts/qcom/pm8150b.dtsi index 058cc5107c75..5d1ec3a6cc3c 100644 --- a/arch/arm64/boot/dts/qcom/pm8150b.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8150b.dtsi @@ -112,9 +112,10 @@ }; pm8150b_gpios: gpio@c000 { - compatible = "qcom,pm8150b-gpio"; + compatible = "qcom,pm8150b-gpio", "qcom,spmi-gpio"; reg = <0xc000>; gpio-controller; + gpio-ranges = <&pm8150b_gpios 0 0 12>; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; @@ -126,5 +127,15 @@ reg = <0x3 SPMI_USID>; #address-cells = <1>; #size-cells = <0>; + + pm8150b_lpg: lpg { + compatible = "qcom,pm8150b-lpg"; + + #address-cells = <1>; + #size-cells = <0>; + #pwm-cells = <2>; + + status = "disabled"; + }; }; }; diff --git a/arch/arm64/boot/dts/qcom/pm8150l.dtsi b/arch/arm64/boot/dts/qcom/pm8150l.dtsi index 52f094a2b713..c62d023b39a2 100644 --- a/arch/arm64/boot/dts/qcom/pm8150l.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8150l.dtsi @@ -100,9 +100,10 @@ }; pm8150l_gpios: gpio@c000 { - compatible = "qcom,pm8150l-gpio"; + compatible = "qcom,pm8150l-gpio", "qcom,spmi-gpio"; reg = <0xc000>; gpio-controller; + gpio-ranges = <&pm8150l_gpios 0 0 12>; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; @@ -114,5 +115,16 @@ reg = <0x5 SPMI_USID>; #address-cells = <1>; #size-cells = <0>; + + pm8150l_lpg: lpg { + compatible = "qcom,pm8150l-lpg"; + + #address-cells = <1>; + #size-cells = <0>; + #pwm-cells = <2>; + + status = "disabled"; + }; + }; }; diff --git a/arch/arm64/boot/dts/qcom/pm8350.dtsi b/arch/arm64/boot/dts/qcom/pm8350.dtsi index b10f33afa5e3..2dfeb99300d7 100644 --- a/arch/arm64/boot/dts/qcom/pm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8350.dtsi @@ -45,9 +45,10 @@ }; pm8350_gpios: gpio@8800 { - compatible = "qcom,pm8350-gpio"; + compatible = "qcom,pm8350-gpio", "qcom,spmi-gpio"; reg = <0x8800>; gpio-controller; + gpio-ranges = <&pm8350_gpios 0 0 10>; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; diff --git a/arch/arm64/boot/dts/qcom/pm8350b.dtsi b/arch/arm64/boot/dts/qcom/pm8350b.dtsi index f1d1d4c8edf8..f1c7bd9d079c 100644 --- a/arch/arm64/boot/dts/qcom/pm8350b.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8350b.dtsi @@ -45,9 +45,10 @@ }; pm8350b_gpios: gpio@8800 { - compatible = "qcom,pm8350b-gpio"; + compatible = "qcom,pm8350b-gpio", "qcom,spmi-gpio"; reg = <0x8800>; gpio-controller; + gpio-ranges = <&pm8350b_gpios 0 0 8>; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; diff --git a/arch/arm64/boot/dts/qcom/pm8916.dtsi b/arch/arm64/boot/dts/qcom/pm8916.dtsi index d58902432812..606c2a6d1f0f 100644 --- a/arch/arm64/boot/dts/qcom/pm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8916.dtsi @@ -108,14 +108,13 @@ }; pm8916_gpios: gpios@c000 { - compatible = "qcom,pm8916-gpio"; + compatible = "qcom,pm8916-gpio", "qcom,spmi-gpio"; reg = <0xc000>; gpio-controller; + gpio-ranges = <&pm8916_gpios 0 0 4>; #gpio-cells = <2>; - interrupts = <0 0xc0 0 IRQ_TYPE_NONE>, - <0 0xc1 0 IRQ_TYPE_NONE>, - <0 0xc2 0 IRQ_TYPE_NONE>, - <0 0xc3 0 IRQ_TYPE_NONE>; + interrupt-controller; + #interrupt-cells = <2>; }; }; @@ -125,6 +124,14 @@ #address-cells = <1>; #size-cells = <0>; + pm8916_pwm: pwm { + compatible = "qcom,pm8916-pwm"; + + #pwm-cells = <2>; + + status = "disabled"; + }; + pm8916_vib: vibrator@c000 { compatible = "qcom,pm8916-vib"; reg = <0xc000>; diff --git a/arch/arm64/boot/dts/qcom/pm8994.dtsi b/arch/arm64/boot/dts/qcom/pm8994.dtsi index 5ab46117d737..ab342397fcd8 100644 --- a/arch/arm64/boot/dts/qcom/pm8994.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8994.dtsi @@ -135,6 +135,16 @@ #address-cells = <1>; #size-cells = <0>; + pm8994_lpg: lpg { + compatible = "qcom,pm8994-lpg"; + + #address-cells = <1>; + #size-cells = <0>; + #pwm-cells = <2>; + + status = "disabled"; + }; + pm8994_spmi_regulators: regulators { compatible = "qcom,pm8994-regulators"; }; diff --git a/arch/arm64/boot/dts/qcom/pmi8994.dtsi b/arch/arm64/boot/dts/qcom/pmi8994.dtsi index 6e7c252568e6..84c44912ec93 100644 --- a/arch/arm64/boot/dts/qcom/pmi8994.dtsi +++ b/arch/arm64/boot/dts/qcom/pmi8994.dtsi @@ -19,6 +19,16 @@ interrupt-controller; #interrupt-cells = <2>; }; + + pmi8994_mpps: mpps@a000 { + compatible = "qcom,pmi8994-mpp"; + reg = <0xa000>; + gpio-controller; + gpio-ranges = <&pmi8994_mpps 0 0 4>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; }; pmic@3 { @@ -27,6 +37,16 @@ #address-cells = <1>; #size-cells = <0>; + pmi8994_lpg: lpg { + compatible = "qcom,pmi8994-lpg"; + + #address-cells = <1>; + #size-cells = <0>; + #pwm-cells = <2>; + + status = "disabled"; + }; + pmi8994_spmi_regulators: regulators { compatible = "qcom,pmi8994-regulators"; #address-cells = <1>; @@ -35,7 +55,7 @@ pmi8994_wled: wled@d800 { compatible = "qcom,pmi8994-wled"; - reg = <0xd800 0xd900>; + reg = <0xd800>, <0xd900>; interrupts = <3 0xd8 0x02 IRQ_TYPE_EDGE_RISING>; interrupt-names = "short"; qcom,cabc; diff --git a/arch/arm64/boot/dts/qcom/pmi8998.dtsi b/arch/arm64/boot/dts/qcom/pmi8998.dtsi index 0fef5f113f05..6d3d212560c1 100644 --- a/arch/arm64/boot/dts/qcom/pmi8998.dtsi +++ b/arch/arm64/boot/dts/qcom/pmi8998.dtsi @@ -42,9 +42,19 @@ }; }; + pmi8998_lpg: lpg { + compatible = "qcom,pmi8998-lpg"; + + #address-cells = <1>; + #size-cells = <0>; + #pwm-cells = <2>; + + status = "disabled"; + }; + pmi8998_wled: leds@d800 { compatible = "qcom,pmi8998-wled"; - reg = <0xd800 0xd900>; + reg = <0xd800>, <0xd900>; interrupts = <0x3 0xd8 0x1 IRQ_TYPE_EDGE_RISING>, <0x3 0xd8 0x2 IRQ_TYPE_EDGE_RISING>; interrupt-names = "ovp", "short"; @@ -52,6 +62,5 @@ status = "disabled"; }; - }; }; diff --git a/arch/arm64/boot/dts/qcom/pmm8155au_1.dtsi b/arch/arm64/boot/dts/qcom/pmm8155au_1.dtsi index 7072e5a2e73f..68e9122363ae 100644 --- a/arch/arm64/boot/dts/qcom/pmm8155au_1.dtsi +++ b/arch/arm64/boot/dts/qcom/pmm8155au_1.dtsi @@ -116,7 +116,7 @@ }; pmm8155au_1_gpios: gpio@c000 { - compatible = "qcom,pmm8155au-gpio"; + compatible = "qcom,pmm8155au-gpio", "qcom,spmi-gpio"; reg = <0xc000>; gpio-controller; #gpio-cells = <2>; diff --git a/arch/arm64/boot/dts/qcom/pmm8155au_2.dtsi b/arch/arm64/boot/dts/qcom/pmm8155au_2.dtsi index 72075964fbb9..c307fc662511 100644 --- a/arch/arm64/boot/dts/qcom/pmm8155au_2.dtsi +++ b/arch/arm64/boot/dts/qcom/pmm8155au_2.dtsi @@ -89,7 +89,7 @@ }; pmm8155au_2_gpios: gpio@c000 { - compatible = "qcom,pmm8155au-gpio"; + compatible = "qcom,pmm8155au-gpio", "qcom,spmi-gpio"; reg = <0xc000>; gpio-controller; #gpio-cells = <2>; diff --git a/arch/arm64/boot/dts/qcom/pmr735b.dtsi b/arch/arm64/boot/dts/qcom/pmr735b.dtsi index 604324188603..ec24c4478005 100644 --- a/arch/arm64/boot/dts/qcom/pmr735b.dtsi +++ b/arch/arm64/boot/dts/qcom/pmr735b.dtsi @@ -45,9 +45,10 @@ }; pmr735b_gpios: gpio@8800 { - compatible = "qcom,pmr735b-gpio"; + compatible = "qcom,pmr735b-gpio", "qcom,spmi-gpio"; reg = <0x8800>; gpio-controller; + gpio-ranges = <&pmr735b_gpios 0 0 4>; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; diff --git a/arch/arm64/boot/dts/qcom/pms405.dtsi b/arch/arm64/boot/dts/qcom/pms405.dtsi index 98d173a377d5..634b0681d04c 100644 --- a/arch/arm64/boot/dts/qcom/pms405.dtsi +++ b/arch/arm64/boot/dts/qcom/pms405.dtsi @@ -38,22 +38,13 @@ #size-cells = <0>; pms405_gpios: gpio@c000 { - compatible = "qcom,pms405-gpio"; + compatible = "qcom,pms405-gpio", "qcom,spmi-gpio"; reg = <0xc000>; gpio-controller; + gpio-ranges = <&pms405_gpios 0 0 12>; #gpio-cells = <2>; - interrupts = <0 0xc0 0 IRQ_TYPE_NONE>, - <0 0xc1 0 IRQ_TYPE_NONE>, - <0 0xc2 0 IRQ_TYPE_NONE>, - <0 0xc3 0 IRQ_TYPE_NONE>, - <0 0xc4 0 IRQ_TYPE_NONE>, - <0 0xc5 0 IRQ_TYPE_NONE>, - <0 0xc6 0 IRQ_TYPE_NONE>, - <0 0xc7 0 IRQ_TYPE_NONE>, - <0 0xc8 0 IRQ_TYPE_NONE>, - <0 0xc9 0 IRQ_TYPE_NONE>, - <0 0xca 0 IRQ_TYPE_NONE>, - <0 0xcb 0 IRQ_TYPE_NONE>; + interrupt-controller; + #interrupt-cells = <2>; }; pon@800 { diff --git a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi index 2f3104a84417..1721ebe5759b 100644 --- a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi @@ -304,7 +304,7 @@ }; &pms405_gpios { - usb_vbus_boost_pin: usb-vbus-boost-pin { + usb_vbus_boost_pin: usb-vbus-boost-state { pinconf { pins = "gpio3"; function = PMIC_GPIO_FUNC_NORMAL; @@ -312,7 +312,7 @@ power-source = <1>; }; }; - usb3_vbus_pin: usb3-vbus-pin { + usb3_vbus_pin: usb3-vbus-state { pinconf { pins = "gpio12"; function = PMIC_GPIO_FUNC_NORMAL; diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index d912166b7552..9ab990061522 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -366,7 +366,7 @@ }; qfprom: qfprom@a4000 { - compatible = "qcom,qfprom"; + compatible = "qcom,qcs404-qfprom", "qcom,qfprom"; reg = <0x000a4000 0x1000>; #address-cells = <1>; #size-cells = <1>; @@ -548,7 +548,7 @@ compatible = "snps,dwc3"; reg = <0x07580000 0xcd00>; interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; - phys = <&usb2_phy_sec>, <&usb3_phy>; + phys = <&usb2_phy_prim>, <&usb3_phy>; phy-names = "usb2-phy", "usb3-phy"; snps,has-lpm-erratum; snps,hird-threshold = /bits/ 8 <0x10>; @@ -577,7 +577,7 @@ compatible = "snps,dwc3"; reg = <0x078c0000 0xcc00>; interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; - phys = <&usb2_phy_prim>; + phys = <&usb2_phy_sec>; phy-names = "usb2-phy"; snps,has-lpm-erratum; snps,hird-threshold = /bits/ 8 <0x10>; @@ -669,8 +669,25 @@ }; blsp1_spi1_default: blsp1-spi1-default { - pins = "gpio22", "gpio23", "gpio24", "gpio25"; - function = "blsp_spi1"; + mosi { + pins = "gpio22"; + function = "blsp_spi_mosi_a1"; + }; + + miso { + pins = "gpio23"; + function = "blsp_spi_miso_a1"; + }; + + cs_n { + pins = "gpio24"; + function = "blsp_spi_cs_n_a1"; + }; + + clk { + pins = "gpio25"; + function = "blsp_spi_clk_a1"; + }; }; blsp1_spi2_default: blsp1-spi2-default { @@ -789,7 +806,7 @@ status = "disabled"; }; - sdcc1: sdcc@7804000 { + sdcc1: mmc@7804000 { compatible = "qcom,qcs404-sdhci", "qcom,sdhci-msm-v5"; reg = <0x07804000 0x1000>, <0x7805000 0x1000>; reg-names = "hc", "cqhci"; @@ -798,10 +815,10 @@ <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "hc_irq", "pwr_irq"; - clocks = <&gcc GCC_SDCC1_APPS_CLK>, - <&gcc GCC_SDCC1_AHB_CLK>, + clocks = <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, <&xo_board>; - clock-names = "core", "iface", "xo"; + clock-names = "iface", "core", "xo"; status = "disabled"; }; @@ -1102,8 +1119,8 @@ status = "disabled"; }; - imem@8600000 { - compatible = "simple-mfd"; + sram@8600000 { + compatible = "qcom,qcs404-imem", "syscon", "simple-mfd"; reg = <0x08600000 0x1000>; #address-cells = <1>; diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts index 0e63f707b911..bf8077a1cf9a 100644 --- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts +++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts @@ -5,6 +5,7 @@ /dts-v1/; +#include <dt-bindings/leds/common.h> #include <dt-bindings/regulator/qcom,rpmh-regulator.h> #include <dt-bindings/sound/qcom,q6afe.h> #include <dt-bindings/sound/qcom,q6asm.h> @@ -57,27 +58,32 @@ leds { compatible = "gpio-leds"; - user4 { + led-user4 { label = "green:user4"; + function = LED_FUNCTION_INDICATOR; + color = <LED_COLOR_ID_GREEN>; gpios = <&pm8150_gpios 10 GPIO_ACTIVE_HIGH>; linux,default-trigger = "panic-indicator"; default-state = "off"; }; - wlan { + led-wlan { label = "yellow:wlan"; + function = LED_FUNCTION_WLAN; + color = <LED_COLOR_ID_YELLOW>; gpios = <&pm8150_gpios 9 GPIO_ACTIVE_HIGH>; linux,default-trigger = "phy0tx"; default-state = "off"; }; - bt { + led-bt { label = "blue:bt"; + function = LED_FUNCTION_BLUETOOTH; + color = <LED_COLOR_ID_BLUE>; gpios = <&pm8150_gpios 7 GPIO_ACTIVE_HIGH>; linux,default-trigger = "bluetooth-power"; default-state = "off"; }; - }; lt9611_1v2: lt9611-vdd12-regulator { @@ -796,7 +802,7 @@ "NC", "PM3003A_MODE"; - lt9611_rst_pin: lt9611-rst-pin { + lt9611_rst_pin: lt9611-rst-state { pins = "gpio5"; function = "normal"; @@ -806,6 +812,38 @@ }; }; +&pm8150l_lpg { + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + + led@1 { + reg = <1>; + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_HEARTBEAT; + function-enumerator = <3>; + + linux,default-trigger = "heartbeat"; + default-state = "on"; + }; + + led@2 { + reg = <2>; + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_INDICATOR; + function-enumerator = <2>; + default-state = "on"; + }; + + led@3 { + reg = <3>; + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_INDICATOR; + function-enumerator = <1>; + }; +}; + &pon_pwrkey { status = "okay"; }; @@ -830,7 +868,7 @@ &q6afedai { qi2s@16 { - reg = <16>; + reg = <PRIMARY_MI2S_RX>; qcom,sd-lines = <0 1 2 3>; }; }; @@ -838,7 +876,7 @@ /* TERT I2S Uses 1 I2S SD Lines for audio on LT9611 HDMI Bridge */ &q6afedai { qi2s@20 { - reg = <20>; + reg = <TERTIARY_MI2S_RX>; qcom,sd-lines = <0>; }; }; @@ -915,7 +953,7 @@ }; codec { - sound-dai = <<9611_codec 0>; + sound-dai = <<9611_codec 0>; }; }; diff --git a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts new file mode 100644 index 000000000000..9398f0349944 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts @@ -0,0 +1,389 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2022, Linaro Limited + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/regulator/qcom,rpmh-regulator.h> +#include <dt-bindings/spmi/spmi.h> + +#include "sa8540p.dtsi" + +/ { + model = "Qualcomm SA8295P ADP"; + compatible = "qcom,sa8295p-adp", "qcom,sa8540p"; + + aliases { + serial0 = &qup2_uart17; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&apps_rsc { + pmm8540-a-regulators { + compatible = "qcom,pm8150-rpmh-regulators"; + qcom,pmic-id = "a"; + + vreg_l3a: ldo3 { + regulator-name = "vreg_l3a"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1208000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + }; + + vreg_l5a: ldo5 { + regulator-name = "vreg_l5a"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + }; + + vreg_l7a: ldo7 { + regulator-name = "vreg_l7a"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + }; + + vreg_l13a: ldo13 { + regulator-name = "vreg_l13a"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + }; + }; + + pmm8540-c-regulators { + compatible = "qcom,pm8150-rpmh-regulators"; + qcom,pmic-id = "c"; + + vreg_l1c: ldo1 { + regulator-name = "vreg_l1c"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + }; + + vreg_l2c: ldo2 { + regulator-name = "vreg_l2c"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + }; + + vreg_l3c: ldo3 { + regulator-name = "vreg_l3c"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + }; + + vreg_l4c: ldo4 { + regulator-name = "vreg_l4c"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1208000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + }; + + vreg_l6c: ldo6 { + regulator-name = "vreg_l6c"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + }; + + vreg_l7c: ldo7 { + regulator-name = "vreg_l7c"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + }; + + vreg_l10c: ldo10 { + regulator-name = "vreg_l10c"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <2504000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + }; + + vreg_l17c: ldo17 { + regulator-name = "vreg_l17c"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <2504000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + }; + }; + + pmm8540-g-regulators { + compatible = "qcom,pm8150-rpmh-regulators"; + qcom,pmic-id = "g"; + + vreg_l3g: ldo3 { + regulator-name = "vreg_l3g"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + }; + + vreg_l7g: ldo7 { + regulator-name = "vreg_l7g"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + }; + + vreg_l8g: ldo8 { + regulator-name = "vreg_l8g"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + }; + }; +}; + +&qup2 { + status = "okay"; +}; + +&qup2_uart17 { + compatible = "qcom,geni-debug-uart"; + status = "okay"; +}; + +&remoteproc_adsp { + firmware-name = "qcom/sa8540p/adsp.mbn"; + status = "okay"; +}; + +&remoteproc_nsp0 { + firmware-name = "qcom/sa8540p/cdsp.mbn"; + status = "okay"; +}; + +&remoteproc_nsp1 { + firmware-name = "qcom/sa8540p/cdsp1.mbn"; + status = "okay"; +}; + +&spmi_bus { + pm8450a: pmic@0 { + compatible = "qcom,pm8150", "qcom,spmi-pmic"; + reg = <0x0 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm8450a_gpios: gpio@c000 { + compatible = "qcom,pm8150-gpio"; + reg = <0xc000>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + pm8450c: pmic@4 { + compatible = "qcom,pm8150", "qcom,spmi-pmic"; + reg = <0x4 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm8450c_gpios: gpio@c000 { + compatible = "qcom,pm8150-gpio"; + reg = <0xc000>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + pm8450e: pmic@8 { + compatible = "qcom,pm8150", "qcom,spmi-pmic"; + reg = <0x8 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm8450e_gpios: gpio@c000 { + compatible = "qcom,pm8150-gpio"; + reg = <0xc000>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + pm8450g: pmic@c { + compatible = "qcom,pm8150", "qcom,spmi-pmic"; + reg = <0xc SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm8450g_gpios: gpio@c000 { + compatible = "qcom,pm8150-gpio"; + reg = <0xc000>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +}; + +&ufs_mem_hc { + reset-gpios = <&tlmm 228 GPIO_ACTIVE_LOW>; + + vcc-supply = <&vreg_l17c>; + vcc-max-microamp = <800000>; + vccq-supply = <&vreg_l6c>; + vccq-max-microamp = <900000>; + + status = "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply = <&vreg_l8g>; + vdda-pll-supply = <&vreg_l3g>; + + status = "okay"; +}; + +&ufs_card_hc { + reset-gpios = <&tlmm 229 GPIO_ACTIVE_LOW>; + + vcc-supply = <&vreg_l10c>; + vcc-max-microamp = <800000>; + vccq-supply = <&vreg_l3c>; + vccq-max-microamp = <900000>; + + status = "okay"; +}; + +&ufs_card_phy { + vdda-phy-supply = <&vreg_l8g>; + vdda-pll-supply = <&vreg_l3g>; + + status = "okay"; +}; + +&usb_0 { + status = "okay"; +}; + +&usb_0_dwc3 { + /* TODO: Define USB-C connector properly */ + dr_mode = "peripheral"; +}; + +&usb_0_hsphy { + vdda-pll-supply = <&vreg_l5a>; + vdda18-supply = <&vreg_l7a>; + vdda33-supply = <&vreg_l13a>; + + status = "okay"; +}; + +&usb_0_qmpphy { + vdda-phy-supply = <&vreg_l3a>; + vdda-pll-supply = <&vreg_l5a>; + + status = "okay"; +}; + +&usb_1 { + status = "okay"; +}; + +&usb_1_dwc3 { + /* TODO: Define USB-C connector properly */ + dr_mode = "host"; +}; + +&usb_1_hsphy { + vdda-pll-supply = <&vreg_l1c>; + vdda18-supply = <&vreg_l7c>; + vdda33-supply = <&vreg_l2c>; + + status = "okay"; +}; + +&usb_1_qmpphy { + vdda-phy-supply = <&vreg_l4c>; + vdda-pll-supply = <&vreg_l1c>; + + status = "okay"; +}; + +&usb_2_hsphy0 { + vdda-pll-supply = <&vreg_l5a>; + vdda18-supply = <&vreg_l7g>; + vdda33-supply = <&vreg_l13a>; + + status = "okay"; +}; + +&usb_2_hsphy1 { + vdda-pll-supply = <&vreg_l5a>; + vdda18-supply = <&vreg_l7g>; + vdda33-supply = <&vreg_l13a>; + + status = "okay"; +}; + +&usb_2_hsphy2 { + vdda-pll-supply = <&vreg_l5a>; + vdda18-supply = <&vreg_l7g>; + vdda33-supply = <&vreg_l13a>; + + status = "okay"; +}; + +&usb_2_hsphy3 { + vdda-pll-supply = <&vreg_l5a>; + vdda18-supply = <&vreg_l7g>; + vdda33-supply = <&vreg_l13a>; + + status = "okay"; +}; + +&usb_2_qmpphy0 { + vdda-phy-supply = <&vreg_l3a>; + vdda-pll-supply = <&vreg_l5a>; + + status = "okay"; +}; + +&usb_2_qmpphy1 { + vdda-phy-supply = <&vreg_l3a>; + vdda-pll-supply = <&vreg_l5a>; + + status = "okay"; +}; + +&xo_board_clk { + clock-frequency = <38400000>; +}; + +/* PINCTRL */ diff --git a/arch/arm64/boot/dts/qcom/sa8540p.dtsi b/arch/arm64/boot/dts/qcom/sa8540p.dtsi new file mode 100644 index 000000000000..8ea2886fbab2 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sa8540p.dtsi @@ -0,0 +1,133 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2022, Linaro Limited + */ + +#include "sc8280xp.dtsi" + +/delete-node/ &cpu0_opp_table; +/delete-node/ &cpu4_opp_table; + +/ { + cpu0_opp_table: cpu0-opp-table { + compatible = "operating-points-v2"; + opp-shared; + + opp-403200000 { + opp-hz = /bits/ 64 <403200000>; + }; + opp-499200000 { + opp-hz = /bits/ 64 <499200000>; + }; + opp-595200000 { + opp-hz = /bits/ 64 <595200000>; + }; + opp-710400000 { + opp-hz = /bits/ 64 <710400000>; + }; + opp-806400000 { + opp-hz = /bits/ 64 <806400000>; + }; + opp-902400000 { + opp-hz = /bits/ 64 <902400000>; + }; + opp-1017600000 { + opp-hz = /bits/ 64 <1017600000>; + }; + opp-1113600000 { + opp-hz = /bits/ 64 <1113600000>; + }; + opp-1209600000 { + opp-hz = /bits/ 64 <1209600000>; + }; + opp-1324800000 { + opp-hz = /bits/ 64 <1324800000>; + }; + opp-1440000000 { + opp-hz = /bits/ 64 <1440000000>; + }; + opp-1555200000 { + opp-hz = /bits/ 64 <1555200000>; + }; + opp-1670400000 { + opp-hz = /bits/ 64 <1670400000>; + }; + opp-1785600000 { + opp-hz = /bits/ 64 <1785600000>; + }; + opp-1881600000 { + opp-hz = /bits/ 64 <1881600000>; + }; + opp-2016000000 { + opp-hz = /bits/ 64 <2016000000>; + }; + opp-2131200000 { + opp-hz = /bits/ 64 <2131200000>; + }; + opp-2246400000 { + opp-hz = /bits/ 64 <2246400000>; + }; + }; + + cpu4_opp_table: cpu4-opp-table { + compatible = "operating-points-v2"; + opp-shared; + + opp-825600000 { + opp-hz = /bits/ 64 <825600000>; + }; + opp-940800000 { + opp-hz = /bits/ 64 <940800000>; + }; + opp-1056000000 { + opp-hz = /bits/ 64 <1056000000>; + }; + opp-1171200000 { + opp-hz = /bits/ 64 <1171200000>; + }; + opp-1286400000 { + opp-hz = /bits/ 64 <1286400000>; + }; + opp-1401600000 { + opp-hz = /bits/ 64 <1401600000>; + }; + opp-1516800000 { + opp-hz = /bits/ 64 <1516800000>; + }; + opp-1632000000 { + opp-hz = /bits/ 64 <1632000000>; + }; + opp-1747200000 { + opp-hz = /bits/ 64 <1747200000>; + }; + opp-1862400000 { + opp-hz = /bits/ 64 <1862400000>; + }; + opp-1977600000 { + opp-hz = /bits/ 64 <1977600000>; + }; + opp-2073600000 { + opp-hz = /bits/ 64 <2073600000>; + }; + opp-2169600000 { + opp-hz = /bits/ 64 <2169600000>; + }; + opp-2284800000 { + opp-hz = /bits/ 64 <2284800000>; + }; + opp-2380800000 { + opp-hz = /bits/ 64 <2380800000>; + }; + opp-2496000000 { + opp-hz = /bits/ 64 <2496000000>; + }; + opp-2592000000 { + opp-hz = /bits/ 64 <2592000000>; + }; + }; +}; + +&rpmhpd { + compatible = "qcom,sa8540p-rpmhpd"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-idp.dts b/arch/arm64/boot/dts/qcom/sc7180-idp.dts index acdb36f4479f..9dee131b1e24 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-idp.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-idp.dts @@ -330,6 +330,7 @@ &dsi_phy { status = "okay"; + vdds-supply = <&vreg_l4a_0p8>; }; &mdp { @@ -389,7 +390,7 @@ pinctrl-names = "default","sleep"; pinctrl-0 = <&sdc2_on>; pinctrl-1 = <&sdc2_off>; - vmmc-supply = <&vreg_l9c_2p9>; + vmmc-supply = <&vreg_l9c_2p9>; vqmmc-supply = <&vreg_l6c_2p9>; cd-gpios = <&tlmm 69 GPIO_ACTIVE_LOW>; @@ -467,7 +468,7 @@ /* PINCTRL - additions to nodes defined in sc7180.dtsi */ &pm6150l_gpio { - disp_pins: disp-pins { + disp_pins: disp-state { pinconf { pins = "gpio3"; function = PMIC_GPIO_FUNC_FUNC1; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi index 8ac1f1e61006..7ee407f7b6bb 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi @@ -81,6 +81,10 @@ }; &cros_ec { + keyboard-controller { + compatible = "google,cros-ec-keyb-switches"; + }; + cros_ec_proximity: proximity { compatible = "google,cros-ec-mkbp-proximity"; label = "proximity-wifi"; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi index d1e2df5164ea..1bd6c7dcd9e9 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi @@ -114,6 +114,12 @@ ap_ts_pen_1v8: &i2c4 { status = "okay"; }; +&cros_ec { + keyboard-controller { + compatible = "google,cros-ec-keyb-switches"; + }; +}; + &panel { compatible = "samsung,atna33xc20"; enable-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown-r0.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown-r0.dts new file mode 100644 index 000000000000..1a62e8d435ab --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown-r0.dts @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Kingoftown board device tree source + * + * Copyright 2021 Google LLC. + */ + +/dts-v1/; + +#include "sc7180-trogdor.dtsi" +#include "sc7180-trogdor-ti-sn65dsi86.dtsi" +#include "sc7180-trogdor-kingoftown.dtsi" + +/ { + model = "Google Kingoftown (rev0)"; + compatible = "google,kingoftown-rev0", "qcom,sc7180"; +}; + +/* + * In rev1+, the enable pin of pp3300_fp_tp will be tied to pp1800_l10a + * power rail instead, since kingoftown does not have FP. + */ +&pp3300_fp_tp { + gpio = <&tlmm 74 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&en_fp_rails>; +}; + +&tlmm { + en_fp_rails: en-fp-rails { + pinmux { + pins = "gpio74"; + function = "gpio"; + }; + + pinconf { + pins = "gpio74"; + drive-strength = <2>; + bias-disable; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown-r1.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown-r1.dts new file mode 100644 index 000000000000..e0752ba7df11 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown-r1.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Kingoftown board device tree source + * + * Copyright 2021 Google LLC. + */ + +/dts-v1/; + +#include "sc7180-trogdor.dtsi" +#include "sc7180-trogdor-parade-ps8640.dtsi" +#include "sc7180-trogdor-kingoftown.dtsi" + +/ { + model = "Google Kingoftown (rev1+)"; + compatible = "google,kingoftown", "qcom,sc7180"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown.dtsi new file mode 100644 index 000000000000..74f0e07ea5cf --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown.dtsi @@ -0,0 +1,225 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Kingoftown board device tree source + * + * Copyright 2021 Google LLC. + */ + +/* This file must be included after sc7180-trogdor.dtsi */ +#include <arm/cros-ec-keyboard.dtsi> +#include "sc7180-trogdor-lte-sku.dtsi" + +&alc5682 { + compatible = "realtek,rt5682s"; + realtek,dmic1-clk-pin = <2>; + realtek,dmic-clk-rate-hz = <2048000>; +}; + +&ap_tp_i2c { + status = "okay"; +}; + +ap_ts_pen_1v8: &i2c4 { + status = "okay"; + clock-frequency = <400000>; + + ap_ts: touchscreen@10 { + compatible = "elan,ekth3500"; + reg = <0x10>; + pinctrl-names = "default"; + pinctrl-0 = <&ts_int_l>, <&ts_reset_l>; + + interrupt-parent = <&tlmm>; + interrupts = <9 IRQ_TYPE_LEVEL_LOW>; + + vcc33-supply = <&pp3300_ts>; + + reset-gpios = <&tlmm 8 GPIO_ACTIVE_LOW>; + }; +}; + +&keyboard_controller { + function-row-physmap = < + MATRIX_KEY(0x00, 0x02, 0) /* T1 */ + MATRIX_KEY(0x03, 0x02, 0) /* T2 */ + MATRIX_KEY(0x02, 0x02, 0) /* T3 */ + MATRIX_KEY(0x01, 0x02, 0) /* T4 */ + MATRIX_KEY(0x03, 0x04, 0) /* T5 */ + MATRIX_KEY(0x02, 0x04, 0) /* T6 */ + MATRIX_KEY(0x01, 0x04, 0) /* T7 */ + MATRIX_KEY(0x02, 0x09, 0) /* T8 */ + MATRIX_KEY(0x01, 0x09, 0) /* T9 */ + MATRIX_KEY(0x00, 0x04, 0) /* T10 */ + >; + linux,keymap = < + MATRIX_KEY(0x00, 0x02, KEY_BACK) + MATRIX_KEY(0x03, 0x02, KEY_REFRESH) + MATRIX_KEY(0x02, 0x02, KEY_ZOOM) + MATRIX_KEY(0x01, 0x02, KEY_SCALE) + MATRIX_KEY(0x03, 0x04, KEY_SYSRQ) + MATRIX_KEY(0x02, 0x04, KEY_BRIGHTNESSDOWN) + MATRIX_KEY(0x01, 0x04, KEY_BRIGHTNESSUP) + MATRIX_KEY(0x02, 0x09, KEY_MUTE) + MATRIX_KEY(0x01, 0x09, KEY_VOLUMEDOWN) + MATRIX_KEY(0x00, 0x04, KEY_VOLUMEUP) + + CROS_STD_MAIN_KEYMAP + >; +}; + +&panel { + compatible = "edp-panel"; +}; + +&pp3300_dx_edp { + gpio = <&tlmm 67 GPIO_ACTIVE_HIGH>; +}; + +&sound { + compatible = "google,sc7180-trogdor"; + model = "sc7180-rt5682s-max98357a-1mic"; +}; + +&wifi { + qcom,ath10k-calibration-variant = "GO_KINGOFTOWN"; +}; + +/* PINCTRL - modifications to sc7180-trogdor.dtsi */ + +&en_pp3300_dx_edp { + pinmux { + pins = "gpio67"; + }; + + pinconf { + pins = "gpio67"; + }; +}; + +/* PINCTRL - board-specific pinctrl */ + +&tlmm { + gpio-line-names = "TP_INT_L", /* 0 */ + "AP_RAM_ID0", + "AP_SKU_ID2", + "AP_RAM_ID1", + "", + "AP_RAM_ID2", + "AP_TP_I2C_SDA", + "AP_TP_I2C_SCL", + "TS_RESET_L", + "TS_INT_L", + "", /* 10 */ + "EDP_BRIJ_IRQ", + "AP_EDP_BKLTEN", + "", + "", + "EDP_BRIJ_I2C_SDA", + "EDP_BRIJ_I2C_SCL", + "HUB_RST_L", + "", + "", + "", /* 20 */ + "", + "", + "AMP_EN", + "", + "", + "", + "", + "HP_IRQ", + "", + "", /* 30 */ + "AP_BRD_ID2", + "BRIJ_SUSPEND", + "AP_BRD_ID0", + "AP_H1_SPI_MISO", + "AP_H1_SPI_MOSI", + "AP_H1_SPI_CLK", + "AP_H1_SPI_CS_L", + "BT_UART_CTS", + "BT_UART_RTS", + "BT_UART_TXD", /* 40 */ + "BT_UART_RXD", + "H1_AP_INT_ODL", + "", + "UART_AP_TX_DBG_RX", + "UART_DBG_TX_AP_RX", + "HP_I2C_SDA", + "HP_I2C_SCL", + "FORCED_USB_BOOT", + "AMP_BCLK", + "AMP_LRCLK", /* 50 */ + "AMP_DIN", + "", + "HP_BCLK", + "HP_LRCLK", + "HP_DOUT", + "HP_DIN", + "HP_MCLK", + "AP_SKU_ID0", + "AP_EC_SPI_MISO", + "AP_EC_SPI_MOSI", /* 60 */ + "AP_EC_SPI_CLK", + "AP_EC_SPI_CS_L", + "AP_SPI_CLK", + "AP_SPI_MOSI", + "AP_SPI_MISO", + /* + * AP_FLASH_WP_L is crossystem ABI. Schematics + * call it BIOS_FLASH_WP_L. + */ + "AP_FLASH_WP_L", + "EN_PP3300_DX_EDP", + "AP_SPI_CS0_L", + "", + "", /* 70 */ + "", + "", + "", + "EN_FP_RAILS", + "UIM2_DATA", + "UIM2_CLK", + "UIM2_RST", + "UIM2_PRESENT_L", + "UIM1_DATA", + "UIM1_CLK", /* 80 */ + "UIM1_RST", + "", + "CODEC_PWR_EN", + "HUB_EN", + "", + "", + "", + "", + "", + "AP_SKU_ID1", /* 90 */ + "AP_RST_REQ", + "", + "AP_BRD_ID1", + "AP_EC_INT_L", + "", + "", + "", + "", + "", + "", /* 100 */ + "", + "", + "", + "EDP_BRIJ_EN", + "", + "", + "", + "", + "", + "", /* 110 */ + "", + "", + "", + "", + "AP_TS_PEN_I2C_SDA", + "AP_TS_PEN_I2C_SCL", + "DP_HOT_PLUG_DET", + "EC_IN_RW_ODL"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi index 88f6a7d4d020..2cf7d5212c61 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi @@ -6,6 +6,7 @@ */ /* This file must be included after sc7180-trogdor.dtsi */ +#include <arm/cros-ec-keyboard.dtsi> &ap_sar_sensor { semtech,cs0-ground; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev0-auo.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev0-auo.dts new file mode 100644 index 000000000000..2767817fb053 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev0-auo.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Mrbland board device tree source + * + * Copyright 2021 Google LLC. + * + * SKU: 0x0 => 0 + * - bits 7..4: Panel ID: 0x0 (AUO) + */ + +/dts-v1/; + +#include "sc7180-trogdor-mrbland-rev0.dtsi" + +/ { + model = "Google Mrbland rev0 AUO panel board"; + compatible = "google,mrbland-rev0-sku0", "qcom,sc7180"; +}; + +&panel { + compatible = "auo,b101uan08.3"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev0-boe.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev0-boe.dts new file mode 100644 index 000000000000..711485574a03 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev0-boe.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Mrbland board device tree source + * + * Copyright 2021 Google LLC. + * + * SKU: 0x10 => 16 + * - bits 7..4: Panel ID: 0x1 (BOE) + */ + +/dts-v1/; + +#include "sc7180-trogdor-mrbland-rev0.dtsi" + +/ { + model = "Google Mrbland rev0 BOE panel board"; + compatible = "google,mrbland-rev0-sku16", "qcom,sc7180"; +}; + +&panel { + compatible = "boe,tv101wum-n53"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev0.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev0.dtsi new file mode 100644 index 000000000000..7bc8402c018e --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev0.dtsi @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Mrbland board device tree source + * + * Copyright 2021 Google LLC. + * + */ + +/dts-v1/; + +#include "sc7180-trogdor-mrbland.dtsi" + +&avdd_lcd { + gpio = <&tlmm 80 GPIO_ACTIVE_HIGH>; +}; + +&panel { + enable-gpios = <&tlmm 76 GPIO_ACTIVE_HIGH>; +}; + +&v1p8_mipi { + gpio = <&tlmm 81 GPIO_ACTIVE_HIGH>; +}; + +/* PINCTRL - modifications to sc7180-trogdor-mrbland.dtsi */ +&avdd_lcd_en { + pinmux { + pins = "gpio80"; + }; + + pinconf { + pins = "gpio80"; + }; +}; + +&mipi_1800_en { + pinmux { + pins = "gpio81"; + }; + + pinconf { + pins = "gpio81"; + }; +}; +&vdd_reset_1800 { + pinmux { + pins = "gpio76"; + }; + + pinconf { + pins = "gpio76"; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev1-auo.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev1-auo.dts new file mode 100644 index 000000000000..275313ef7554 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev1-auo.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Mrbland board device tree source + * + * Copyright 2021 Google LLC. + * + * SKU: 0x600 => 1536 + * - bits 11..8: Panel ID: 0x6 (AUO) + */ + +/dts-v1/; + +#include "sc7180-trogdor-mrbland.dtsi" + +/ { + model = "Google Mrbland rev1+ AUO panel board"; + compatible = "google,mrbland-sku1536", "qcom,sc7180"; +}; + +&panel { + compatible = "auo,b101uan08.3"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev1-boe.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev1-boe.dts new file mode 100644 index 000000000000..87c6b6c30b5e --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev1-boe.dts @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Mrbland board device tree source + * + * Copyright 2021 Google LLC. + * + * SKU: 0x300 => 768 + * - bits 11..8: Panel ID: 0x3 (BOE) + */ + +/dts-v1/; + +#include "sc7180-trogdor-mrbland.dtsi" + +/ { + model = "Google Mrbland (rev1 - 2) BOE panel board"; + /* Uses ID 768 on rev1 and 1024 on rev2+ */ + compatible = "google,mrbland-sku1024", "google,mrbland-sku768", + "qcom,sc7180"; +}; + +&panel { + compatible = "boe,tv101wum-n53"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland.dtsi new file mode 100644 index 000000000000..97cba7f8064f --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland.dtsi @@ -0,0 +1,350 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Mrbland board device tree source + * + * Copyright 2021 Google LLC. + */ + +/dts-v1/; + +#include "sc7180-trogdor.dtsi" + +/* This board only has 1 USB Type-C port. */ +/delete-node/ &usb_c1; + +/ { + avdd_lcd: avdd-lcd { + compatible = "regulator-fixed"; + regulator-name = "avdd_lcd"; + + gpio = <&tlmm 88 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&avdd_lcd_en>; + + vin-supply = <&pp5000_a>; + }; + + avee_lcd: avee-lcd { + compatible = "regulator-fixed"; + regulator-name = "avee_lcd"; + + gpio = <&tlmm 21 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&avee_lcd_en>; + + vin-supply = <&pp5000_a>; + }; + + v1p8_mipi: v1p8-mipi { + compatible = "regulator-fixed"; + regulator-name = "v1p8_mipi"; + + gpio = <&tlmm 86 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&mipi_1800_en>; + + vin-supply = <&pp3300_a>; + }; +}; + +&backlight { + pwms = <&cros_ec_pwm 0>; +}; + +&camcc { + status = "okay"; +}; + +&cros_ec { + keyboard-controller { + compatible = "google,cros-ec-keyb-switches"; + }; +}; + +&dsi0 { + + panel: panel@0 { + /* Compatible will be filled in per-board */ + reg = <0>; + enable-gpios = <&tlmm 87 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vdd_reset_1800>; + avdd-supply = <&avdd_lcd>; + avee-supply = <&avee_lcd>; + pp1800-supply = <&v1p8_mipi>; + pp3300-supply = <&pp3300_dx_edp>; + backlight = <&backlight>; + rotation = <270>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + panel_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + }; + }; + + ports { + port@1 { + endpoint { + remote-endpoint = <&panel_in>; + data-lanes = <0 1 2 3>; + }; + }; + }; +}; + +&gpio_keys { + status = "okay"; +}; + +&i2c4 { + status = "okay"; + clock-frequency = <400000>; + + ap_ts: touchscreen@5d { + compatible = "goodix,gt7375p"; + reg = <0x5d>; + pinctrl-names = "default"; + pinctrl-0 = <&ts_int_l>, <&ts_reset_l>; + + interrupt-parent = <&tlmm>; + interrupts = <9 IRQ_TYPE_LEVEL_LOW>; + + reset-gpios = <&tlmm 8 GPIO_ACTIVE_LOW>; + + vdd-supply = <&pp3300_ts>; + }; +}; + +&pp1800_uf_cam { + status = "okay"; +}; + +&pp1800_wf_cam { + status = "okay"; +}; + +&pp2800_uf_cam { + status = "okay"; +}; + +&pp2800_wf_cam { + status = "okay"; +}; + +&wifi { + qcom,ath10k-calibration-variant = "GO_MRBLAND"; +}; + +/* + * No eDP on this board but it's logically the same signal so just give it + * a new name and assign the proper GPIO. + */ +pp3300_disp_on: &pp3300_dx_edp { + gpio = <&tlmm 85 GPIO_ACTIVE_HIGH>; +}; + +/* PINCTRL - modifications to sc7180-trogdor.dtsi */ + +/* + * No eDP on this board but it's logically the same signal so just give it + * a new name and assign the proper GPIO. + */ + +tp_en: &en_pp3300_dx_edp { + pinmux { + pins = "gpio85"; + }; + + pinconf { + pins = "gpio85"; + }; +}; + +/* PINCTRL - board-specific pinctrl */ + +&tlmm { + gpio-line-names = "HUB_RST_L", + "AP_RAM_ID0", + "AP_SKU_ID2", + "AP_RAM_ID1", + "", + "AP_RAM_ID2", + "UF_CAM_EN", + "WF_CAM_EN", + "TS_RESET_L", + "TS_INT_L", + "", + "", + "AP_EDP_BKLTEN", + "UF_CAM_MCLK", + "WF_CAM_CLK", + "", + "", + "UF_CAM_SDA", + "UF_CAM_SCL", + "WF_CAM_SDA", + "WF_CAM_SCL", + "AVEE_LCD_EN", + "", + "AMP_EN", + "", + "", + "", + "", + "HP_IRQ", + "WF_CAM_RST_L", + "UF_CAM_RST_L", + "AP_BRD_ID2", + "", + "AP_BRD_ID0", + "AP_H1_SPI_MISO", + "AP_H1_SPI_MOSI", + "AP_H1_SPI_CLK", + "AP_H1_SPI_CS_L", + "BT_UART_CTS", + "BT_UART_RTS", + "BT_UART_TXD", + "BT_UART_RXD", + "H1_AP_INT_ODL", + "", + "UART_AP_TX_DBG_RX", + "UART_DBG_TX_AP_RX", + "HP_I2C_SDA", + "HP_I2C_SCL", + "FORCED_USB_BOOT", + "AMP_BCLK", + "AMP_LRCLK", + "AMP_DIN", + "PEN_DET_ODL", + "HP_BCLK", + "HP_LRCLK", + "HP_DOUT", + "HP_DIN", + "HP_MCLK", + "AP_SKU_ID0", + "AP_EC_SPI_MISO", + "AP_EC_SPI_MOSI", + "AP_EC_SPI_CLK", + "AP_EC_SPI_CS_L", + "AP_SPI_CLK", + "AP_SPI_MOSI", + "AP_SPI_MISO", + /* + * AP_FLASH_WP_L is crossystem ABI. Schematics + * call it BIOS_FLASH_WP_L. + */ + "AP_FLASH_WP_L", + "", + "AP_SPI_CS0_L", + "", + "", + "", + "", + "WLAN_SW_CTRL", + "", + "REPORT_E", + "", + "ID0", + "", + "ID1", + "", + "", + "", + "CODEC_PWR_EN", + "HUB_EN", + "TP_EN", + "MIPI_1.8V_EN", + "VDD_RESET_1.8V", + "AVDD_LCD_EN", + "", + "AP_SKU_ID1", + "AP_RST_REQ", + "", + "AP_BRD_ID1", + "AP_EC_INT_L", + "SDM_GRFC_3", + "", + "", + "BOOT_CONFIG_4", + "BOOT_CONFIG_2", + "", + "", + "", + "", + "", + "", + "", + "BOOT_CONFIG_3", + "WCI2_LTE_COEX_TXD", + "WCI2_LTE_COEX_RXD", + "", + "", + "", + "", + "FORCED_USB_BOOT_POL", + "AP_TS_PEN_I2C_SDA", + "AP_TS_PEN_I2C_SCL", + "DP_HOT_PLUG_DET", + "EC_IN_RW_ODL"; + + avdd_lcd_en: avdd-lcd-en { + pinmux { + pins = "gpio88"; + function = "gpio"; + }; + + pinconf { + pins = "gpio88"; + drive-strength = <2>; + bias-disable; + }; + }; + + avee_lcd_en: avee-lcd-en { + pinmux { + pins = "gpio21"; + function = "gpio"; + }; + + pinconf { + pins = "gpio21"; + drive-strength = <2>; + bias-disable; + }; + }; + + mipi_1800_en: mipi-1800-en { + pinmux { + pins = "gpio86"; + function = "gpio"; + }; + + pinconf { + pins = "gpio86"; + drive-strength = <2>; + bias-disable; + }; + }; + + vdd_reset_1800: vdd-reset-1800 { + pinmux { + pins = "gpio87"; + function = "gpio"; + }; + + pinconf { + pins = "gpio87"; + drive-strength = <2>; + bias-disable; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel-lte-parade.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel-lte-parade.dts new file mode 100644 index 000000000000..764c451c1a85 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel-lte-parade.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Pazquel board device tree source + * + * Copyright 2021 Google LLC. + */ + +/dts-v1/; + +#include "sc7180-trogdor.dtsi" +#include "sc7180-trogdor-parade-ps8640.dtsi" +#include "sc7180-trogdor-pazquel.dtsi" +#include "sc7180-trogdor-lte-sku.dtsi" + +/ { + model = "Google Pazquel (Parade,LTE)"; + compatible = "google,pazquel-sku4", "qcom,sc7180"; +}; + +&ap_sar_sensor_i2c { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel-lte-ti.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel-lte-ti.dts new file mode 100644 index 000000000000..9145b74e9009 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel-lte-ti.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Pazquel board device tree source + * + * Copyright 2021 Google LLC. + */ + +/dts-v1/; + +#include "sc7180-trogdor.dtsi" +#include "sc7180-trogdor-ti-sn65dsi86.dtsi" +#include "sc7180-trogdor-pazquel.dtsi" +#include "sc7180-trogdor-lte-sku.dtsi" + +/ { + model = "Google Pazquel (TI,LTE)"; + compatible = "google,pazquel-sku0", "google,pazquel-sku2", "qcom,sc7180"; +}; + +&ap_sar_sensor_i2c { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel-parade.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel-parade.dts new file mode 100644 index 000000000000..9a0e6632a786 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel-parade.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Pazquel board device tree source + * + * Copyright 2022 Google LLC. + */ + +/dts-v1/; + +#include "sc7180-trogdor.dtsi" +#include "sc7180-trogdor-parade-ps8640.dtsi" +#include "sc7180-trogdor-pazquel.dtsi" + +/ { + model = "Google Pazquel (Parade)"; + compatible = "google,pazquel-sku5", "qcom,sc7180"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel-ti.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel-ti.dts new file mode 100644 index 000000000000..47c5970d8c22 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel-ti.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Pazquel board device tree source + * + * Copyright 2021 Google LLC. + */ + +/dts-v1/; + +#include "sc7180-trogdor.dtsi" +#include "sc7180-trogdor-ti-sn65dsi86.dtsi" +#include "sc7180-trogdor-pazquel.dtsi" + +/ { + model = "Google Pazquel (TI)"; + compatible = "google,pazquel-sku1", "qcom,sc7180"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel.dtsi new file mode 100644 index 000000000000..56d787785fd5 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel.dtsi @@ -0,0 +1,222 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Pazquel board device tree source + * + * Copyright 2021 Google LLC. + */ + +/* This file must be included after sc7180-trogdor.dtsi */ +#include <arm/cros-ec-keyboard.dtsi> + +&ap_sar_sensor { + compatible = "semtech,sx9324"; + semtech,ph0-pin = <1 3 3>; + semtech,ph1-pin = <3 1 3>; + semtech,ph2-pin = <1 3 3>; + semtech,ph3-pin = <0 0 0>; + semtech,ph01-resolution = <1024>; + semtech,ph23-resolution = <1024>; + semtech,startup-sensor = <1>; + semtech,ph01-proxraw-strength = <3>; + semtech,ph23-proxraw-strength = <1>; + semtech,avg-pos-strength = <128>; + semtech,input-analog-gain = <0>; + semtech,cs-idle-sleep = "gnd"; + + /delete-property/ svdd-supply; + vdd-supply = <&pp1800_prox>; +}; + +/delete-node/&trackpad; +&ap_tp_i2c { + status = "okay"; + trackpad: trackpad@15 { + compatible = "hid-over-i2c"; + reg = <0x15>; + pinctrl-names = "default"; + pinctrl-0 = <&tp_int_odl>; + + interrupt-parent = <&tlmm>; + interrupts = <0 IRQ_TYPE_EDGE_FALLING>; + + vcc-supply = <&pp3300_fp_tp>; + post-power-on-delay-ms = <100>; + hid-descr-addr = <0x0001>; + + wakeup-source; + }; +}; + +&keyboard_controller { + function-row-physmap = < + MATRIX_KEY(0x00, 0x02, 0) /* T1 */ + MATRIX_KEY(0x03, 0x02, 0) /* T2 */ + MATRIX_KEY(0x02, 0x02, 0) /* T3 */ + MATRIX_KEY(0x01, 0x02, 0) /* T4 */ + MATRIX_KEY(0x03, 0x04, 0) /* T5 */ + MATRIX_KEY(0x02, 0x04, 0) /* T6 */ + MATRIX_KEY(0x01, 0x04, 0) /* T7 */ + MATRIX_KEY(0x02, 0x09, 0) /* T8 */ + MATRIX_KEY(0x01, 0x09, 0) /* T9 */ + MATRIX_KEY(0x00, 0x04, 0) /* T10 */ + >; + linux,keymap = < + MATRIX_KEY(0x00, 0x02, KEY_BACK) + MATRIX_KEY(0x03, 0x02, KEY_REFRESH) + MATRIX_KEY(0x02, 0x02, KEY_ZOOM) + MATRIX_KEY(0x01, 0x02, KEY_SCALE) + MATRIX_KEY(0x03, 0x04, KEY_SYSRQ) + MATRIX_KEY(0x02, 0x04, KEY_BRIGHTNESSDOWN) + MATRIX_KEY(0x01, 0x04, KEY_BRIGHTNESSUP) + MATRIX_KEY(0x02, 0x09, KEY_MUTE) + MATRIX_KEY(0x01, 0x09, KEY_VOLUMEDOWN) + MATRIX_KEY(0x00, 0x04, KEY_VOLUMEUP) + CROS_STD_MAIN_KEYMAP + >; +}; + +&panel { + compatible = "edp-panel"; +}; + +&pp3300_dx_edp { + gpio = <&tlmm 67 GPIO_ACTIVE_HIGH>; +}; + +&en_pp3300_dx_edp { + pinmux { + pins = "gpio67"; + }; + + pinconf { + pins = "gpio67"; + }; +}; + +/* PINCTRL - board-specific pinctrl */ + +&tlmm { + gpio-line-names = "TP_INT_ODL", + "AP_RAM_ID0", + "AP_SKU_ID2", + "AP_RAM_ID1", + "", + "AP_RAM_ID2", + "AP_TP_I2C_SDA", + "AP_TP_I2C_SCL", + "TS_RESET_L", + "TS_INT_L", + "", + "EDP_BRIJ_IRQ", + "AP_EDP_BKLTEN", + "", + "", + "EDP_BRIJ_I2C_SDA", + "EDP_BRIJ_I2C_SCL", + "HUB_RST_L", + "", + "", + "", + "", + "", + "AMP_EN", + "P_SENSOR_INT_L", + "AP_SAR_SENSOR_SDA", + "AP_SAR_SENSOR_SCL", + "", + "HP_IRQ", + "", + "", + "AP_BRD_ID2", + "BRIJ_SUSPEND", + "AP_BRD_ID0", + "AP_H1_SPI_MISO", + "AP_H1_SPI_MOSI", + "AP_H1_SPI_CLK", + "AP_H1_SPI_CS_L", + "", + "", + "", + "", + "H1_AP_INT_ODL", + "", + "UART_AP_TX_DBG_RX", + "UART_DBG_TX_AP_RX", + "HP_I2C_SDA", + "HP_I2C_SCL", + "FORCED_USB_BOOT", + "AMP_BCLK", + "AMP_LRCLK", + "AMP_DIN", + "", + "HP_BCLK", + "HP_LRCLK", + "HP_DOUT", + "HP_DIN", + "HP_MCLK", + "AP_SKU_ID0", + "AP_EC_SPI_MISO", + "AP_EC_SPI_MOSI", + "AP_EC_SPI_CLK", + "AP_EC_SPI_CS_L", + "AP_SPI_CLK", + "AP_SPI_MOSI", + "AP_SPI_MISO", + /* + * AP_FLASH_WP_L is crossystem ABI. Schematics + * call it BIOS_FLASH_WP_L. + */ + "AP_FLASH_WP_L", + "EN_PP3300_DX_EDP", + "AP_SPI_CS0_L", + "", + "", + "", + "", + "", + "", + "UIM2_DATA", + "UIM2_CLK", + "UIM2_RST", + "UIM2_PRESENT", + "UIM1_DATA", + "UIM1_CLK", + "UIM1_RST", + "", + "CODEC_PWR_EN", + "HUB_EN", + "", + "", + "", + "", + "", + "AP_SKU_ID1", + "AP_RST_REQ", + "", + "AP_BRD_ID1", + "AP_EC_INT_L", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "EDP_BRIJ_EN", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "AP_TS_PEN_I2C_SDA", + "AP_TS_PEN_I2C_SCL", + "DP_HOT_PLUG_DET", + "EC_IN_RW_ODL"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi index 3df4920295ad..a7582fb547ee 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi @@ -6,6 +6,8 @@ */ #include "sc7180-trogdor.dtsi" +/* Must come after sc7180-trogdor.dtsi to modify cros_ec */ +#include <arm/cros-ec-keyboard.dtsi> #include "sc7180-trogdor-ti-sn65dsi86.dtsi" / { diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick-r0-lte.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick-r0-lte.dts new file mode 100644 index 000000000000..35e8945fc56d --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick-r0-lte.dts @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Quackingstick board device tree source + * + * Copyright 2021 Google LLC. + * + * SKU: 0x600 => 1536 + * - bits 11..8: Panel ID: 0x6 (AUO) + */ + +#include "sc7180-trogdor-quackingstick-r0.dts" +#include "sc7180-trogdor-lte-sku.dtsi" + +/ { + model = "Google Quackingstick (rev0+) with LTE"; + compatible = "google,quackingstick-sku1536", "qcom,sc7180"; +}; + +&ap_sar_sensor { + compatible = "semtech,sx9324"; + semtech,ph0-pin = <3 1 3>; + semtech,ph1-pin = <2 1 2>; + semtech,ph2-pin = <3 3 1>; + semtech,ph3-pin = <1 3 3>; + semtech,ph01-resolution = <1024>; + semtech,ph23-resolution = <1024>; + semtech,startup-sensor = <1>; + semtech,ph01-proxraw-strength = <3>; + semtech,ph23-proxraw-strength = <3>; + semtech,avg-pos-strength = <256>; + + /delete-property/ svdd-supply; + vdd-supply = <&pp1800_prox>; +}; + +&ap_sar_sensor_i2c { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick-r0.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick-r0.dts new file mode 100644 index 000000000000..5c81e44ed4a5 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick-r0.dts @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Quackingstick board device tree source + * + * Copyright 2021 Google LLC. + * + * SKU: 0x601 => 1537 + * - bits 11..8: Panel ID: 0x6 (AUO) + */ + +#include "sc7180-trogdor-quackingstick.dtsi" + +/ { + model = "Google Quackingstick (rev0+)"; + compatible = "google,quackingstick-sku1537", "qcom,sc7180"; +}; + +&dsi_phy { + qcom,phy-rescode-offset-top = /bits/ 8 <(-13) (-13) (-13) (-13) (-13)>; + qcom,phy-rescode-offset-bot = /bits/ 8 <(-13) (-13) (-13) (-13) (-13)>; + qcom,phy-drive-ldo-level = <375>; +}; + +&panel { + compatible = "auo,b101uan08.3"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick.dtsi new file mode 100644 index 000000000000..695b04fe7221 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick.dtsi @@ -0,0 +1,324 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Quackingstick board device tree source + * + * Copyright 2021 Google LLC. + */ + +/dts-v1/; + +#include "sc7180-trogdor.dtsi" + +/* This board only has 1 USB Type-C port. */ +/delete-node/ &usb_c1; + +/ { + ppvar_lcd: ppvar-lcd { + compatible = "regulator-fixed"; + regulator-name = "ppvar_lcd"; + + gpio = <&tlmm 88 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&ppvar_lcd_en>; + + vin-supply = <&pp5000_a>; + }; + + v1p8_disp: v1p8-disp { + compatible = "regulator-fixed"; + regulator-name = "v1p8_disp"; + + gpio = <&tlmm 86 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&pp1800_disp_on>; + + vin-supply = <&pp3300_a>; + }; +}; + +&backlight { + pwms = <&cros_ec_pwm 0>; +}; + +&camcc { + status = "okay"; +}; + +&cros_ec { + keyboard-controller { + compatible = "google,cros-ec-keyb-switches"; + }; +}; + +&dsi0 { + panel: panel@0 { + /* Compatible will be filled in per-board */ + reg = <0>; + enable-gpios = <&tlmm 87 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_rst>; + avdd-supply = <&ppvar_lcd>; + pp1800-supply = <&v1p8_disp>; + pp3300-supply = <&pp3300_dx_edp>; + backlight = <&backlight>; + rotation = <270>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + panel_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + }; + }; + + ports { + port@1 { + endpoint { + remote-endpoint = <&panel_in>; + data-lanes = <0 1 2 3>; + }; + }; + }; +}; + +&gpio_keys { + status = "okay"; +}; + +&i2c4 { + status = "okay"; + clock-frequency = <400000>; + + ap_ts: touchscreen@10 { + compatible = "hid-over-i2c"; + reg = <0x10>; + pinctrl-names = "default"; + pinctrl-0 = <&ts_int_l>, <&ts_reset_l>; + + interrupt-parent = <&tlmm>; + interrupts = <9 IRQ_TYPE_LEVEL_LOW>; + + post-power-on-delay-ms = <20>; + hid-descr-addr = <0x0001>; + + vdd-supply = <&pp3300_ts>; + }; +}; + +&sdhc_2 { + status = "okay"; +}; + +&pp1800_uf_cam { + status = "okay"; +}; + +&pp1800_wf_cam { + status = "okay"; +}; + +&pp2800_uf_cam { + status = "okay"; +}; + +&pp2800_wf_cam { + status = "okay"; +}; + +/* + * No eDP on this board but it's logically the same signal so just give it + * a new name and assign the proper GPIO. + */ +pp3300_disp_on: &pp3300_dx_edp { + gpio = <&tlmm 67 GPIO_ACTIVE_HIGH>; +}; + +/* PINCTRL - modifications to sc7180-trogdor.dtsi */ + +/* + * No eDP on this board but it's logically the same signal so just give it + * a new name and assign the proper GPIO. + */ + +tp_en: &en_pp3300_dx_edp { + pinmux { + pins = "gpio67"; + }; + + pinconf { + pins = "gpio67"; + }; +}; + +/* PINCTRL - board-specific pinctrl */ + +&tlmm { + gpio-line-names = "HUB_RST_L", + "AP_RAM_ID0", + "AP_SKU_ID2", + "AP_RAM_ID1", + "", + "AP_RAM_ID2", + "UF_CAM_EN", + "WF_CAM_EN", + "TS_RESET_L", + "TS_INT_L", + "", + "", + "AP_EDP_BKLTEN", + "UF_CAM_MCLK", + "WF_CAM_CLK", + "EDP_BRIJ_I2C_SDA", + "EDP_BRIJ_I2C_SCL", + "UF_CAM_SDA", + "UF_CAM_SCL", + "WF_CAM_SDA", + "WF_CAM_SCL", + "", + "", + "AMP_EN", + "P_SENSOR_INT_L", + "AP_SAR_SENSOR_SDA", + "AP_SAR_SENSOR_SCL", + "", + "HP_IRQ", + "WF_CAM_RST_L", + "UF_CAM_RST_L", + "AP_BRD_ID2", + "", + "AP_BRD_ID0", + "AP_H1_SPI_MISO", + "AP_H1_SPI_MOSI", + "AP_H1_SPI_CLK", + "AP_H1_SPI_CS_L", + "", + "", + "", + "", + "H1_AP_INT_ODL", + "", + "UART_AP_TX_DBG_RX", + "UART_DBG_TX_AP_RX", + "HP_I2C_SDA", + "HP_I2C_SCL", + "FORCED_USB_BOOT", + "", + "", + "AMP_DIN", + "PEN_DET_ODL", + "HP_BCLK", + "HP_LRCLK", + "HP_DOUT", + "HP_DIN", + "HP_MCLK", + "AP_SKU_ID0", + "AP_EC_SPI_MISO", + "AP_EC_SPI_MOSI", + "AP_EC_SPI_CLK", + "AP_EC_SPI_CS_L", + "AP_SPI_CLK", + "AP_SPI_MOSI", + "AP_SPI_MISO", + /* + * AP_FLASH_WP_L is crossystem ABI. Schematics + * call it BIOS_FLASH_WP_L. + */ + "AP_FLASH_WP_L", + "EN_PP3300_DX_EDP", + "AP_SPI_CS0_L", + "SD_CD_ODL", + "", + "", + "", + "", + "", + "UIM2_DATA", + "UIM2_CLK", + "UIM2_RST", + "UIM2_PRESENT_L", + "UIM1_DATA", + "UIM1_CLK", + "UIM1_RST", + "", + "CODEC_PWR_EN", + "HUB_EN", + "", + "PP1800_DISP_ON", + "LCD_RST", + "PPVAR_LCD_EN", + "", + "AP_SKU_ID1", + "AP_RST_REQ", + "", + "AP_BRD_ID1", + "AP_EC_INT_L", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "AP_TS_I2C_SDA", + "AP_TS_I2C_SCL", + "DP_HOT_PLUG_DET", + "EC_IN_RW_ODL"; + + lcd_rst: lcd-rst { + pinmux { + pins = "gpio87"; + function = "gpio"; + }; + + pinconf { + pins = "gpio87"; + drive-strength = <2>; + bias-disable; + }; + }; + + ppvar_lcd_en: ppvar-lcd-en { + pinmux { + pins = "gpio88"; + function = "gpio"; + }; + + pinconf { + pins = "gpio88"; + drive-strength = <2>; + bias-disable; + }; + }; + + pp1800_disp_on: pp1800-disp-on { + pinmux { + pins = "gpio86"; + function = "gpio"; + }; + + pinconf { + pins = "gpio86"; + drive-strength = <2>; + bias-disable; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-r1.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-r1.dts index 352827e5740a..59a23d0e9651 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-r1.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-r1.dts @@ -8,6 +8,8 @@ /dts-v1/; #include "sc7180-trogdor.dtsi" +/* Must come after sc7180-trogdor.dtsi to modify cros_ec */ +#include <arm/cros-ec-keyboard.dtsi> #include "sc7180-trogdor-ti-sn65dsi86.dtsi" / { diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev0-boe.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev0-boe.dts new file mode 100644 index 000000000000..d6ed7d0afe4a --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev0-boe.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Wormdingler board device tree source + * + * Copyright 2021 Google LLC. + * + * SKU: 0x10 => 16 + * - bits 7..4: Panel ID: 0x1 (BOE) + */ + +/dts-v1/; + +#include "sc7180-trogdor-wormdingler-rev0.dtsi" + +/ { + model = "Google Wormdingler rev0 BOE panel board"; + compatible = "google,wormdingler-rev0-sku16", "qcom,sc7180"; +}; + +&panel { + compatible = "boe,tv110c9m-ll3"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev0-inx.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev0-inx.dts new file mode 100644 index 000000000000..c03525ea64ca --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev0-inx.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Wormdingler board device tree source + * + * Copyright 2021 Google LLC. + * + * SKU: 0x0 => 0 + * - bits 7..4: Panel ID: 0x0 (INX) + */ + +/dts-v1/; + +#include "sc7180-trogdor-wormdingler-rev0.dtsi" + +/ { + model = "Google Wormdingler rev0 INX panel board"; + compatible = "google,wormdingler-rev0-sku0", "qcom,sc7180"; +}; + +&panel { + compatible = "innolux,hj110iz-01a"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev0.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev0.dtsi new file mode 100644 index 000000000000..db29e0cba29d --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev0.dtsi @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Wormdingler board device tree source + * + * Copyright 2021 Google LLC. + * + */ + +/dts-v1/; + +#include "sc7180-trogdor-wormdingler.dtsi" + +&avdd_lcd { + gpio = <&tlmm 80 GPIO_ACTIVE_HIGH>; +}; + +&panel { + enable-gpios = <&tlmm 76 GPIO_ACTIVE_HIGH>; +}; + +&v1p8_mipi { + gpio = <&tlmm 81 GPIO_ACTIVE_HIGH>; +}; + +/* PINCTRL - modifications to sc7180-trogdor-wormdingler.dtsi */ +&avdd_lcd_en { + pinmux { + pins = "gpio80"; + }; + + pinconf { + pins = "gpio80"; + }; +}; + +&mipi_1800_en { + pinmux { + pins = "gpio81"; + }; + + pinconf { + pins = "gpio81"; + }; +}; +&vdd_reset_1800 { + pinmux { + pins = "gpio76"; + }; + + pinconf { + pins = "gpio76"; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev1-boe-rt5682s.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev1-boe-rt5682s.dts new file mode 100644 index 000000000000..aa605885c371 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev1-boe-rt5682s.dts @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Wormdingler board device tree source + * + * Copyright 2021 Google LLC. + * + * SKU: 0x401 => 1025 + * - bits 11..8: Panel ID: 0x4 (BOE) + */ + +/dts-v1/; + +#include "sc7180-trogdor-wormdingler-rev1-boe.dts" + +/ { + model = "Google Wormdingler rev1+ (BOE, rt5682s)"; + compatible = "google,wormdingler-sku1025", "qcom,sc7180"; +}; + +&alc5682 { + compatible = "realtek,rt5682s"; + realtek,dmic1-clk-pin = <2>; + realtek,dmic-clk-rate-hz = <2048000>; +}; + +&sound { + compatible = "google,sc7180-trogdor"; + model = "sc7180-rt5682s-max98357a-1mic"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev1-boe.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev1-boe.dts new file mode 100644 index 000000000000..c5b0658bd632 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev1-boe.dts @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Wormdingler board device tree source + * + * Copyright 2021 Google LLC. + * + * SKU: 0x400 => 1024 + * - bits 11..8: Panel ID: 0x4 (BOE) + */ + +/dts-v1/; + +#include "sc7180-trogdor-wormdingler.dtsi" + +/ { + model = "Google Wormdingler rev1+ BOE panel board"; + compatible = "google,wormdingler-sku1024", "qcom,sc7180"; +}; + +&dsi_phy { + qcom,phy-rescode-offset-top = /bits/ 8 <31 31 31 31 (-32)>; + qcom,phy-rescode-offset-bot = /bits/ 8 <31 31 31 31 (-32)>; + qcom,phy-drive-ldo-level = <450>; +}; + +&panel { + compatible = "boe,tv110c9m-ll3"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev1-inx-rt5682s.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev1-inx-rt5682s.dts new file mode 100644 index 000000000000..7116c44c8d85 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev1-inx-rt5682s.dts @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Wormdingler board device tree source + * + * Copyright 2021 Google LLC. + * + * SKU: 0x0001 => 1 + * - bits 11..8: Panel ID: 0x0 (INX) + */ + +/dts-v1/; + +#include "sc7180-trogdor-wormdingler-rev1-inx.dts" + +/ { + model = "Google Wormdingler rev1+ (INX, rt5682s)"; + compatible = "google,wormdingler-sku1", "qcom,sc7180"; +}; + +&alc5682 { + compatible = "realtek,rt5682s"; + realtek,dmic1-clk-pin = <2>; + realtek,dmic-clk-rate-hz = <2048000>; +}; + +&sound { + compatible = "google,sc7180-trogdor"; + model = "sc7180-rt5682s-max98357a-1mic"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev1-inx.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev1-inx.dts new file mode 100644 index 000000000000..dd34a2297ea0 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev1-inx.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Wormdingler board device tree source + * + * Copyright 2021 Google LLC. + * + * SKU: 0x0000 => 0 + * - bits 11..8: Panel ID: 0x0 (INX) + */ + +/dts-v1/; + +#include "sc7180-trogdor-wormdingler.dtsi" + +/ { + model = "Google Wormdingler rev1+ INX panel board"; + compatible = "google,wormdingler-sku0", "qcom,sc7180"; +}; + +&panel { + compatible = "innolux,hj110iz-01a"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler.dtsi new file mode 100644 index 000000000000..6312108e8b3e --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler.dtsi @@ -0,0 +1,412 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Wormdingler board device tree source + * + * Copyright 2021 Google LLC. + */ + +/dts-v1/; + +#include "sc7180-trogdor.dtsi" + +/ { + avdd_lcd: avdd-lcd { + compatible = "regulator-fixed"; + regulator-name = "avdd_lcd"; + + gpio = <&tlmm 88 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&avdd_lcd_en>; + + vin-supply = <&pp5000_a>; + }; + + avee_lcd: avee-lcd { + compatible = "regulator-fixed"; + regulator-name = "avee_lcd"; + + gpio = <&tlmm 21 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&avee_lcd_en>; + + vin-supply = <&pp5000_a>; + }; + + pp1800_ts: + v1p8_mipi: v1p8-mipi { + compatible = "regulator-fixed"; + regulator-name = "v1p8_mipi"; + + gpio = <&tlmm 86 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&mipi_1800_en>; + + vin-supply = <&pp3300_a>; + }; + + thermal-zones { + skin_temp_thermal: skin-temp-thermal { + polling-delay-passive = <250>; + polling-delay = <0>; + + thermal-sensors = <&pm6150_adc_tm 1>; + sustainable-power = <574>; + + trips { + skin_temp_alert0: trip-point0 { + temperature = <58000>; + hysteresis = <1000>; + type = "passive"; + }; + + skin_temp_alert1: trip-point1 { + temperature = <62500>; + hysteresis = <1000>; + type = "passive"; + }; + + skin-temp-crit { + temperature = <68000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&skin_temp_alert0>; + cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + + map1 { + trip = <&skin_temp_alert1>; + cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; +}; + +&backlight { + pwms = <&cros_ec_pwm 0>; +}; + +&camcc { + status = "okay"; +}; + +&cros_ec { + base_detection: cbas { + compatible = "google,cros-cbas"; + }; + + keyboard-controller { + compatible = "google,cros-ec-keyb-switches"; + }; +}; + +&dsi0 { + + panel: panel@0 { + reg = <0>; + enable-gpios = <&tlmm 87 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vdd_reset_1800>; + avdd-supply = <&avdd_lcd>; + avee-supply = <&avee_lcd>; + pp1800-supply = <&v1p8_mipi>; + pp3300-supply = <&pp3300_dx_edp>; + backlight = <&backlight>; + rotation = <270>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + panel_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + }; + }; + + ports { + port@1 { + endpoint { + remote-endpoint = <&panel_in>; + data-lanes = <0 1 2 3>; + }; + }; + }; +}; + +&i2c4 { + status = "okay"; + clock-frequency = <400000>; + + ap_ts: touchscreen@1 { + compatible = "hid-over-i2c"; + reg = <0x01>; + pinctrl-names = "default"; + pinctrl-0 = <&ts_int_l>; + + interrupt-parent = <&tlmm>; + interrupts = <9 IRQ_TYPE_EDGE_FALLING>; + + post-power-on-delay-ms = <70>; + hid-descr-addr = <0x0001>; + + vdd-supply = <&pp3300_ts>; + vddl-supply = <&pp1800_ts>; + }; +}; + +&pm6150_adc { + skin-temp-thermistor@4d { + reg = <ADC5_AMUX_THM1_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; +}; + +&pm6150_adc_tm { + status = "okay"; + + skin-temp-thermistor@1 { + reg = <1>; + io-channels = <&pm6150_adc ADC5_AMUX_THM1_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; +}; + +&pp1800_uf_cam { + status = "okay"; +}; + +&pp1800_wf_cam { + status = "okay"; +}; + +&pp2800_uf_cam { + status = "okay"; +}; + +&pp2800_wf_cam { + status = "okay"; +}; + +&wifi { + qcom,ath10k-calibration-variant = "GO_WORMDINGLER"; +}; + +/* + * No eDP on this board but it's logically the same signal so just give it + * a new name and assign the proper GPIO. + */ +pp3300_disp_on: &pp3300_dx_edp { + gpio = <&tlmm 85 GPIO_ACTIVE_HIGH>; +}; + +/* PINCTRL - modifications to sc7180-trogdor.dtsi */ + +/* + * No eDP on this board but it's logically the same signal so just give it + * a new name and assign the proper GPIO. + */ + +tp_en: &en_pp3300_dx_edp { + pinmux { + pins = "gpio85"; + }; + + pinconf { + pins = "gpio85"; + }; +}; + +/* PINCTRL - board-specific pinctrl */ + +&tlmm { + gpio-line-names = "HUB_RST_L", + "AP_RAM_ID0", + "AP_SKU_ID2", + "AP_RAM_ID1", + "", + "AP_RAM_ID2", + "UF_CAM_EN", + "WF_CAM_EN", + "TS_RESET_L", + "TS_INT_L", + "", + "", + "AP_EDP_BKLTEN", + "UF_CAM_MCLK", + "WF_CAM_CLK", + "", + "", + "UF_CAM_SDA", + "UF_CAM_SCL", + "WF_CAM_SDA", + "WF_CAM_SCL", + "AVEE_LCD_EN", + "", + "AMP_EN", + "", + "", + "", + "", + "HP_IRQ", + "WF_CAM_RST_L", + "UF_CAM_RST_L", + "AP_BRD_ID2", + "", + "AP_BRD_ID0", + "AP_H1_SPI_MISO", + "AP_H1_SPI_MOSI", + "AP_H1_SPI_CLK", + "AP_H1_SPI_CS_L", + "BT_UART_CTS", + "BT_UART_RTS", + "BT_UART_TXD", + "BT_UART_RXD", + "H1_AP_INT_ODL", + "", + "UART_AP_TX_DBG_RX", + "UART_DBG_TX_AP_RX", + "HP_I2C_SDA", + "HP_I2C_SCL", + "FORCED_USB_BOOT", + "AMP_BCLK", + "AMP_LRCLK", + "AMP_DIN", + "", + "HP_BCLK", + "HP_LRCLK", + "HP_DOUT", + "HP_DIN", + "HP_MCLK", + "AP_SKU_ID0", + "AP_EC_SPI_MISO", + "AP_EC_SPI_MOSI", + "AP_EC_SPI_CLK", + "AP_EC_SPI_CS_L", + "AP_SPI_CLK", + "AP_SPI_MOSI", + "AP_SPI_MISO", + /* + * AP_FLASH_WP_L is crossystem ABI. Schematics + * call it BIOS_FLASH_WP_L. + */ + "AP_FLASH_WP_L", + "", + "AP_SPI_CS0_L", + "", + "", + "", + "", + "WLAN_SW_CTRL", + "", + "REPORT_E", + "", + "ID0", + "", + "ID1", + "", + "", + "", + "CODEC_PWR_EN", + "HUB_EN", + "TP_EN", + "MIPI_1.8V_EN", + "VDD_RESET_1.8V", + "AVDD_LCD_EN", + "", + "AP_SKU_ID1", + "AP_RST_REQ", + "", + "AP_BRD_ID1", + "AP_EC_INT_L", + "SDM_GRFC_3", + "", + "", + "BOOT_CONFIG_4", + "BOOT_CONFIG_2", + "", + "", + "", + "", + "", + "", + "", + "BOOT_CONFIG_3", + "WCI2_LTE_COEX_TXD", + "WCI2_LTE_COEX_RXD", + "", + "", + "", + "", + "FORCED_USB_BOOT_POL", + "AP_TS_PEN_I2C_SDA", + "AP_TS_PEN_I2C_SCL", + "DP_HOT_PLUG_DET", + "EC_IN_RW_ODL"; + + avdd_lcd_en: avdd-lcd-en { + pinmux { + pins = "gpio88"; + function = "gpio"; + }; + + pinconf { + pins = "gpio88"; + drive-strength = <2>; + bias-disable; + }; + }; + + avee_lcd_en: avee-lcd-en { + pinmux { + pins = "gpio21"; + function = "gpio"; + }; + + pinconf { + pins = "gpio21"; + drive-strength = <2>; + bias-disable; + }; + }; + + mipi_1800_en: mipi-1800-en { + pinmux { + pins = "gpio86"; + function = "gpio"; + }; + + pinconf { + pins = "gpio86"; + drive-strength = <2>; + bias-disable; + }; + }; + + vdd_reset_1800: vdd-reset-1800 { + pinmux { + pins = "gpio87"; + function = "gpio"; + }; + + pinconf { + pins = "gpio87"; + drive-strength = <2>; + bias-disable; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi index e55dbaa6dc12..b5f534db135a 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi @@ -8,6 +8,7 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/gpio-keys.h> #include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> #include <dt-bindings/regulator/qcom,rpmh-regulator.h> #include <dt-bindings/sound/sc7180-lpass.h> @@ -43,6 +44,7 @@ */ /delete-node/ &hyp_mem; +/delete-node/ &ipa_fw_mem; /delete-node/ &xbl_mem; /delete-node/ &aop_mem; /delete-node/ &sec_apps_mem; @@ -330,7 +332,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pen_pdct_l>; - pen_insert: pen-insert { + pen_insert: switch-pen-insert { label = "Pen Insert"; /* Insert = low, eject = high */ @@ -355,6 +357,7 @@ keyboard_backlight: keyboard-backlight { status = "disabled"; label = "cros_ec::kbd_backlight"; + function = LED_FUNCTION_KBD_BACKLIGHT; pwms = <&cros_ec_pwm 0>; max-brightness = <1023>; }; @@ -812,8 +815,6 @@ hp_i2c: &i2c9 { pinctrl-names = "default"; pinctrl-0 = <&dp_hot_plug_det>; data-lanes = <0 1>; - vdda-1p2-supply = <&vdda_usb_ss_dp_1p2>; - vdda-0p9-supply = <&vdda_usb_ss_dp_core>; }; &pm6150_adc { @@ -903,7 +904,6 @@ ap_spi_fp: &spi10 { }; }; -#include <arm/cros-ec-keyboard.dtsi> #include <arm/cros-ec-sbs.dtsi> &uart3 { diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 5dcaac23a138..b82c335c25af 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -398,7 +398,7 @@ }; }; - cpu0_opp_table: cpu0_opp_table { + cpu0_opp_table: opp-table-cpu0 { compatible = "operating-points-v2"; opp-shared; @@ -453,7 +453,7 @@ }; }; - cpu6_opp_table: cpu6_opp_table { + cpu6_opp_table: opp-table-cpu6 { compatible = "operating-points-v2"; opp-shared; @@ -693,7 +693,7 @@ }; }; - sdhc_1: sdhci@7c4000 { + sdhc_1: mmc@7c4000 { compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5"; reg = <0 0x7c4000 0 0x1000>, <0 0x07c5000 0 0x1000>; @@ -704,10 +704,10 @@ <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "hc_irq", "pwr_irq"; - clocks = <&gcc GCC_SDCC1_APPS_CLK>, - <&gcc GCC_SDCC1_AHB_CLK>, + clocks = <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, <&rpmhcc RPMH_CXO_CLK>; - clock-names = "core", "iface", "xo"; + clock-names = "iface", "core", "xo"; interconnects = <&aggre1_noc MASTER_EMMC 0 &mc_virt SLAVE_EBI1 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_EMMC_CFG 0>; interconnect-names = "sdhc-ddr","cpu-sdhc"; @@ -725,7 +725,7 @@ status = "disabled"; - sdhc1_opp_table: sdhc1-opp-table { + sdhc1_opp_table: opp-table { compatible = "operating-points-v2"; opp-100000000 { @@ -744,7 +744,7 @@ }; }; - qup_opp_table: qup-opp-table { + qup_opp_table: opp-table-qup { compatible = "operating-points-v2"; opp-75000000 { @@ -2048,7 +2048,7 @@ }; gmu: gmu@506a000 { - compatible="qcom,adreno-gmu-618.0", "qcom,adreno-gmu"; + compatible = "qcom,adreno-gmu-618.0", "qcom,adreno-gmu"; reg = <0 0x0506a000 0 0x31000>, <0 0x0b290000 0 0x10000>, <0 0x0b490000 0 0x10000>; reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; @@ -2578,7 +2578,7 @@ }; }; - sdhc_2: sdhci@8804000 { + sdhc_2: mmc@8804000 { compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5"; reg = <0 0x08804000 0 0x1000>; @@ -2587,10 +2587,10 @@ <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "hc_irq", "pwr_irq"; - clocks = <&gcc GCC_SDCC2_APPS_CLK>, - <&gcc GCC_SDCC2_AHB_CLK>, + clocks = <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, <&rpmhcc RPMH_CXO_CLK>; - clock-names = "core", "iface", "xo"; + clock-names = "iface", "core", "xo"; interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; @@ -2602,7 +2602,7 @@ status = "disabled"; - sdhc2_opp_table: sdhc2-opp-table { + sdhc2_opp_table: opp-table { compatible = "operating-points-v2"; opp-100000000 { @@ -2621,7 +2621,7 @@ }; }; - qspi_opp_table: qspi-opp-table { + qspi_opp_table: opp-table-qspi { compatible = "operating-points-v2"; opp-75000000 { @@ -2825,7 +2825,7 @@ compatible = "venus-encoder"; }; - venus_opp_table: venus-opp-table { + venus_opp_table: opp-table { compatible = "operating-points-v2"; opp-150000000 { @@ -2896,9 +2896,6 @@ <&dispcc DISP_CC_MDSS_MDP_CLK>; clock-names = "iface", "ahb", "core"; - assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; - assigned-clock-rates = <300000000>; - interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; interrupt-controller; #interrupt-cells = <1>; @@ -2914,7 +2911,7 @@ status = "disabled"; - mdp: mdp@ae01000 { + mdp: display-controller@ae01000 { compatible = "qcom,sc7180-dpu"; reg = <0 0x0ae01000 0 0x8f000>, <0 0x0aeb0000 0 0x2008>; @@ -2928,12 +2925,10 @@ <&dispcc DISP_CC_MDSS_VSYNC_CLK>; clock-names = "bus", "iface", "rot", "lut", "core", "vsync"; - assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, - <&dispcc DISP_CC_MDSS_VSYNC_CLK>, + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>, <&dispcc DISP_CC_MDSS_ROT_CLK>, <&dispcc DISP_CC_MDSS_AHB_CLK>; - assigned-clock-rates = <300000000>, - <19200000>, + assigned-clock-rates = <19200000>, <19200000>, <19200000>; operating-points-v2 = <&mdp_opp_table>; @@ -2963,7 +2958,7 @@ }; }; - mdp_opp_table: mdp-opp-table { + mdp_opp_table: opp-table { compatible = "operating-points-v2"; opp-200000000 { @@ -3042,7 +3037,7 @@ }; }; - dsi_opp_table: dsi-opp-table { + dsi_opp_table: opp-table { compatible = "operating-points-v2"; opp-187500000 { @@ -3085,7 +3080,11 @@ compatible = "qcom,sc7180-dp"; status = "disabled"; - reg = <0 0x0ae90000 0 0x1400>; + reg = <0 0xae90000 0 0x200>, + <0 0xae90200 0 0x200>, + <0 0xae90400 0 0xc00>, + <0 0xae91000 0 0x400>, + <0 0xae91400 0 0x400>; interrupt-parent = <&mdss>; interrupts = <12>; @@ -3097,7 +3096,6 @@ <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; clock-names = "core_iface", "core_aux", "ctrl_link", "ctrl_link_iface", "stream_pixel"; - #clock-cells = <1>; assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>; @@ -3215,7 +3213,7 @@ }; aoss_qmp: power-controller@c300000 { - compatible = "qcom,sc7180-aoss-qmp"; + compatible = "qcom,sc7180-aoss-qmp", "qcom,aoss-qmp"; reg = <0 0x0c300000 0 0x400>; interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; mboxes = <&apss_shared 0>; @@ -3247,8 +3245,8 @@ cell-index = <0>; }; - imem@146aa000 { - compatible = "simple-mfd"; + sram@146aa000 { + compatible = "qcom,sc7180-imem", "syscon", "simple-mfd"; reg = <0 0x146aa000 0 0x2000>; #address-cells = <1>; @@ -3384,9 +3382,9 @@ }; timer@17c20000{ - #address-cells = <2>; - #size-cells = <2>; - ranges; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0x20000000>; compatible = "arm,armv7-timer-mem"; reg = <0 0x17c20000 0 0x1000>; @@ -3394,49 +3392,49 @@ frame-number = <0>; interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; - reg = <0 0x17c21000 0 0x1000>, - <0 0x17c22000 0 0x1000>; + reg = <0x17c21000 0x1000>, + <0x17c22000 0x1000>; }; frame@17c23000 { frame-number = <1>; interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; - reg = <0 0x17c23000 0 0x1000>; + reg = <0x17c23000 0x1000>; status = "disabled"; }; frame@17c25000 { frame-number = <2>; interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; - reg = <0 0x17c25000 0 0x1000>; + reg = <0x17c25000 0x1000>; status = "disabled"; }; frame@17c27000 { frame-number = <3>; interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; - reg = <0 0x17c27000 0 0x1000>; + reg = <0x17c27000 0x1000>; status = "disabled"; }; frame@17c29000 { frame-number = <4>; interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; - reg = <0 0x17c29000 0 0x1000>; + reg = <0x17c29000 0x1000>; status = "disabled"; }; frame@17c2b000 { frame-number = <5>; interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; - reg = <0 0x17c2b000 0 0x1000>; + reg = <0x17c2b000 0x1000>; status = "disabled"; }; frame@17c2d000 { frame-number = <6>; interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; - reg = <0 0x17c2d000 0 0x1000>; + reg = <0x17c2d000 0x1000>; status = "disabled"; }; }; @@ -3584,7 +3582,7 @@ compatible = "qcom,sc7180-lpass-cpu"; reg = <0 0x62d87000 0 0x68000>, <0 0x62f00000 0 0x29000>; - reg-names = "lpass-hdmiif", "lpass-lpaif"; + reg-names = "lpass-hdmiif", "lpass-lpaif"; iommus = <&apps_smmu 0x1020 0>, <&apps_smmu 0x1021 0>, diff --git a/arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi b/arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi index 9f4a9c263c35..cfe2741456a1 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi @@ -88,10 +88,26 @@ status = "okay"; compatible = "qcom,sc7280-mss-pil"; iommus = <&apps_smmu 0x124 0x0>, <&apps_smmu 0x488 0x7>; + interconnects = <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>; memory-region = <&mba_mem>, <&mpss_mem>; + firmware-name = "qcom/sc7280-herobrine/modem/mba.mbn", + "qcom/sc7280-herobrine/modem/qdsp6sw.mbn"; +}; + +&remoteproc_wpss { + status = "okay"; + firmware-name = "ath11k/WCN6750/hw1.0/wpss.mdt"; }; /* Increase the size from 2.5MB to 8MB */ &rmtfs_mem { reg = <0x0 0x9c900000 0x0 0x800000>; }; + +&wifi { + status = "okay"; + + wifi-firmware { + iommus = <&apps_smmu 0x1c02 0x1>; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-audio-wcd9385.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine-audio-wcd9385.dtsi new file mode 100644 index 000000000000..859faaa8b7e0 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-audio-wcd9385.dtsi @@ -0,0 +1,84 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * sc7280 device tree source for boards using Max98360 and wcd9385 codec + * + * Copyright (c) 2022, The Linux Foundation. All rights reserved. + */ + +/* PINCTRL */ + +&lpass_dmic01_clk { + drive-strength = <8>; + bias-disable; +}; + +&lpass_dmic01_clk_sleep { + drive-strength = <2>; +}; + +&lpass_dmic01_data { + bias-pull-down; +}; + +&lpass_dmic23_clk { + drive-strength = <8>; + bias-disable; +}; + +&lpass_dmic23_clk_sleep { + drive-strength = <2>; +}; + +&lpass_dmic23_data { + bias-pull-down; +}; + +&lpass_rx_swr_clk { + drive-strength = <2>; + slew-rate = <1>; + bias-disable; +}; + +&lpass_rx_swr_clk_sleep { + bias-pull-down; +}; + +&lpass_rx_swr_data { + drive-strength = <2>; + slew-rate = <1>; + bias-bus-hold; +}; + +&lpass_rx_swr_data_sleep { + bias-pull-down; +}; + +&lpass_tx_swr_clk { + drive-strength = <2>; + slew-rate = <1>; + bias-disable; +}; + +&lpass_tx_swr_clk_sleep { + bias-pull-down; +}; + +&lpass_tx_swr_data { + drive-strength = <2>; + slew-rate = <1>; + bias-bus-hold; +}; + +&mi2s1_data0 { + drive-strength = <6>; + bias-disable; +}; + +&mi2s1_sclk { + drive-strength = <6>; + bias-disable; +}; + +&mi2s1_ws { + drive-strength = <6>; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts b/arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts index a4ac33c4fd59..7881bbc641a0 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts @@ -8,6 +8,7 @@ /dts-v1/; #include "sc7280-herobrine.dtsi" +#include "sc7280-herobrine-audio-wcd9385.dtsi" / { model = "Qualcomm Technologies, Inc. sc7280 CRD platform (rev5+)"; @@ -134,6 +135,17 @@ ap_ts_pen_1v8: &i2c13 { status = "okay"; }; +/* PINCTRL - ADDITIONS TO NODES IN PARENT DEVICE TREE FILES */ + +/* + * This pin goes to the display panel but then doesn't actually do anything + * on the panel itself (it doesn't connect to the touchscreen controller). + * We'll set a pullup here just to park the line. + */ +&ts_rst_conn { + bias-pull-up; +}; + /* PINCTRL - BOARD-SPECIFIC */ /* diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r1.dts b/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r1.dts index b69ca09d9bfb..c1647a85a371 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r1.dts +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r1.dts @@ -128,6 +128,17 @@ ts_i2c: &i2c13 { status = "okay"; }; +/* PINCTRL - ADDITIONS TO NODES IN PARENT DEVICE TREE FILES */ + +/* + * This pin goes to the display panel but then doesn't actually do anything + * on the panel itself (it doesn't connect to the touchscreen controller). + * We'll set a pullup here just to park the line. + */ +&ts_rst_conn { + bias-pull-up; +}; + /* PINCTRL - BOARD-SPECIFIC */ /* diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-villager-r0.dts b/arch/arm64/boot/dts/qcom/sc7280-herobrine-villager-r0.dts index d3d6ffad4eff..2cacafd8faa8 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-villager-r0.dts +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-villager-r0.dts @@ -46,6 +46,25 @@ ap_tp_i2c: &i2c0 { }; }; +ts_i2c: &i2c13 { + status = "okay"; + clock-frequency = <400000>; + + ap_ts: touchscreen@10 { + compatible = "elan,ekth6915"; + reg = <0x10>; + pinctrl-names = "default"; + pinctrl-0 = <&ts_int_conn>, <&ts_rst_conn>; + + interrupt-parent = <&tlmm>; + interrupts = <55 IRQ_TYPE_LEVEL_LOW>; + + reset-gpios = <&tlmm 54 GPIO_ACTIVE_LOW>; + + vcc33-supply = <&ts_avdd>; + }; +}; + &ap_sar_sensor_i2c { status = "okay"; }; @@ -76,11 +95,21 @@ ap_tp_i2c: &i2c0 { status = "okay"; }; +&pwmleds { + status = "okay"; +}; + /* For eMMC */ &sdhc_1 { status = "okay"; }; +/* PINCTRL - ADDITIONS TO NODES IN PARENT DEVICE TREE FILES */ + +&ts_rst_conn { + bias-disable; +}; + /* PINCTRL - BOARD-SPECIFIC */ /* diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi index 9cb1bc8ed6b5..3f8996c00b05 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi @@ -15,6 +15,7 @@ #include <dt-bindings/input/gpio-keys.h> #include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> #include "sc7280-qcard.dtsi" #include "sc7280-chrome-common.dtsi" @@ -295,12 +296,12 @@ /* BOARD-SPECIFIC TOP LEVEL NODES */ - pwmleds { + pwmleds: pwmleds { compatible = "pwm-leds"; status = "disabled"; keyboard_backlight: keyboard-backlight { - status = "disabled"; label = "cros_ec::kbd_backlight"; + function = LED_FUNCTION_KBD_BACKLIGHT; pwms = <&cros_ec_pwm 0>; max-brightness = <1023>; }; @@ -388,7 +389,7 @@ ap_sar_sensor_i2c: &i2c1 { vdd-supply = <&pp1800_prox>; - label = "proximity-wifi-lte0"; + label = "proximity-wifi_cellular-0"; status = "disabled"; }; @@ -404,7 +405,7 @@ ap_sar_sensor_i2c: &i2c1 { vdd-supply = <&pp1800_prox>; - label = "proximity-wifi-lte1"; + label = "proximity-wifi_cellular-1"; status = "disabled"; }; }; @@ -429,6 +430,13 @@ ap_i2c_tpm: &i2c14 { status = "okay"; }; +&mdss_dp { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&dp_hot_plug_det>; + data-lanes = <0 1>; +}; + &mdss_mdp { status = "okay"; }; @@ -476,6 +484,10 @@ ap_i2c_tpm: &i2c14 { cd-gpios = <&tlmm 91 GPIO_ACTIVE_LOW>; }; +&spi_flash { + spi-max-frequency = <50000000>; +}; + /* Fingerprint, enabled on a per-board basis */ ap_spi_fp: &spi9 { pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs_gpio_init_high>, <&qup_spi9_cs_gpio>; diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi index 5eb668991e24..a74e0b730db6 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi @@ -27,7 +27,7 @@ pinctrl-names = "default"; pinctrl-0 = <&key_vol_up_default>; - volume-up { + key-volume-up { label = "volume_up"; gpios = <&pm7325_gpios 6 GPIO_ACTIVE_LOW>; linux,input-type = <1>; @@ -367,8 +367,84 @@ bias-disable; }; +&lpass_dmic01_clk { + drive-strength = <8>; + bias-disable; +}; + +&lpass_dmic01_clk_sleep { + drive-strength = <2>; +}; + +&lpass_dmic01_data { + bias-pull-down; +}; + +&lpass_dmic23_clk { + drive-strength = <8>; + bias-disable; +}; + +&lpass_dmic23_clk_sleep { + drive-strength = <2>; +}; + +&lpass_dmic23_data { + bias-pull-down; +}; + +&lpass_rx_swr_clk { + drive-strength = <2>; + slew-rate = <1>; + bias-disable; +}; + +&lpass_rx_swr_clk_sleep { + bias-pull-down; +}; + +&lpass_rx_swr_data { + drive-strength = <2>; + slew-rate = <1>; + bias-bus-hold; +}; + +&lpass_rx_swr_data_sleep { + bias-pull-down; +}; + +&lpass_tx_swr_clk { + drive-strength = <2>; + slew-rate = <1>; + bias-disable; +}; + +&lpass_tx_swr_clk_sleep { + bias-pull-down; +}; + +&lpass_tx_swr_data { + drive-strength = <2>; + slew-rate = <1>; + bias-bus-hold; +}; + +&mi2s1_data0 { + drive-strength = <6>; + bias-disable; +}; + +&mi2s1_sclk { + drive-strength = <6>; + bias-disable; +}; + +&mi2s1_ws { + drive-strength = <6>; +}; + &pm7325_gpios { - key_vol_up_default: key-vol-up-default { + key_vol_up_default: key-vol-up-state { pins = "gpio6"; function = "normal"; input-enable; @@ -560,14 +636,3 @@ bias-pull-down; }; }; - -&remoteproc_wpss { - status = "okay"; -}; - -&wifi { - status = "okay"; - wifi-firmware { - iommus = <&apps_smmu 0x1c02 0x1>; - }; -}; diff --git a/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi b/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi index d59002d4492e..7adf31bb9827 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi @@ -123,6 +123,12 @@ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; + vreg_l17b_1p8: ldo17 { + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <1900000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + vdd_px_wcd9385: vdd_txrx: vddpx_0: @@ -305,9 +311,6 @@ /* NOTE: Not all Qcards have eDP connector stuffed */ &mdss_edp { - vdda-0p9-supply = <&vdd_a_edp_0_0p9>; - vdda-1p2-supply = <&vdd_a_edp_0_1p2>; - aux-bus { edp_panel: panel { compatible = "edp-panel"; @@ -517,7 +520,7 @@ mos_bt_uart: &uart7 { */ &pm8350c_gpios { - pmic_edp_bl_en: pmic-edp-bl-en { + pmic_edp_bl_en: pmic-edp-bl-en-state { pins = "gpio7"; function = "normal"; bias-disable; @@ -527,7 +530,7 @@ mos_bt_uart: &uart7 { output-low; }; - pmic_edp_bl_pwm: pmic-edp-bl-pwm { + pmic_edp_bl_pwm: pmic-edp-bl-pwm-state { pins = "gpio8"; function = "func1"; bias-disable; @@ -604,7 +607,6 @@ mos_bt_uart: &uart7 { ts_rst_conn: ts-rst-conn { pins = "gpio54"; function = "gpio"; - bias-pull-up; drive-strength = <2>; }; }; diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index e66fc67de206..13d7f267b289 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -417,7 +417,7 @@ }; }; - cpu0_opp_table: cpu0-opp-table { + cpu0_opp_table: opp-table-cpu0 { compatible = "operating-points-v2"; opp-shared; @@ -477,7 +477,7 @@ }; }; - cpu4_opp_table: cpu4-opp-table { + cpu4_opp_table: opp-table-cpu4 { compatible = "operating-points-v2"; opp-shared; @@ -547,7 +547,7 @@ }; }; - cpu7_opp_table: cpu7-opp-table { + cpu7_opp_table: opp-table-cpu7 { compatible = "operating-points-v2"; opp-shared; @@ -763,7 +763,7 @@ method = "smc"; }; - qspi_opp_table: qspi-opp-table { + qspi_opp_table: opp-table-qspi { compatible = "operating-points-v2"; opp-75000000 { @@ -787,7 +787,7 @@ }; }; - qup_opp_table: qup-opp-table { + qup_opp_table: opp-table-qup { compatible = "operating-points-v2"; opp-75000000 { @@ -818,7 +818,7 @@ reg = <0 0x00100000 0 0x1f0000>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, - <0>, <&pcie1_lane 0>, + <0>, <&pcie1_lane>, <0>, <0>, <0>, <0>; clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", "pcie_0_pipe_clk", "pcie_1_pipe_clk", @@ -857,7 +857,7 @@ }; }; - sdhc_1: sdhci@7c4000 { + sdhc_1: mmc@7c4000 { compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&sdc1_clk>, <&sdc1_cmd>, <&sdc1_data>, <&sdc1_rclk>; @@ -873,10 +873,10 @@ <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "hc_irq", "pwr_irq"; - clocks = <&gcc GCC_SDCC1_APPS_CLK>, - <&gcc GCC_SDCC1_AHB_CLK>, + clocks = <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, <&rpmhcc RPMH_CXO_CLK>; - clock-names = "core", "iface", "xo"; + clock-names = "iface", "core", "xo"; interconnects = <&aggre1_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>, <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_1 0>; interconnect-names = "sdhc-ddr","cpu-sdhc"; @@ -2035,7 +2035,7 @@ clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, <&gcc GCC_PCIE_1_PIPE_CLK_SRC>, - <&pcie1_lane 0>, + <&pcie1_lane>, <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_PCIE_1_AUX_CLK>, <&gcc GCC_PCIE_1_CFG_AHB_CLK>, @@ -2110,7 +2110,7 @@ clock-names = "pipe0"; #phy-cells = <0>; - #clock-cells = <1>; + #clock-cells = <0>; clock-output-names = "pcie_1_pipe_clk"; }; }; @@ -2201,7 +2201,7 @@ lpasscore: clock-controller@3900000 { compatible = "qcom,sc7280-lpasscorecc"; reg = <0 0x03900000 0 0x50000>; - clocks = <&rpmhcc RPMH_CXO_CLK>; + clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "bi_tcxo"; power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>; #clock-cells = <1>; @@ -2224,6 +2224,98 @@ qcom,bcm-voters = <&apps_bcm_voter>; }; + lpass_tlmm: pinctrl@33c0000 { + compatible = "qcom,sc7280-lpass-lpi-pinctrl"; + reg = <0 0x033c0000 0x0 0x20000>, + <0 0x03550000 0x0 0x10000>; + qcom,adsp-bypass-mode; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&lpass_tlmm 0 0 15>; + + #clock-cells = <1>; + + lpass_dmic01_clk: dmic01-clk { + pins = "gpio6"; + function = "dmic1_clk"; + }; + + lpass_dmic01_clk_sleep: dmic01-clk-sleep { + pins = "gpio6"; + function = "dmic1_clk"; + }; + + lpass_dmic01_data: dmic01-data { + pins = "gpio7"; + function = "dmic1_data"; + }; + + lpass_dmic01_data_sleep: dmic01-data-sleep { + pins = "gpio7"; + function = "dmic1_data"; + }; + + lpass_dmic23_clk: dmic23-clk { + pins = "gpio8"; + function = "dmic2_clk"; + }; + + lpass_dmic23_clk_sleep: dmic23-clk-sleep { + pins = "gpio8"; + function = "dmic2_clk"; + }; + + lpass_dmic23_data: dmic23-data { + pins = "gpio9"; + function = "dmic2_data"; + }; + + lpass_dmic23_data_sleep: dmic23-data-sleep { + pins = "gpio9"; + function = "dmic2_data"; + }; + + lpass_rx_swr_clk: rx-swr-clk { + pins = "gpio3"; + function = "swr_rx_clk"; + }; + + lpass_rx_swr_clk_sleep: rx-swr-clk-sleep { + pins = "gpio3"; + function = "swr_rx_clk"; + }; + + lpass_rx_swr_data: rx-swr-data { + pins = "gpio4", "gpio5"; + function = "swr_rx_data"; + }; + + lpass_rx_swr_data_sleep: rx-swr-data-sleep { + pins = "gpio4", "gpio5"; + function = "swr_rx_data"; + }; + + lpass_tx_swr_clk: tx-swr-clk { + pins = "gpio0"; + function = "swr_tx_clk"; + }; + + lpass_tx_swr_clk_sleep: tx-swr-clk-sleep { + pins = "gpio0"; + function = "swr_tx_clk"; + }; + + lpass_tx_swr_data: tx-swr-data { + pins = "gpio1", "gpio2", "gpio14"; + function = "swr_tx_data"; + }; + + lpass_tx_swr_data_sleep: tx-swr-data-sleep { + pins = "gpio1", "gpio2", "gpio14"; + function = "swr_tx_data"; + }; + }; + gpu: gpu@3d00000 { compatible = "qcom,adreno-635.0", "qcom,adreno"; reg = <0 0x03d00000 0 0x40000>, @@ -2305,7 +2397,7 @@ }; gmu: gmu@3d6a000 { - compatible="qcom,adreno-gmu-635.0", "qcom,adreno-gmu"; + compatible = "qcom,adreno-gmu-635.0", "qcom,adreno-gmu"; reg = <0 0x03d6a000 0 0x34000>, <0 0x3de0000 0 0x10000>, <0 0x0b290000 0 0x10000>; @@ -2313,13 +2405,13 @@ interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "hfi", "gmu"; - clocks = <&gpucc 5>, - <&gpucc 8>, - <&gcc GCC_DDRSS_GPU_AXI_CLK>, - <&gcc GCC_GPU_MEMNOC_GFX_CLK>, - <&gpucc 2>, - <&gpucc 15>, - <&gpucc 11>; + clocks = <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_CXO_CLK>, + <&gcc GCC_DDRSS_GPU_AXI_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gpucc GPU_CC_AHB_CLK>, + <&gpucc GPU_CC_HUB_CX_INT_CLK>, + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; clock-names = "gmu", "cxo", "axi", @@ -2327,8 +2419,8 @@ "ahb", "hub", "smmu_vote"; - power-domains = <&gpucc 0>, - <&gpucc 1>; + power-domains = <&gpucc GPU_CC_CX_GDSC>, + <&gpucc GPU_CC_GX_GDSC>; power-domain-names = "cx", "gx"; iommus = <&adreno_smmu 5 0x400>; @@ -2377,12 +2469,12 @@ <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, - <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, - <&gpucc 2>, - <&gpucc 11>, - <&gpucc 5>, - <&gpucc 15>, - <&gpucc 13>; + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, + <&gpucc GPU_CC_AHB_CLK>, + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, + <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_HUB_CX_INT_CLK>, + <&gpucc GPU_CC_HUB_AON_CLK>; clock-names = "gcc_gpu_memnoc_gfx_clk", "gcc_gpu_snoc_dvm_gfx_clk", "gpu_cc_ahb_clk", @@ -2391,7 +2483,7 @@ "gpu_cc_hub_cx_int_clk", "gpu_cc_hub_aon_clk"; - power-domains = <&gpucc 0>; + power-domains = <&gpucc GPU_CC_CX_GDSC>; }; remoteproc_mpss: remoteproc@4080000 { @@ -2936,7 +3028,7 @@ }; }; - sdhc_2: sdhci@8804000 { + sdhc_2: mmc@8804000 { compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&sdc2_clk>, <&sdc2_cmd>, <&sdc2_data>; @@ -2950,10 +3042,10 @@ <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "hc_irq", "pwr_irq"; - clocks = <&gcc GCC_SDCC2_APPS_CLK>, - <&gcc GCC_SDCC2_AHB_CLK>, + clocks = <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, <&rpmhcc RPMH_CXO_CLK>; - clock-names = "core", "iface", "xo"; + clock-names = "iface", "core", "xo"; interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_2 0>; interconnect-names = "sdhc-ddr","cpu-sdhc"; @@ -3082,10 +3174,11 @@ assigned-clock-rates = <19200000>, <200000000>; interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, - <&pdc 13 IRQ_TYPE_EDGE_RISING>, - <&pdc 12 IRQ_TYPE_EDGE_RISING>; + <&pdc 12 IRQ_TYPE_EDGE_RISING>, + <&pdc 13 IRQ_TYPE_EDGE_RISING>; interrupt-names = "hs_phy_irq", - "dm_hs_phy_irq", "dp_hs_phy_irq"; + "dp_hs_phy_irq", + "dm_hs_phy_irq"; power-domains = <&gcc GCC_USB30_SEC_GDSC>; @@ -3265,13 +3358,13 @@ assigned-clock-rates = <19200000>, <200000000>; interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, - <&pdc 17 IRQ_TYPE_EDGE_BOTH>, + <&pdc 14 IRQ_TYPE_LEVEL_HIGH>, <&pdc 15 IRQ_TYPE_EDGE_BOTH>, - <&pdc 14 IRQ_TYPE_LEVEL_HIGH>; + <&pdc 17 IRQ_TYPE_EDGE_BOTH>; interrupt-names = "hs_phy_irq", - "ss_phy_irq", + "dp_hs_phy_irq", "dm_hs_phy_irq", - "dp_hs_phy_irq"; + "ss_phy_irq"; power-domains = <&gcc GCC_USB30_PRIM_GDSC>; @@ -3334,7 +3427,7 @@ iommus = <&apps_smmu 0x21a2 0x0>; }; - venus_opp_table: venus-opp-table { + venus_opp_table: opp-table { compatible = "operating-points-v2"; opp-133330000 { @@ -3426,9 +3519,6 @@ "ahb", "core"; - assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; - assigned-clock-rates = <300000000>; - interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; interrupt-controller; #interrupt-cells = <1>; @@ -3462,11 +3552,9 @@ "lut", "core", "vsync"; - assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, - <&dispcc DISP_CC_MDSS_VSYNC_CLK>, + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>, <&dispcc DISP_CC_MDSS_AHB_CLK>; - assigned-clock-rates = <300000000>, - <19200000>, + assigned-clock-rates = <19200000>, <19200000>; operating-points-v2 = <&mdp_opp_table>; power-domains = <&rpmhpd SC7280_CX>; @@ -3629,21 +3717,16 @@ interrupt-parent = <&mdss>; interrupts = <14>; - clocks = <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_EDP_CLKREF_EN>, - <&dispcc DISP_CC_MDSS_AHB_CLK>, + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, <&dispcc DISP_CC_MDSS_EDP_AUX_CLK>, <&dispcc DISP_CC_MDSS_EDP_LINK_CLK>, <&dispcc DISP_CC_MDSS_EDP_LINK_INTF_CLK>, <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK>; - clock-names = "core_xo", - "core_ref", - "core_iface", + clock-names = "core_iface", "core_aux", "ctrl_link", "ctrl_link_iface", "stream_pixel"; - #clock-cells = <1>; assigned-clocks = <&dispcc DISP_CC_MDSS_EDP_LINK_CLK_SRC>, <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK_SRC>; assigned-clock-parents = <&mdss_edp_phy 0>, <&mdss_edp_phy 1>; @@ -3654,9 +3737,6 @@ operating-points-v2 = <&edp_opp_table>; power-domains = <&rpmhpd SC7280_CX>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; ports { @@ -3723,7 +3803,11 @@ mdss_dp: displayport-controller@ae90000 { compatible = "qcom,sc7280-dp"; - reg = <0 0x0ae90000 0 0x1400>; + reg = <0 0xae90000 0 0x200>, + <0 0xae90200 0 0x200>, + <0 0xae90400 0 0xc00>, + <0 0xae91000 0 0x400>, + <0 0xae91400 0 0x400>; interrupt-parent = <&mdss>; interrupts = <12>; @@ -3733,12 +3817,11 @@ <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; - clock-names = "core_iface", + clock-names = "core_iface", "core_aux", "ctrl_link", "ctrl_link_iface", "stream_pixel"; - #clock-cells = <1>; assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>; @@ -3843,7 +3926,7 @@ }; aoss_qmp: power-controller@c300000 { - compatible = "qcom,sc7280-aoss-qmp"; + compatible = "qcom,sc7280-aoss-qmp", "qcom,aoss-qmp"; reg = <0 0x0c300000 0 0x400>; interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP @@ -3898,6 +3981,46 @@ function = "edp_hot"; }; + mi2s0_data0: mi2s0-data0 { + pins = "gpio98"; + function = "mi2s0_data0"; + }; + + mi2s0_data1: mi2s0-data1 { + pins = "gpio99"; + function = "mi2s0_data1"; + }; + + mi2s0_mclk: mi2s0-mclk { + pins = "gpio96"; + function = "pri_mi2s"; + }; + + mi2s0_sclk: mi2s0-sclk { + pins = "gpio97"; + function = "mi2s0_sck"; + }; + + mi2s0_ws: mi2s0-ws { + pins = "gpio100"; + function = "mi2s0_ws"; + }; + + mi2s1_data0: mi2s1-data0 { + pins = "gpio107"; + function = "mi2s1_data0"; + }; + + mi2s1_sclk: mi2s1-sclk { + pins = "gpio106"; + function = "mi2s1_sck"; + }; + + mi2s1_ws: mi2s1-ws { + pins = "gpio108"; + function = "mi2s1_ws"; + }; + pcie1_clkreq_n: pcie1-clkreq-n { pins = "gpio79"; function = "pcie1_clkreqn"; @@ -4639,8 +4762,8 @@ }; }; - imem@146a5000 { - compatible = "qcom,sc7280-imem", "syscon"; + sram@146a5000 { + compatible = "qcom,sc7280-imem", "syscon", "simple-mfd"; reg = <0 0x146a5000 0 0x6000>; #address-cells = <1>; @@ -4771,9 +4894,9 @@ }; timer@17c20000 { - #address-cells = <2>; - #size-cells = <2>; - ranges; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0x20000000>; compatible = "arm,armv7-timer-mem"; reg = <0 0x17c20000 0 0x1000>; @@ -4781,49 +4904,49 @@ frame-number = <0>; interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; - reg = <0 0x17c21000 0 0x1000>, - <0 0x17c22000 0 0x1000>; + reg = <0x17c21000 0x1000>, + <0x17c22000 0x1000>; }; frame@17c23000 { frame-number = <1>; interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; - reg = <0 0x17c23000 0 0x1000>; + reg = <0x17c23000 0x1000>; status = "disabled"; }; frame@17c25000 { frame-number = <2>; interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; - reg = <0 0x17c25000 0 0x1000>; + reg = <0x17c25000 0x1000>; status = "disabled"; }; frame@17c27000 { frame-number = <3>; interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; - reg = <0 0x17c27000 0 0x1000>; + reg = <0x17c27000 0x1000>; status = "disabled"; }; frame@17c29000 { frame-number = <4>; interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; - reg = <0 0x17c29000 0 0x1000>; + reg = <0x17c29000 0x1000>; status = "disabled"; }; frame@17c2b000 { frame-number = <5>; interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; - reg = <0 0x17c2b000 0 0x1000>; + reg = <0x17c2b000 0x1000>; status = "disabled"; }; frame@17c2d000 { frame-number = <6>; interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; - reg = <0 0x17c2d000 0 0x1000>; + reg = <0x17c2d000 0x1000>; status = "disabled"; }; }; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts new file mode 100644 index 000000000000..45058ad0a1c8 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts @@ -0,0 +1,427 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2022, Linaro Limited + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/regulator/qcom,rpmh-regulator.h> + +#include "sc8280xp.dtsi" +#include "sc8280xp-pmics.dtsi" + +/ { + model = "Qualcomm SC8280XP CRD"; + compatible = "qcom,sc8280xp-crd", "qcom,sc8280xp"; + + aliases { + serial0 = &qup2_uart17; + }; + + backlight { + compatible = "pwm-backlight"; + pwms = <&pmc8280c_lpg 3 1000000>; + enable-gpios = <&pmc8280_1_gpios 8 GPIO_ACTIVE_HIGH>; + power-supply = <&vreg_edp_bl>; + + pinctrl-names = "default"; + pinctrl-0 = <&edp_bl_en>, <&edp_bl_pwm>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + vreg_edp_bl: regulator-edp-bl { + compatible = "regulator-fixed"; + + regulator-name = "VREG_EDP_BL"; + regulator-min-microvolt = <3600000>; + regulator-max-microvolt = <3600000>; + + gpio = <&pmc8280_1_gpios 9 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&edp_bl_reg_en>; + + regulator-boot-on; + }; + + vreg_misc_3p3: regulator-misc-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_MISC_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&pmc8280_1_gpios 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&misc_3p3_reg_en>; + + regulator-boot-on; + regulator-always-on; + }; +}; + +&apps_rsc { + pmc8280-1-rpmh-regulators { + compatible = "qcom,pm8350-rpmh-regulators"; + qcom,pmic-id = "b"; + + vdd-l3-l5-supply = <&vreg_s11b>; + + vreg_s11b: smps11 { + regulator-name = "vreg_s11b"; + regulator-min-microvolt = <1272000>; + regulator-max-microvolt = <1272000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l3b: ldo3 { + regulator-name = "vreg_l3b"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-boot-on; + regulator-always-on; + }; + + vreg_l4b: ldo4 { + regulator-name = "vreg_l4b"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + }; + + vreg_l6b: ldo6 { + regulator-name = "vreg_l6b"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-boot-on; + }; + }; + + pmc8280c-rpmh-regulators { + compatible = "qcom,pm8350c-rpmh-regulators"; + qcom,pmic-id = "c"; + + vreg_l1c: ldo1 { + regulator-name = "vreg_l1c"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + }; + + vreg_l7c: ldo7 { + regulator-name = "vreg_l7c"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <2504000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + }; + + vreg_l13c: ldo13 { + regulator-name = "vreg_l13c"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + }; + }; + + pmc8280-2-rpmh-regulators { + compatible = "qcom,pm8350-rpmh-regulators"; + qcom,pmic-id = "d"; + + vdd-l1-l4-supply = <&vreg_s11b>; + + vreg_l3d: ldo3 { + regulator-name = "vreg_l3d"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + }; + + vreg_l4d: ldo4 { + regulator-name = "vreg_l4d"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + }; + + vreg_l6d: ldo6 { + regulator-name = "vreg_l6d"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + }; + + vreg_l7d: ldo7 { + regulator-name = "vreg_l7d"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + }; + + vreg_l9d: ldo9 { + regulator-name = "vreg_l9d"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + }; + }; +}; + +&pmc8280c_lpg { + status = "okay"; +}; + +&pmk8280_pon_pwrkey { + status = "okay"; +}; + +&qup0 { + status = "okay"; +}; + +&qup0_i2c4 { + clock-frequency = <400000>; + + pinctrl-names = "default"; + pinctrl-0 = <&qup0_i2c4_default>, <&ts0_default>; + + status = "okay"; + + touchscreen@10 { + compatible = "hid-over-i2c"; + reg = <0x10>; + hid-descr-addr = <0x1>; + interrupts-extended = <&tlmm 175 IRQ_TYPE_LEVEL_LOW>; + vdd-supply = <&vreg_misc_3p3>; + }; +}; + +&qup1 { + status = "okay"; +}; + +&qup2 { + status = "okay"; +}; + +&qup2_i2c5 { + clock-frequency = <400000>; + + pinctrl-names = "default"; + pinctrl-0 = <&qup2_i2c5_default>, <&kybd_default>, <&tpad_default>; + + status = "okay"; + + touchpad@15 { + compatible = "hid-over-i2c"; + reg = <0x15>; + hid-descr-addr = <0x1>; + interrupts-extended = <&tlmm 182 IRQ_TYPE_LEVEL_LOW>; + vdd-supply = <&vreg_misc_3p3>; + }; + + keyboard@68 { + compatible = "hid-over-i2c"; + reg = <0x68>; + hid-descr-addr = <0x1>; + interrupts-extended = <&tlmm 104 IRQ_TYPE_LEVEL_LOW>; + vdd-supply = <&vreg_misc_3p3>; + }; +}; + +&qup2_uart17 { + compatible = "qcom,geni-debug-uart"; + + status = "okay"; +}; + +&remoteproc_adsp { + firmware-name = "qcom/sc8280xp/qcadsp8280.mbn"; + + status = "okay"; +}; + +&remoteproc_nsp0 { + firmware-name = "qcom/sc8280xp/qccdsp8280.mbn"; + + status = "okay"; +}; + +&ufs_mem_hc { + reset-gpios = <&tlmm 228 GPIO_ACTIVE_LOW>; + + vcc-supply = <&vreg_l7c>; + vcc-max-microamp = <800000>; + vccq-supply = <&vreg_l3d>; + vccq-max-microamp = <900000>; + + status = "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply = <&vreg_l6b>; + vdda-pll-supply = <&vreg_l3b>; + + status = "okay"; +}; + +&usb_0 { + status = "okay"; +}; + +&usb_0_dwc3 { + /* TODO: Define USB-C connector properly */ + dr_mode = "host"; +}; + +&usb_0_hsphy { + vdda-pll-supply = <&vreg_l9d>; + vdda18-supply = <&vreg_l1c>; + vdda33-supply = <&vreg_l7d>; + + status = "okay"; +}; + +&usb_0_qmpphy { + vdda-phy-supply = <&vreg_l9d>; + vdda-pll-supply = <&vreg_l4d>; + + status = "okay"; +}; + +&usb_1 { + status = "okay"; +}; + +&usb_1_dwc3 { + /* TODO: Define USB-C connector properly */ + dr_mode = "host"; +}; + +&usb_1_hsphy { + vdda-pll-supply = <&vreg_l4b>; + vdda18-supply = <&vreg_l1c>; + vdda33-supply = <&vreg_l13c>; + + status = "okay"; +}; + +&usb_1_qmpphy { + vdda-phy-supply = <&vreg_l4b>; + vdda-pll-supply = <&vreg_l3b>; + + status = "okay"; +}; + +&xo_board_clk { + clock-frequency = <38400000>; +}; + +/* PINCTRL - additions to nodes defined in sc8280xp.dtsi */ + +&pmc8280_1_gpios { + edp_bl_en: edp-bl-en-state { + pins = "gpio8"; + function = "normal"; + }; + + edp_bl_reg_en: edp-bl-reg-en-state { + pins = "gpio9"; + function = "normal"; + }; + + misc_3p3_reg_en: misc-3p3-reg-en-state { + pins = "gpio1"; + function = "normal"; + }; +}; + +&pmc8280c_gpios { + edp_bl_pwm: edp-bl-pwm-state { + pins = "gpio8"; + function = "func1"; + }; +}; + +&tlmm { + gpio-reserved-ranges = <74 6>, <83 4>, <125 2>, <128 2>, <154 7>; + + kybd_default: kybd-default-state { + disable { + pins = "gpio102"; + function = "gpio"; + output-low; + }; + + int-n { + pins = "gpio104"; + function = "gpio"; + bias-disable; + }; + + reset { + pins = "gpio105"; + function = "gpio"; + bias-disable; + }; + }; + + qup0_i2c4_default: qup0-i2c4-default-state { + pins = "gpio171", "gpio172"; + function = "qup4"; + + bias-disable; + drive-strength = <16>; + }; + + qup2_i2c5_default: qup2-i2c5-default-state { + pins = "gpio81", "gpio82"; + function = "qup21"; + + bias-disable; + drive-strength = <16>; + }; + + tpad_default: tpad-default-state { + int-n { + pins = "gpio182"; + function = "gpio"; + bias-disable; + }; + }; + + ts0_default: ts0-default-state { + int-n { + pins = "gpio175"; + function = "gpio"; + bias-pull-up; + }; + + reset-n { + pins = "gpio99"; + function = "gpio"; + output-high; + drive-strength = <16>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts new file mode 100644 index 000000000000..84dc92dda0b8 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts @@ -0,0 +1,386 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2022, Linaro Limited + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/regulator/qcom,rpmh-regulator.h> + +#include "sc8280xp.dtsi" +#include "sc8280xp-pmics.dtsi" + +/ { + model = "Lenovo ThinkPad X13s"; + compatible = "lenovo,thinkpad-x13s", "qcom,sc8280xp"; + + backlight { + compatible = "pwm-backlight"; + pwms = <&pmc8280c_lpg 3 1000000>; + enable-gpios = <&pmc8280_1_gpios 8 GPIO_ACTIVE_HIGH>; + power-supply = <&vreg_edp_bl>; + + pinctrl-names = "default"; + pinctrl-0 = <&edp_bl_en>, <&edp_bl_pwm>; + }; + + vreg_edp_bl: regulator-edp-bl { + compatible = "regulator-fixed"; + + regulator-name = "VBL9"; + regulator-min-microvolt = <3600000>; + regulator-max-microvolt = <3600000>; + + gpio = <&pmc8280_1_gpios 9 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&edp_bl_reg_en>; + + regulator-boot-on; + }; + + vreg_misc_3p3: regulator-misc-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VCC3B"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&pmc8280_1_gpios 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&misc_3p3_reg_en>; + + regulator-boot-on; + regulator-always-on; + }; +}; + +&apps_rsc { + pmc8280-1-rpmh-regulators { + compatible = "qcom,pm8350-rpmh-regulators"; + qcom,pmic-id = "b"; + + vdd-l3-l5-supply = <&vreg_s11b>; + + vreg_s11b: smps11 { + regulator-name = "vreg_s11b"; + regulator-min-microvolt = <1272000>; + regulator-max-microvolt = <1272000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l3b: ldo3 { + regulator-name = "vreg_l3b"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-boot-on; + }; + + vreg_l4b: ldo4 { + regulator-name = "vreg_l4b"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + }; + + vreg_l6b: ldo6 { + regulator-name = "vreg_l6b"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-boot-on; + regulator-always-on; // FIXME: VDD_A_EDP_0_0P9 + }; + }; + + pmc8280c-rpmh-regulators { + compatible = "qcom,pm8350c-rpmh-regulators"; + qcom,pmic-id = "c"; + + vreg_l1c: ldo1 { + regulator-name = "vreg_l1c"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + }; + + vreg_l12c: ldo12 { + regulator-name = "vreg_l12c"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + }; + + vreg_l13c: ldo13 { + regulator-name = "vreg_l13c"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + }; + }; + + pmc8280-2-rpmh-regulators { + compatible = "qcom,pm8350-rpmh-regulators"; + qcom,pmic-id = "d"; + + vdd-l1-l4-supply = <&vreg_s11b>; + + vreg_l3d: ldo3 { + regulator-name = "vreg_l3d"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + }; + + vreg_l4d: ldo4 { + regulator-name = "vreg_l4d"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + }; + + vreg_l7d: ldo7 { + regulator-name = "vreg_l7d"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + }; + + vreg_l9d: ldo9 { + regulator-name = "vreg_l9d"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + }; + }; +}; + +&pmc8280c_lpg { + status = "okay"; +}; + +&pmk8280_pon_pwrkey { + status = "okay"; +}; + +&qup0 { + status = "okay"; +}; + +&qup0_i2c4 { + clock-frequency = <400000>; + + pinctrl-names = "default"; + pinctrl-0 = <&qup0_i2c4_default>, <&ts0_default>; + + status = "okay"; + + /* FIXME: verify */ + touchscreen@10 { + compatible = "hid-over-i2c"; + reg = <0x10>; + hid-descr-addr = <0x1>; + interrupts-extended = <&tlmm 175 IRQ_TYPE_LEVEL_LOW>; + vdd-supply = <&vreg_misc_3p3>; + }; +}; + +&qup1 { + status = "okay"; +}; + +&qup2 { + status = "okay"; +}; + +&qup2_i2c5 { + clock-frequency = <400000>; + + pinctrl-names = "default"; + pinctrl-0 = <&qup2_i2c5_default>, <&kybd_default>, <&tpad_default>; + + status = "okay"; + + touchpad@2c { + compatible = "hid-over-i2c"; + reg = <0x2c>; + hid-descr-addr = <0x20>; + interrupts-extended = <&tlmm 182 IRQ_TYPE_LEVEL_LOW>; + vdd-supply = <&vreg_misc_3p3>; + }; + + keyboard@68 { + compatible = "hid-over-i2c"; + reg = <0x68>; + hid-descr-addr = <0x1>; + interrupts-extended = <&tlmm 104 IRQ_TYPE_LEVEL_LOW>; + vdd-supply = <&vreg_misc_3p3>; + }; +}; + +&remoteproc_adsp { + firmware-name = "qcom/sc8280xp/qcadsp8280.mbn"; + + status = "okay"; +}; + +&remoteproc_nsp0 { + firmware-name = "qcom/sc8280xp/qccdsp8280.mbn"; + + status = "okay"; +}; + +&usb_0 { + status = "okay"; +}; + +&usb_0_dwc3 { + /* TODO: Define USB-C connector properly */ + dr_mode = "host"; +}; + +&usb_0_hsphy { + vdda-pll-supply = <&vreg_l9d>; + vdda18-supply = <&vreg_l1c>; + vdda33-supply = <&vreg_l7d>; + + status = "okay"; +}; + +&usb_0_qmpphy { + vdda-phy-supply = <&vreg_l9d>; + vdda-pll-supply = <&vreg_l4d>; + + status = "okay"; +}; + +&usb_1 { + status = "okay"; +}; + +&usb_1_dwc3 { + /* TODO: Define USB-C connector properly */ + dr_mode = "host"; +}; + +&usb_1_hsphy { + vdda-pll-supply = <&vreg_l4b>; + vdda18-supply = <&vreg_l1c>; + vdda33-supply = <&vreg_l13c>; + + status = "okay"; +}; + +&usb_1_qmpphy { + vdda-phy-supply = <&vreg_l4b>; + vdda-pll-supply = <&vreg_l3b>; + + status = "okay"; +}; + +&xo_board_clk { + clock-frequency = <38400000>; +}; + +/* PINCTRL */ + +&pmc8280_1_gpios { + edp_bl_en: edp-bl-en-state { + pins = "gpio8"; + function = "normal"; + }; + + edp_bl_reg_en: edp-bl-reg-en-state { + pins = "gpio9"; + function = "normal"; + }; + + misc_3p3_reg_en: misc-3p3-reg-en-state { + pins = "gpio1"; + function = "normal"; + }; +}; + +&pmc8280c_gpios { + edp_bl_pwm: edp-bl-pwm-state { + pins = "gpio8"; + function = "func1"; + }; +}; + +&tlmm { + gpio-reserved-ranges = <70 2>, <74 6>, <83 4>, <125 2>, <128 2>, <154 7>; + + kybd_default: kybd-default-state { + disable { + pins = "gpio102"; + function = "gpio"; + output-low; + }; + + int-n { + pins = "gpio104"; + function = "gpio"; + bias-disable; + }; + + reset { + pins = "gpio105"; + function = "gpio"; + bias-disable; + }; + }; + + qup0_i2c4_default: qup0-i2c4-default-state { + pins = "gpio171", "gpio172"; + function = "qup4"; + bias-disable; + drive-strength = <16>; + }; + + qup2_i2c5_default: qup2-i2c5-default-state { + pins = "gpio81", "gpio82"; + function = "qup21"; + bias-disable; + drive-strength = <16>; + }; + + tpad_default: tpad-default-state { + int-n { + pins = "gpio182"; + function = "gpio"; + bias-disable; + }; + }; + + ts0_default: ts0-default-state { + int-n { + pins = "gpio175"; + function = "gpio"; + bias-pull-up; + }; + + reset-n { + pins = "gpio99"; + function = "gpio"; + output-high; + drive-strength = <16>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi new file mode 100644 index 000000000000..ae90b97aecb8 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi @@ -0,0 +1,109 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022, Linaro Limited + */ + +#include <dt-bindings/input/input.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/spmi/spmi.h> + +&spmi_bus { + pmk8280: pmic@0 { + compatible = "qcom,pmk8350", "qcom,spmi-pmic"; + reg = <0x0 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmk8280_pon: pon@1300 { + compatible = "qcom,pm8998-pon"; + reg = <0x1300>; + + pmk8280_pon_pwrkey: pwrkey { + compatible = "qcom,pmk8350-pwrkey"; + interrupts = <0x0 0x13 0x7 IRQ_TYPE_EDGE_BOTH>; + linux,code = <KEY_POWER>; + status = "disabled"; + }; + }; + }; + + pmc8280_1: pmic@1 { + compatible = "qcom,pm8350", "qcom,spmi-pmic"; + reg = <0x1 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmc8280_1_gpios: gpio@8800 { + compatible = "qcom,pm8350-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pmc8280_1_gpios 0 0 10>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + pmc8280c: pmic@2 { + compatible = "qcom,pm8350c", "qcom,spmi-pmic"; + reg = <0x2 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmc8280c_gpios: gpio@8800 { + compatible = "qcom,pm8350c-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pmc8280c_gpios 0 0 9>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + pmc8280c_lpg: lpg@e800 { + compatible = "qcom,pm8350c-pwm"; + reg = <0xe800>; + + #address-cells = <1>; + #size-cells = <0>; + + #pwm-cells = <2>; + + status = "disabled"; + }; + }; + + pmc8280_2: pmic@3 { + compatible = "qcom,pm8350", "qcom,spmi-pmic"; + reg = <0x3 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmc8280_2_gpios: gpio@8800 { + compatible = "qcom,pm8350-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pmc8280_2_gpios 0 0 10>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + pmr735a: pmic@4 { + compatible = "qcom,pmr735a", "qcom,spmi-pmic"; + reg = <0x4 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmr735a_gpios: gpio@8800 { + compatible = "qcom,pmr735a-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pmr735a_gpios 0 0 4>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi new file mode 100644 index 000000000000..49ea8b5612fc --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -0,0 +1,2147 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2022, Linaro Limited + */ + +#include <dt-bindings/clock/qcom,gcc-sc8280xp.h> +#include <dt-bindings/clock/qcom,rpmh.h> +#include <dt-bindings/interconnect/qcom,sc8280xp.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/mailbox/qcom-ipcc.h> +#include <dt-bindings/power/qcom-rpmpd.h> +#include <dt-bindings/soc/qcom,rpmh-rsc.h> +#include <dt-bindings/thermal/thermal.h> + +/ { + interrupt-parent = <&intc>; + + #address-cells = <2>; + #size-cells = <2>; + + clocks { + xo_board_clk: xo-board-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32764>; + }; + }; + + cpu0_opp_table: cpu0-opp-table { + compatible = "operating-points-v2"; + opp-shared; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + }; + opp-403200000 { + opp-hz = /bits/ 64 <403200000>; + }; + opp-499200000 { + opp-hz = /bits/ 64 <499200000>; + }; + opp-595200000 { + opp-hz = /bits/ 64 <595200000>; + }; + opp-691200000 { + opp-hz = /bits/ 64 <691200000>; + }; + opp-806400000 { + opp-hz = /bits/ 64 <806400000>; + }; + opp-902400000 { + opp-hz = /bits/ 64 <902400000>; + }; + opp-1017600000 { + opp-hz = /bits/ 64 <1017600000>; + }; + opp-1113600000 { + opp-hz = /bits/ 64 <1113600000>; + }; + opp-1209600000 { + opp-hz = /bits/ 64 <1209600000>; + }; + opp-1324800000 { + opp-hz = /bits/ 64 <1324800000>; + }; + opp-1440000000 { + opp-hz = /bits/ 64 <1440000000>; + }; + opp-1555200000 { + opp-hz = /bits/ 64 <1555200000>; + }; + opp-1670400000 { + opp-hz = /bits/ 64 <1670400000>; + }; + opp-1785600000 { + opp-hz = /bits/ 64 <1785600000>; + }; + opp-1881600000 { + opp-hz = /bits/ 64 <1881600000>; + }; + opp-1996800000 { + opp-hz = /bits/ 64 <1996800000>; + }; + opp-2112000000 { + opp-hz = /bits/ 64 <2112000000>; + }; + opp-2227200000 { + opp-hz = /bits/ 64 <2227200000>; + }; + opp-2342400000 { + opp-hz = /bits/ 64 <2342400000>; + }; + opp-2438400000 { + opp-hz = /bits/ 64 <2438400000>; + }; + }; + + cpu4_opp_table: cpu4-opp-table { + compatible = "operating-points-v2"; + opp-shared; + + opp-825600000 { + opp-hz = /bits/ 64 <825600000>; + }; + opp-940800000 { + opp-hz = /bits/ 64 <940800000>; + }; + opp-1056000000 { + opp-hz = /bits/ 64 <1056000000>; + }; + opp-1171200000 { + opp-hz = /bits/ 64 <1171200000>; + }; + opp-1286400000 { + opp-hz = /bits/ 64 <1286400000>; + }; + opp-1401600000 { + opp-hz = /bits/ 64 <1401600000>; + }; + opp-1516800000 { + opp-hz = /bits/ 64 <1516800000>; + }; + opp-1632000000 { + opp-hz = /bits/ 64 <1632000000>; + }; + opp-1747200000 { + opp-hz = /bits/ 64 <1747200000>; + }; + opp-1862400000 { + opp-hz = /bits/ 64 <1862400000>; + }; + opp-1977600000 { + opp-hz = /bits/ 64 <1977600000>; + }; + opp-2073600000 { + opp-hz = /bits/ 64 <2073600000>; + }; + opp-2169600000 { + opp-hz = /bits/ 64 <2169600000>; + }; + opp-2284800000 { + opp-hz = /bits/ 64 <2284800000>; + }; + opp-2400000000 { + opp-hz = /bits/ 64 <2400000000>; + }; + opp-2496000000 { + opp-hz = /bits/ 64 <2496000000>; + }; + opp-2592000000 { + opp-hz = /bits/ 64 <2592000000>; + }; + opp-2688000000 { + opp-hz = /bits/ 64 <2688000000>; + }; + opp-2803200000 { + opp-hz = /bits/ 64 <2803200000>; + }; + opp-2899200000 { + opp-hz = /bits/ 64 <2899200000>; + }; + opp-2995200000 { + opp-hz = /bits/ 64 <2995200000>; + }; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x0>; + enable-method = "psci"; + capacity-dmips-mhz = <602>; + next-level-cache = <&L2_0>; + power-domains = <&CPU_PD0>; + power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 0>; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; + L2_0: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + L3_0: l3-cache { + compatible = "cache"; + }; + }; + }; + + CPU1: cpu@100 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x100>; + enable-method = "psci"; + capacity-dmips-mhz = <602>; + next-level-cache = <&L2_100>; + power-domains = <&CPU_PD1>; + power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 0>; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; + L2_100: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU2: cpu@200 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x200>; + enable-method = "psci"; + capacity-dmips-mhz = <602>; + next-level-cache = <&L2_200>; + power-domains = <&CPU_PD2>; + power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 0>; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; + L2_200: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU3: cpu@300 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x300>; + enable-method = "psci"; + capacity-dmips-mhz = <602>; + next-level-cache = <&L2_300>; + power-domains = <&CPU_PD3>; + power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 0>; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; + L2_300: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU4: cpu@400 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x400>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + next-level-cache = <&L2_400>; + power-domains = <&CPU_PD4>; + power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 1>; + operating-points-v2 = <&cpu4_opp_table>; + #cooling-cells = <2>; + L2_400: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU5: cpu@500 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x500>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + next-level-cache = <&L2_500>; + power-domains = <&CPU_PD5>; + power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 1>; + operating-points-v2 = <&cpu4_opp_table>; + #cooling-cells = <2>; + L2_500: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU6: cpu@600 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x600>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + next-level-cache = <&L2_600>; + power-domains = <&CPU_PD6>; + power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 1>; + operating-points-v2 = <&cpu4_opp_table>; + #cooling-cells = <2>; + L2_600: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU7: cpu@700 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x700>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + next-level-cache = <&L2_700>; + power-domains = <&CPU_PD7>; + power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 1>; + operating-points-v2 = <&cpu4_opp_table>; + #cooling-cells = <2>; + L2_700: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + + core1 { + cpu = <&CPU1>; + }; + + core2 { + cpu = <&CPU2>; + }; + + core3 { + cpu = <&CPU3>; + }; + + core4 { + cpu = <&CPU4>; + }; + + core5 { + cpu = <&CPU5>; + }; + + core6 { + cpu = <&CPU6>; + }; + + core7 { + cpu = <&CPU7>; + }; + }; + }; + + idle-states { + entry-method = "psci"; + + LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { + compatible = "arm,idle-state"; + idle-state-name = "little-rail-power-collapse"; + arm,psci-suspend-param = <0x40000004>; + entry-latency-us = <355>; + exit-latency-us = <909>; + min-residency-us = <3934>; + local-timer-stop; + }; + + BIG_CPU_SLEEP_0: cpu-sleep-1-0 { + compatible = "arm,idle-state"; + idle-state-name = "big-rail-power-collapse"; + arm,psci-suspend-param = <0x40000004>; + entry-latency-us = <241>; + exit-latency-us = <1461>; + min-residency-us = <4488>; + local-timer-stop; + }; + }; + + domain-idle-states { + CLUSTER_SLEEP_0: cluster-sleep-0 { + compatible = "domain-idle-state"; + idle-state-name = "cluster-power-collapse"; + arm,psci-suspend-param = <0x4100c344>; + entry-latency-us = <3263>; + exit-latency-us = <6562>; + min-residency-us = <9987>; + }; + }; + }; + + firmware { + scm: scm { + compatible = "qcom,scm-sc8280xp", "qcom,scm"; + }; + }; + + aggre1_noc: interconnect-aggre1-noc { + compatible = "qcom,sc8280xp-aggre1-noc"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + aggre2_noc: interconnect-aggre2-noc { + compatible = "qcom,sc8280xp-aggre2-noc"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + clk_virt: interconnect-clk-virt { + compatible = "qcom,sc8280xp-clk-virt"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + config_noc: interconnect-config-noc { + compatible = "qcom,sc8280xp-config-noc"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + dc_noc: interconnect-dc-noc { + compatible = "qcom,sc8280xp-dc-noc"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + gem_noc: interconnect-gem-noc { + compatible = "qcom,sc8280xp-gem-noc"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + lpass_noc: interconnect-lpass-ag-noc { + compatible = "qcom,sc8280xp-lpass-ag-noc"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + mc_virt: interconnect-mc-virt { + compatible = "qcom,sc8280xp-mc-virt"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + mmss_noc: interconnect-mmss-noc { + compatible = "qcom,sc8280xp-mmss-noc"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + nspa_noc: interconnect-nspa-noc { + compatible = "qcom,sc8280xp-nspa-noc"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + nspb_noc: interconnect-nspb-noc { + compatible = "qcom,sc8280xp-nspb-noc"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + system_noc: interconnect-system-noc { + compatible = "qcom,sc8280xp-system-noc"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + memory@80000000 { + device_type = "memory"; + /* We expect the bootloader to fill in the size */ + reg = <0x0 0x80000000 0x0 0x0>; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + + CPU_PD0: cpu0 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD1: cpu1 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD2: cpu2 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD3: cpu3 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD4: cpu4 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&BIG_CPU_SLEEP_0>; + }; + + CPU_PD5: cpu5 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&BIG_CPU_SLEEP_0>; + }; + + CPU_PD6: cpu6 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&BIG_CPU_SLEEP_0>; + }; + + CPU_PD7: cpu7 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&BIG_CPU_SLEEP_0>; + }; + + CLUSTER_PD: cpu-cluster0 { + #power-domain-cells = <0>; + domain-idle-states = <&CLUSTER_SLEEP_0>; + }; + }; + + qup_opp_table_100mhz: qup-100mhz-opp-table { + compatible = "operating-points-v2"; + + opp-75000000 { + opp-hz = /bits/ 64 <75000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + reserved-region@80000000 { + reg = <0 0x80000000 0 0x860000>; + no-map; + }; + + cmd_db: cmd-db-region@80860000 { + compatible = "qcom,cmd-db"; + reg = <0 0x80860000 0 0x20000>; + no-map; + }; + + reserved-region@80880000 { + reg = <0 0x80880000 0 0x80000>; + no-map; + }; + + smem_mem: smem-region@80900000 { + compatible = "qcom,smem"; + reg = <0 0x80900000 0 0x200000>; + no-map; + hwlocks = <&tcsr_mutex 3>; + }; + + reserved-region@80b00000 { + reg = <0 0x80b00000 0 0x100000>; + no-map; + }; + + reserved-region@83b00000 { + reg = <0 0x83b00000 0 0x1700000>; + no-map; + }; + + reserved-region@85b00000 { + reg = <0 0x85b00000 0 0xc00000>; + no-map; + }; + + pil_adsp_mem: adsp-region@86c00000 { + reg = <0 0x86c00000 0 0x2000000>; + no-map; + }; + + pil_nsp0_mem: cdsp0-region@8a100000 { + reg = <0 0x8a100000 0 0x1e00000>; + no-map; + }; + + pil_nsp1_mem: cdsp1-region@8c600000 { + reg = <0 0x8c600000 0 0x1e00000>; + no-map; + }; + + reserved-region@aeb00000 { + reg = <0 0xaeb00000 0 0x16600000>; + no-map; + }; + }; + + smp2p-adsp { + compatible = "qcom,smp2p"; + qcom,smem = <443>, <429>; + interrupts-extended = <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,local-pid = <0>; + qcom,remote-pid = <2>; + + smp2p_adsp_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_adsp_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + smp2p-nsp0 { + compatible = "qcom,smp2p"; + qcom,smem = <94>, <432>; + interrupts-extended = <&ipcc IPCC_CLIENT_CDSP + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_CDSP + IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,local-pid = <0>; + qcom,remote-pid = <5>; + + smp2p_nsp0_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_nsp0_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + smp2p-nsp1 { + compatible = "qcom,smp2p"; + qcom,smem = <617>, <616>; + interrupts-extended = <&ipcc IPCC_CLIENT_NSP1 + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_NSP1 + IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,local-pid = <0>; + qcom,remote-pid = <12>; + + smp2p_nsp1_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_nsp1_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + soc: soc@0 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0 0 0 0 0x10 0>; + dma-ranges = <0 0 0 0 0x10 0>; + + gcc: clock-controller@100000 { + compatible = "qcom,gcc-sc8280xp"; + reg = <0x0 0x00100000 0x0 0x1f0000>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&sleep_clk>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <&usb_0_ssphy>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <&usb_1_ssphy>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>; + power-domains = <&rpmhpd SC8280XP_CX>; + }; + + ipcc: mailbox@408000 { + compatible = "qcom,sc8280xp-ipcc", "qcom,ipcc"; + reg = <0 0x00408000 0 0x1000>; + interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <3>; + #mbox-cells = <2>; + }; + + qup2: geniqup@8c0000 { + compatible = "qcom,geni-se-qup"; + reg = <0 0x008c0000 0 0x2000>; + clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; + clock-names = "m-ahb", "s-ahb"; + iommus = <&apps_smmu 0xa3 0>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + status = "disabled"; + + qup2_uart17: serial@884000 { + compatible = "qcom,geni-uart"; + reg = <0 0x00884000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; + operating-points-v2 = <&qup_opp_table_100mhz>; + power-domains = <&rpmhpd SC8280XP_CX>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; + + qup2_i2c5: i2c@894000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00894000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; + interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&rpmhpd SC8280XP_CX>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, + <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + status = "disabled"; + }; + }; + + qup0: geniqup@9c0000 { + compatible = "qcom,geni-se-qup"; + reg = <0 0x009c0000 0 0x6000>; + clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + clock-names = "m-ahb", "s-ahb"; + iommus = <&apps_smmu 0x563 0>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + status = "disabled"; + + qup0_i2c4: i2c@990000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00990000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&rpmhpd SC8280XP_CX>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + status = "disabled"; + }; + }; + + qup1: geniqup@ac0000 { + compatible = "qcom,geni-se-qup"; + reg = <0 0x00ac0000 0 0x6000>; + clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + clock-names = "m-ahb", "s-ahb"; + iommus = <&apps_smmu 0x83 0>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + status = "disabled"; + }; + + ufs_mem_hc: ufs@1d84000 { + compatible = "qcom,sc8280xp-ufshc", "qcom,ufshc", + "jedec,ufs-2.0"; + reg = <0 0x01d84000 0 0x3000>; + interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; + phys = <&ufs_mem_phy_lanes>; + phy-names = "ufsphy"; + lanes-per-direction = <2>; + #reset-cells = <1>; + resets = <&gcc GCC_UFS_PHY_BCR>; + reset-names = "rst"; + + power-domains = <&gcc UFS_PHY_GDSC>; + required-opps = <&rpmhpd_opp_nom>; + + iommus = <&apps_smmu 0xe0 0x0>; + + clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>, + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; + clock-names = "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk", + "rx_lane1_sync_clk"; + freq-table-hz = <75000000 300000000>, + <0 0>, + <0 0>, + <75000000 300000000>, + <0 0>, + <0 0>, + <0 0>, + <0 0>; + status = "disabled"; + }; + + ufs_mem_phy: phy@1d87000 { + compatible = "qcom,sc8280xp-qmp-ufs-phy"; + reg = <0 0x01d87000 0 0xe10>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + clock-names = "ref", + "ref_aux"; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; + + resets = <&ufs_mem_hc 0>; + reset-names = "ufsphy"; + status = "disabled"; + + ufs_mem_phy_lanes: phy@1d87400 { + reg = <0 0x01d87400 0 0x108>, + <0 0x01d87600 0 0x1e0>, + <0 0x01d87c00 0 0x1dc>, + <0 0x01d87800 0 0x108>, + <0 0x01d87a00 0 0x1e0>; + #phy-cells = <0>; + }; + }; + + ufs_card_hc: ufs@1da4000 { + compatible = "qcom,sc8280xp-ufshc", "qcom,ufshc", + "jedec,ufs-2.0"; + reg = <0 0x01da4000 0 0x3000>; + interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; + phys = <&ufs_card_phy_lanes>; + phy-names = "ufsphy"; + lanes-per-direction = <2>; + #reset-cells = <1>; + resets = <&gcc GCC_UFS_CARD_BCR>; + reset-names = "rst"; + + power-domains = <&gcc UFS_CARD_GDSC>; + + iommus = <&apps_smmu 0x4a0 0x0>; + + clocks = <&gcc GCC_UFS_CARD_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_CARD_AXI_CLK>, + <&gcc GCC_UFS_CARD_AHB_CLK>, + <&gcc GCC_UFS_CARD_UNIPRO_CORE_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_CARD_TX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_CARD_RX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_CARD_RX_SYMBOL_1_CLK>; + clock-names = "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk", + "rx_lane1_sync_clk"; + freq-table-hz = <75000000 300000000>, + <0 0>, + <0 0>, + <75000000 300000000>, + <0 0>, + <0 0>, + <0 0>, + <0 0>; + status = "disabled"; + }; + + ufs_card_phy: phy@1da7000 { + compatible = "qcom,sc8280xp-qmp-ufs-phy"; + reg = <0 0x01da7000 0 0xe10>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + clock-names = "ref", + "ref_aux"; + clocks = <&gcc GCC_UFS_1_CARD_CLKREF_CLK>, + <&gcc GCC_UFS_CARD_PHY_AUX_CLK>; + + resets = <&ufs_card_hc 0>; + reset-names = "ufsphy"; + + status = "disabled"; + + ufs_card_phy_lanes: phy@1da7400 { + reg = <0 0x01da7400 0 0x108>, + <0 0x01da7600 0 0x1e0>, + <0 0x01da7c00 0 0x1dc>, + <0 0x01da7800 0 0x108>, + <0 0x01da7a00 0 0x1e0>; + #phy-cells = <0>; + }; + }; + + tcsr_mutex: hwlock@1f40000 { + compatible = "qcom,tcsr-mutex"; + reg = <0x0 0x01f40000 0x0 0x20000>; + #hwlock-cells = <1>; + }; + + usb_0_hsphy: phy@88e5000 { + compatible = "qcom,sc8280xp-usb-hs-phy", + "qcom,usb-snps-hs-5nm-phy"; + reg = <0 0x088e5000 0 0x400>; + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "ref"; + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; + + #phy-cells = <0>; + + status = "disabled"; + }; + + usb_2_hsphy0: phy@88e7000 { + compatible = "qcom,sc8280xp-usb-hs-phy", + "qcom,usb-snps-hs-5nm-phy"; + reg = <0 0x088e7000 0 0x400>; + clocks = <&gcc GCC_USB2_HS0_CLKREF_CLK>; + clock-names = "ref"; + resets = <&gcc GCC_QUSB2PHY_HS0_MP_BCR>; + + #phy-cells = <0>; + + status = "disabled"; + }; + + usb_2_hsphy1: phy@88e8000 { + compatible = "qcom,sc8280xp-usb-hs-phy", + "qcom,usb-snps-hs-5nm-phy"; + reg = <0 0x088e8000 0 0x400>; + clocks = <&gcc GCC_USB2_HS1_CLKREF_CLK>; + clock-names = "ref"; + resets = <&gcc GCC_QUSB2PHY_HS1_MP_BCR>; + + #phy-cells = <0>; + + status = "disabled"; + }; + + usb_2_hsphy2: phy@88e9000 { + compatible = "qcom,sc8280xp-usb-hs-phy", + "qcom,usb-snps-hs-5nm-phy"; + reg = <0 0x088e9000 0 0x400>; + clocks = <&gcc GCC_USB2_HS2_CLKREF_CLK>; + clock-names = "ref"; + resets = <&gcc GCC_QUSB2PHY_HS2_MP_BCR>; + + #phy-cells = <0>; + + status = "disabled"; + }; + + usb_2_hsphy3: phy@88ea000 { + compatible = "qcom,sc8280xp-usb-hs-phy", + "qcom,usb-snps-hs-5nm-phy"; + reg = <0 0x088ea000 0 0x400>; + clocks = <&gcc GCC_USB2_HS3_CLKREF_CLK>; + clock-names = "ref"; + resets = <&gcc GCC_QUSB2PHY_HS3_MP_BCR>; + + #phy-cells = <0>; + + status = "disabled"; + }; + + usb_2_qmpphy0: phy-wrapper@88ef000 { + compatible = "qcom,sc8280xp-qmp-usb3-uni-phy"; + reg = <0 0x088ef000 0 0x1c8>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB3_MP0_CLKREF_CLK>, + <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>; + clock-names = "aux", "ref_clk_src", "ref", "com_aux"; + + resets = <&gcc GCC_USB3_UNIPHY_MP0_BCR>, + <&gcc GCC_USB3UNIPHY_PHY_MP0_BCR>; + reset-names = "phy", "common"; + + power-domains = <&gcc USB30_MP_GDSC>; + + status = "disabled"; + + usb_2_ssphy0: phy@88efe00 { + reg = <0 0x088efe00 0 0x160>, + <0 0x088f0000 0 0x1ec>, + <0 0x088ef200 0 0x1f0>; + #phy-cells = <0>; + #clock-cells = <0>; + clocks = <&gcc GCC_USB3_MP_PHY_PIPE_0_CLK>; + clock-names = "pipe0"; + clock-output-names = "usb2_phy0_pipe_clk"; + }; + }; + + usb_2_qmpphy1: phy-wrapper@88f1000 { + compatible = "qcom,sc8280xp-qmp-usb3-uni-phy"; + reg = <0 0x088f1000 0 0x1c8>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB3_MP1_CLKREF_CLK>, + <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>; + clock-names = "aux", "ref_clk_src", "ref", "com_aux"; + + resets = <&gcc GCC_USB3_UNIPHY_MP1_BCR>, + <&gcc GCC_USB3UNIPHY_PHY_MP1_BCR>; + reset-names = "phy", "common"; + + power-domains = <&gcc USB30_MP_GDSC>; + + status = "disabled"; + + usb_2_ssphy1: phy@88f1e00 { + reg = <0 0x088f1e00 0 0x160>, + <0 0x088f2000 0 0x1ec>, + <0 0x088f1200 0 0x1f0>; + #phy-cells = <0>; + #clock-cells = <0>; + clocks = <&gcc GCC_USB3_MP_PHY_PIPE_1_CLK>; + clock-names = "pipe0"; + clock-output-names = "usb2_phy1_pipe_clk"; + }; + }; + + remoteproc_adsp: remoteproc@3000000 { + compatible = "qcom,sc8280xp-adsp-pas"; + reg = <0 0x03000000 0 0x100>; + + interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, + <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", + "handover", "stop-ack", "shutdown-ack"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + power-domains = <&rpmhpd SC8280XP_LCX>, + <&rpmhpd SC8280XP_LMX>; + power-domain-names = "lcx", "lmx"; + + memory-region = <&pil_adsp_mem>; + + qcom,qmp = <&aoss_qmp>; + + qcom,smem-states = <&smp2p_adsp_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + remoteproc_adsp_glink: glink-edge { + interrupts-extended = <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_GLINK_QMP>; + + label = "lpass"; + qcom,remote-pid = <2>; + }; + }; + + usb_0_qmpphy: phy-wrapper@88ec000 { + compatible = "qcom,sc8280xp-qmp-usb43dp-phy"; + reg = <0 0x088ec000 0 0x1e4>, + <0 0x088eb000 0 0x40>, + <0 0x088ed000 0 0x1c8>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB4_EUD_CLKREF_CLK>, + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; + clock-names = "aux", "ref_clk_src", "ref", "com_aux"; + + resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, + <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; + reset-names = "phy", "common"; + + power-domains = <&gcc USB30_PRIM_GDSC>; + + status = "disabled"; + + usb_0_ssphy: usb3-phy@88eb400 { + reg = <0 0x088eb400 0 0x100>, + <0 0x088eb600 0 0x3ec>, + <0 0x088ec400 0 0x1f0>, + <0 0x088eba00 0 0x100>, + <0 0x088ebc00 0 0x3ec>, + <0 0x088ec700 0 0x64>; + #phy-cells = <0>; + #clock-cells = <0>; + clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; + clock-names = "pipe0"; + clock-output-names = "usb0_phy_pipe_clk_src"; + }; + + usb_0_dpphy: dp-phy@88ed200 { + reg = <0 0x088ed200 0 0x200>, + <0 0x088ed400 0 0x200>, + <0 0x088eda00 0 0x200>, + <0 0x088ea600 0 0x200>, + <0 0x088ea800 0 0x200>; + #clock-cells = <1>; + #phy-cells = <0>; + }; + }; + + usb_1_hsphy: phy@8902000 { + compatible = "qcom,sc8280xp-usb-hs-phy", + "qcom,usb-snps-hs-5nm-phy"; + reg = <0 0x08902000 0 0x400>; + #phy-cells = <0>; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "ref"; + + resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; + + status = "disabled"; + }; + + usb_1_qmpphy: phy-wrapper@8904000 { + compatible = "qcom,sc8280xp-qmp-usb43dp-phy"; + reg = <0 0x08904000 0 0x1e4>, + <0 0x08903000 0 0x40>, + <0 0x08905000 0 0x1c8>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB4_CLKREF_CLK>, + <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; + clock-names = "aux", "ref_clk_src", "ref", "com_aux"; + + resets = <&gcc GCC_USB3_PHY_SEC_BCR>, + <&gcc GCC_USB4_1_DP_PHY_PRIM_BCR>; + reset-names = "phy", "common"; + + power-domains = <&gcc USB30_SEC_GDSC>; + + status = "disabled"; + + usb_1_ssphy: usb3-phy@8903400 { + reg = <0 0x08903400 0 0x100>, + <0 0x08903c00 0 0x3ec>, + <0 0x08904400 0 0x1f0>, + <0 0x08903a00 0 0x100>, + <0 0x08903c00 0 0x3ec>, + <0 0x08904200 0 0x18>; + #phy-cells = <0>; + #clock-cells = <0>; + clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; + clock-names = "pipe0"; + clock-output-names = "usb1_phy_pipe_clk_src"; + }; + + usb_1_dpphy: dp-phy@8904200 { + reg = <0 0x08904200 0 0x200>, + <0 0x08904400 0 0x200>, + <0 0x08904a00 0 0x200>, + <0 0x08904600 0 0x200>, + <0 0x08904800 0 0x200>; + #clock-cells = <1>; + #phy-cells = <0>; + }; + }; + + system-cache-controller@9200000 { + compatible = "qcom,sc8280xp-llcc"; + reg = <0 0x09200000 0 0x58000>, <0 0x09600000 0 0x58000>; + reg-names = "llcc_base", "llcc_broadcast_base"; + interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; + }; + + usb_0: usb@a6f8800 { + compatible = "qcom,sc8280xp-dwc3", "qcom,dwc3"; + reg = <0 0x0a6f8800 0 0x400>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, + <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>, + <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>, + <&gcc GCC_SYS_NOC_USB_AXI_CLK>; + clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi", + "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys"; + + assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>; + assigned-clock-rates = <19200000>, <200000000>; + + interrupts-extended = <&intc GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 14 IRQ_TYPE_EDGE_BOTH>, + <&pdc 15 IRQ_TYPE_EDGE_BOTH>, + <&pdc 138 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pwr_event", + "dp_hs_phy_irq", + "dm_hs_phy_irq", + "ss_phy_irq"; + + power-domains = <&gcc USB30_PRIM_GDSC>; + + resets = <&gcc GCC_USB30_PRIM_BCR>; + + interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>; + interconnect-names = "usb-ddr", "apps-usb"; + + status = "disabled"; + + usb_0_dwc3: usb@a600000 { + compatible = "snps,dwc3"; + reg = <0 0x0a600000 0 0xcd00>; + interrupts = <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>; + iommus = <&apps_smmu 0x820 0x0>; + phys = <&usb_0_hsphy>, <&usb_0_ssphy>; + phy-names = "usb2-phy", "usb3-phy"; + }; + }; + + usb_1: usb@a8f8800 { + compatible = "qcom,sc8280xp-dwc3", "qcom,dwc3"; + reg = <0 0x0a8f8800 0 0x400>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, + <&gcc GCC_USB30_SEC_MASTER_CLK>, + <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, + <&gcc GCC_USB30_SEC_SLEEP_CLK>, + <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, + <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, + <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>, + <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>, + <&gcc GCC_SYS_NOC_USB_AXI_CLK>; + clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi", + "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys"; + + assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_SEC_MASTER_CLK>; + assigned-clock-rates = <19200000>, <200000000>; + + interrupts-extended = <&intc GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 12 IRQ_TYPE_EDGE_BOTH>, + <&pdc 13 IRQ_TYPE_EDGE_BOTH>, + <&pdc 136 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pwr_event", + "dp_hs_phy_irq", + "dm_hs_phy_irq", + "ss_phy_irq"; + + power-domains = <&gcc USB30_SEC_GDSC>; + + resets = <&gcc GCC_USB30_SEC_BCR>; + + interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>; + interconnect-names = "usb-ddr", "apps-usb"; + + status = "disabled"; + + usb_1_dwc3: usb@a800000 { + compatible = "snps,dwc3"; + reg = <0 0x0a800000 0 0xcd00>; + interrupts = <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>; + iommus = <&apps_smmu 0x860 0x0>; + phys = <&usb_1_hsphy>, <&usb_1_ssphy>; + phy-names = "usb2-phy", "usb3-phy"; + }; + }; + + pdc: interrupt-controller@b220000 { + compatible = "qcom,sc8280xp-pdc", "qcom,pdc"; + reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>; + qcom,pdc-ranges = <0 480 40>, + <40 140 14>, + <54 263 1>, + <55 306 4>, + <59 312 3>, + <62 374 2>, + <64 434 2>, + <66 438 3>, + <69 86 1>, + <70 520 54>, + <124 609 28>, + <159 638 1>, + <160 720 8>, + <168 801 1>, + <169 728 30>, + <199 416 2>, + <201 449 1>, + <202 89 1>, + <203 451 1>, + <204 462 1>, + <205 264 1>, + <206 579 1>, + <207 653 1>, + <208 656 1>, + <209 659 1>, + <210 122 1>, + <211 699 1>, + <212 705 1>, + <213 450 1>, + <214 643 1>, + <216 646 5>, + <221 390 5>, + <226 700 3>, + <229 240 3>, + <232 269 1>, + <233 377 1>, + <234 372 1>, + <235 138 1>, + <236 857 1>, + <237 860 1>, + <238 137 1>, + <239 668 1>, + <240 366 1>, + <241 949 1>, + <242 815 5>, + <247 769 1>, + <248 768 1>, + <249 663 1>, + <250 799 2>, + <252 798 1>, + <253 765 1>, + <254 763 1>, + <255 454 1>, + <258 139 1>, + <259 786 2>, + <261 370 2>, + <263 158 2>; + #interrupt-cells = <2>; + interrupt-parent = <&intc>; + interrupt-controller; + }; + + tsens0: thermal-sensor@c263000 { + compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2"; + reg = <0 0x0c263000 0 0x1ff>, /* TM */ + <0 0x0c222000 0 0x8>; /* SROT */ + #qcom,sensors = <14>; + interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 28 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "uplow", "critical"; + #thermal-sensor-cells = <1>; + }; + + tsens1: thermal-sensor@c265000 { + compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2"; + reg = <0 0x0c265000 0 0x1ff>, /* TM */ + <0 0x0c223000 0 0x8>; /* SROT */ + #qcom,sensors = <16>; + interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 29 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "uplow", "critical"; + #thermal-sensor-cells = <1>; + }; + + aoss_qmp: power-controller@c300000 { + compatible = "qcom,sc8280xp-aoss-qmp", "qcom,aoss-qmp"; + reg = <0 0x0c300000 0 0x400>; + interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; + + #clock-cells = <0>; + }; + + spmi_bus: spmi@c440000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0 0x0c440000 0 0x1100>, + <0 0x0c600000 0 0x2000000>, + <0 0x0e600000 0 0x100000>, + <0 0x0e700000 0 0xa0000>, + <0 0x0c40a000 0 0x26000>; + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; + interrupt-names = "periph_irq"; + interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; + qcom,ee = <0>; + qcom,channel = <0>; + #address-cells = <1>; + #size-cells = <1>; + interrupt-controller; + #interrupt-cells = <4>; + }; + + tlmm: pinctrl@f100000 { + compatible = "qcom,sc8280xp-tlmm"; + reg = <0 0x0f100000 0 0x300000>; + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&tlmm 0 0 230>; + }; + + apps_smmu: iommu@15000000 { + compatible = "qcom,sc8280xp-smmu-500", "arm,mmu-500"; + reg = <0 0x15000000 0 0x100000>; + #iommu-cells = <2>; + #global-interrupts = <2>; + interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 912 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 911 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 910 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 909 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 908 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 907 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 906 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 905 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 904 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 903 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 902 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 901 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 900 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 899 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 898 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 895 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 894 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 893 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 892 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 891 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 890 IRQ_TYPE_LEVEL_HIGH>; + }; + + intc: interrupt-controller@17a00000 { + compatible = "arm,gic-v3"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ + <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; + #redistributor-regions = <1>; + redistributor-stride = <0 0x20000>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gic-its@17a40000 { + compatible = "arm,gic-v3-its"; + reg = <0 0x17a40000 0 0x20000>; + msi-controller; + #msi-cells = <1>; + }; + }; + + watchdog@17c10000 { + compatible = "qcom,apss-wdt-sc8280xp", "qcom,kpss-wdt"; + reg = <0 0x17c10000 0 0x1000>; + clocks = <&sleep_clk>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; + }; + + timer@17c20000 { + compatible = "arm,armv7-timer-mem"; + reg = <0x0 0x17c20000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x0 0x20000000>; + + frame@17c21000 { + frame-number = <0>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x17c21000 0x1000>, + <0x17c22000 0x1000>; + }; + + frame@17c23000 { + frame-number = <1>; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x17c23000 0x1000>; + status = "disabled"; + }; + + frame@17c25000 { + frame-number = <2>; + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x17c25000 0x1000>; + status = "disabled"; + }; + + frame@17c27000 { + frame-number = <3>; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x17c26000 0x1000>; + status = "disabled"; + }; + + frame@17c29000 { + frame-number = <4>; + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x17c29000 0x1000>; + status = "disabled"; + }; + + frame@17c2b000 { + frame-number = <5>; + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x17c2b000 0x1000>; + status = "disabled"; + }; + + frame@17c2d000 { + frame-number = <6>; + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x17c2d000 0x1000>; + status = "disabled"; + }; + }; + + apps_rsc: rsc@18200000 { + compatible = "qcom,rpmh-rsc"; + reg = <0x0 0x18200000 0x0 0x10000>, + <0x0 0x18210000 0x0 0x10000>, + <0x0 0x18220000 0x0 0x10000>; + reg-names = "drv-0", "drv-1", "drv-2"; + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; + qcom,tcs-offset = <0xd00>; + qcom,drv-id = <2>; + qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, + <WAKE_TCS 3>, <CONTROL_TCS 1>; + label = "apps_rsc"; + + apps_bcm_voter: bcm-voter { + compatible = "qcom,bcm-voter"; + }; + + rpmhcc: clock-controller { + compatible = "qcom,sc8280xp-rpmh-clk"; + #clock-cells = <1>; + clock-names = "xo"; + clocks = <&xo_board_clk>; + }; + + rpmhpd: power-controller { + compatible = "qcom,sc8280xp-rpmhpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmhpd_opp_table>; + + rpmhpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmhpd_opp_ret: opp1 { + opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; + }; + + rpmhpd_opp_min_svs: opp2 { + opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; + }; + + rpmhpd_opp_low_svs: opp3 { + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; + }; + + rpmhpd_opp_svs: opp4 { + opp-level = <RPMH_REGULATOR_LEVEL_SVS>; + }; + + rpmhpd_opp_svs_l1: opp5 { + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; + }; + + rpmhpd_opp_nom: opp6 { + opp-level = <RPMH_REGULATOR_LEVEL_NOM>; + }; + + rpmhpd_opp_nom_l1: opp7 { + opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; + }; + + rpmhpd_opp_nom_l2: opp8 { + opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; + }; + + rpmhpd_opp_turbo: opp9 { + opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; + }; + + rpmhpd_opp_turbo_l1: opp10 { + opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; + }; + }; + }; + }; + + cpufreq_hw: cpufreq@18591000 { + compatible = "qcom,sc8280xp-cpufreq-epss", "qcom,cpufreq-epss"; + reg = <0 0x18591000 0 0x1000>, + <0 0x18592000 0 0x1000>; + reg-names = "freq-domain0", "freq-domain1"; + + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; + clock-names = "xo", "alternate"; + + #freq-domain-cells = <1>; + }; + + remoteproc_nsp0: remoteproc@1b300000 { + compatible = "qcom,sc8280xp-nsp0-pas"; + reg = <0 0x1b300000 0 0x100>; + + interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, + <&smp2p_nsp0_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_nsp0_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_nsp0_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_nsp0_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", + "handover", "stop-ack"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + power-domains = <&rpmhpd SC8280XP_NSP>; + power-domain-names = "nsp"; + + memory-region = <&pil_nsp0_mem>; + + qcom,smem-states = <&smp2p_nsp0_out 0>; + qcom,smem-state-names = "stop"; + + interconnects = <&nspa_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>; + + status = "disabled"; + + glink-edge { + interrupts-extended = <&ipcc IPCC_CLIENT_CDSP + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_CDSP + IPCC_MPROC_SIGNAL_GLINK_QMP>; + + label = "nsp0"; + qcom,remote-pid = <5>; + + fastrpc { + compatible = "qcom,fastrpc"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + label = "cdsp"; + #address-cells = <1>; + #size-cells = <0>; + + compute-cb@1 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <1>; + iommus = <&apps_smmu 0x3181 0x0420>; + }; + + compute-cb@2 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <2>; + iommus = <&apps_smmu 0x3182 0x0420>; + }; + + compute-cb@3 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <3>; + iommus = <&apps_smmu 0x3183 0x0420>; + }; + + compute-cb@4 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <4>; + iommus = <&apps_smmu 0x3184 0x0420>; + }; + + compute-cb@5 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <5>; + iommus = <&apps_smmu 0x3185 0x0420>; + }; + + compute-cb@6 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <6>; + iommus = <&apps_smmu 0x3186 0x0420>; + }; + + compute-cb@7 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <7>; + iommus = <&apps_smmu 0x3187 0x0420>; + }; + + compute-cb@8 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <8>; + iommus = <&apps_smmu 0x3188 0x0420>; + }; + + compute-cb@9 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <9>; + iommus = <&apps_smmu 0x318b 0x0420>; + }; + + compute-cb@10 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <10>; + iommus = <&apps_smmu 0x318b 0x0420>; + }; + + compute-cb@11 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <11>; + iommus = <&apps_smmu 0x318c 0x0420>; + }; + + compute-cb@12 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <12>; + iommus = <&apps_smmu 0x318d 0x0420>; + }; + + compute-cb@13 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <13>; + iommus = <&apps_smmu 0x318e 0x0420>; + }; + + compute-cb@14 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <14>; + iommus = <&apps_smmu 0x318f 0x0420>; + }; + }; + }; + }; + + remoteproc_nsp1: remoteproc@21300000 { + compatible = "qcom,sc8280xp-nsp1-pas"; + reg = <0 0x21300000 0 0x100>; + + interrupts-extended = <&intc GIC_SPI 887 IRQ_TYPE_LEVEL_HIGH>, + <&smp2p_nsp1_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_nsp1_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_nsp1_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_nsp1_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", + "handover", "stop-ack"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + power-domains = <&rpmhpd SC8280XP_NSP>; + power-domain-names = "nsp"; + + memory-region = <&pil_nsp1_mem>; + + qcom,smem-states = <&smp2p_nsp1_out 0>; + qcom,smem-state-names = "stop"; + + interconnects = <&nspb_noc MASTER_CDSP_PROC_B 0 &mc_virt SLAVE_EBI1 0>; + + status = "disabled"; + + glink-edge { + interrupts-extended = <&ipcc IPCC_CLIENT_NSP1 + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_NSP1 + IPCC_MPROC_SIGNAL_GLINK_QMP>; + + label = "nsp1"; + qcom,remote-pid = <12>; + }; + }; + }; + + thermal-zones { + cpu0-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 1>; + + trips { + cpu-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu1-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 2>; + + trips { + cpu-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu2-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 3>; + + trips { + cpu-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu3-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 4>; + + trips { + cpu-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu4-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 5>; + + trips { + cpu-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu5-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 6>; + + trips { + cpu-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu6-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 7>; + + trips { + cpu-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu7-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 8>; + + trips { + cpu-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cluster0-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 9>; + + trips { + cpu-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + mem-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens1 15>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts b/arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts new file mode 100644 index 000000000000..28050bc5f081 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts @@ -0,0 +1,461 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2021, Linaro Ltd. + * Copyright (c) 2020, Konrad Dybcio <konrad.dybcio@somainline.org> + * Copyright (c) 2020, AngeloGioacchino Del Regno + * <angelogioacchino.delregno@somainline.org> + */ + +/dts-v1/; + +#include "sdm660.dtsi" +#include "pm660.dtsi" +#include "pm660l.dtsi" + +/ { + model = "Inforce 6560 Single Board Computer"; + compatible = "inforce,ifc6560", "qcom,sda660"; + chassis-type = "embedded"; /* SBC */ + + aliases { + serial0 = &blsp1_uart2; + serial1 = &blsp2_uart1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + volup { + label = "Volume Up"; + gpios = <&pm660l_gpios 7 GPIO_ACTIVE_LOW>; + linux,code = <KEY_VOLUMEUP>; + debounce-interval = <15>; + }; + }; + + /* + * Until we hook up type-c detection, we + * have to stick with this. But it works. + */ + extcon_usb: extcon-usb { + compatible = "linux,extcon-usb-gpio"; + id-gpio = <&tlmm 58 GPIO_ACTIVE_HIGH>; + }; + + hdmi-out { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con: endpoint { + remote-endpoint = <&adv7533_out>; + }; + }; + }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3800000>; + regulator-max-microvolt = <3800000>; + + regulator-always-on; + regulator-boot-on; + }; + + v3p3_bck_bst: v3p3-bck-bst-regulator { + compatible = "regulator-fixed"; + regulator-name = "v3p3_bck_bst"; + + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + vin-supply = <&vph_pwr>; + }; + + v1p2_ldo: v1p2-ldo-regulator { + compatible = "regulator-fixed"; + regulator-name = "v1p2_ldo"; + + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + + vin-supply = <&vph_pwr>; + }; + + v5p0_boost: v5p0-boost-regulator { + compatible = "regulator-fixed"; + regulator-name = "v5p0_boost"; + + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + + vin-supply = <&vph_pwr>; + }; +}; + +&adsp_pil { + firmware-name = "qcom/ifc6560/adsp.mbn"; +}; + +&blsp_i2c6 { + status = "okay"; + + adv7533: hdmi@39 { + compatible = "adi,adv7535"; + reg = <0x39>, <0x66>; + reg-names = "main", "edid"; + + interrupt-parent = <&pm660l_gpios>; + interrupts = <11 IRQ_TYPE_EDGE_FALLING>; + + clocks = <&rpmcc RPM_SMD_BB_CLK2>; + clock-names = "cec"; + /* + * Limit to 3 lanes to prevent the bridge from changing amount + * of lanes in the fly. MSM DSI host doesn't like that. + */ + adi,dsi-lanes = <3>; + avdd-supply = <&vreg_l13a_1p8>; + dvdd-supply = <&vreg_l13a_1p8>; + pvdd-supply = <&vreg_l13a_1p8>; + a2vdd-supply = <&vreg_l13a_1p8>; + v3p3-supply = <&v3p3_bck_bst>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + adv7533_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + + port@1 { + reg = <1>; + + adv7533_out: endpoint { + remote-endpoint = <&hdmi_con>; + }; + }; + }; + }; +}; + +&blsp1_dma { + /* + * The board will lock up if we toggle the BLSP clock, unless the + * BAM DMA interconnects support is in place. + */ + /delete-property/ clocks; +}; + +&blsp1_uart2 { + status = "okay"; +}; + +&blsp2_dma { + /* + * The board will lock up if we toggle the BLSP clock, unless the + * BAM DMA interconnects support is in place. + */ + /delete-property/ clocks; +}; + +&blsp2_uart1 { + status = "okay"; + + bluetooth { + compatible = "qcom,wcn3990-bt"; + + vddio-supply = <&vreg_l13a_1p8>; + vddxo-supply = <&vreg_l9a_1p8>; + vddrf-supply = <&vreg_l6a_1p3>; + vddch0-supply = <&vreg_l19a_3p3>; + max-speed = <3200000>; + }; +}; + +&dsi0 { + status = "okay"; + vdda-supply = <&vreg_l1a_1p225>; +}; + +&dsi0_out { + remote-endpoint = <&adv7533_in>; + data-lanes = <0 1 2 3>; +}; + +&dsi0_phy { + status = "okay"; + vcca-supply = <&vreg_l1b_0p925>; +}; + +&mdss { + status = "okay"; +}; + +&mmss_smmu { + status = "okay"; +}; + +&pon_pwrkey { + status = "okay"; +}; + +&pon_resin { + status = "okay"; + + linux,code = <KEY_VOLUMEUP>; +}; + +&qusb2phy0 { + status = "okay"; + + vdd-supply = <&vreg_l1b_0p925>; + vdda-phy-dpdm-supply = <&vreg_l7b_3p125>; +}; + +&qusb2phy1 { + status = "okay"; + + vdd-supply = <&vreg_l1b_0p925>; + vdda-phy-dpdm-supply = <&vreg_l7b_3p125>; +}; + +&rpm_requests { + pm660-regulators { + compatible = "qcom,rpm-pm660-regulators"; + + vdd_s1-supply = <&vph_pwr>; + vdd_s2-supply = <&vph_pwr>; + vdd_s3-supply = <&vph_pwr>; + vdd_s4-supply = <&vph_pwr>; + vdd_s5-supply = <&vph_pwr>; + vdd_s6-supply = <&vph_pwr>; + + vdd_l1_l6_l7-supply = <&vreg_s5a_1p35>; + vdd_l2_l3-supply = <&vreg_s2b_1p05>; + vdd_l5-supply = <&vreg_s2b_1p05>; + vdd_l8_l9_l10_l11_l12_l13_l14-supply = <&vreg_s4a_2p04>; + vdd_l15_l16_l17_l18_l19-supply = <&vreg_bob>; + + vreg_s4a_2p04: s4 { + regulator-min-microvolt = <1805000>; + regulator-max-microvolt = <2040000>; + regulator-enable-ramp-delay = <200>; + regulator-ramp-delay = <0>; + regulator-always-on; + }; + + vreg_s5a_1p35: s5 { + regulator-min-microvolt = <1224000>; + regulator-max-microvolt = <1350000>; + regulator-enable-ramp-delay = <200>; + regulator-ramp-delay = <0>; + }; + + vreg_l1a_1p225: l1 { + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1250000>; + regulator-enable-ramp-delay = <250>; + regulator-allow-set-load; + }; + + vreg_l6a_1p3: l6 { + regulator-min-microvolt = <1304000>; + regulator-max-microvolt = <1368000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + regulator-allow-set-load; + }; + + vreg_l8a_1p8: l8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + regulator-system-load = <325000>; + regulator-allow-set-load; + }; + + vreg_l9a_1p8: l9 { + regulator-min-microvolt = <1804000>; + regulator-max-microvolt = <1896000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + regulator-allow-set-load; + }; + + vreg_l13a_1p8: l13 { + /* This gives power to the LPDDR4: never turn it off! */ + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1944000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + regulator-always-on; + regulator-boot-on; + }; + + vreg_l19a_3p3: l19 { + regulator-min-microvolt = <3312000>; + regulator-max-microvolt = <3400000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + regulator-allow-set-load; + }; + }; + + pm660l-regulators { + compatible = "qcom,rpm-pm660l-regulators"; + + vdd_s1-supply = <&vph_pwr>; + vdd_s2-supply = <&vph_pwr>; + vdd_s3_s4-supply = <&vph_pwr>; + vdd_s5-supply = <&vph_pwr>; + vdd_s6-supply = <&vph_pwr>; + + vdd_l1_l9_l10-supply = <&vreg_s2b_1p05>; + vdd_l2-supply = <&vreg_bob>; + vdd_l3_l5_l7_l8-supply = <&vreg_bob>; + vdd_l4_l6-supply = <&vreg_bob>; + vdd_bob-supply = <&vph_pwr>; + + vreg_s2b_1p05: s2 { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + regulator-enable-ramp-delay = <200>; + regulator-ramp-delay = <0>; + }; + + vreg_l1b_0p925: l1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <925000>; + regulator-enable-ramp-delay = <250>; + regulator-allow-set-load; + }; + + vreg_l2b_2p95: l2 { + regulator-min-microvolt = <1648000>; + regulator-max-microvolt = <3100000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + regulator-allow-set-load; + }; + + vreg_l4b_2p95: l4 { + regulator-min-microvolt = <2944000>; + regulator-max-microvolt = <2952000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + + regulator-min-microamp = <200>; + regulator-max-microamp = <600000>; + regulator-system-load = <570000>; + regulator-allow-set-load; + }; + + /* + * Downstream specifies a range of 1721-3600mV, + * but the only assigned consumers are SDHCI2 VMMC + * and Coresight QPDI that both request pinned 2.95V. + * Tighten the range to 1.8-3.328 (closest to 3.3) to + * make the mmc driver happy. + */ + vreg_l5b_2p95: l5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3328000>; + regulator-enable-ramp-delay = <250>; + regulator-system-load = <800000>; + regulator-ramp-delay = <0>; + regulator-allow-set-load; + }; + + vreg_l7b_3p125: l7 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3125000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l8b_3p3: l8 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3400000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + }; + + vreg_bob: bob { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3624000>; + regulator-enable-ramp-delay = <500>; + regulator-ramp-delay = <0>; + }; + }; +}; + +&sdc2_state_on { + sd-cd { + pins = "gpio54"; + bias-pull-up; + drive-strength = <2>; + }; +}; + +&sdc2_state_off { + sd-cd { + pins = "gpio54"; + bias-disable; + drive-strength = <2>; + }; +}; + +&sdhc_1 { + status = "okay"; + supports-cqe; + + vmmc-supply = <&vreg_l4b_2p95>; + vqmmc-supply = <&vreg_l8a_1p8>; + + mmc-ddr-1_8v; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; +}; + +&sdhc_2 { + status = "okay"; + + vmmc-supply = <&vreg_l5b_2p95>; + vqmmc-supply = <&vreg_l2b_2p95>; + + cd-gpios = <&tlmm 54 GPIO_ACTIVE_LOW>; + no-sdio; + no-emmc; +}; + +&tlmm { + gpio-reserved-ranges = <0 4>, <8 4>; +}; + +&usb2 { + status = "okay"; +}; + +&usb2_dwc3 { + dr_mode = "host"; +}; + +&usb3 { + status = "okay"; +}; + +&usb3_dwc3 { + dr_mode = "peripheral"; + extcon = <&extcon_usb>; +}; diff --git a/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi b/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi index 42af1fade461..09c07800793a 100644 --- a/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi @@ -10,6 +10,7 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> #include <dt-bindings/input/gpio-keys.h> +#include <dt-bindings/leds/common.h> / { /* required for bootloader to select correct board */ @@ -34,7 +35,7 @@ height = <1920>; stride = <(1080 * 4)>; format = "a8r8g8b8"; - status= "okay"; + status = "okay"; }; }; @@ -87,13 +88,10 @@ pinctrl-0 = <&imx300_vana_default>; }; - gpio_keys { - status = "okay"; + gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - camera_focus { + key-camera-focus { label = "Camera Focus"; gpios = <&tlmm 64 GPIO_ACTIVE_LOW>; linux,input-type = <1>; @@ -101,7 +99,7 @@ debounce-interval = <15>; }; - camera_snapshot { + key-camera-snapshot { label = "Camera Snapshot"; gpios = <&tlmm 113 GPIO_ACTIVE_LOW>; linux,input-type = <1>; @@ -109,7 +107,7 @@ debounce-interval = <15>; }; - vol_down { + key-vol-down { label = "Volume Down"; gpios = <&pm660l_gpios 7 GPIO_ACTIVE_LOW>; linux,input-type = <1>; @@ -214,6 +212,35 @@ /* HCI Bluetooth */ }; +&pm660l_lpg { + qcom,power-source = <1>; + + status = "okay"; + + multi-led { + color = <LED_COLOR_ID_RGB>; + function = LED_FUNCTION_STATUS; + + #address-cells = <1>; + #size-cells = <0>; + + led@1 { + reg = <1>; + color = <LED_COLOR_ID_BLUE>; + }; + + led@2 { + reg = <2>; + color = <LED_COLOR_ID_GREEN>; + }; + + led@3 { + reg = <3>; + color = <LED_COLOR_ID_RED>; + }; + }; +}; + &pon_pwrkey { status = "okay"; }; @@ -224,7 +251,7 @@ linux,code = <KEY_VOLUMEUP>; }; -&qusb2phy { +&qusb2phy0 { status = "okay"; vdd-supply = <&vreg_l1b_0p925>; @@ -549,6 +576,22 @@ }; }; +&sdc2_state_on { + sd-cd { + pins = "gpio54"; + bias-pull-up; + drive-strength = <2>; + }; +}; + +&sdc2_state_off { + sd-cd { + pins = "gpio54"; + bias-disable; + drive-strength = <2>; + }; +}; + &sdhc_1 { status = "okay"; supports-cqe; diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi index b72e8e6c52f3..1bc9091cad2a 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -8,6 +8,7 @@ #include <dt-bindings/clock/qcom,gpucc-sdm660.h> #include <dt-bindings/clock/qcom,mmcc-sdm660.h> #include <dt-bindings/clock/qcom,rpmcc.h> +#include <dt-bindings/interconnect/qcom,sdm660.h> #include <dt-bindings/power/qcom-rpmpd.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/arm-gic.h> @@ -552,19 +553,19 @@ }; qfprom: qfprom@780000 { - compatible = "qcom,qfprom"; + compatible = "qcom,sdm630-qfprom", "qcom,qfprom"; reg = <0x00780000 0x621c>; #address-cells = <1>; #size-cells = <1>; qusb2_hstx_trim: hstx-trim@240 { - reg = <0x240 0x1>; - bits = <25 3>; + reg = <0x243 0x1>; + bits = <1 3>; }; gpu_speed_bin: gpu-speed-bin@41a0 { - reg = <0x41a0 0x1>; - bits = <21 7>; + reg = <0x41a2 0x1>; + bits = <5 7>; }; }; @@ -982,12 +983,6 @@ bias-pull-up; drive-strength = <10>; }; - - sd-cd { - pins = "gpio54"; - bias-pull-up; - drive-strength = <2>; - }; }; sdc2_state_off: sdc2-off { @@ -1008,12 +1003,6 @@ bias-pull-up; drive-strength = <2>; }; - - sd-cd { - pins = "gpio54"; - bias-disable; - drive-strength = <2>; - }; }; }; @@ -1045,13 +1034,15 @@ nvmem-cells = <&gpu_speed_bin>; nvmem-cell-names = "speed_bin"; - interconnects = <&gnoc 1 &bimc 5>; + interconnects = <&bimc MASTER_OXILI &bimc SLAVE_EBI>; interconnect-names = "gfx-mem"; operating-points-v2 = <&gpu_sdm630_opp_table>; + status = "disabled"; + gpu_sdm630_opp_table: opp-table { - compatible = "operating-points-v2"; + compatible = "operating-points-v2"; opp-775000000 { opp-hz = /bits/ 64 <775000000>; opp-level = <RPM_SMD_LEVEL_TURBO>; @@ -1252,19 +1243,19 @@ * haven't seen any devices making use of it. */ maximum-speed = "high-speed"; - phys = <&qusb2phy>; + phys = <&qusb2phy0>; phy-names = "usb2-phy"; snps,hird-threshold = /bits/ 8 <0>; }; }; - qusb2phy: phy@c012000 { + qusb2phy0: phy@c012000 { compatible = "qcom,sdm660-qusb2-phy"; reg = <0x0c012000 0x180>; #phy-cells = <0>; clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, - <&gcc GCC_RX1_USB2_CLKREF_CLK>; + <&gcc GCC_RX0_USB2_CLKREF_CLK>; clock-names = "cfg_ahb", "ref"; resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; @@ -1272,7 +1263,21 @@ status = "disabled"; }; - sdhc_2: sdhci@c084000 { + qusb2phy1: phy@c014000 { + compatible = "qcom,sdm660-qusb2-phy"; + reg = <0x0c014000 0x180>; + #phy-cells = <0>; + + clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, + <&gcc GCC_RX1_USB2_CLKREF_CLK>; + clock-names = "cfg_ahb", "ref"; + + resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; + nvmem-cells = <&qusb2_hstx_trim>; + status = "disabled"; + }; + + sdhc_2: mmc@c084000 { compatible = "qcom,sdm630-sdhci", "qcom,sdhci-msm-v5"; reg = <0x0c084000 0x1000>; reg-names = "hc"; @@ -1282,13 +1287,16 @@ interrupt-names = "hc_irq", "pwr_irq"; bus-width = <4>; - clocks = <&gcc GCC_SDCC2_APPS_CLK>, - <&gcc GCC_SDCC2_AHB_CLK>, + + clocks = <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, <&xo_board>; - clock-names = "core", "iface", "xo"; + clock-names = "iface", "core", "xo"; + interconnects = <&a2noc 3 &a2noc 10>, <&gnoc 0 &cnoc 28>; + interconnect-names = "sdhc-ddr","cpu-sdhc"; operating-points-v2 = <&sdhc2_opp_table>; pinctrl-names = "default", "sleep"; @@ -1322,7 +1330,7 @@ }; }; - sdhc_1: sdhci@c0c4000 { + sdhc_1: mmc@c0c4000 { compatible = "qcom,sdm630-sdhci", "qcom,sdhci-msm-v5"; reg = <0x0c0c4000 0x1000>, <0x0c0c5000 0x1000>, @@ -1333,15 +1341,15 @@ <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "hc_irq", "pwr_irq"; - clocks = <&gcc GCC_SDCC1_APPS_CLK>, - <&gcc GCC_SDCC1_AHB_CLK>, + clocks = <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, <&xo_board>, <&gcc GCC_SDCC1_ICE_CORE_CLK>; - clock-names = "core", "iface", "xo", "ice"; + clock-names = "iface", "core", "xo", "ice"; interconnects = <&a2noc 2 &a2noc 10>, <&gnoc 0 &cnoc 27>; - interconnect-names = "sdhc1-ddr", "cpu-sdhc1"; + interconnect-names = "sdhc-ddr", "cpu-sdhc"; operating-points-v2 = <&sdhc1_opp_table>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&sdc1_state_on>; @@ -1377,6 +1385,47 @@ }; }; + usb2: usb@c2f8800 { + compatible = "qcom,sdm660-dwc3", "qcom,dwc3"; + reg = <0x0c2f8800 0x400>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + clocks = <&gcc GCC_CFG_NOC_USB2_AXI_CLK>, + <&gcc GCC_USB20_MASTER_CLK>, + <&gcc GCC_USB20_MOCK_UTMI_CLK>, + <&gcc GCC_USB20_SLEEP_CLK>; + clock-names = "cfg_noc", "core", + "mock_utmi", "sleep"; + + assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, + <&gcc GCC_USB20_MASTER_CLK>; + assigned-clock-rates = <19200000>, <60000000>; + + interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hs_phy_irq"; + + qcom,select-utmi-as-pipe-clk; + + resets = <&gcc GCC_USB_20_BCR>; + + usb2_dwc3: usb@c200000 { + compatible = "snps,dwc3"; + reg = <0x0c200000 0xc8d0>; + interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + + /* This is the HS-only host */ + maximum-speed = "high-speed"; + phys = <&qusb2phy1>; + phy-names = "usb2-phy"; + snps,hird-threshold = /bits/ 8 <0>; + }; + }; + mmcc: clock-controller@c8c0000 { compatible = "qcom,mmcc-sdm630"; reg = <0x0c8c0000 0x40000>; @@ -1405,7 +1454,7 @@ <0>; }; - dsi_opp_table: dsi-opp-table { + dsi_opp_table: opp-table-dsi { compatible = "operating-points-v2"; opp-131250000 { @@ -1494,7 +1543,7 @@ }; }; - mdp_opp_table: mdp-opp { + mdp_opp_table: opp-table { compatible = "operating-points-v2"; opp-150000000 { @@ -1563,6 +1612,8 @@ phys = <&dsi0_phy>; phy-names = "dsi"; + status = "disabled"; + ports { #address-cells = <1>; #size-cells = <0>; @@ -1596,6 +1647,7 @@ clocks = <&mmcc MDSS_AHB_CLK>, <&xo_board>; clock-names = "iface", "ref"; + status = "disabled"; }; }; @@ -1829,8 +1881,8 @@ status = "disabled"; }; - imem@146bf000 { - compatible = "simple-mfd"; + sram@146bf000 { + compatible = "qcom,sdm630-imem", "syscon", "simple-mfd"; reg = <0x146bf000 0x1000>; #address-cells = <1>; @@ -1846,138 +1898,138 @@ camss: camss@ca00000 { compatible = "qcom,sdm660-camss"; - reg = <0x0c824000 0x1000>, + reg = <0x0ca00020 0x10>, + <0x0ca30000 0x100>, + <0x0ca30400 0x100>, + <0x0ca30800 0x100>, + <0x0ca30c00 0x100>, + <0x0c824000 0x1000>, <0x0ca00120 0x4>, <0x0c825000 0x1000>, <0x0ca00124 0x4>, <0x0c826000 0x1000>, <0x0ca00128 0x4>, - <0x0ca30000 0x100>, - <0x0ca30400 0x100>, - <0x0ca30800 0x100>, - <0x0ca30c00 0x100>, <0x0ca31000 0x500>, - <0x0ca00020 0x10>, <0x0ca10000 0x1000>, <0x0ca14000 0x1000>; - reg-names = "csiphy0", + reg-names = "csi_clk_mux", + "csid0", + "csid1", + "csid2", + "csid3", + "csiphy0", "csiphy0_clk_mux", "csiphy1", "csiphy1_clk_mux", "csiphy2", "csiphy2_clk_mux", - "csid0", - "csid1", - "csid2", - "csid3", "ispif", - "csi_clk_mux", "vfe0", "vfe1"; - interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>, + interrupts = <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 297 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 298 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 299 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 309 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 314 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 315 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "csiphy0", - "csiphy1", - "csiphy2", - "csid0", + interrupt-names = "csid0", "csid1", "csid2", "csid3", + "csiphy0", + "csiphy1", + "csiphy2", "ispif", "vfe0", "vfe1"; - clocks = <&mmcc CAMSS_TOP_AHB_CLK>, - <&mmcc THROTTLE_CAMSS_AXI_CLK>, - <&mmcc CAMSS_ISPIF_AHB_CLK>, - <&mmcc CAMSS_CSI0PHYTIMER_CLK>, - <&mmcc CAMSS_CSI1PHYTIMER_CLK>, - <&mmcc CAMSS_CSI2PHYTIMER_CLK>, - <&mmcc CAMSS_CSI0_AHB_CLK>, - <&mmcc CAMSS_CSI0_CLK>, - <&mmcc CAMSS_CPHY_CSID0_CLK>, - <&mmcc CAMSS_CSI0PIX_CLK>, - <&mmcc CAMSS_CSI0RDI_CLK>, - <&mmcc CAMSS_CSI1_AHB_CLK>, - <&mmcc CAMSS_CSI1_CLK>, - <&mmcc CAMSS_CPHY_CSID1_CLK>, - <&mmcc CAMSS_CSI1PIX_CLK>, - <&mmcc CAMSS_CSI1RDI_CLK>, - <&mmcc CAMSS_CSI2_AHB_CLK>, - <&mmcc CAMSS_CSI2_CLK>, - <&mmcc CAMSS_CPHY_CSID2_CLK>, - <&mmcc CAMSS_CSI2PIX_CLK>, - <&mmcc CAMSS_CSI2RDI_CLK>, - <&mmcc CAMSS_CSI3_AHB_CLK>, - <&mmcc CAMSS_CSI3_CLK>, - <&mmcc CAMSS_CPHY_CSID3_CLK>, - <&mmcc CAMSS_CSI3PIX_CLK>, - <&mmcc CAMSS_CSI3RDI_CLK>, - <&mmcc CAMSS_AHB_CLK>, - <&mmcc CAMSS_VFE0_CLK>, - <&mmcc CAMSS_CSI_VFE0_CLK>, - <&mmcc CAMSS_VFE0_AHB_CLK>, - <&mmcc CAMSS_VFE0_STREAM_CLK>, - <&mmcc CAMSS_VFE1_CLK>, - <&mmcc CAMSS_CSI_VFE1_CLK>, - <&mmcc CAMSS_VFE1_AHB_CLK>, - <&mmcc CAMSS_VFE1_STREAM_CLK>, - <&mmcc CAMSS_VFE_VBIF_AHB_CLK>, - <&mmcc CAMSS_VFE_VBIF_AXI_CLK>, - <&mmcc CSIPHY_AHB2CRIF_CLK>, - <&mmcc CAMSS_CPHY_CSID0_CLK>, - <&mmcc CAMSS_CPHY_CSID1_CLK>, - <&mmcc CAMSS_CPHY_CSID2_CLK>, - <&mmcc CAMSS_CPHY_CSID3_CLK>; - clock-names = "top_ahb", - "throttle_axi", - "ispif_ahb", - "csiphy0_timer", - "csiphy1_timer", - "csiphy2_timer", - "csi0_ahb", - "csi0", - "csi0_phy", - "csi0_pix", - "csi0_rdi", - "csi1_ahb", - "csi1", - "csi1_phy", - "csi1_pix", - "csi1_rdi", - "csi2_ahb", - "csi2", - "csi2_phy", - "csi2_pix", - "csi2_rdi", - "csi3_ahb", - "csi3", - "csi3_phy", - "csi3_pix", - "csi3_rdi", - "ahb", - "vfe0", - "csi_vfe0", - "vfe0_ahb", - "vfe0_stream", - "vfe1", - "csi_vfe1", - "vfe1_ahb", - "vfe1_stream", - "vfe_ahb", - "vfe_axi", - "csiphy_ahb2crif", - "cphy_csid0", - "cphy_csid1", - "cphy_csid2", - "cphy_csid3"; + clocks = <&mmcc CAMSS_AHB_CLK>, + <&mmcc CAMSS_CPHY_CSID0_CLK>, + <&mmcc CAMSS_CPHY_CSID1_CLK>, + <&mmcc CAMSS_CPHY_CSID2_CLK>, + <&mmcc CAMSS_CPHY_CSID3_CLK>, + <&mmcc CAMSS_CSI0_AHB_CLK>, + <&mmcc CAMSS_CSI0_CLK>, + <&mmcc CAMSS_CPHY_CSID0_CLK>, + <&mmcc CAMSS_CSI0PIX_CLK>, + <&mmcc CAMSS_CSI0RDI_CLK>, + <&mmcc CAMSS_CSI1_AHB_CLK>, + <&mmcc CAMSS_CSI1_CLK>, + <&mmcc CAMSS_CPHY_CSID1_CLK>, + <&mmcc CAMSS_CSI1PIX_CLK>, + <&mmcc CAMSS_CSI1RDI_CLK>, + <&mmcc CAMSS_CSI2_AHB_CLK>, + <&mmcc CAMSS_CSI2_CLK>, + <&mmcc CAMSS_CPHY_CSID2_CLK>, + <&mmcc CAMSS_CSI2PIX_CLK>, + <&mmcc CAMSS_CSI2RDI_CLK>, + <&mmcc CAMSS_CSI3_AHB_CLK>, + <&mmcc CAMSS_CSI3_CLK>, + <&mmcc CAMSS_CPHY_CSID3_CLK>, + <&mmcc CAMSS_CSI3PIX_CLK>, + <&mmcc CAMSS_CSI3RDI_CLK>, + <&mmcc CAMSS_CSI0PHYTIMER_CLK>, + <&mmcc CAMSS_CSI1PHYTIMER_CLK>, + <&mmcc CAMSS_CSI2PHYTIMER_CLK>, + <&mmcc CSIPHY_AHB2CRIF_CLK>, + <&mmcc CAMSS_CSI_VFE0_CLK>, + <&mmcc CAMSS_CSI_VFE1_CLK>, + <&mmcc CAMSS_ISPIF_AHB_CLK>, + <&mmcc THROTTLE_CAMSS_AXI_CLK>, + <&mmcc CAMSS_TOP_AHB_CLK>, + <&mmcc CAMSS_VFE0_AHB_CLK>, + <&mmcc CAMSS_VFE0_CLK>, + <&mmcc CAMSS_VFE0_STREAM_CLK>, + <&mmcc CAMSS_VFE1_AHB_CLK>, + <&mmcc CAMSS_VFE1_CLK>, + <&mmcc CAMSS_VFE1_STREAM_CLK>, + <&mmcc CAMSS_VFE_VBIF_AHB_CLK>, + <&mmcc CAMSS_VFE_VBIF_AXI_CLK>; + clock-names = "ahb", + "cphy_csid0", + "cphy_csid1", + "cphy_csid2", + "cphy_csid3", + "csi0_ahb", + "csi0", + "csi0_phy", + "csi0_pix", + "csi0_rdi", + "csi1_ahb", + "csi1", + "csi1_phy", + "csi1_pix", + "csi1_rdi", + "csi2_ahb", + "csi2", + "csi2_phy", + "csi2_pix", + "csi2_rdi", + "csi3_ahb", + "csi3", + "csi3_phy", + "csi3_pix", + "csi3_rdi", + "csiphy0_timer", + "csiphy1_timer", + "csiphy2_timer", + "csiphy_ahb2crif", + "csi_vfe0", + "csi_vfe1", + "ispif_ahb", + "throttle_axi", + "top_ahb", + "vfe0_ahb", + "vfe0", + "vfe0_stream", + "vfe1_ahb", + "vfe1", + "vfe1_stream", + "vfe_ahb", + "vfe_axi"; interconnects = <&mnoc 5 &bimc 5>; interconnect-names = "vfe-mem"; iommus = <&mmss_smmu 0xc00>, @@ -2158,8 +2210,6 @@ label = "lpass"; mboxes = <&apcs_glb 9>; qcom,remote-pid = <2>; - #address-cells = <1>; - #size-cells = <0>; apr { compatible = "qcom,apr-v2"; diff --git a/arch/arm64/boot/dts/qcom/sdm632-fairphone-fp3.dts b/arch/arm64/boot/dts/qcom/sdm632-fairphone-fp3.dts index 8b815b2a60a7..891e314bc782 100644 --- a/arch/arm64/boot/dts/qcom/sdm632-fairphone-fp3.dts +++ b/arch/arm64/boot/dts/qcom/sdm632-fairphone-fp3.dts @@ -27,7 +27,7 @@ gpio-keys { compatible = "gpio-keys"; - volume-up { + key-volume-up { label = "volume_up"; linux,code = <KEY_VOLUMEUP>; gpios = <&tlmm 85 GPIO_ACTIVE_LOW>; diff --git a/arch/arm64/boot/dts/qcom/sdm636-sony-xperia-ganges-mermaid.dts b/arch/arm64/boot/dts/qcom/sdm636-sony-xperia-ganges-mermaid.dts index b96da53f2f1e..58f687fc49e0 100644 --- a/arch/arm64/boot/dts/qcom/sdm636-sony-xperia-ganges-mermaid.dts +++ b/arch/arm64/boot/dts/qcom/sdm636-sony-xperia-ganges-mermaid.dts @@ -19,7 +19,7 @@ }; &sdc2_state_on { - pinconf-clk { + clk { drive-strength = <14>; }; }; diff --git a/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts b/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts index dcbaacf18f66..a3559f6e34a5 100644 --- a/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts +++ b/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts @@ -51,7 +51,7 @@ gpio-keys { compatible = "gpio-keys"; - volup { + key-volup { label = "Volume Up"; gpios = <&pm660l_gpios 7 GPIO_ACTIVE_LOW>; linux,code = <KEY_VOLUMEUP>; @@ -103,7 +103,7 @@ linux,code = <KEY_VOLUMEDOWN>; }; -&qusb2phy { +&qusb2phy0 { status = "okay"; vdd-supply = <&vreg_l1b_0p925>; @@ -363,6 +363,30 @@ }; }; +&pm660l_wled { + status = "okay"; + + qcom,switching-freq = <800>; + qcom,current-limit-microamp = <20000>; + qcom,num-strings = <2>; +}; + +&sdc2_state_on { + sd-cd { + pins = "gpio54"; + bias-pull-up; + drive-strength = <2>; + }; +}; + +&sdc2_state_off { + sd-cd { + pins = "gpio54"; + bias-disable; + drive-strength = <2>; + }; +}; + &sdhc_1 { status = "okay"; supports-cqe; diff --git a/arch/arm64/boot/dts/qcom/sdm660.dtsi b/arch/arm64/boot/dts/qcom/sdm660.dtsi index 1d748c5305f4..43220af1b685 100644 --- a/arch/arm64/boot/dts/qcom/sdm660.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm660.dtsi @@ -14,7 +14,7 @@ operating-points-v2 = <&gpu_sdm660_opp_table>; gpu_sdm660_opp_table: opp-table { - compatible = "operating-points-v2"; + compatible = "operating-points-v2"; /* * 775MHz is only available on the highest speed bin @@ -192,6 +192,8 @@ phys = <&dsi1_phy>; phy-names = "dsi"; + status = "disabled"; + ports { #address-cells = <1>; #size-cells = <0>; @@ -225,6 +227,7 @@ clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>; clock-names = "iface", "ref"; + status = "disabled"; }; }; diff --git a/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi b/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi index e7e4cc5936aa..b5eb8f7eca1d 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi @@ -119,7 +119,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pen_eject_odl>; - pen-insert { + switch-pen-insert { label = "Pen Insert"; /* Insert = low, eject = high */ gpios = <&tlmm 119 GPIO_ACTIVE_LOW>; @@ -130,7 +130,7 @@ }; panel: panel { - compatible ="innolux,p120zdg-bf1"; + compatible = "innolux,p120zdg-bf1"; power-supply = <&pp3300_dx_edp>; backlight = <&backlight>; no-hpd; @@ -145,6 +145,138 @@ }; }; +&psci { + /delete-node/ cpu0; + /delete-node/ cpu1; + /delete-node/ cpu2; + /delete-node/ cpu3; + /delete-node/ cpu4; + /delete-node/ cpu5; + /delete-node/ cpu6; + /delete-node/ cpu7; + /delete-node/ cpu-cluster0; +}; + +&cpus { + /delete-node/ domain-idle-states; +}; + +&cpu_idle_states { + LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { + compatible = "arm,idle-state"; + idle-state-name = "little-power-down"; + arm,psci-suspend-param = <0x40000003>; + entry-latency-us = <350>; + exit-latency-us = <461>; + min-residency-us = <1890>; + local-timer-stop; + }; + + LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { + compatible = "arm,idle-state"; + idle-state-name = "little-rail-power-down"; + arm,psci-suspend-param = <0x40000004>; + entry-latency-us = <360>; + exit-latency-us = <531>; + min-residency-us = <3934>; + local-timer-stop; + }; + + BIG_CPU_SLEEP_0: cpu-sleep-1-0 { + compatible = "arm,idle-state"; + idle-state-name = "big-power-down"; + arm,psci-suspend-param = <0x40000003>; + entry-latency-us = <264>; + exit-latency-us = <621>; + min-residency-us = <952>; + local-timer-stop; + }; + + BIG_CPU_SLEEP_1: cpu-sleep-1-1 { + compatible = "arm,idle-state"; + idle-state-name = "big-rail-power-down"; + arm,psci-suspend-param = <0x40000004>; + entry-latency-us = <702>; + exit-latency-us = <1061>; + min-residency-us = <4488>; + local-timer-stop; + }; + + CLUSTER_SLEEP_0: cluster-sleep-0 { + compatible = "arm,idle-state"; + idle-state-name = "cluster-power-down"; + arm,psci-suspend-param = <0x400000F4>; + entry-latency-us = <3263>; + exit-latency-us = <6562>; + min-residency-us = <9987>; + local-timer-stop; + }; +}; + +&CPU0 { + /delete-property/ power-domains; + /delete-property/ power-domain-names; + cpu-idle-states = <&LITTLE_CPU_SLEEP_0 + &LITTLE_CPU_SLEEP_1 + &CLUSTER_SLEEP_0>; +}; + +&CPU1 { + /delete-property/ power-domains; + /delete-property/ power-domain-names; + cpu-idle-states = <&LITTLE_CPU_SLEEP_0 + &LITTLE_CPU_SLEEP_1 + &CLUSTER_SLEEP_0>; +}; + +&CPU2 { + /delete-property/ power-domains; + /delete-property/ power-domain-names; + cpu-idle-states = <&LITTLE_CPU_SLEEP_0 + &LITTLE_CPU_SLEEP_1 + &CLUSTER_SLEEP_0>; +}; + +&CPU3 { + /delete-property/ power-domains; + /delete-property/ power-domain-names; + cpu-idle-states = <&LITTLE_CPU_SLEEP_0 + &LITTLE_CPU_SLEEP_1 + &CLUSTER_SLEEP_0>; +}; + +&CPU4 { + /delete-property/ power-domains; + /delete-property/ power-domain-names; + cpu-idle-states = <&BIG_CPU_SLEEP_0 + &BIG_CPU_SLEEP_1 + &CLUSTER_SLEEP_0>; +}; + +&CPU5 { + /delete-property/ power-domains; + /delete-property/ power-domain-names; + cpu-idle-states = <&BIG_CPU_SLEEP_0 + &BIG_CPU_SLEEP_1 + &CLUSTER_SLEEP_0>; +}; + +&CPU6 { + /delete-property/ power-domains; + /delete-property/ power-domain-names; + cpu-idle-states = <&BIG_CPU_SLEEP_0 + &BIG_CPU_SLEEP_1 + &CLUSTER_SLEEP_0>; +}; + +&CPU7 { + /delete-property/ power-domains; + /delete-property/ power-domain-names; + cpu-idle-states = <&BIG_CPU_SLEEP_0 + &BIG_CPU_SLEEP_1 + &CLUSTER_SLEEP_0>; +}; + /* * Reserved memory changes * diff --git a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts index 194ebeb3259c..c6e2c571b452 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts @@ -5,6 +5,7 @@ /dts-v1/; +#include <dt-bindings/leds/common.h> #include <dt-bindings/pinctrl/qcom,pmic-gpio.h> #include <dt-bindings/regulator/qcom,rpmh-regulator.h> #include <dt-bindings/sound/qcom,q6afe.h> @@ -43,14 +44,14 @@ regulator-always-on; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; autorepeat; pinctrl-names = "default"; pinctrl-0 = <&vol_up_pin_a>; - vol-up { + key-vol-up { label = "Volume Up"; linux,code = <KEY_VOLUMEUP>; gpios = <&pm8998_gpio 6 GPIO_ACTIVE_LOW>; @@ -60,22 +61,28 @@ leds { compatible = "gpio-leds"; - user4 { + led-0 { label = "green:user4"; + function = LED_FUNCTION_INDICATOR; + color = <LED_COLOR_ID_GREEN>; gpios = <&pm8998_gpio 13 GPIO_ACTIVE_HIGH>; linux,default-trigger = "panic-indicator"; default-state = "off"; }; - wlan { + led-1 { label = "yellow:wlan"; + function = LED_FUNCTION_WLAN; + color = <LED_COLOR_ID_YELLOW>; gpios = <&pm8998_gpio 9 GPIO_ACTIVE_HIGH>; linux,default-trigger = "phy0tx"; default-state = "off"; }; - bt { + led-2 { label = "blue:bt"; + function = LED_FUNCTION_BLUETOOTH; + color = <LED_COLOR_ID_BLUE>; gpios = <&pm8998_gpio 5 GPIO_ACTIVE_HIGH>; linux,default-trigger = "bluetooth-power"; default-state = "off"; @@ -436,6 +443,10 @@ status = "okay"; }; +&gpi_dma1 { + status = "okay"; +}; + &gpu { status = "okay"; zap-shader { @@ -488,12 +499,14 @@ &i2c11 { /* On Low speed expansion */ + clock-frequency = <100000>; label = "LS-I2C1"; status = "okay"; }; &i2c14 { /* On Low speed expansion */ + clock-frequency = <100000>; label = "LS-I2C0"; status = "okay"; }; @@ -569,7 +582,7 @@ "OPTION2", "PM845_SLB"; - cam0_dvdd_1v2_en_default: cam0-dvdd-1v2-en { + cam0_dvdd_1v2_en_default: cam0-dvdd-1v2-en-state { pins = "gpio12"; function = "normal"; @@ -578,7 +591,7 @@ qcom,drive-strength = <PMIC_GPIO_STRENGTH_HIGH>; }; - cam0_avdd_2v8_en_default: cam0-avdd-2v8-en { + cam0_avdd_2v8_en_default: cam0-avdd-2v8-en-state { pins = "gpio10"; function = "normal"; @@ -587,7 +600,7 @@ qcom,drive-strength = <PMIC_GPIO_STRENGTH_HIGH>; }; - vol_up_pin_a: vol-up-active { + vol_up_pin_a: vol-up-active-state { pins = "gpio6"; function = "normal"; input-enable; @@ -606,10 +619,40 @@ }; }; +&pmi8998_lpg { + status = "okay"; + + qcom,power-source = <1>; + + led@3 { + reg = <3>; + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_HEARTBEAT; + function-enumerator = <3>; + + linux,default-trigger = "heartbeat"; + default-state = "on"; + }; + + led@4 { + reg = <4>; + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_INDICATOR; + function-enumerator = <2>; + }; + + led@5 { + reg = <5>; + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_INDICATOR; + function-enumerator = <1>; + }; +}; + /* QUAT I2S Uses 4 I2S SD Lines for audio on LT9611 HDMI Bridge */ &q6afedai { qi2s@22 { - reg = <22>; + reg = <QUATERNARY_MI2S_RX>; qcom,sd-lines = <0 1 2 3>; }; }; @@ -718,7 +761,7 @@ }; codec { - sound-dai = <<9611_codec 0>; + sound-dai = <<9611_codec 0>; }; }; @@ -733,7 +776,7 @@ }; codec { - sound-dai = <&left_spkr>, <&right_spkr>, <&swm 0>, <&wcd9340 0>; + sound-dai = <&left_spkr>, <&right_spkr>, <&swm 0>, <&wcd9340 0>; }; }; @@ -1144,7 +1187,8 @@ }; &camss { - vdda-supply = <&vreg_l1a_0p875>; + vdda-phy-supply = <&vreg_l1a_0p875>; + vdda-pll-supply = <&vreg_l26a_1p2>; status = "ok"; diff --git a/arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi new file mode 100644 index 000000000000..20f275f8694d --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi @@ -0,0 +1,614 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * SDM845 LG G7 / V35 (judyln / judyp) common device tree + * + * Copyright (c) 2022, The Linux Foundation. All rights reserved. + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pinctrl/qcom,pmic-gpio.h> +#include <dt-bindings/regulator/qcom,rpmh-regulator.h> + +#include "sdm845.dtsi" +#include "pm8998.dtsi" +#include "pmi8998.dtsi" + +/delete-node/ &adsp_mem; +/delete-node/ &cdsp_mem; +/delete-node/ &gpu_mem; +/delete-node/ &ipa_fw_mem; +/delete-node/ &mba_region; +/delete-node/ &mpss_region; +/delete-node/ &qseecom_mem; +/delete-node/ &rmtfs_mem; +/delete-node/ &slpi_mem; +/delete-node/ &spss_mem; +/delete-node/ &venus_mem; +/delete-node/ &wlan_msa_mem; + +/ { + chosen { + #address-cells = <2>; + #size-cells = <2>; + ranges; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + qseecom_mem: memory@b2000000 { + reg = <0 0xb2000000 0 0x1800000>; + no-map; + }; + + gpu_mem: memory@8c415000 { + reg = <0 0x8c415000 0 0x2000>; + no-map; + }; + + ipa_fw_mem: memory@8c400000 { + reg = <0 0x8c400000 0 0x10000>; + no-map; + }; + + adsp_mem: memory@8c500000 { + reg = <0 0x8c500000 0 0x1e00000>; + no-map; + }; + + wlan_msa_mem: memory@8e300000 { + reg = <0 0x8e300000 0 0x100000>; + no-map; + }; + + mpss_region: memory@8e400000 { + reg = <0 0x8e400000 0 0x8900000>; + no-map; + }; + + venus_mem: memory@96d00000 { + reg = <0 0x96d00000 0 0x500000>; + no-map; + }; + + cdsp_mem: memory@97200000 { + reg = <0 0x97200000 0 0x800000>; + no-map; + }; + + mba_region: memory@97a00000 { + reg = <0 0x97a00000 0 0x200000>; + no-map; + }; + + slpi_mem: memory@97c00000 { + reg = <0 0x97c00000 0 0x1400000>; + no-map; + }; + + spss_mem: memory@99000000 { + reg = <0 0x99000000 0 0x100000>; + no-map; + }; + + /* Framebuffer region */ + memory@9d400000 { + reg = <0x0 0x9d400000 0x0 0x2400000>; + no-map; + }; + + /* rmtfs lower guard */ + memory@f0800000 { + reg = <0 0xf0800000 0 0x1000>; + no-map; + }; + + rmtfs_mem: memory@f0801000 { + compatible = "qcom,rmtfs-mem"; + reg = <0 0xf0801000 0 0x200000>; + no-map; + + qcom,client-id = <1>; + qcom,vmid = <15>; + }; + + /* rmtfs upper guard */ + memory@f0a01000 { + reg = <0 0xf0a01000 0 0x1000>; + no-map; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&vol_up_pin_a>; + + label = "GPIO Buttons"; + + key-vol-up { + label = "Volume up"; + linux,code = <KEY_VOLUMEUP>; + gpios = <&pm8998_gpio 6 GPIO_ACTIVE_LOW>; + }; + }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + }; + + /* + * Apparently RPMh does not provide support for PM8998 S4 because it + * is always-on; model it as a fixed regulator. + */ + vreg_s4a_1p8: pm8998-smps4-regulator { + compatible = "regulator-fixed"; + regulator-name = "vreg_s4a_1p8"; + + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-always-on; + regulator-boot-on; + + vin-supply = <&vph_pwr>; + }; +}; + +&adsp_pas { + status = "okay"; +}; + +&apps_rsc { + pm8998-rpmh-regulators { + compatible = "qcom,pm8998-rpmh-regulators"; + qcom,pmic-id = "a"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-s8-supply = <&vph_pwr>; + vdd-s9-supply = <&vph_pwr>; + vdd-s10-supply = <&vph_pwr>; + vdd-s11-supply = <&vph_pwr>; + vdd-s12-supply = <&vph_pwr>; + vdd-s13-supply = <&vph_pwr>; + vdd-l1-l27-supply = <&vreg_s7a_1p025>; + vdd-l2-l8-l17-supply = <&vreg_s3a_1p35>; + vdd-l3-l11-supply = <&vreg_s7a_1p025>; + vdd-l4-l5-supply = <&vreg_s7a_1p025>; + vdd-l6-supply = <&vph_pwr>; + vdd-l7-l12-l14-l15-supply = <&vreg_s5a_2p04>; + vdd-l9-supply = <&vreg_bob>; + vdd-l10-l23-l25-supply = <&vreg_bob>; + vdd-l13-l19-l21-supply = <&vreg_bob>; + vdd-l16-l28-supply = <&vreg_bob>; + vdd-l18-l22-supply = <&vreg_bob>; + vdd-l20-l24-supply = <&vreg_bob>; + vdd-l26-supply = <&vreg_s3a_1p35>; + vin-lvs-1-2-supply = <&vreg_s4a_1p8>; + + vreg_s2a_1p125: smps2 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + }; + + vreg_s3a_1p35: smps3 { + regulator-min-microvolt = <1352000>; + regulator-max-microvolt = <1352000>; + }; + + vreg_s5a_2p04: smps5 { + regulator-min-microvolt = <1904000>; + regulator-max-microvolt = <2040000>; + }; + + vreg_s7a_1p025: smps7 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1028000>; + }; + + vdd_qusb_hs0: + vdda_hp_pcie_core: + vdda_mipi_csi0_0p9: + vdda_mipi_csi1_0p9: + vdda_mipi_csi2_0p9: + vdda_mipi_dsi0_pll: + vdda_mipi_dsi1_pll: + vdda_qlink_lv: + vdda_qlink_lv_ck: + vdda_qrefs_0p875: + vdda_pcie_core: + vdda_pll_cc_ebi01: + vdda_pll_cc_ebi23: + vdda_sp_sensor: + vdda_ufs1_core: + vdda_ufs2_core: + vdda_usb1_ss_core: + vdda_usb2_ss_core: + vreg_l1a_0p875: ldo1 { + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vddpx_10: + vreg_l2a_1p2: ldo2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-always-on; + }; + + vreg_l3a_1p0: ldo3 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vdd_wcss_cx: + vdd_wcss_mx: + vdda_wcss_pll: + vreg_l5a_0p8: ldo5 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vddpx_13: + vreg_l6a_1p8: ldo6 { + regulator-min-microvolt = <1856000>; + regulator-max-microvolt = <1856000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l7a_1p8: ldo7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l8a_1p2: ldo8 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1248000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l9a_1p8: ldo9 { + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <2928000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l10a_1p8: ldo10 { + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <2928000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l11a_1p0: ldo11 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1048000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vdd_qfprom: + vdd_qfprom_sp: + vdda_apc1_cs_1p8: + vdda_gfx_cs_1p8: + vdda_qrefs_1p8: + vdda_qusb_hs0_1p8: + vddpx_11: + vreg_l12a_1p8: ldo12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vddpx_2: + vreg_l13a_2p95: ldo13 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l14a_1p88: ldo14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1880000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l15a_1p8: ldo15 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l17a_1p3: ldo17 { + regulator-min-microvolt = <1304000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l18a_2p7: ldo18 { + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l20a_2p95: ldo20 { + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l21a_2p95: ldo21 { + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l22a_2p85: ldo22 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l23a_3p3: ldo23 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3312000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vdda_qusb_hs0_3p1: + vreg_l24a_3p075: ldo24 { + regulator-min-microvolt = <3088000>; + regulator-max-microvolt = <3088000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l25a_3p3: ldo25 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3312000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vdda_hp_pcie_1p2: + vdda_hv_ebi0: + vdda_hv_ebi1: + vdda_hv_ebi2: + vdda_hv_ebi3: + vdda_mipi_csi_1p25: + vdda_mipi_dsi0_1p2: + vdda_mipi_dsi1_1p2: + vdda_pcie_1p2: + vdda_ufs1_1p2: + vdda_ufs2_1p2: + vdda_usb1_ss_1p2: + vdda_usb2_ss_1p2: + vreg_l26a_1p2: ldo26 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l28a_3p0: ldo28 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_lvs1a_1p8: lvs1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vreg_lvs2a_1p8: lvs2 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + }; + + pmi8998-rpmh-regulators { + compatible = "qcom,pmi8998-rpmh-regulators"; + qcom,pmic-id = "b"; + + vdd-bob-supply = <&vph_pwr>; + + vreg_bob: bob { + regulator-min-microvolt = <3312000>; + regulator-max-microvolt = <3600000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>; + regulator-allow-bypass; + }; + }; + + pm8005-rpmh-regulators { + compatible = "qcom,pm8005-rpmh-regulators"; + qcom,pmic-id = "c"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + + vreg_s3c_0p6: smps3 { + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <600000>; + }; + }; +}; + +&cdsp_pas { + status = "okay"; +}; + +&dispcc { + status = "disabled"; +}; + +&gcc { + protected-clocks = <GCC_QSPI_CORE_CLK>, + <GCC_QSPI_CORE_CLK_SRC>, + <GCC_QSPI_CNOC_PERIPH_AHB_CLK>, + <GCC_LPASS_Q6_AXI_CLK>, + <GCC_LPASS_SWAY_CLK>; +}; + +&gpu { + status = "okay"; + + zap-shader { + memory-region = <&gpu_mem>; + }; +}; + +&ipa { + status = "okay"; + modem-init; +}; + +&mss_pil { + status = "okay"; +}; + +&pm8998_pon { + resin { + compatible = "qcom,pm8941-resin"; + interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>; + debounce = <15625>; + bias-pull-up; + linux,code = <KEY_VOLUMEDOWN>; + }; +}; + +&sdhc_2 { + status = "okay"; + + cd-gpios = <&tlmm 126 GPIO_ACTIVE_LOW>; + + pinctrl-names = "default"; + pinctrl-0 = <&sdc2_clk &sdc2_cmd &sdc2_data &sd_card_det_n>; + + vmmc-supply = <&vreg_l21a_2p95>; + vqmmc-supply = <&vddpx_2>; +}; + +/* + * UFS works partially and only with clk_ignore_unused. + * Sometimes it crashes with I/O errors. + */ +&ufs_mem_hc { + status = "okay"; + + reset-gpios = <&tlmm 150 GPIO_ACTIVE_LOW>; + + vcc-supply = <&vreg_l20a_2p95>; + vcc-max-microamp = <600000>; +}; + +&ufs_mem_phy { + status = "okay"; + + vdda-phy-supply = <&vdda_ufs1_core>; + vdda-pll-supply = <&vdda_ufs1_1p2>; +}; + +&usb_1 { + status = "okay"; +}; + +&usb_1_dwc3 { + /* TODO: these devices have usb id pin */ + dr_mode = "peripheral"; +}; + +&usb_1_hsphy { + status = "okay"; + + vdd-supply = <&vdda_usb1_ss_core>; + vdda-pll-supply = <&vdda_qusb_hs0_1p8>; + vdda-phy-dpdm-supply = <&vdda_qusb_hs0_3p1>; + + qcom,imp-res-offset-value = <8>; + qcom,hstx-trim-value = <QUSB2_V2_HSTX_TRIM_21_6_MA>; + qcom,preemphasis-level = <QUSB2_V2_PREEMPHASIS_5_PERCENT>; + qcom,preemphasis-width = <QUSB2_V2_PREEMPHASIS_WIDTH_HALF_BIT>; +}; + +&usb_1_qmpphy { + status = "okay"; + + vdda-phy-supply = <&vdda_usb1_ss_1p2>; + vdda-pll-supply = <&vdda_usb1_ss_core>; +}; + +/* PINCTRL - additions to nodes defined in sdm845.dtsi */ + +&tlmm { + gpio-reserved-ranges = <28 4>, <81 4>; + + sdc2_clk: sdc2-clk { + pinconf { + pins = "sdc2_clk"; + bias-disable; + + /* + * It seems that mmc_test reports errors if drive + * strength is not 16 on clk, cmd, and data pins. + * + * TODO: copy-pasted from mtp, try other values + * on these devices. + */ + drive-strength = <16>; + }; + }; + + sdc2_cmd: sdc2-cmd { + pinconf { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <16>; + }; + }; + + sdc2_data: sdc2-data { + pinconf { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <16>; + }; + }; + + sd_card_det_n: sd-card-det-n { + pinmux { + pins = "gpio126"; + function = "gpio"; + }; + + pinconf { + pins = "gpio126"; + bias-pull-up; + }; + }; +}; + +&pm8998_gpio { + vol_up_pin_a: vol-up-active-pins { + pins = "gpio6"; + function = "normal"; + input-enable; + bias-pull-up; + qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sdm845-lg-judyln.dts b/arch/arm64/boot/dts/qcom/sdm845-lg-judyln.dts new file mode 100644 index 000000000000..7d967a104b3e --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sdm845-lg-judyln.dts @@ -0,0 +1,68 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * SDM845 LG G7 (judyln) device tree. + * + * Copyright (c) 2022, The Linux Foundation. All rights reserved. + */ + +/dts-v1/; + +#include "sdm845-lg-common.dtsi" + +/ { + model = "LG G7 ThinQ"; + compatible = "lg,judyln", "qcom,sdm845"; + + chosen { + framebuffer@9d400000 { + compatible = "simple-framebuffer"; + reg = <0x0 0x9d400000 0x0 (1440 * 3120 * 4)>; + width = <1440>; + height = <3120>; + stride = <(1440 * 4)>; + format = "a8r8g8b8"; + lab-supply = <&lab>; + ibb-supply = <&ibb>; + }; + }; + + /* Additional ThinQ key */ + gpio-keys { + pinctrl-0 = <&vol_up_pin_a &thinq_key_default>; + + key-thinq { + label = "ThinQ"; + linux,code = <KEY_ASSISTANT>; + interrupt-parent = <&tlmm>; + interrupts = <89 IRQ_TYPE_LEVEL_LOW>; + }; + }; +}; + +&adsp_pas { + firmware-name = "qcom/sdm845/judyln/adsp.mbn"; +}; + +&cdsp_pas { + firmware-name = "qcom/sdm845/judyln/cdsp.mbn"; +}; + +&gpu { + zap-shader { + firmware-name = "qcom/sdm845/judyln/a630_zap.mbn"; + }; +}; + +&mss_pil { + firmware-name = "qcom/sdm845/judyln/mba.mbn", "qcom/sdm845/judyln/modem.mbn"; +}; + +&tlmm { + thinq_key_default: thinq-key-default { + pins = "gpio89"; + function = "gpio"; + + drive-strength = <2>; + bias-pull-up; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sdm845-lg-judyp.dts b/arch/arm64/boot/dts/qcom/sdm845-lg-judyp.dts new file mode 100644 index 000000000000..d17d4d4d5609 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sdm845-lg-judyp.dts @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * SDM845 LG V35 (judyp) device tree. + * + * Copyright (c) 2022, The Linux Foundation. All rights reserved. + */ + +/dts-v1/; + +#include "sdm845-lg-common.dtsi" + +/ { + model = "LG V35 ThinQ"; + compatible = "lg,judyp", "qcom,sdm845"; + + chosen { + framebuffer@9d400000 { + compatible = "simple-framebuffer"; + reg = <0x0 0x9d400000 0x0 (1440 * 2880 * 4)>; + width = <1440>; + height = <2880>; + stride = <(1440 * 4)>; + format = "a8r8g8b8"; + }; + }; +}; + +&adsp_pas { + firmware-name = "qcom/sdm845/judyp/adsp.mbn"; +}; + +&cdsp_pas { + firmware-name = "qcom/sdm845/judyp/cdsp.mbn"; +}; + +&gpu { + zap-shader { + firmware-name = "qcom/sdm845/judyp/a630_zap.mbn"; + }; +}; + +&mss_pil { + firmware-name = "qcom/sdm845/judyp/mba.mbn", "qcom/sdm845/judyp/modem.mbn"; +}; diff --git a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi index 07b729f9fec5..392461c29e76 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi @@ -34,14 +34,14 @@ pinctrl-names = "default"; pinctrl-0 = <&volume_down_gpio &volume_up_gpio>; - vol-down { + key-vol-down { label = "Volume down"; linux,code = <KEY_VOLUMEDOWN>; gpios = <&pm8998_gpio 5 GPIO_ACTIVE_LOW>; debounce-interval = <15>; }; - vol-up { + key-vol-up { label = "Volume up"; linux,code = <KEY_VOLUMEUP>; gpios = <&pm8998_gpio 6 GPIO_ACTIVE_LOW>; @@ -440,7 +440,7 @@ }; &pm8998_gpio { - volume_down_gpio: pm8998_gpio5 { + volume_down_gpio: pm8998-gpio5-state { pinconf { pins = "gpio5"; function = "normal"; @@ -450,7 +450,7 @@ }; }; - volume_up_gpio: pm8998_gpio6 { + volume_up_gpio: pm8998-gpio6-state { pinconf { pins = "gpio6"; function = "normal"; diff --git a/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts b/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts index 103cc40816fd..83261c9bb4f2 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts @@ -2,11 +2,13 @@ /* * Copyright (c) 2022, Alexander Martinz <amartinz@shiftphones.com> * Copyright (c) 2022, Caleb Connolly <caleb@connolly.tech> + * Copyright (c) 2022, Dylan Van Assche <me@dylanvanassche.be> */ /dts-v1/; #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/leds/common.h> #include <dt-bindings/regulator/qcom,rpmh-regulator.h> #include "sdm845.dtsi" #include "pm8998.dtsi" @@ -48,7 +50,7 @@ pinctrl-names = "default"; pinctrl-0 = <&volume_up_gpio>; - vol-up { + key-vol-up { label = "volume_up"; linux,code = <KEY_VOLUMEUP>; gpios = <&pm8998_gpio 6 GPIO_ACTIVE_LOW>; @@ -468,7 +470,7 @@ }; &i2c5 { - status="okay"; + status = "okay"; touchscreen@38 { compatible = "focaltech,fts8719"; @@ -508,7 +510,7 @@ }; &pm8998_gpio { - volume_up_gpio: pm8998_gpio6 { + volume_up_gpio: pm8998-gpio6-state { pinconf { pins = "gpio6"; function = "normal"; @@ -529,6 +531,33 @@ }; }; +&pmi8998_lpg { + status = "okay"; + + multi-led { + color = <LED_COLOR_ID_RGB>; + function = LED_FUNCTION_STATUS; + + #address-cells = <1>; + #size-cells = <0>; + + led@3 { + reg = <3>; + color = <LED_COLOR_ID_BLUE>; + }; + + led@4 { + reg = <4>; + color = <LED_COLOR_ID_GREEN>; + }; + + led@5 { + reg = <5>; + color = <LED_COLOR_ID_RED>; + }; + }; +}; + &qup_uart9_default { pinconf-rx { pins = "gpio5"; diff --git a/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama-akatsuki.dts b/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama-akatsuki.dts index 8a0d94e7f598..2f5e12deaada 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama-akatsuki.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama-akatsuki.dts @@ -19,8 +19,9 @@ }; &vreg_l22a_2p8 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; + /* Note: Round-down from 2700000 to be a multiple of PLDO step-size 8000 */ + regulator-min-microvolt = <2696000>; + regulator-max-microvolt = <2696000>; }; &vreg_l28a_2p8 { diff --git a/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi b/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi index 281fe6dea62a..51ee42e3c995 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi @@ -19,7 +19,7 @@ /* Neither Camera Focus, nor Camera Shutter seem to work... */ - vol-down { + key-vol-down { label = "volume_down"; gpios = <&pm8998_gpio 5 GPIO_ACTIVE_LOW>; linux,code = <KEY_VOLUMEDOWN>; diff --git a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts index d88dc07205f7..82c27f90d300 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts @@ -45,7 +45,7 @@ pinctrl-names = "default"; pinctrl-0 = <&vol_up_pin_a>; - vol-up { + key-vol-up { label = "Volume Up"; linux,code = <KEY_VOLUMEUP>; gpios = <&pm8998_gpio 6 GPIO_ACTIVE_LOW>; @@ -306,7 +306,7 @@ }; &pm8998_gpio { - vol_up_pin_a: vol-up-active { + vol_up_pin_a: vol-up-active-state { pins = "gpio6"; function = "normal"; input-enable; @@ -339,7 +339,7 @@ /* QUAT I2S Uses 1 I2S SD Line for audio on TAS2559/60 amplifiers */ &q6afedai { qi2s@22 { - reg = <22>; + reg = <QUATERNARY_MI2S_RX>; qcom,sd-lines = <0>; }; }; @@ -419,7 +419,7 @@ }; codec { - sound-dai = <&wcd9340 0>; + sound-dai = <&wcd9340 0>; }; }; diff --git a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts new file mode 100644 index 000000000000..7747081b9887 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts @@ -0,0 +1,762 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2020, Xilin Wu <strongtz@yeah.net> + * Copyright (c) 2022, Molly Sophia <mollysophia379@gmail.com> + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pinctrl/qcom,pmic-gpio.h> +#include <dt-bindings/regulator/qcom,rpmh-regulator.h> +#include <dt-bindings/input/linux-event-codes.h> +#include <dt-bindings/sound/qcom,q6afe.h> +#include <dt-bindings/sound/qcom,q6asm.h> +#include "sdm845.dtsi" +#include "pm8998.dtsi" +#include "pmi8998.dtsi" +#include "pm8005.dtsi" + +/* + * Delete following upstream (sdm845.dtsi) reserved + * memory mappings which are different in this device. + */ +/delete-node/ &rmtfs_mem; +/delete-node/ &adsp_mem; +/delete-node/ &wlan_msa_mem; +/delete-node/ &mpss_region; +/delete-node/ &venus_mem; +/delete-node/ &cdsp_mem; +/delete-node/ &mba_region; +/delete-node/ &slpi_mem; +/delete-node/ &spss_mem; + +/ { + model = "Xiaomi Mi MIX 2S"; + compatible = "xiaomi,polaris", "qcom,sdm845"; + chassis-type = "handset"; + + /* required for bootloader to select correct board */ + qcom,msm-id = <0x141 0x20001>; + qcom,board-id = <0x2a 0x0>; + + aliases { + serial0 = &uart9; + serial1 = &uart6; + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + + pinctrl-names = "default"; + pinctrl-0 = <&volume_up_gpio>; + + key-vol-up { + label = "Volume Up"; + linux,code = <KEY_VOLUMEUP>; + gpios = <&pm8998_gpio 6 GPIO_ACTIVE_LOW>; + debounce-interval = <15>; + }; + }; + + reserved-memory { + adsp_mem: memory@8c500000 { + reg = <0 0x8c500000 0 0x1e00000>; + no-map; + }; + + wlan_msa_mem: memory@8e300000 { + reg = <0 0x8e300000 0 0x100000>; + no-map; + }; + + mpss_region: memory@8e400000 { + reg = <0 0x8e400000 0 0x7800000>; + no-map; + }; + + venus_mem: memory@95c00000 { + reg = <0 0x95c00000 0 0x500000>; + no-map; + }; + + cdsp_mem: memory@96100000 { + reg = <0 0x96100000 0 0x800000>; + no-map; + }; + + mba_region: memory@96900000 { + reg = <0 0x96900000 0 0x200000>; + no-map; + }; + + slpi_mem: memory@96b00000 { + reg = <0 0x96b00000 0 0x1400000>; + no-map; + }; + + spss_mem: memory@97f00000 { + reg = <0 0x97f00000 0 0x100000>; + no-map; + }; + + rmtfs_mem: memory@f6301000 { + compatible = "qcom,rmtfs-mem"; + reg = <0 0xf6301000 0 0x200000>; + no-map; + + qcom,client-id = <1>; + qcom,vmid = <15>; + }; + }; + + battery: battery { + compatible = "simple-battery"; + + charge-full-design-microamp-hours = <3400000>; + voltage-min-design-microvolt = <3400000>; + voltage-max-design-microvolt = <4400000>; + }; + + vreg_tp_vddio: vreg-tp-vddio { + compatible = "regulator-fixed"; + regulator-name = "vreg_tp_vddio"; + + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + gpio = <&tlmm 23 0>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + }; + + vreg_s4a_1p8: vreg-s4a-1p8 { + compatible = "regulator-fixed"; + regulator-name = "vreg_s4a_1p8"; + + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; +}; + +&apps_rsc { + pm8998-rpmh-regulators { + compatible = "qcom,pm8998-rpmh-regulators"; + qcom,pmic-id = "a"; + + vreg_s2a_1p1: smps2 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + }; + + vreg_s3a_1p35: smps3 { + regulator-min-microvolt = <1352000>; + regulator-max-microvolt = <1352000>; + }; + + vreg_s5a_2p04: smps5 { + regulator-min-microvolt = <1904000>; + regulator-max-microvolt = <2040000>; + }; + + vreg_s7a_1p025: smps7 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1028000>; + }; + + vdda_mipi_dsi0_pll: + vdda_ufs1_core: + vreg_l1a_0p875: ldo1 { + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l2a_1p2: ldo2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-always-on; + }; + + vreg_l3a_1p0: ldo3 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l5a_0p8: ldo5 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l6a_1p8: ldo6 { + regulator-min-microvolt = <1856000>; + regulator-max-microvolt = <1856000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l7a_1p8: ldo7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l8a_1p2: ldo8 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1248000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l9a_1p8: ldo9 { + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <2928000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l10a_2p95: ldo10 { + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <2928000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l11a_1p05: ldo11 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1048000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l12a_1p8: ldo12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l13a_2p95: ldo13 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l14a_1p8: ldo14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1880000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-always-on; + }; + + vreg_l15a_1p8: ldo15 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l16a_2p7: ldo16 { + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <2704000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l17a_1p3: ldo17 { + regulator-min-microvolt = <1304000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-always-on; + }; + + vreg_l18a_2p9: ldo18 { + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l19a_3p1: ldo19 { + regulator-min-microvolt = <2856000>; + regulator-max-microvolt = <3104000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l20a_2p95: ldo20 { + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l21a_2p95: ldo21 { + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l22a_3p3: ldo22 { + regulator-min-microvolt = <2864000>; + regulator-max-microvolt = <3312000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l23a_3p3: ldo23 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3312000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l24a_3p075: ldo24 { + regulator-min-microvolt = <3088000>; + regulator-max-microvolt = <3088000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l25a_3p3: ldo25 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3312000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-always-on; + }; + + vdda_mipi_dsi0_1p2: + vdda_ufs1_1p2: + vreg_l26a_1p2: ldo26 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l28a_3p0: ldo28 { + regulator-min-microvolt = <2856000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-always-on; + }; + + vreg_lvs1a_1p8: lvs1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vreg_lvs2a_1p8: lvs2 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + }; + + pmi8998-rpmh-regulators { + compatible = "qcom,pmi8998-rpmh-regulators"; + qcom,pmic-id = "b"; + + vreg_bob: bob { + regulator-min-microvolt = <3312000>; + regulator-max-microvolt = <3600000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>; + regulator-allow-bypass; + }; + }; + + pm8005-rpmh-regulators { + compatible = "qcom,pm8005-rpmh-regulators"; + qcom,pmic-id = "c"; + + vreg_smp3c_0p6: smps3 { + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <600000>; + regulator-always-on; + }; + }; +}; + +&cdsp_pas { + firmware-name = "qcom/sdm845/polaris/cdsp.mbn"; + status = "okay"; +}; + +&dsi0 { + vdda-supply = <&vdda_mipi_dsi0_1p2>; + status = "okay"; + + display_panel: panel@0 { + compatible = "jdi,fhd-nt35596s"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>; + vddio-supply = <&vreg_l14a_1p8>; + backlight = <&pmi8998_wled>; + vddpos-supply = <&lab>; + vddneg-supply = <&ibb>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sde_dsi_active>; + pinctrl-1 = <&sde_dsi_suspend>; + + port { + panel_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + }; +}; + +&dsi0_out { + remote-endpoint = <&panel_in>; + data-lanes = <0 1 2 3>; +}; + +&dsi0_phy { + vdds-supply = <&vdda_mipi_dsi0_pll>; + status = "okay"; +}; + +&gcc { + protected-clocks = <GCC_QSPI_CORE_CLK>, + <GCC_QSPI_CORE_CLK_SRC>, + <GCC_QSPI_CNOC_PERIPH_AHB_CLK>, + <GCC_LPASS_Q6_AXI_CLK>, + <GCC_LPASS_SWAY_CLK>; +}; + +&gmu { + status = "okay"; +}; + +&gpi_dma0 { + status = "okay"; +}; + +&gpi_dma1 { + status = "okay"; +}; + +&gpu { + status = "okay"; + + zap-shader { + memory-region = <&gpu_mem>; + firmware-name = "qcom/sdm845/polaris/a630_zap.mbn"; + }; +}; + +&ibb { + regulator-min-microvolt = <4600000>; + regulator-max-microvolt = <6000000>; + regulator-over-current-protection; + regulator-pull-down; + regulator-soft-start; + qcom,discharge-resistor-kohms = <300>; +}; + +&ipa { + memory-region = <&ipa_fw_mem>; + firmware-name = "qcom/sdm845/polaris/ipa_fws.mbn"; + status = "okay"; +}; + +&i2c14 { + clock-frequency = <400000>; + dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, + <&gpi_dma1 1 6 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "okay"; + + touchscreen@20 { + compatible = "syna,rmi4-i2c"; + reg = <0x20>; + #address-cells = <1>; + #size-cells = <0>; + interrupts-extended = <&tlmm 125 0x2008>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&ts_int_default &ts_reset_default>; + pinctrl-1 = <&ts_int_sleep &ts_reset_sleep>; + + vdd-supply = <&vreg_l28a_3p0>; + vio-supply = <&vreg_tp_vddio>; + + syna,startup-delay-ms = <0xc8>; + syna,reset-delay-ms = <0xc8>; + + rmi4-f01@1 { + syna,nosleep-mode = <0x1>; + reg = <0x1>; + }; + + rmi4-f12@12 { + syna,rezero-wait-ms = <0xc8>; + syna,clip-x-high = <0x438>; + syna,clip-y-high = <0x870>; + syna,sensor-type = <0x1>; + syna,clip-x-low = <0x0>; + syna,clip-y-low = <0x0>; + }; + }; +}; + +&lab { + regulator-min-microvolt = <4600000>; + regulator-max-microvolt = <6000000>; + regulator-soft-start; + regulator-pull-down; +}; + +&mdss { + status = "okay"; +}; + +&mss_pil { + firmware-name = "qcom/sdm845/polaris/mba.mbn", "qcom/sdm845/polaris/modem.mbn"; + status = "okay"; +}; + +&pmi8998_wled { + qcom,current-limit-microamp = <20000>; + qcom,current-boost-limit = <970>; + qcom,ovp-millivolt = <19600>; + qcom,switching-freq = <600>; + qcom,num-strings = <4>; + qcom,cabc; + + status = "okay"; +}; + +&pm8998_gpio { + volume_up_gpio: pm8998_gpio6 { + pinconf { + qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>; + function = "normal"; + pins = "gpio6"; + input-enable; + bias-pull-up; + }; + }; +}; + +&pm8998_pon { + resin { + interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>; + compatible = "qcom,pm8941-resin"; + linux,code = <KEY_VOLUMEDOWN>; + debounce = <15625>; + bias-pull-up; + }; +}; + +&q6afedai { + qi2s@22 { + reg = <22>; + qcom,sd-lines = <0>; + }; +}; + +&q6asmdai { + dai@0 { + reg = <0>; + }; + + dai@1 { + reg = <1>; + }; + + dai@2 { + reg = <2>; + }; +}; + +&qupv3_id_0 { + status = "okay"; +}; + +&qupv3_id_1 { + status = "okay"; +}; + +&qup_i2c14_default { + pinconf { + pins = "gpio33", "gpio34"; + drive-strength = <2>; + bias-disable; + }; +}; + +&tlmm { + gpio-reserved-ranges = <0 4>, <81 4>; + + ts_reset_default: ts-reset-default { + pins = "gpio99"; + function = "gpio"; + drive-strength = <16>; + output-high; + }; + + ts_int_default: ts-int-default { + pins = "gpio125"; + function = "gpio"; + bias-pull-down; + drive-strength = <16>; + input-enable; + }; + + ts_reset_sleep: ts-reset-sleep { + pins = "gpio99"; + function = "gpio"; + bias-disable; + drive-strength = <2>; + }; + + ts_int_sleep: ts-int-sleep { + pins = "gpio125"; + function = "gpio"; + bias-pull-down; + drive-strength = <2>; + input-enable; + }; + + sde_dsi_active: sde-dsi-active { + pins = "gpio6", "gpio10"; + function = "gpio"; + drive-strength = <8>; + bias-disable = <0>; + }; + + sde_dsi_suspend: sde-dsi-suspend { + pins = "gpio6", "gpio10"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + wcd_intr_default: wcd-intr-default { + pins = "goui54"; + function = "gpio"; + input-enable; + bias-pull-down; + drive-strength = <2>; + }; +}; + +&uart6 { + status = "okay"; + + bluetooth { + compatible = "qcom,wcn3990-bt"; + + /* This path is relative to the qca/ subdir under lib/firmware. */ + firmware-name = "polaris/crnv21.bin"; + + vddio-supply = <&vreg_s4a_1p8>; + vddxo-supply = <&vreg_l7a_1p8>; + vddrf-supply = <&vreg_l17a_1p3>; + vddch0-supply = <&vreg_l25a_3p3>; + max-speed = <3200000>; + }; +}; + +&usb_1 { + /* We'll use this as USB 2.0 only */ + qcom,select-utmi-as-pipe-clk; + status = "okay"; +}; + +&usb_1_dwc3 { + dr_mode = "peripheral"; + + /* Fastest mode for USB 2 */ + maximum-speed = "high-speed"; + + /* Remove USB3 phy */ + phys = <&usb_1_hsphy>; + phy-names = "usb2-phy"; +}; + +&usb_1_hsphy { + vdda-phy-dpdm-supply = <&vreg_l24a_3p075>; + vdda-pll-supply = <&vreg_l12a_1p8>; + vdd-supply = <&vreg_l1a_0p875>; + + qcom,preemphasis-width = <QUSB2_V2_PREEMPHASIS_WIDTH_HALF_BIT>; + qcom,preemphasis-level = <QUSB2_V2_PREEMPHASIS_5_PERCENT>; + qcom,hstx-trim-value = <QUSB2_V2_HSTX_TRIM_21_6_MA>; + qcom,imp-res-offset-value = <8>; + + status = "okay"; +}; + +&usb_1_qmpphy { + vdda-pll-supply = <&vreg_l1a_0p875>; + vdda-phy-supply = <&vreg_l26a_1p2>; + status = "okay"; +}; + +&ufs_mem_hc { + reset-gpios = <&tlmm 150 GPIO_ACTIVE_LOW>; + vcc-supply = <&vreg_l20a_2p95>; + vcc-max-microamp = <800000>; + status = "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply = <&vdda_ufs1_core>; + vdda-pll-supply = <&vdda_ufs1_1p2>; + status = "okay"; +}; + +&venus { + firmware-name = "qcom/sdm845/polaris/venus.mbn"; + status = "okay"; +}; + +&wcd9340 { + pinctrl-0 = <&wcd_intr_default>; + pinctrl-names = "default"; + clock-names = "extclk"; + clocks = <&rpmhcc RPMH_LN_BB_CLK2>; + reset-gpios = <&tlmm 64 0>; + vdd-buck-sido-supply = <&vreg_s4a_1p8>; + vdd-buck-supply = <&vreg_s4a_1p8>; + vdd-tx-supply = <&vreg_s4a_1p8>; + vdd-rx-supply = <&vreg_s4a_1p8>; + vdd-io-supply = <&vreg_s4a_1p8>; + + qcom,micbias1-microvolt = <2700000>; + qcom,micbias2-microvolt = <1800000>; + qcom,micbias3-microvolt = <2700000>; + qcom,micbias4-microvolt = <2700000>; +}; + +&wifi { + vdd-0.8-cx-mx-supply = <&vreg_l5a_0p8>; + vdd-1.8-xo-supply = <&vreg_l7a_1p8>; + vdd-1.3-rfa-supply = <&vreg_l17a_1p3>; + vdd-3.3-ch0-supply = <&vreg_l25a_3p3>; + vdd-3.3-ch1-supply = <&vreg_l23a_3p3>; + + qcom,snoc-host-cap-skip-quirk; + status = "okay"; +}; + +/* PINCTRL - additions to nodes defined in sdm845.dtsi */ + +&qup_uart6_default { + pinmux { + pins = "gpio45", "gpio46", "gpio47", "gpio48"; + function = "qup6"; + }; + + cts { + pins = "gpio45"; + bias-disable; + }; + + rts-tx { + pins = "gpio46", "gpio47"; + drive-strength = <2>; + bias-disable; + }; + + rx { + pins = "gpio48"; + bias-pull-up; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 038538c8c614..f0e286715d1b 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -188,7 +188,7 @@ }; }; - cpus { + cpus: cpus { #address-cells = <2>; #size-cells = <0>; @@ -197,15 +197,14 @@ compatible = "qcom,kryo385"; reg = <0x0 0x0>; enable-method = "psci"; - cpu-idle-states = <&LITTLE_CPU_SLEEP_0 - &LITTLE_CPU_SLEEP_1 - &CLUSTER_SLEEP_0>; capacity-dmips-mhz = <611>; dynamic-power-coefficient = <290>; qcom,freq-domain = <&cpufreq_hw 0>; operating-points-v2 = <&cpu0_opp_table>; interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + power-domains = <&CPU_PD0>; + power-domain-names = "psci"; #cooling-cells = <2>; next-level-cache = <&L2_0>; L2_0: l2-cache { @@ -222,15 +221,14 @@ compatible = "qcom,kryo385"; reg = <0x0 0x100>; enable-method = "psci"; - cpu-idle-states = <&LITTLE_CPU_SLEEP_0 - &LITTLE_CPU_SLEEP_1 - &CLUSTER_SLEEP_0>; capacity-dmips-mhz = <611>; dynamic-power-coefficient = <290>; qcom,freq-domain = <&cpufreq_hw 0>; operating-points-v2 = <&cpu0_opp_table>; interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + power-domains = <&CPU_PD1>; + power-domain-names = "psci"; #cooling-cells = <2>; next-level-cache = <&L2_100>; L2_100: l2-cache { @@ -244,15 +242,14 @@ compatible = "qcom,kryo385"; reg = <0x0 0x200>; enable-method = "psci"; - cpu-idle-states = <&LITTLE_CPU_SLEEP_0 - &LITTLE_CPU_SLEEP_1 - &CLUSTER_SLEEP_0>; capacity-dmips-mhz = <611>; dynamic-power-coefficient = <290>; qcom,freq-domain = <&cpufreq_hw 0>; operating-points-v2 = <&cpu0_opp_table>; interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + power-domains = <&CPU_PD2>; + power-domain-names = "psci"; #cooling-cells = <2>; next-level-cache = <&L2_200>; L2_200: l2-cache { @@ -266,9 +263,6 @@ compatible = "qcom,kryo385"; reg = <0x0 0x300>; enable-method = "psci"; - cpu-idle-states = <&LITTLE_CPU_SLEEP_0 - &LITTLE_CPU_SLEEP_1 - &CLUSTER_SLEEP_0>; capacity-dmips-mhz = <611>; dynamic-power-coefficient = <290>; qcom,freq-domain = <&cpufreq_hw 0>; @@ -276,6 +270,8 @@ interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; #cooling-cells = <2>; + power-domains = <&CPU_PD3>; + power-domain-names = "psci"; next-level-cache = <&L2_300>; L2_300: l2-cache { compatible = "cache"; @@ -289,14 +285,13 @@ reg = <0x0 0x400>; enable-method = "psci"; capacity-dmips-mhz = <1024>; - cpu-idle-states = <&BIG_CPU_SLEEP_0 - &BIG_CPU_SLEEP_1 - &CLUSTER_SLEEP_0>; dynamic-power-coefficient = <442>; qcom,freq-domain = <&cpufreq_hw 1>; operating-points-v2 = <&cpu4_opp_table>; interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + power-domains = <&CPU_PD4>; + power-domain-names = "psci"; #cooling-cells = <2>; next-level-cache = <&L2_400>; L2_400: l2-cache { @@ -311,14 +306,13 @@ reg = <0x0 0x500>; enable-method = "psci"; capacity-dmips-mhz = <1024>; - cpu-idle-states = <&BIG_CPU_SLEEP_0 - &BIG_CPU_SLEEP_1 - &CLUSTER_SLEEP_0>; dynamic-power-coefficient = <442>; qcom,freq-domain = <&cpufreq_hw 1>; operating-points-v2 = <&cpu4_opp_table>; interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + power-domains = <&CPU_PD5>; + power-domain-names = "psci"; #cooling-cells = <2>; next-level-cache = <&L2_500>; L2_500: l2-cache { @@ -333,14 +327,13 @@ reg = <0x0 0x600>; enable-method = "psci"; capacity-dmips-mhz = <1024>; - cpu-idle-states = <&BIG_CPU_SLEEP_0 - &BIG_CPU_SLEEP_1 - &CLUSTER_SLEEP_0>; dynamic-power-coefficient = <442>; qcom,freq-domain = <&cpufreq_hw 1>; operating-points-v2 = <&cpu4_opp_table>; interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + power-domains = <&CPU_PD6>; + power-domain-names = "psci"; #cooling-cells = <2>; next-level-cache = <&L2_600>; L2_600: l2-cache { @@ -355,14 +348,13 @@ reg = <0x0 0x700>; enable-method = "psci"; capacity-dmips-mhz = <1024>; - cpu-idle-states = <&BIG_CPU_SLEEP_0 - &BIG_CPU_SLEEP_1 - &CLUSTER_SLEEP_0>; dynamic-power-coefficient = <442>; qcom,freq-domain = <&cpufreq_hw 1>; operating-points-v2 = <&cpu4_opp_table>; interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + power-domains = <&CPU_PD7>; + power-domain-names = "psci"; #cooling-cells = <2>; next-level-cache = <&L2_700>; L2_700: l2-cache { @@ -407,53 +399,35 @@ }; }; - idle-states { + cpu_idle_states: idle-states { entry-method = "psci"; LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { compatible = "arm,idle-state"; - idle-state-name = "little-power-down"; - arm,psci-suspend-param = <0x40000003>; + idle-state-name = "little-rail-power-collapse"; + arm,psci-suspend-param = <0x40000004>; entry-latency-us = <350>; exit-latency-us = <461>; min-residency-us = <1890>; local-timer-stop; }; - LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { - compatible = "arm,idle-state"; - idle-state-name = "little-rail-power-down"; - arm,psci-suspend-param = <0x40000004>; - entry-latency-us = <360>; - exit-latency-us = <531>; - min-residency-us = <3934>; - local-timer-stop; - }; - BIG_CPU_SLEEP_0: cpu-sleep-1-0 { compatible = "arm,idle-state"; - idle-state-name = "big-power-down"; - arm,psci-suspend-param = <0x40000003>; + idle-state-name = "big-rail-power-collapse"; + arm,psci-suspend-param = <0x40000004>; entry-latency-us = <264>; exit-latency-us = <621>; min-residency-us = <952>; local-timer-stop; }; + }; - BIG_CPU_SLEEP_1: cpu-sleep-1-1 { - compatible = "arm,idle-state"; - idle-state-name = "big-rail-power-down"; - arm,psci-suspend-param = <0x40000004>; - entry-latency-us = <702>; - exit-latency-us = <1061>; - min-residency-us = <4488>; - local-timer-stop; - }; - + domain-idle-states { CLUSTER_SLEEP_0: cluster-sleep-0 { - compatible = "arm,idle-state"; - idle-state-name = "cluster-power-down"; - arm,psci-suspend-param = <0x400000F4>; + compatible = "domain-idle-state"; + idle-state-name = "cluster-power-collapse"; + arm,psci-suspend-param = <0x4100c244>; entry-latency-us = <3263>; exit-latency-us = <6562>; min-residency-us = <9987>; @@ -462,7 +436,7 @@ }; }; - cpu0_opp_table: cpu0_opp_table { + cpu0_opp_table: opp-table-cpu0 { compatible = "operating-points-v2"; opp-shared; @@ -557,7 +531,7 @@ }; }; - cpu4_opp_table: cpu4_opp_table { + cpu4_opp_table: opp-table-cpu4 { compatible = "operating-points-v2"; opp-shared; @@ -1050,9 +1024,62 @@ }; }; - psci { + psci: psci { compatible = "arm,psci-1.0"; method = "smc"; + + CPU_PD0: power-domain-cpu0 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD1: power-domain-cpu1 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD2: power-domain-cpu2 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD3: power-domain-cpu3 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD4: power-domain-cpu4 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&BIG_CPU_SLEEP_0>; + }; + + CPU_PD5: power-domain-cpu5 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&BIG_CPU_SLEEP_0>; + }; + + CPU_PD6: power-domain-cpu6 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&BIG_CPU_SLEEP_0>; + }; + + CPU_PD7: power-domain-cpu7 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&BIG_CPU_SLEEP_0>; + }; + + CLUSTER_PD: power-domain-cluster { + #power-domain-cells = <0>; + domain-idle-states = <&CLUSTER_SLEEP_0>; + }; }; soc: soc@0 { @@ -1104,7 +1131,7 @@ clock-names = "core"; }; - qup_opp_table: qup-opp-table { + qup_opp_table: opp-table-qup { compatible = "operating-points-v2"; opp-50000000 { @@ -1181,6 +1208,9 @@ <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, + <&gpi_dma0 1 0 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1235,6 +1265,9 @@ <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, + <&gpi_dma0 1 1 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1251,6 +1284,9 @@ interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; interconnect-names = "qup-core", "qup-config"; + dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, + <&gpi_dma0 1 1 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1286,6 +1322,9 @@ <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, + <&gpi_dma0 1 2 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1302,6 +1341,9 @@ interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; interconnect-names = "qup-core", "qup-config"; + dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, + <&gpi_dma0 1 2 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1337,6 +1379,9 @@ <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, + <&gpi_dma0 1 3 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1353,6 +1398,9 @@ interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; interconnect-names = "qup-core", "qup-config"; + dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, + <&gpi_dma0 1 3 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1388,6 +1436,9 @@ <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, + <&gpi_dma0 1 4 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1404,6 +1455,9 @@ interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; interconnect-names = "qup-core", "qup-config"; + dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, + <&gpi_dma0 1 4 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1439,6 +1493,9 @@ <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, + <&gpi_dma0 1 5 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1455,6 +1512,9 @@ interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; interconnect-names = "qup-core", "qup-config"; + dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, + <&gpi_dma0 1 5 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1490,6 +1550,9 @@ <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, + <&gpi_dma0 1 6 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1506,6 +1569,9 @@ interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; interconnect-names = "qup-core", "qup-config"; + dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, + <&gpi_dma0 1 6 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1553,6 +1619,9 @@ interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; interconnect-names = "qup-core", "qup-config"; + dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, + <&gpi_dma0 1 7 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1626,6 +1695,9 @@ <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, + <&gpi_dma1 1 0 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1642,6 +1714,9 @@ interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; interconnect-names = "qup-core", "qup-config"; + dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, + <&gpi_dma1 1 0 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1677,6 +1752,9 @@ <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, + <&gpi_dma1 1 1 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1693,6 +1771,9 @@ interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; interconnect-names = "qup-core", "qup-config"; + dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, + <&gpi_dma1 1 1 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1728,6 +1809,9 @@ <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, + <&gpi_dma1 1 2 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1744,6 +1828,9 @@ interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; interconnect-names = "qup-core", "qup-config"; + dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, + <&gpi_dma1 1 2 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1779,6 +1866,9 @@ <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, + <&gpi_dma1 1 3 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1795,6 +1885,9 @@ interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; interconnect-names = "qup-core", "qup-config"; + dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, + <&gpi_dma1 1 3 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1830,6 +1923,9 @@ <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, + <&gpi_dma1 1 4 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1846,6 +1942,9 @@ interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; interconnect-names = "qup-core", "qup-config"; + dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, + <&gpi_dma1 1 4 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1881,6 +1980,9 @@ <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, + <&gpi_dma1 1 5 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1897,6 +1999,9 @@ interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; interconnect-names = "qup-core", "qup-config"; + dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, + <&gpi_dma1 1 5 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1932,6 +2037,9 @@ <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, + <&gpi_dma1 1 6 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1948,6 +2056,9 @@ interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; interconnect-names = "qup-core", "qup-config"; + dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, + <&gpi_dma1 1 6 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1984,6 +2095,9 @@ <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, + <&gpi_dma1 1 7 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; }; spi15: spi@a9c000 { @@ -1999,6 +2113,9 @@ interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; interconnect-names = "qup-core", "qup-config"; + dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>, + <&gpi_dma1 1 7 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -2026,6 +2143,43 @@ interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; }; + pmu@1436400 { + compatible = "qcom,sdm845-bwmon", "qcom,msm8998-bwmon"; + reg = <0 0x01436400 0 0x600>; + interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; + interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_LLCC 3>; + + operating-points-v2 = <&cpu_bwmon_opp_table>; + + cpu_bwmon_opp_table: opp-table { + compatible = "operating-points-v2"; + + /* + * The interconnect path bandwidth taken from + * cpu4_opp_table bandwidth for OSM L3 + * interconnect. This also matches the OSM L3 + * from bandwidth table of qcom,cpu4-l3lat-mon + * (qcom,core-dev-table, bus width: 16 bytes) + * from msm-4.9 downstream kernel. + */ + opp-0 { + opp-peak-kBps = <4800000>; + }; + opp-1 { + opp-peak-kBps = <9216000>; + }; + opp-2 { + opp-peak-kBps = <15052800>; + }; + opp-3 { + opp-peak-kBps = <20889600>; + }; + opp-4 { + opp-peak-kBps = <25497600>; + }; + }; + }; + pcie0: pci@1c00000 { compatible = "qcom,pcie-sdm845"; reg = <0 0x01c00000 0 0x2000>, @@ -3551,7 +3705,7 @@ }; }; - sdhc_2: sdhci@8804000 { + sdhc_2: mmc@8804000 { compatible = "qcom,sdm845-sdhci", "qcom,sdhci-msm-v5"; reg = <0 0x08804000 0 0x1000>; @@ -3569,7 +3723,7 @@ status = "disabled"; - sdhc2_opp_table: sdhc2-opp-table { + sdhc2_opp_table: opp-table { compatible = "operating-points-v2"; opp-9600000 { @@ -3594,7 +3748,7 @@ }; }; - qspi_opp_table: qspi-opp-table { + qspi_opp_table: opp-table-qspi { compatible = "operating-points-v2"; opp-19200000 { @@ -3640,7 +3794,7 @@ qcom,apps-ch-pipes = <0x780000>; qcom,ea-pc = <0x270>; status = "okay"; - dmas = <&slimbam 3>, <&slimbam 4>, + dmas = <&slimbam 3>, <&slimbam 4>, <&slimbam 5>, <&slimbam 6>; dma-names = "rx", "tx", "tx2", "rx2"; @@ -3655,13 +3809,13 @@ wcd9340_ifd: ifd@0{ compatible = "slim217,250"; - reg = <0 0>; + reg = <0 0>; }; wcd9340: codec@1{ compatible = "slim217,250"; - reg = <1 0>; - slim-ifc-dev = <&wcd9340_ifd>; + reg = <1 0>; + slim-ifc-dev = <&wcd9340_ifd>; #sound-dai-cells = <1>; @@ -3692,8 +3846,8 @@ reg = <0xc85 0x40>; interrupts-extended = <&wcd9340 20>; - qcom,dout-ports = <6>; - qcom,din-ports = <2>; + qcom,dout-ports = <6>; + qcom,din-ports = <2>; qcom,ports-sinterval-low =/bits/ 8 <0x07 0x1F 0x3F 0x7 0x1F 0x3F 0x0F 0x0F>; qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0C 0x6 0x12 0x0D 0x07 0x0A >; qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x1F 0x00 0x00 0x1F 0x00 0x00>; @@ -3971,7 +4125,7 @@ compatible = "venus-encoder"; }; - venus_opp_table: venus-opp-table { + venus_opp_table: opp-table { compatible = "operating-points-v2"; opp-100000000 { @@ -4208,7 +4362,7 @@ clock-names = "bi_tcxo"; }; - dsi_opp_table: dsi-opp-table { + dsi_opp_table: opp-table-dsi { compatible = "operating-points-v2"; opp-19200000 { @@ -4248,9 +4402,6 @@ <&dispcc DISP_CC_MDSS_MDP_CLK>; clock-names = "iface", "core"; - assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; - assigned-clock-rates = <300000000>; - interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; interrupt-controller; #interrupt-cells = <1>; @@ -4268,7 +4419,7 @@ #size-cells = <2>; ranges; - mdss_mdp: mdp@ae01000 { + mdss_mdp: display-controller@ae01000 { compatible = "qcom,sdm845-dpu"; reg = <0 0x0ae01000 0 0x8f000>, <0 0x0aeb0000 0 0x2008>; @@ -4281,10 +4432,8 @@ <&dispcc DISP_CC_MDSS_VSYNC_CLK>; clock-names = "gcc-bus", "iface", "bus", "core", "vsync"; - assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, - <&dispcc DISP_CC_MDSS_VSYNC_CLK>; - assigned-clock-rates = <300000000>, - <19200000>; + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <19200000>; operating-points-v2 = <&mdp_opp_table>; power-domains = <&rpmhpd SDM845_CX>; @@ -4310,7 +4459,7 @@ }; }; - mdp_opp_table: mdp-opp-table { + mdp_opp_table: opp-table { compatible = "operating-points-v2"; opp-19200000 { @@ -4574,7 +4723,7 @@ }; gmu: gmu@506a000 { - compatible="qcom,adreno-gmu-630.2", "qcom,adreno-gmu"; + compatible = "qcom,adreno-gmu-630.2", "qcom,adreno-gmu"; reg = <0 0x506a000 0 0x30000>, <0 0xb280000 0 0x10000>, @@ -4721,8 +4870,8 @@ cell-index = <0>; }; - imem@146bf000 { - compatible = "simple-mfd"; + sram@146bf000 { + compatible = "qcom,sdm845-imem", "syscon", "simple-mfd"; reg = <0 0x146bf000 0 0x1000>; #address-cells = <1>; @@ -4939,7 +5088,7 @@ compatible = "qcom,bam-v1.7.0"; qcom,controlled-remotely; reg = <0 0x17184000 0 0x2a000>; - num-channels = <31>; + num-channels = <31>; interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; #dma-cells = <1>; qcom,ee = <1>; @@ -4948,9 +5097,9 @@ }; timer@17c90000 { - #address-cells = <2>; - #size-cells = <2>; - ranges; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0x20000000>; compatible = "arm,armv7-timer-mem"; reg = <0 0x17c90000 0 0x1000>; @@ -4958,49 +5107,49 @@ frame-number = <0>; interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; - reg = <0 0x17ca0000 0 0x1000>, - <0 0x17cb0000 0 0x1000>; + reg = <0x17ca0000 0x1000>, + <0x17cb0000 0x1000>; }; frame@17cc0000 { frame-number = <1>; interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; - reg = <0 0x17cc0000 0 0x1000>; + reg = <0x17cc0000 0x1000>; status = "disabled"; }; frame@17cd0000 { frame-number = <2>; interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; - reg = <0 0x17cd0000 0 0x1000>; + reg = <0x17cd0000 0x1000>; status = "disabled"; }; frame@17ce0000 { frame-number = <3>; interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; - reg = <0 0x17ce0000 0 0x1000>; + reg = <0x17ce0000 0x1000>; status = "disabled"; }; frame@17cf0000 { frame-number = <4>; interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; - reg = <0 0x17cf0000 0 0x1000>; + reg = <0x17cf0000 0x1000>; status = "disabled"; }; frame@17d00000 { frame-number = <5>; interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; - reg = <0 0x17d00000 0 0x1000>; + reg = <0x17d00000 0x1000>; status = "disabled"; }; frame@17d10000 { frame-number = <6>; interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; - reg = <0 0x17d10000 0 0x1000>; + reg = <0x17d10000 0x1000>; status = "disabled"; }; }; diff --git a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts index f1619b3f97ef..a7af1bed4312 100644 --- a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts +++ b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts @@ -41,7 +41,7 @@ pinctrl-names = "default"; pinctrl-0 = <&lid_pin_active>, <&mode_pin_active>; - lid { + switch-lid { gpios = <&tlmm 124 GPIO_ACTIVE_HIGH>; linux,input-type = <EV_SW>; linux,code = <SW_LID>; @@ -49,7 +49,7 @@ wakeup-event-action = <EV_ACT_DEASSERTED>; }; - mode { + switch-mode { gpios = <&tlmm 95 GPIO_ACTIVE_HIGH>; linux,input-type = <EV_SW>; linux,code = <SW_TABLET_MODE>; @@ -581,7 +581,7 @@ }; codec { - sound-dai = <&left_spkr>, <&right_spkr>, <&swm 0>, <&wcd9340 0>; + sound-dai = <&left_spkr>, <&right_spkr>, <&swm 0>, <&wcd9340 0>; }; }; @@ -611,7 +611,7 @@ }; codec { - sound-dai = <&wcd9340 2>; + sound-dai = <&wcd9340 2>; }; }; }; @@ -817,5 +817,5 @@ &crypto { /* FIXME: qce_start triggers an SError */ - status= "disable"; + status = "disable"; }; diff --git a/arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dts b/arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dts index 2a552d817b03..b0315eeb1320 100644 --- a/arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dts +++ b/arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dts @@ -509,7 +509,7 @@ }; codec { - sound-dai = <&left_spkr>, <&right_spkr>, <&swm 0>, <&wcd9340 0>; + sound-dai = <&left_spkr>, <&right_spkr>, <&swm 0>, <&wcd9340 0>; }; }; @@ -539,7 +539,7 @@ }; codec { - sound-dai = <&wcd9340 2>; + sound-dai = <&wcd9340 2>; }; }; }; diff --git a/arch/arm64/boot/dts/qcom/sdm850.dtsi b/arch/arm64/boot/dts/qcom/sdm850.dtsi index b1c2cf566c7a..da9f6fbe32f6 100644 --- a/arch/arm64/boot/dts/qcom/sdm850.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm850.dtsi @@ -16,6 +16,5 @@ cpu4_opp34: opp-2956800000 { opp-hz = /bits/ 64 <2956800000>; opp-peak-kBps = <7216000 25497600>; - turbo-mode; }; }; diff --git a/arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts b/arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts index 871ccbba445b..0aad2e94e757 100644 --- a/arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts +++ b/arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts @@ -42,11 +42,9 @@ gpio-keys { status = "okay"; compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; autorepeat; - vol-dn { + key-vol-dn { label = "Volume Down"; gpios = <&tlmm 47 GPIO_ACTIVE_LOW>; linux,input-type = <1>; @@ -88,11 +86,19 @@ status = "okay"; }; -&sdc2_state_off { +&sdc2_off_state { sd-cd { pins = "gpio98"; + drive-strength = <2>; bias-disable; + }; +}; + +&sdc2_on_state { + sd-cd { + pins = "gpio98"; drive-strength = <2>; + bias-pull-up; }; }; @@ -102,32 +108,6 @@ &tlmm { gpio-reserved-ranges = <22 2>, <28 6>; - - sdc2_state_on: sdc2-on { - clk { - pins = "sdc2_clk"; - bias-disable; - drive-strength = <16>; - }; - - cmd { - pins = "sdc2_cmd"; - bias-pull-up; - drive-strength = <10>; - }; - - data { - pins = "sdc2_data"; - bias-pull-up; - drive-strength = <10>; - }; - - sd-cd { - pins = "gpio98"; - bias-pull-up; - drive-strength = <2>; - }; - }; }; &usb3 { diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi index 135e6e0da27a..8c582a9e4ada 100644 --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi @@ -386,23 +386,43 @@ interrupt-controller; #interrupt-cells = <2>; - sdc2_state_off: sdc2-off { + sdc2_off_state: sdc2-off-state { clk { pins = "sdc2_clk"; - bias-disable; drive-strength = <2>; + bias-disable; }; cmd { pins = "sdc2_cmd"; + drive-strength = <2>; bias-pull-up; + }; + + data { + pins = "sdc2_data"; drive-strength = <2>; + bias-pull-up; + }; + }; + + sdc2_on_state: sdc2-on-state { + clk { + pins = "sdc2_clk"; + drive-strength = <16>; + bias-disable; + }; + + cmd { + pins = "sdc2_cmd"; + drive-strength = <10>; + bias-pull-up; }; data { pins = "sdc2_data"; + drive-strength = <10>; bias-pull-up; - drive-strength = <2>; }; }; }; @@ -435,7 +455,7 @@ reg = <0x045f0000 0x7000>; }; - sdhc_1: sdhci@4744000 { + sdhc_1: mmc@4744000 { compatible = "qcom,sm6125-sdhci", "qcom,sdhci-msm-v5"; reg = <0x04744000 0x1000>, <0x04745000 0x1000>; reg-names = "hc", "core"; @@ -451,12 +471,15 @@ power-domains = <&rpmpd SM6125_VDDCX>; + qcom,dll-config = <0x000f642c>; + qcom,ddr-config = <0x80040873>; + bus-width = <8>; non-removable; status = "disabled"; }; - sdhc_2: sdhci@4784000 { + sdhc_2: mmc@4784000 { compatible = "qcom,sm6125-sdhci", "qcom,sdhci-msm-v5"; reg = <0x04784000 0x1000>; reg-names = "hc"; @@ -470,12 +493,15 @@ <&xo_board>; clock-names = "iface", "core", "xo"; - pinctrl-0 = <&sdc2_state_on>; - pinctrl-1 = <&sdc2_state_off>; + pinctrl-0 = <&sdc2_on_state>; + pinctrl-1 = <&sdc2_off_state>; pinctrl-names = "default", "sleep"; power-domains = <&rpmpd SM6125_VDDCX>; + qcom,dll-config = <0x0007642c>; + qcom,ddr-config = <0x80040873>; + bus-width = <4>; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index d4f8f33f3f0c..d06aefdf3d9e 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -472,7 +472,7 @@ clock-names = "core"; }; - sdhc_1: sdhci@7c4000 { + sdhc_1: mmc@7c4000 { compatible = "qcom,sm6350-sdhci", "qcom,sdhci-msm-v5"; reg = <0 0x007c4000 0 0x1000>, <0 0x007c5000 0 0x1000>, @@ -489,7 +489,7 @@ clock-names = "iface", "core", "xo"; qcom,dll-config = <0x000f642c>; qcom,ddr-config = <0x80040868>; - power-domains = <&rpmhpd 0>; + power-domains = <&rpmhpd SM6350_CX>; operating-points-v2 = <&sdhc1_opp_table>; bus-width = <8>; non-removable; @@ -497,7 +497,7 @@ status = "disabled"; - sdhc1_opp_table: sdhc1-opp-table { + sdhc1_opp_table: opp-table { compatible = "operating-points-v2"; opp-19200000 { @@ -921,7 +921,7 @@ }; }; - sdhc_2: sdhci@8804000 { + sdhc_2: mmc@8804000 { compatible = "qcom,sm6350-sdhci", "qcom,sdhci-msm-v5"; reg = <0 0x08804000 0 0x1000>; @@ -935,13 +935,13 @@ clock-names = "iface", "core", "xo"; qcom,dll-config = <0x0007642c>; qcom,ddr-config = <0x80040868>; - power-domains = <&rpmhpd 0>; + power-domains = <&rpmhpd SM6350_CX>; operating-points-v2 = <&sdhc2_opp_table>; bus-width = <4>; status = "disabled"; - sdhc2_opp_table: sdhc2-opp-table { + sdhc2_opp_table: opp-table { compatible = "operating-points-v2"; opp-100000000 { @@ -1304,57 +1304,57 @@ compatible = "arm,armv7-timer-mem"; reg = <0x0 0x17c20000 0x0 0x1000>; clock-frequency = <19200000>; - #address-cells = <2>; - #size-cells = <2>; - ranges; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0x20000000>; frame@17c21000 { frame-number = <0>; interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x0 0x17c21000 0x0 0x1000>, - <0x0 0x17c22000 0x0 0x1000>; + reg = <0x17c21000 0x1000>, + <0x17c22000 0x1000>; }; frame@17c23000 { frame-number = <1>; interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x0 0x17c23000 0x0 0x1000>; + reg = <0x17c23000 0x1000>; status = "disabled"; }; frame@17c25000 { frame-number = <2>; interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x0 0x17c25000 0x0 0x1000>; + reg = <0x17c25000 0x1000>; status = "disabled"; }; frame@17c27000 { frame-number = <3>; interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x0 0x17c27000 0x0 0x1000>; + reg = <0x17c27000 0x1000>; status = "disabled"; }; frame@17c29000 { frame-number = <4>; interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x0 0x17c29000 0x0 0x1000>; + reg = <0x17c29000 0x1000>; status = "disabled"; }; frame@17c2b000 { frame-number = <5>; interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x0 0x17c2b000 0x0 0x1000>; + reg = <0x17c2b000 0x1000>; status = "disabled"; }; frame@17c2d000 { frame-number = <6>; interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x0 0x17c2d000 0x0 0x1000>; + reg = <0x17c2d000 0x1000>; status = "disabled"; }; }; diff --git a/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts b/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts index 61925216f5e3..c76abe7587b4 100644 --- a/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts +++ b/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts @@ -48,7 +48,7 @@ pinctrl-names = "default"; pinctrl-0 = <&gpio_keys_pin>; - volume-up { + key-volume-up { label = "volume_up"; linux,code = <KEY_VOLUMEUP>; gpios = <&pm6350_gpios 2 GPIO_ACTIVE_LOW>; @@ -339,7 +339,7 @@ }; &pm6350_gpios { - gpio_keys_pin: gpio-keys-pin { + gpio_keys_pin: gpio-keys-state { pins = "gpio2"; function = PMIC_GPIO_FUNC_NORMAL; bias-pull-up; diff --git a/arch/arm64/boot/dts/qcom/sm8150-hdk.dts b/arch/arm64/boot/dts/qcom/sm8150-hdk.dts index 37ddca0f0223..3331ee957d64 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8150-hdk.dts @@ -44,10 +44,10 @@ vin-supply = <&vph_pwr>; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; - vol-up { + key-vol-up { label = "Volume Up"; linux,code = <KEY_VOLUMEUP>; gpios = <&pm8150_gpios 6 GPIO_ACTIVE_LOW>; diff --git a/arch/arm64/boot/dts/qcom/sm8150-microsoft-surface-duo.dts b/arch/arm64/boot/dts/qcom/sm8150-microsoft-surface-duo.dts index a73317e1a824..bb278ecac3fa 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-microsoft-surface-duo.dts +++ b/arch/arm64/boot/dts/qcom/sm8150-microsoft-surface-duo.dts @@ -49,10 +49,10 @@ vin-supply = <&vph_pwr>; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; - vol_up { + key-vol-up { label = "Volume Up"; gpios = <&pm8150_gpios 6 GPIO_ACTIVE_LOW>; linux,code = <KEY_VOLUMEUP>; diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index 8ea44c4b56b4..7d509ecd44da 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -288,7 +288,7 @@ }; }; - cpu0_opp_table: cpu0_opp_table { + cpu0_opp_table: opp-table-cpu0 { compatible = "operating-points-v2"; opp-shared; @@ -383,7 +383,7 @@ }; }; - cpu4_opp_table: cpu4_opp_table { + cpu4_opp_table: opp-table-cpu4 { compatible = "operating-points-v2"; opp-shared; @@ -473,7 +473,7 @@ }; }; - cpu7_opp_table: cpu7_opp_table { + cpu7_opp_table: opp-table-cpu7 { compatible = "operating-points-v2"; opp-shared; @@ -2187,7 +2187,7 @@ }; gmu: gmu@2c6a000 { - compatible="qcom,adreno-gmu-640.1", "qcom,adreno-gmu"; + compatible = "qcom,adreno-gmu-640.1", "qcom,adreno-gmu"; reg = <0 0x02c6a000 0 0x30000>, <0 0x0b290000 0 0x10000>, @@ -3543,7 +3543,7 @@ }; }; - sdhc_2: sdhci@8804000 { + sdhc_2: mmc@8804000 { compatible = "qcom,sm8150-sdhci", "qcom,sdhci-msm-v5"; reg = <0 0x08804000 0 0x1000>; @@ -3563,7 +3563,7 @@ status = "disabled"; - sdhc2_opp_table: sdhc2-opp-table { + sdhc2_opp_table: opp-table { compatible = "operating-points-v2"; opp-19200000 { @@ -3718,7 +3718,7 @@ }; aoss_qmp: power-controller@c300000 { - compatible = "qcom,sm8150-aoss-qmp"; + compatible = "qcom,sm8150-aoss-qmp", "qcom,aoss-qmp"; reg = <0x0 0x0c300000 0x0 0x400>; interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; mboxes = <&apss_shared 0>; @@ -3944,9 +3944,9 @@ }; timer@17c20000 { - #address-cells = <2>; - #size-cells = <2>; - ranges; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0x20000000>; compatible = "arm,armv7-timer-mem"; reg = <0x0 0x17c20000 0x0 0x1000>; clock-frequency = <19200000>; @@ -3955,49 +3955,49 @@ frame-number = <0>; interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x0 0x17c21000 0x0 0x1000>, - <0x0 0x17c22000 0x0 0x1000>; + reg = <0x17c21000 0x1000>, + <0x17c22000 0x1000>; }; frame@17c23000 { frame-number = <1>; interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x0 0x17c23000 0x0 0x1000>; + reg = <0x17c23000 0x1000>; status = "disabled"; }; frame@17c25000 { frame-number = <2>; interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x0 0x17c25000 0x0 0x1000>; + reg = <0x17c25000 0x1000>; status = "disabled"; }; frame@17c27000 { frame-number = <3>; interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x0 0x17c26000 0x0 0x1000>; + reg = <0x17c26000 0x1000>; status = "disabled"; }; frame@17c29000 { frame-number = <4>; interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x0 0x17c29000 0x0 0x1000>; + reg = <0x17c29000 0x1000>; status = "disabled"; }; frame@17c2b000 { frame-number = <5>; interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x0 0x17c2b000 0x0 0x1000>; + reg = <0x17c2b000 0x1000>; status = "disabled"; }; frame@17c2d000 { frame-number = <6>; interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x0 0x17c2d000 0x0 0x1000>; + reg = <0x17c2d000 0x1000>; status = "disabled"; }; }; diff --git a/arch/arm64/boot/dts/qcom/sm8250-hdk.dts b/arch/arm64/boot/dts/qcom/sm8250-hdk.dts index 3b082472062b..632e98193d27 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8250-hdk.dts @@ -53,10 +53,10 @@ vin-supply = <&vph_pwr>; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; - vol-up { + key-vol-up { label = "Volume Up"; linux,code = <KEY_VOLUMEUP>; gpios = <&pm8150_gpios 6 GPIO_ACTIVE_LOW>; diff --git a/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi b/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi index e819b5b77363..549e0a2aa9fe 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi @@ -57,7 +57,7 @@ * case, they are both on &pm8150b_gpios: camera focus(2), camera snapshot(1). */ - vol-down { + key-vol-down { label = "Volume Down"; linux,code = <KEY_VOLUMEDOWN>; gpios = <&pm8150_gpios 1 GPIO_ACTIVE_LOW>; diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index cf0c97bd5ad3..bc773e210023 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -8,6 +8,8 @@ #include <dt-bindings/clock/qcom,gcc-sm8250.h> #include <dt-bindings/clock/qcom,gpucc-sm8250.h> #include <dt-bindings/clock/qcom,rpmh.h> +#include <dt-bindings/clock/qcom,sm8250-lpass-aoncc.h> +#include <dt-bindings/clock/qcom,sm8250-lpass-audiocc.h> #include <dt-bindings/dma/qcom-gpi.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interconnect/qcom,osm-l3.h> @@ -336,7 +338,7 @@ }; }; - cpu0_opp_table: cpu0_opp_table { + cpu0_opp_table: opp-table-cpu0 { compatible = "operating-points-v2"; opp-shared; @@ -426,7 +428,7 @@ }; }; - cpu4_opp_table: cpu4_opp_table { + cpu4_opp_table: opp-table-cpu4 { compatible = "operating-points-v2"; opp-shared; @@ -521,7 +523,7 @@ }; }; - cpu7_opp_table: cpu7_opp_table { + cpu7_opp_table: opp-table-cpu7 { compatible = "operating-points-v2"; opp-shared; @@ -628,7 +630,7 @@ firmware { scm: scm { - compatible = "qcom,scm"; + compatible = "qcom,scm-sm8250", "qcom,scm"; #reset-cells = <1>; }; }; @@ -702,6 +704,25 @@ }; }; + qup_opp_table: opp-table-qup { + compatible = "operating-points-v2"; + + opp-50000000 { + opp-hz = /bits/ 64 <50000000>; + required-opps = <&rpmhpd_opp_min_svs>; + }; + + opp-75000000 { + opp-hz = /bits/ 64 <75000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-120000000 { + opp-hz = /bits/ 64 <120000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + }; + reserved-memory { #address-cells = <2>; #size-cells = <2>; @@ -914,25 +935,6 @@ clock-names = "core"; }; - qup_opp_table: qup-opp-table { - compatible = "operating-points-v2"; - - opp-50000000 { - opp-hz = /bits/ 64 <50000000>; - required-opps = <&rpmhpd_opp_min_svs>; - }; - - opp-75000000 { - opp-hz = /bits/ 64 <75000000>; - required-opps = <&rpmhpd_opp_low_svs>; - }; - - opp-120000000 { - opp-hz = /bits/ 64 <120000000>; - required-opps = <&rpmhpd_opp_svs>; - }; - }; - gpi_dma2: dma-controller@800000 { compatible = "qcom,sm8250-gpi-dma"; reg = <0 0x00800000 0 0x70000>; @@ -1884,6 +1886,8 @@ clock-names = "pipe0"; #phy-cells = <0>; + + #clock-cells = <0>; clock-output-names = "pcie_0_pipe_clk"; }; }; @@ -1990,6 +1994,8 @@ clock-names = "pipe0"; #phy-cells = <0>; + + #clock-cells = <0>; clock-output-names = "pcie_1_pipe_clk"; }; }; @@ -2096,6 +2102,8 @@ clock-names = "pipe0"; #phy-cells = <0>; + + #clock-cells = <0>; clock-output-names = "pcie_2_pipe_clk"; }; }; @@ -2188,11 +2196,11 @@ wsamacro: codec@3240000 { compatible = "qcom,sm8250-lpass-wsa-macro"; reg = <0 0x03240000 0 0x1000>; - clocks = <&audiocc 1>, - <&audiocc 0>, + clocks = <&audiocc LPASS_CDC_WSA_MCLK>, + <&audiocc LPASS_CDC_WSA_NPL>, <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, - <&aoncc 0>, + <&aoncc LPASS_CDC_VA_MCLK>, <&vamacro>; clock-names = "mclk", "npl", "macro", "dcodec", "va", "fsgen"; @@ -2239,7 +2247,7 @@ vamacro: codec@3370000 { compatible = "qcom,sm8250-lpass-va-macro"; reg = <0 0x03370000 0 0x1000>; - clocks = <&aoncc 0>, + clocks = <&aoncc LPASS_CDC_VA_MCLK>, <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; @@ -2569,7 +2577,7 @@ }; gmu: gmu@3d6a000 { - compatible="qcom,adreno-gmu-650.2", "qcom,adreno-gmu"; + compatible = "qcom,adreno-gmu-650.2", "qcom,adreno-gmu"; reg = <0 0x03d6a000 0 0x30000>, <0 0x3de0000 0 0x10000>, @@ -2623,7 +2631,7 @@ }; adreno_smmu: iommu@3da0000 { - compatible = "qcom,sm8250-smmu-500", "arm,mmu-500"; + compatible = "qcom,sm8250-smmu-500", "qcom,adreno-smmu", "arm,mmu-500"; reg = <0 0x03da0000 0 0x10000>; #iommu-cells = <2>; #global-interrupts = <2>; @@ -2917,7 +2925,7 @@ }; }; - sdhc_2: sdhci@8804000 { + sdhc_2: mmc@8804000 { compatible = "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5"; reg = <0 0x08804000 0 0x1000>; @@ -2937,7 +2945,7 @@ status = "disabled"; - sdhc2_opp_table: sdhc2-opp-table { + sdhc2_opp_table: opp-table { compatible = "operating-points-v2"; opp-19200000 { @@ -3010,11 +3018,13 @@ assigned-clock-rates = <19200000>, <200000000>; interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, - <&pdc 14 IRQ_TYPE_EDGE_BOTH>, + <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, <&pdc 15 IRQ_TYPE_EDGE_BOTH>, - <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", - "dm_hs_phy_irq", "ss_phy_irq"; + <&pdc 14 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "hs_phy_irq", + "ss_phy_irq", + "dm_hs_phy_irq", + "dp_hs_phy_irq"; power-domains = <&gcc USB30_PRIM_GDSC>; @@ -3065,11 +3075,13 @@ assigned-clock-rates = <19200000>, <200000000>; interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, - <&pdc 12 IRQ_TYPE_EDGE_BOTH>, + <&pdc 16 IRQ_TYPE_LEVEL_HIGH>, <&pdc 13 IRQ_TYPE_EDGE_BOTH>, - <&pdc 16 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", - "dm_hs_phy_irq", "ss_phy_irq"; + <&pdc 12 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "hs_phy_irq", + "ss_phy_irq", + "dm_hs_phy_irq", + "dp_hs_phy_irq"; power-domains = <&gcc USB30_SEC_GDSC>; @@ -3123,7 +3135,7 @@ compatible = "venus-encoder"; }; - venus_opp_table: venus-opp-table { + venus_opp_table: opp-table { compatible = "operating-points-v2"; opp-720000000 { @@ -3407,6 +3419,7 @@ clock-names = "iface", "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; power-domains = <&rpmhpd SM8250_MMCX>; required-opps = <&rpmhpd_opp_low_svs>; + status = "disabled"; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; @@ -3429,9 +3442,6 @@ <&dispcc DISP_CC_MDSS_MDP_CLK>; clock-names = "iface", "bus", "nrt_bus", "core"; - assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; - assigned-clock-rates = <460000000>; - interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; interrupt-controller; #interrupt-cells = <1>; @@ -3444,7 +3454,7 @@ #size-cells = <2>; ranges; - mdss_mdp: mdp@ae01000 { + mdss_mdp: display-controller@ae01000 { compatible = "qcom,sm8250-dpu"; reg = <0 0x0ae01000 0 0x8f000>, <0 0x0aeb0000 0 0x2008>; @@ -3456,10 +3466,8 @@ <&dispcc DISP_CC_MDSS_VSYNC_CLK>; clock-names = "iface", "bus", "core", "vsync"; - assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, - <&dispcc DISP_CC_MDSS_VSYNC_CLK>; - assigned-clock-rates = <460000000>, - <19200000>; + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <19200000>; operating-points-v2 = <&mdp_opp_table>; power-domains = <&rpmhpd SM8250_MMCX>; @@ -3486,7 +3494,7 @@ }; }; - mdp_opp_table: mdp-opp-table { + mdp_opp_table: opp-table { compatible = "operating-points-v2"; opp-200000000 { @@ -3656,7 +3664,7 @@ status = "disabled"; - dsi_opp_table: dsi-opp-table { + dsi_opp_table: opp-table { compatible = "operating-points-v2"; opp-187500000 { @@ -3734,7 +3742,7 @@ }; aoss_qmp: power-controller@c300000 { - compatible = "qcom,sm8250-aoss-qmp"; + compatible = "qcom,sm8250-aoss-qmp", "qcom,aoss-qmp"; reg = <0 0x0c300000 0 0x400>; interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP @@ -4867,9 +4875,9 @@ }; timer@17c20000 { - #address-cells = <2>; - #size-cells = <2>; - ranges; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0x20000000>; compatible = "arm,armv7-timer-mem"; reg = <0x0 0x17c20000 0x0 0x1000>; clock-frequency = <19200000>; @@ -4878,49 +4886,49 @@ frame-number = <0>; interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x0 0x17c21000 0x0 0x1000>, - <0x0 0x17c22000 0x0 0x1000>; + reg = <0x17c21000 0x1000>, + <0x17c22000 0x1000>; }; frame@17c23000 { frame-number = <1>; interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x0 0x17c23000 0x0 0x1000>; + reg = <0x17c23000 0x1000>; status = "disabled"; }; frame@17c25000 { frame-number = <2>; interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x0 0x17c25000 0x0 0x1000>; + reg = <0x17c25000 0x1000>; status = "disabled"; }; frame@17c27000 { frame-number = <3>; interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x0 0x17c27000 0x0 0x1000>; + reg = <0x17c27000 0x1000>; status = "disabled"; }; frame@17c29000 { frame-number = <4>; interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x0 0x17c29000 0x0 0x1000>; + reg = <0x17c29000 0x1000>; status = "disabled"; }; frame@17c2b000 { frame-number = <5>; interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x0 0x17c2b000 0x0 0x1000>; + reg = <0x17c2b000 0x1000>; status = "disabled"; }; frame@17c2d000 { frame-number = <6>; interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x0 0x17c2d000 0x0 0x1000>; + reg = <0x17c2d000 0x1000>; status = "disabled"; }; }; diff --git a/arch/arm64/boot/dts/qcom/sm8350-microsoft-surface-duo2.dts b/arch/arm64/boot/dts/qcom/sm8350-microsoft-surface-duo2.dts index 9a6faa9393dc..9c4cfd995ff2 100644 --- a/arch/arm64/boot/dts/qcom/sm8350-microsoft-surface-duo2.dts +++ b/arch/arm64/boot/dts/qcom/sm8350-microsoft-surface-duo2.dts @@ -336,9 +336,7 @@ status = "okay"; vdda-phy-supply = <&vreg_l5b_0p88>; - vdda-max-microamp = <91600>; vdda-pll-supply = <&vreg_l6b_1p2>; - vdda-pll-max-microamp = <19000>; }; &usb_1 { diff --git a/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi b/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi index 90b13cbe2fa6..cb9bbd234b7b 100644 --- a/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi @@ -49,7 +49,7 @@ /* For reasons still unknown, GAssist key and Camera Focus/Shutter don't work.. */ - vol-down { + key-vol-down { label = "Volume Down"; linux,code = <KEY_VOLUMEDOWN>; gpios = <&pmk8350_gpios 3 GPIO_ACTIVE_LOW>; diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index 743cba9b683c..e72a04411888 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -4,6 +4,7 @@ */ #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/qcom,dispcc-sm8350.h> #include <dt-bindings/clock/qcom,gcc-sm8350.h> #include <dt-bindings/clock/qcom,rpmh.h> #include <dt-bindings/dma/qcom-gpi.h> @@ -341,6 +342,44 @@ }; }; + qup_opp_table_100mhz: opp-table-qup100mhz { + compatible = "operating-points-v2"; + + opp-50000000 { + opp-hz = /bits/ 64 <50000000>; + required-opps = <&rpmhpd_opp_min_svs>; + }; + + opp-75000000 { + opp-hz = /bits/ 64 <75000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + }; + + qup_opp_table_120mhz: opp-table-qup120mhz { + compatible = "operating-points-v2"; + + opp-50000000 { + opp-hz = /bits/ 64 <50000000>; + required-opps = <&rpmhpd_opp_min_svs>; + }; + + opp-75000000 { + opp-hz = /bits/ 64 <75000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-120000000 { + opp-hz = /bits/ 64 <120000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + }; + reserved_memory: reserved-memory { #address-cells = <2>; #size-cells = <2>; @@ -638,44 +677,6 @@ #mbox-cells = <2>; }; - qup_opp_table_100mhz: qup-100mhz-opp-table { - compatible = "operating-points-v2"; - - opp-50000000 { - opp-hz = /bits/ 64 <50000000>; - required-opps = <&rpmhpd_opp_min_svs>; - }; - - opp-75000000 { - opp-hz = /bits/ 64 <75000000>; - required-opps = <&rpmhpd_opp_low_svs>; - }; - - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - required-opps = <&rpmhpd_opp_svs>; - }; - }; - - qup_opp_table_120mhz: qup-120mhz-opp-table { - compatible = "operating-points-v2"; - - opp-50000000 { - opp-hz = /bits/ 64 <50000000>; - required-opps = <&rpmhpd_opp_min_svs>; - }; - - opp-75000000 { - opp-hz = /bits/ 64 <75000000>; - required-opps = <&rpmhpd_opp_low_svs>; - }; - - opp-120000000 { - opp-hz = /bits/ 64 <120000000>; - required-opps = <&rpmhpd_opp_svs>; - }; - }; - gpi_dma2: dma-controller@800000 { compatible = "qcom,sm8350-gpi-dma"; reg = <0 0x00800000 0 0x60000>; @@ -1656,8 +1657,8 @@ clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "xo"; - power-domains = <&rpmhpd 0>, - <&rpmhpd 12>; + power-domains = <&rpmhpd SM8350_CX>, + <&rpmhpd SM8350_MSS>; power-domain-names = "cx", "mss"; interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>; @@ -1677,7 +1678,6 @@ IRQ_TYPE_EDGE_RISING>; mboxes = <&ipcc IPCC_CLIENT_MPSS IPCC_MPROC_SIGNAL_GLINK_QMP>; - interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; label = "modem"; qcom,remote-pid = <1>; }; @@ -1718,7 +1718,7 @@ }; aoss_qmp: power-controller@c300000 { - compatible = "qcom,sm8350-aoss-qmp"; + compatible = "qcom,sm8350-aoss-qmp", "qcom,aoss-qmp"; reg = <0 0x0c300000 0 0x400>; interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP IRQ_TYPE_EDGE_RISING>; @@ -1933,9 +1933,9 @@ timer@17c20000 { compatible = "arm,armv7-timer-mem"; - #address-cells = <2>; - #size-cells = <2>; - ranges; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0x20000000>; reg = <0x0 0x17c20000 0x0 0x1000>; clock-frequency = <19200000>; @@ -1943,49 +1943,49 @@ frame-number = <0>; interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x0 0x17c21000 0x0 0x1000>, - <0x0 0x17c22000 0x0 0x1000>; + reg = <0x17c21000 0x1000>, + <0x17c22000 0x1000>; }; frame@17c23000 { frame-number = <1>; interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x0 0x17c23000 0x0 0x1000>; + reg = <0x17c23000 0x1000>; status = "disabled"; }; frame@17c25000 { frame-number = <2>; interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x0 0x17c25000 0x0 0x1000>; + reg = <0x17c25000 0x1000>; status = "disabled"; }; frame@17c27000 { frame-number = <3>; interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x0 0x17c27000 0x0 0x1000>; + reg = <0x17c27000 0x1000>; status = "disabled"; }; frame@17c29000 { frame-number = <4>; interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x0 0x17c29000 0x0 0x1000>; + reg = <0x17c29000 0x1000>; status = "disabled"; }; frame@17c2b000 { frame-number = <5>; interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x0 0x17c2b000 0x0 0x1000>; + reg = <0x17c2b000 0x1000>; status = "disabled"; }; frame@17c2d000 { frame-number = <6>; interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x0 0x17c2d000 0x0 0x1000>; + reg = <0x17c2d000 0x1000>; status = "disabled"; }; }; @@ -2148,7 +2148,6 @@ <0 0x01d87800 0 0x108>, <0 0x01d87a00 0 0x1e0>; #phy-cells = <0>; - #clock-cells = <0>; }; }; @@ -2167,8 +2166,8 @@ clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "xo"; - power-domains = <&rpmhpd 4>, - <&rpmhpd 5>; + power-domains = <&rpmhpd SM8350_LCX>, + <&rpmhpd SM8350_LMX>; power-domain-names = "lcx", "lmx"; memory-region = <&pil_slpi_mem>; @@ -2235,8 +2234,8 @@ clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "xo"; - power-domains = <&rpmhpd 0>, - <&rpmhpd 10>; + power-domains = <&rpmhpd SM8350_CX>, + <&rpmhpd SM8350_MXC>; power-domain-names = "cx", "mxc"; interconnects = <&compute_noc MASTER_CDSP_PROC &mc_virt SLAVE_EBI1>; @@ -2381,7 +2380,7 @@ <0 0x088e9800 0 0x200>, <0 0x088e9a00 0 0x100>; #phy-cells = <0>; - #clock-cells = <1>; + #clock-cells = <0>; clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; clock-names = "pipe0"; clock-output-names = "usb3_phy_pipe_clk_src"; @@ -2411,7 +2410,7 @@ <0 0x088ec000 0 0x200>, <0 0x088eb200 0 0x1100>; #phy-cells = <0>; - #clock-cells = <1>; + #clock-cells = <0>; clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; clock-names = "pipe0"; clock-output-names = "usb3_uni_phy_pipe_clk_src"; @@ -2462,11 +2461,13 @@ assigned-clock-rates = <19200000>, <200000000>; interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, - <&pdc 14 IRQ_TYPE_EDGE_BOTH>, + <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, <&pdc 15 IRQ_TYPE_EDGE_BOTH>, - <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", - "dm_hs_phy_irq", "ss_phy_irq"; + <&pdc 14 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "hs_phy_irq", + "ss_phy_irq", + "dm_hs_phy_irq", + "dp_hs_phy_irq"; power-domains = <&gcc USB30_PRIM_GDSC>; @@ -2510,11 +2511,13 @@ assigned-clock-rates = <19200000>, <200000000>; interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, - <&pdc 12 IRQ_TYPE_EDGE_BOTH>, + <&pdc 16 IRQ_TYPE_LEVEL_HIGH>, <&pdc 13 IRQ_TYPE_EDGE_BOTH>, - <&pdc 16 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", - "dm_hs_phy_irq", "ss_phy_irq"; + <&pdc 12 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "hs_phy_irq", + "ss_phy_irq", + "dm_hs_phy_irq", + "dp_hs_phy_irq"; power-domains = <&gcc USB30_SEC_GDSC>; @@ -2532,6 +2535,31 @@ }; }; + dispcc: clock-controller@af00000 { + compatible = "qcom,sm8350-dispcc"; + reg = <0 0x0af00000 0 0x10000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>; + clock-names = "bi_tcxo", + "dsi0_phy_pll_out_byteclk", + "dsi0_phy_pll_out_dsiclk", + "dsi1_phy_pll_out_byteclk", + "dsi1_phy_pll_out_dsiclk", + "dp_phy_pll_link_clk", + "dp_phy_pll_vco_div_clk"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + + power-domains = <&rpmhpd SM8350_MMCX>; + power-domain-names = "mmcx"; + }; + adsp: remoteproc@17300000 { compatible = "qcom,sm8350-adsp-pas"; reg = <0 0x17300000 0 0x100>; @@ -2547,8 +2575,8 @@ clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "xo"; - power-domains = <&rpmhpd 4>, - <&rpmhpd 5>; + power-domains = <&rpmhpd SM8350_LCX>, + <&rpmhpd SM8350_LMX>; power-domain-names = "lcx", "lmx"; memory-region = <&pil_adsp_mem>; diff --git a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts index 4e51a9d6af98..38ccd44620d0 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts @@ -418,8 +418,6 @@ vdda-phy-supply = <&vreg_l5b_0p88>; vdda-pll-supply = <&vreg_l6b_1p2>; - vdda-max-microamp = <173000>; - vdda-pll-max-microamp = <24900>; }; &usb_1 { diff --git a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts index 236e53974fdd..e58fc7399799 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts @@ -424,8 +424,6 @@ vdda-phy-supply = <&vreg_l5b_0p88>; vdda-pll-supply = <&vreg_l6b_1p2>; - vdda-max-microamp = <173000>; - vdda-pll-max-microamp = <24900>; }; &usb_1 { diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index b87756bf1ce4..4978c5ba5dd0 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -6,6 +6,7 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/clock/qcom,gcc-sm8450.h> #include <dt-bindings/clock/qcom,rpmh.h> +#include <dt-bindings/clock/qcom,sm8450-camcc.h> #include <dt-bindings/dma/qcom-gpi.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/mailbox/qcom-ipcc.h> @@ -258,17 +259,18 @@ firmware { scm: scm { compatible = "qcom,scm-sm8450", "qcom,scm"; + interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; #reset-cells = <1>; }; }; - clk_virt: interconnect@0 { + clk_virt: interconnect-0 { compatible = "qcom,sm8450-clk-virt"; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; - mc_virt: interconnect@1 { + mc_virt: interconnect-1 { compatible = "qcom,sm8450-mc-virt"; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; @@ -343,7 +345,7 @@ }; }; - qup_opp_table_100mhz: qup-100mhz-opp-table { + qup_opp_table_100mhz: opp-table-qup { compatible = "operating-points-v2"; opp-50000000 { @@ -976,6 +978,19 @@ status = "disabled"; }; + uart20: serial@894000 { + compatible = "qcom,geni-uart"; + reg = <0 0x00894000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_uart20_default>; + interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + spi20: spi@894000 { compatible = "qcom,geni-spi"; reg = <0 0x00894000 0 0x4000>; @@ -2001,7 +2016,7 @@ <0 0x088e9800 0 0x200>, <0 0x088e9a00 0 0x100>; #phy-cells = <0>; - #clock-cells = <1>; + #clock-cells = <0>; clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; clock-names = "pipe0"; clock-output-names = "usb3_phy_pipe_clk_src"; @@ -2012,7 +2027,7 @@ compatible = "qcom,sm8450-slpi-pas"; reg = <0 0x02400000 0 0x4000>; - interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&pdc 9 IRQ_TYPE_EDGE_RISING>, <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>, <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>, <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>, @@ -2079,7 +2094,7 @@ compatible = "qcom,sm8450-adsp-pas"; reg = <0 0x030000000 0 0x100>; - interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, @@ -2145,7 +2160,7 @@ compatible = "qcom,sm8450-cdsp-pas"; reg = <0 0x032300000 0 0x1400000>; - interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, @@ -2251,7 +2266,7 @@ compatible = "qcom,sm8450-mpss-pas"; reg = <0x0 0x04080000 0x0 0x4040>; - interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, @@ -2282,12 +2297,26 @@ IRQ_TYPE_EDGE_RISING>; mboxes = <&ipcc IPCC_CLIENT_MPSS IPCC_MPROC_SIGNAL_GLINK_QMP>; - interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; label = "modem"; qcom,remote-pid = <1>; }; }; + camcc: clock-controller@ade0000 { + compatible = "qcom,sm8450-camcc"; + reg = <0 0x0ade0000 0 0x20000>; + clocks = <&gcc GCC_CAMERA_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>; + power-domains = <&rpmhpd SM8450_MMCX>; + required-opps = <&rpmhpd_opp_low_svs>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + status = "disabled"; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,sm8450-pdc", "qcom,pdc"; reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>; @@ -2738,6 +2767,12 @@ drive-strength = <2>; bias-disable; }; + + qup_uart20_default: qup-uart20-default { + pins = "gpio76", "gpio77", "gpio78", "gpio79"; + function = "qup20"; + }; + }; apps_smmu: iommu@15000000 { @@ -2867,9 +2902,9 @@ timer@17420000 { compatible = "arm,armv7-timer-mem"; - #address-cells = <2>; - #size-cells = <2>; - ranges; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0x20000000>; reg = <0x0 0x17420000 0x0 0x1000>; clock-frequency = <19200000>; @@ -2877,49 +2912,49 @@ frame-number = <0>; interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x0 0x17421000 0x0 0x1000>, - <0x0 0x17422000 0x0 0x1000>; + reg = <0x17421000 0x1000>, + <0x17422000 0x1000>; }; frame@17423000 { frame-number = <1>; interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x0 0x17423000 0x0 0x1000>; + reg = <0x17423000 0x1000>; status = "disabled"; }; frame@17425000 { frame-number = <2>; interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x0 0x17425000 0x0 0x1000>; + reg = <0x17425000 0x1000>; status = "disabled"; }; frame@17427000 { frame-number = <3>; interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x0 0x17427000 0x0 0x1000>; + reg = <0x17427000 0x1000>; status = "disabled"; }; frame@17429000 { frame-number = <4>; interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x0 0x17429000 0x0 0x1000>; + reg = <0x17429000 0x1000>; status = "disabled"; }; frame@1742b000 { frame-number = <5>; interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x0 0x1742b000 0x0 0x1000>; + reg = <0x1742b000 0x1000>; status = "disabled"; }; frame@1742d000 { frame-number = <6>; interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x0 0x1742d000 0x0 0x1000>; + reg = <0x1742d000 0x1000>; status = "disabled"; }; }; @@ -3102,7 +3137,6 @@ <0 0x01d87800 0 0x108>, <0 0x01d87a00 0 0x1e0>; #phy-cells = <0>; - #clock-cells = <0>; }; }; diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile index e66d76d42e52..7a647860ef35 100644 --- a/arch/arm64/boot/dts/renesas/Makefile +++ b/arch/arm64/boot/dts/renesas/Makefile @@ -85,3 +85,6 @@ dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-smarc.dtb dtb-$(CONFIG_ARCH_R9A07G054) += r9a07g054l2-smarc.dtb dtb-$(CONFIG_ARCH_R9A09G011) += r9a09g011-v2mevk2.dtb + +dtb-$(CONFIG_ARCH_RCAR_GEN3) += draak-ebisu-panel-aa104xd12.dtbo +dtb-$(CONFIG_ARCH_RCAR_GEN3) += salvator-panel-aa104xd12.dtbo diff --git a/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi b/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi index 142e7ffbd2bd..63e7a39e100e 100644 --- a/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi +++ b/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi @@ -146,7 +146,7 @@ }; }; - reg_audio: regulator_audio { + reg_audio: regulator-audio { compatible = "regulator-fixed"; regulator-name = "audio-1.8V"; regulator-min-microvolt = <1800000>; @@ -174,7 +174,7 @@ vin-supply = <®_lcd>; }; - reg_cam0: regulator_camera { + reg_cam0: regulator-cam0 { compatible = "regulator-fixed"; regulator-name = "reg_cam0"; regulator-min-microvolt = <1800000>; @@ -183,7 +183,7 @@ enable-active-high; }; - reg_cam1: regulator_camera { + reg_cam1: regulator-cam1 { compatible = "regulator-fixed"; regulator-name = "reg_cam1"; regulator-min-microvolt = <1800000>; diff --git a/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi b/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi index 877d076ffcc9..f5c1d74b738b 100644 --- a/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi +++ b/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi @@ -20,7 +20,7 @@ clock-output-names = "osc_32k"; }; - reg_1p8v: regulator0 { + reg_1p8v: regulator-1p8v { compatible = "regulator-fixed"; regulator-name = "fixed-1.8V"; regulator-min-microvolt = <1800000>; @@ -29,7 +29,7 @@ regulator-always-on; }; - reg_3p3v: regulator1 { + reg_3p3v: regulator-3p3v { compatible = "regulator-fixed"; regulator-name = "fixed-3.3V"; regulator-min-microvolt = <3300000>; diff --git a/arch/arm64/boot/dts/renesas/draak-ebisu-panel-aa104xd12.dts b/arch/arm64/boot/dts/renesas/draak-ebisu-panel-aa104xd12.dts new file mode 100644 index 000000000000..258f8668ca36 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/draak-ebisu-panel-aa104xd12.dts @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree overlay for the AA104XD12 panel connected to LVDS1 on a Draak or + * Ebisu board + * + * Copyright 2021 Ideas on Board Oy + */ + +/dts-v1/; +/plugin/; + +&{/} { +#include "panel-aa104xd12.dtsi" +}; + +&{/panel} { + backlight = <&backlight>; + + port { + panel_in: endpoint { + remote-endpoint = <&lvds1_out>; + }; + }; +}; + +&lvds1 { + status = "okay"; + + ports { + port@1 { + lvds1_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/renesas/draak.dtsi b/arch/arm64/boot/dts/renesas/draak.dtsi index 7231f820d601..ef3bb835d5c0 100644 --- a/arch/arm64/boot/dts/renesas/draak.dtsi +++ b/arch/arm64/boot/dts/renesas/draak.dtsi @@ -630,7 +630,7 @@ bitclock-master = <&rsnd_for_ak4613>; frame-master = <&rsnd_for_ak4613>; playback = <&ssi3>, <&src5>, <&dvc0>; - capture = <&ssi4>, <&src6>, <&dvc1>; + capture = <&ssi4>, <&src6>, <&dvc1>; }; }; }; diff --git a/arch/arm64/boot/dts/renesas/ebisu.dtsi b/arch/arm64/boot/dts/renesas/ebisu.dtsi index 72f359efa23e..8fc03491a11c 100644 --- a/arch/arm64/boot/dts/renesas/ebisu.dtsi +++ b/arch/arm64/boot/dts/renesas/ebisu.dtsi @@ -145,7 +145,7 @@ reg = <0x0 0x48000000 0x0 0x38000000>; }; - reg_1p8v: regulator0 { + reg_1p8v: regulator-1p8v { compatible = "regulator-fixed"; regulator-name = "fixed-1.8V"; regulator-min-microvolt = <1800000>; @@ -154,7 +154,7 @@ regulator-always-on; }; - reg_3p3v: regulator1 { + reg_3p3v: regulator-3p3v { compatible = "regulator-fixed"; regulator-name = "fixed-3.3V"; regulator-min-microvolt = <3300000>; @@ -163,7 +163,7 @@ regulator-always-on; }; - reg_12p0v: regulator2 { + reg_12p0v: regulator-12p0v { compatible = "regulator-fixed"; regulator-name = "D12.0V"; regulator-min-microvolt = <12000000>; @@ -711,7 +711,7 @@ rcar_sound,dai { dai0 { playback = <&ssi0>, <&src0>, <&dvc0>; - capture = <&ssi1>, <&src1>, <&dvc1>; + capture = <&ssi1>, <&src1>, <&dvc1>; }; }; diff --git a/arch/arm64/boot/dts/renesas/hihope-common.dtsi b/arch/arm64/boot/dts/renesas/hihope-common.dtsi index 935d06515aa6..b062f41ee270 100644 --- a/arch/arm64/boot/dts/renesas/hihope-common.dtsi +++ b/arch/arm64/boot/dts/renesas/hihope-common.dtsi @@ -53,7 +53,7 @@ }; }; - reg_1p8v: regulator0 { + reg_1p8v: regulator-1p8v { compatible = "regulator-fixed"; regulator-name = "fixed-1.8V"; regulator-min-microvolt = <1800000>; @@ -62,7 +62,7 @@ regulator-always-on; }; - reg_3p3v: regulator1 { + reg_3p3v: regulator-3p3v { compatible = "regulator-fixed"; regulator-name = "fixed-3.3V"; regulator-min-microvolt = <3300000>; diff --git a/arch/arm64/boot/dts/renesas/panel-aa104xd12.dtsi b/arch/arm64/boot/dts/renesas/panel-aa104xd12.dtsi new file mode 100644 index 000000000000..4b1f0982b9e4 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/panel-aa104xd12.dtsi @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Common file for the AA104XD12 panel connected to Renesas R-Car Gen3 boards. + * + * Copyright (C) 2014 Renesas Electronics Corp. + */ + +panel { + compatible = "mitsubishi,aa104xd12", "panel-lvds"; + + width-mm = <210>; + height-mm = <158>; + data-mapping = "jeida-18"; + + panel-timing { + /* 1024x768 @65Hz */ + clock-frequency = <65000000>; + hactive = <1024>; + vactive = <768>; + hsync-len = <136>; + hfront-porch = <20>; + hback-porch = <160>; + vfront-porch = <3>; + vback-porch = <29>; + vsync-len = <6>; + }; + + port { + }; +}; diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi index b6aeb22e8836..c563d26a7a71 100644 --- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi @@ -1281,7 +1281,7 @@ vin4csi40: endpoint@2 { reg = <2>; - remote-endpoint= <&csi40vin4>; + remote-endpoint = <&csi40vin4>; }; }; }; @@ -1309,7 +1309,7 @@ vin5csi40: endpoint@2 { reg = <2>; - remote-endpoint= <&csi40vin5>; + remote-endpoint = <&csi40vin5>; }; }; }; @@ -1952,7 +1952,7 @@ cpu-thermal { polling-delay-passive = <250>; polling-delay = <0>; - thermal-sensors = <&thermal 0>; + thermal-sensors = <&thermal>; sustainable-power = <717>; cooling-maps { diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi index d33021202637..565e9d85946e 100644 --- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi @@ -1324,7 +1324,7 @@ vin4csi40: endpoint@2 { reg = <2>; - remote-endpoint= <&csi40vin4>; + remote-endpoint = <&csi40vin4>; }; }; }; @@ -1352,7 +1352,7 @@ vin5csi40: endpoint@2 { reg = <2>; - remote-endpoint= <&csi40vin5>; + remote-endpoint = <&csi40vin5>; }; }; }; @@ -2129,7 +2129,7 @@ cpu-thermal { polling-delay-passive = <250>; polling-delay = <0>; - thermal-sensors = <&thermal 0>; + thermal-sensors = <&thermal>; sustainable-power = <717>; cooling-maps { diff --git a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi index b9731504b7cd..3d668709d8a8 100644 --- a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi @@ -41,6 +41,7 @@ device_type = "cpu"; power-domains = <&sysc R8A779A0_PD_A1E0D0C0>; next-level-cache = <&L3_CA76_0>; + clocks = <&cpg CPG_CORE R8A779A0_CLK_Z0>; }; L3_CA76_0: cache-controller-0 { @@ -105,7 +106,8 @@ }; gpio0: gpio@e6058180 { - compatible = "renesas,gpio-r8a779a0"; + compatible = "renesas,gpio-r8a779a0", + "renesas,rcar-gen4-gpio"; reg = <0 0xe6058180 0 0x54>; interrupts = <GIC_SPI 832 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 916>; @@ -119,7 +121,8 @@ }; gpio1: gpio@e6050180 { - compatible = "renesas,gpio-r8a779a0"; + compatible = "renesas,gpio-r8a779a0", + "renesas,rcar-gen4-gpio"; reg = <0 0xe6050180 0 0x54>; interrupts = <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 915>; @@ -133,7 +136,8 @@ }; gpio2: gpio@e6050980 { - compatible = "renesas,gpio-r8a779a0"; + compatible = "renesas,gpio-r8a779a0", + "renesas,rcar-gen4-gpio"; reg = <0 0xe6050980 0 0x54>; interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 915>; @@ -147,7 +151,8 @@ }; gpio3: gpio@e6058980 { - compatible = "renesas,gpio-r8a779a0"; + compatible = "renesas,gpio-r8a779a0", + "renesas,rcar-gen4-gpio"; reg = <0 0xe6058980 0 0x54>; interrupts = <GIC_SPI 844 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 916>; @@ -161,7 +166,8 @@ }; gpio4: gpio@e6060180 { - compatible = "renesas,gpio-r8a779a0"; + compatible = "renesas,gpio-r8a779a0", + "renesas,rcar-gen4-gpio"; reg = <0 0xe6060180 0 0x54>; interrupts = <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 917>; @@ -175,7 +181,8 @@ }; gpio5: gpio@e6060980 { - compatible = "renesas,gpio-r8a779a0"; + compatible = "renesas,gpio-r8a779a0", + "renesas,rcar-gen4-gpio"; reg = <0 0xe6060980 0 0x54>; interrupts = <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 917>; @@ -189,7 +196,8 @@ }; gpio6: gpio@e6068180 { - compatible = "renesas,gpio-r8a779a0"; + compatible = "renesas,gpio-r8a779a0", + "renesas,rcar-gen4-gpio"; reg = <0 0xe6068180 0 0x54>; interrupts = <GIC_SPI 856 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 918>; @@ -203,7 +211,8 @@ }; gpio7: gpio@e6068980 { - compatible = "renesas,gpio-r8a779a0"; + compatible = "renesas,gpio-r8a779a0", + "renesas,rcar-gen4-gpio"; reg = <0 0xe6068980 0 0x54>; interrupts = <GIC_SPI 860 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 918>; @@ -217,7 +226,8 @@ }; gpio8: gpio@e6069180 { - compatible = "renesas,gpio-r8a779a0"; + compatible = "renesas,gpio-r8a779a0", + "renesas,rcar-gen4-gpio"; reg = <0 0xe6069180 0 0x54>; interrupts = <GIC_SPI 864 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 918>; @@ -231,7 +241,8 @@ }; gpio9: gpio@e6069980 { - compatible = "renesas,gpio-r8a779a0"; + compatible = "renesas,gpio-r8a779a0", + "renesas,rcar-gen4-gpio"; reg = <0 0xe6069980 0 0x54>; interrupts = <GIC_SPI 868 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 918>; diff --git a/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi index 41aa8591b3b1..28fbf7bc1eb4 100644 --- a/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi @@ -55,6 +55,11 @@ function = "i2c4"; }; + scif0_pins: scif0 { + groups = "scif0_data", "scif0_ctrl"; + function = "scif0"; + }; + scif3_pins: scif3 { groups = "scif3_data", "scif3_ctrl"; function = "scif3"; @@ -71,6 +76,14 @@ status = "okay"; }; +&scif0 { + pinctrl-0 = <&scif0_pins>; + pinctrl-names = "default"; + + uart-has-rtscts; + status = "okay"; +}; + &scif3 { pinctrl-0 = <&scif3_pins>; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/renesas/r8a779f0-spider.dts b/arch/arm64/boot/dts/renesas/r8a779f0-spider.dts index 2e3b719cc749..7a7c8ffba711 100644 --- a/arch/arm64/boot/dts/renesas/r8a779f0-spider.dts +++ b/arch/arm64/boot/dts/renesas/r8a779f0-spider.dts @@ -15,6 +15,7 @@ aliases { serial0 = &scif3; + serial1 = &scif0; }; chosen { diff --git a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi index df46fb87cffc..384817ffa4de 100644 --- a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi @@ -18,11 +18,171 @@ #address-cells = <1>; #size-cells = <0>; + cpu-map { + cluster0 { + core0 { + cpu = <&a55_0>; + }; + core1 { + cpu = <&a55_1>; + }; + }; + + cluster1 { + core0 { + cpu = <&a55_2>; + }; + core1 { + cpu = <&a55_3>; + }; + }; + + cluster2 { + core0 { + cpu = <&a55_4>; + }; + core1 { + cpu = <&a55_5>; + }; + }; + + cluster3 { + core0 { + cpu = <&a55_6>; + }; + core1 { + cpu = <&a55_7>; + }; + }; + }; + a55_0: cpu@0 { compatible = "arm,cortex-a55"; reg = <0>; device_type = "cpu"; power-domains = <&sysc R8A779F0_PD_A1E0D0C0>; + next-level-cache = <&L3_CA55_0>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; + clocks = <&cpg CPG_CORE R8A779F0_CLK_Z0>; + }; + + a55_1: cpu@100 { + compatible = "arm,cortex-a55"; + reg = <0x100>; + device_type = "cpu"; + power-domains = <&sysc R8A779F0_PD_A1E0D0C1>; + next-level-cache = <&L3_CA55_0>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; + clocks = <&cpg CPG_CORE R8A779F0_CLK_Z0>; + }; + + a55_2: cpu@10000 { + compatible = "arm,cortex-a55"; + reg = <0x10000>; + device_type = "cpu"; + power-domains = <&sysc R8A779F0_PD_A1E0D1C0>; + next-level-cache = <&L3_CA55_1>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; + clocks = <&cpg CPG_CORE R8A779F0_CLK_Z0>; + }; + + a55_3: cpu@10100 { + compatible = "arm,cortex-a55"; + reg = <0x10100>; + device_type = "cpu"; + power-domains = <&sysc R8A779F0_PD_A1E0D1C1>; + next-level-cache = <&L3_CA55_1>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; + clocks = <&cpg CPG_CORE R8A779F0_CLK_Z0>; + }; + + a55_4: cpu@20000 { + compatible = "arm,cortex-a55"; + reg = <0x20000>; + device_type = "cpu"; + power-domains = <&sysc R8A779F0_PD_A1E1D0C0>; + next-level-cache = <&L3_CA55_2>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; + clocks = <&cpg CPG_CORE R8A779F0_CLK_Z1>; + }; + + a55_5: cpu@20100 { + compatible = "arm,cortex-a55"; + reg = <0x20100>; + device_type = "cpu"; + power-domains = <&sysc R8A779F0_PD_A1E1D0C1>; + next-level-cache = <&L3_CA55_2>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; + clocks = <&cpg CPG_CORE R8A779F0_CLK_Z1>; + }; + + a55_6: cpu@30000 { + compatible = "arm,cortex-a55"; + reg = <0x30000>; + device_type = "cpu"; + power-domains = <&sysc R8A779F0_PD_A1E1D1C0>; + next-level-cache = <&L3_CA55_3>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; + clocks = <&cpg CPG_CORE R8A779F0_CLK_Z1>; + }; + + a55_7: cpu@30100 { + compatible = "arm,cortex-a55"; + reg = <0x30100>; + device_type = "cpu"; + power-domains = <&sysc R8A779F0_PD_A1E1D1C1>; + next-level-cache = <&L3_CA55_3>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; + clocks = <&cpg CPG_CORE R8A779F0_CLK_Z1>; + }; + + L3_CA55_0: cache-controller-0 { + compatible = "cache"; + power-domains = <&sysc R8A779F0_PD_A2E0D0>; + cache-unified; + cache-level = <3>; + }; + + L3_CA55_1: cache-controller-1 { + compatible = "cache"; + power-domains = <&sysc R8A779F0_PD_A2E0D1>; + cache-unified; + cache-level = <3>; + }; + + L3_CA55_2: cache-controller-2 { + compatible = "cache"; + power-domains = <&sysc R8A779F0_PD_A2E1D0>; + cache-unified; + cache-level = <3>; + }; + + L3_CA55_3: cache-controller-3 { + compatible = "cache"; + power-domains = <&sysc R8A779F0_PD_A2E1D1>; + cache-unified; + cache-level = <3>; + }; + + idle-states { + entry-method = "psci"; + + CPU_SLEEP_0: cpu-sleep-0 { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x0010000>; + local-timer-stop; + entry-latency-us = <400>; + exit-latency-us = <500>; + min-residency-us = <4000>; + }; }; }; @@ -45,6 +205,11 @@ interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; }; + psci { + compatible = "arm,psci-1.0", "arm,psci-0.2"; + method = "smc"; + }; + /* External SCIF clock - to be overridden by boards that provide it */ scif_clk: scif { compatible = "fixed-clock"; @@ -157,6 +322,18 @@ #power-domain-cells = <1>; }; + tsc: thermal@e6198000 { + compatible = "renesas,r8a779f0-thermal"; + /* The 4th sensor is in control domain and not for Linux */ + reg = <0 0xe6198000 0 0x200>, + <0 0xe61a0000 0 0x200>, + <0 0xe61a8000 0 0x200>; + clocks = <&cpg CPG_MOD 919>; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 919>; + #thermal-sensor-cells = <1>; + }; + i2c0: i2c@e6500000 { compatible = "renesas,i2c-r8a779f0", "renesas,rcar-gen4-i2c"; @@ -259,6 +436,120 @@ status = "disabled"; }; + hscif0: serial@e6540000 { + compatible = "renesas,hscif-r8a779f0", + "renesas,rcar-gen4-hscif", "renesas,hscif"; + reg = <0 0xe6540000 0 0x60>; + interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 514>, + <&cpg CPG_CORE R8A779F0_CLK_S0D3>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x31>, <&dmac0 0x30>, + <&dmac1 0x31>, <&dmac1 0x30>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 514>; + status = "disabled"; + }; + + hscif1: serial@e6550000 { + compatible = "renesas,hscif-r8a779f0", + "renesas,rcar-gen4-hscif", "renesas,hscif"; + reg = <0 0xe6550000 0 0x60>; + interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 515>, + <&cpg CPG_CORE R8A779F0_CLK_S0D3>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x33>, <&dmac0 0x32>, + <&dmac1 0x33>, <&dmac1 0x32>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 515>; + status = "disabled"; + }; + + hscif2: serial@e6560000 { + compatible = "renesas,hscif-r8a779f0", + "renesas,rcar-gen4-hscif", "renesas,hscif"; + reg = <0 0xe6560000 0 0x60>; + interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 516>, + <&cpg CPG_CORE R8A779F0_CLK_S0D3>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x35>, <&dmac0 0x34>, + <&dmac1 0x35>, <&dmac1 0x34>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 516>; + status = "disabled"; + }; + + hscif3: serial@e66a0000 { + compatible = "renesas,hscif-r8a779f0", + "renesas,rcar-gen4-hscif", "renesas,hscif"; + reg = <0 0xe66a0000 0 0x60>; + interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 517>, + <&cpg CPG_CORE R8A779F0_CLK_S0D3>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x37>, <&dmac0 0x36>, + <&dmac1 0x37>, <&dmac1 0x36>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 517>; + status = "disabled"; + }; + + ufs: ufs@e6860000 { + compatible = "renesas,r8a779f0-ufs"; + reg = <0 0xe6860000 0 0x100>; + interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 1514>, <&ufs30_clk>; + clock-names = "fck", "ref_clk"; + freq-table-hz = <200000000 200000000>, <38400000 38400000>; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 1514>; + status = "disabled"; + }; + + scif0: serial@e6e60000 { + compatible = "renesas,scif-r8a779f0", + "renesas,rcar-gen4-scif", "renesas,scif"; + reg = <0 0xe6e60000 0 64>; + interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 702>, + <&cpg CPG_CORE R8A779F0_CLK_S0D3_PER>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x51>, <&dmac0 0x50>, + <&dmac1 0x51>, <&dmac1 0x50>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 702>; + status = "disabled"; + }; + + scif1: serial@e6e68000 { + compatible = "renesas,scif-r8a779f0", + "renesas,rcar-gen4-scif", "renesas,scif"; + reg = <0 0xe6e68000 0 64>; + interrupts = <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 703>, + <&cpg CPG_CORE R8A779F0_CLK_S0D3_PER>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x53>, <&dmac0 0x52>, + <&dmac1 0x53>, <&dmac1 0x52>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 703>; + status = "disabled"; + }; + scif3: serial@e6c50000 { compatible = "renesas,scif-r8a779f0", "renesas,rcar-gen4-scif", "renesas,scif"; @@ -268,11 +559,31 @@ <&cpg CPG_CORE R8A779F0_CLK_S0D3_PER>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x57>, <&dmac0 0x56>, + <&dmac1 0x57>, <&dmac1 0x56>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; resets = <&cpg 704>; status = "disabled"; }; + scif4: serial@e6c40000 { + compatible = "renesas,scif-r8a779f0", + "renesas,rcar-gen4-scif", "renesas,scif"; + reg = <0 0xe6c40000 0 64>; + interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 705>, + <&cpg CPG_CORE R8A779F0_CLK_S0D3_PER>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x59>, <&dmac0 0x58>, + <&dmac1 0x59>, <&dmac1 0x58>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 705>; + status = "disabled"; + }; + dmac0: dma-controller@e7350000 { compatible = "renesas,dmac-r8a779f0", "renesas,rcar-gen4-dmac"; @@ -306,6 +617,14 @@ resets = <&cpg 709>; #dma-cells = <1>; dma-channels = <16>; + iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>, + <&ipmmu_ds0 2>, <&ipmmu_ds0 3>, + <&ipmmu_ds0 4>, <&ipmmu_ds0 5>, + <&ipmmu_ds0 6>, <&ipmmu_ds0 7>, + <&ipmmu_ds0 8>, <&ipmmu_ds0 9>, + <&ipmmu_ds0 10>, <&ipmmu_ds0 11>, + <&ipmmu_ds0 12>, <&ipmmu_ds0 13>, + <&ipmmu_ds0 14>, <&ipmmu_ds0 15>; }; dmac1: dma-controller@e7351000 { @@ -341,6 +660,60 @@ resets = <&cpg 710>; #dma-cells = <1>; dma-channels = <16>; + iommus = <&ipmmu_ds0 16>, <&ipmmu_ds0 17>, + <&ipmmu_ds0 18>, <&ipmmu_ds0 19>, + <&ipmmu_ds0 20>, <&ipmmu_ds0 21>, + <&ipmmu_ds0 22>, <&ipmmu_ds0 23>, + <&ipmmu_ds0 24>, <&ipmmu_ds0 25>, + <&ipmmu_ds0 26>, <&ipmmu_ds0 27>, + <&ipmmu_ds0 28>, <&ipmmu_ds0 29>, + <&ipmmu_ds0 30>, <&ipmmu_ds0 31>; + }; + + ipmmu_rt0: iommu@ee480000 { + compatible = "renesas,ipmmu-r8a779f0", + "renesas,rcar-gen4-ipmmu-vmsa"; + reg = <0 0xee480000 0 0x20000>; + renesas,ipmmu-main = <&ipmmu_mm 10>; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_rt1: iommu@ee4c0000 { + compatible = "renesas,ipmmu-r8a779f0", + "renesas,rcar-gen4-ipmmu-vmsa"; + reg = <0 0xee4c0000 0 0x20000>; + renesas,ipmmu-main = <&ipmmu_mm 19>; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_ds0: iommu@eed00000 { + compatible = "renesas,ipmmu-r8a779f0", + "renesas,rcar-gen4-ipmmu-vmsa"; + reg = <0 0xeed00000 0 0x20000>; + renesas,ipmmu-main = <&ipmmu_mm 0>; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_hc: iommu@eed40000 { + compatible = "renesas,ipmmu-r8a779f0", + "renesas,rcar-gen4-ipmmu-vmsa"; + reg = <0 0xeed40000 0 0x20000>; + renesas,ipmmu-main = <&ipmmu_mm 2>; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_mm: iommu@eefc0000 { + compatible = "renesas,ipmmu-r8a779f0", + "renesas,rcar-gen4-ipmmu-vmsa"; + reg = <0 0xeefc0000 0 0x20000>; + interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + #iommu-cells = <1>; }; gic: interrupt-controller@f1000000 { @@ -351,7 +724,7 @@ reg = <0x0 0xf1000000 0 0x20000>, <0x0 0xf1060000 0 0x110000>; interrupts = <GIC_PPI 9 - (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; + (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; }; prr: chipid@fff00044 { @@ -360,11 +733,62 @@ }; }; + thermal-zones { + sensor_thermal1: sensor1-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsc 0>; + + trips { + sensor1_crit: sensor1-crit { + temperature = <120000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + sensor_thermal2: sensor2-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsc 1>; + + trips { + sensor2_crit: sensor2-crit { + temperature = <120000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + sensor_thermal3: sensor3-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsc 2>; + + trips { + sensor3_crit: sensor3-crit { + temperature = <120000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + }; + timer { compatible = "arm,armv8-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; + interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; + }; + + ufs30_clk: ufs30-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a779m8.dtsi b/arch/arm64/boot/dts/renesas/r8a779m8.dtsi index 752440b0c40f..750bd8ccdb7f 100644 --- a/arch/arm64/boot/dts/renesas/r8a779m8.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779m8.dtsi @@ -10,3 +10,8 @@ / { compatible = "renesas,r8a779m8", "renesas,r8a7795"; }; + +&cluster0_opp { + /delete-node/ opp-1600000000; + /delete-node/ opp-1700000000; +}; diff --git a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi index b31fb713ae4d..40201a16d653 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi @@ -483,8 +483,27 @@ }; adc: adc@10059000 { + compatible = "renesas,r9a07g043-adc", "renesas,rzg2l-adc"; reg = <0 0x10059000 0 0x400>; - /* place holder */ + interrupts = <GIC_SPI 347 IRQ_TYPE_EDGE_RISING>; + clocks = <&cpg CPG_MOD R9A07G043_ADC_ADCLK>, + <&cpg CPG_MOD R9A07G043_ADC_PCLK>; + clock-names = "adclk", "pclk"; + resets = <&cpg R9A07G043_ADC_PRESETN>, + <&cpg R9A07G043_ADC_ADRST_N>; + reset-names = "presetn", "adrst-n"; + power-domains = <&cpg>; + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + channel@0 { + reg = <0>; + }; + channel@1 { + reg = <1>; + }; }; tsu: thermal@10059400 { diff --git a/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts index 2d740bd420ca..121e55282d18 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts @@ -13,9 +13,3 @@ model = "Renesas SMARC EVK based on r9a07g043u11"; compatible = "renesas,smarc-evk", "renesas,r9a07g043u11", "renesas,r9a07g043"; }; - -&spi1 { - /delete-property/ pinctrl-0; - /delete-property/ pinctrl-names; - status = "disabled"; -}; diff --git a/arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts index 4e07e1a0fb66..3d01a4cf0fbe 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) /* - * Device Tree Source for the RZ/G2L SMARC EVK board + * Device Tree Source for the RZ/V2L SMARC EVK board * * Copyright (C) 2021 Renesas Electronics Corp. */ diff --git a/arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dts b/arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dts index c207d8ce5523..c3a52fa0b16e 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dts @@ -14,6 +14,7 @@ aliases { serial0 = &uart0; + ethernet0 = &avb; }; chosen { @@ -35,6 +36,19 @@ }; }; +&avb { + renesas,no-ether-link; + phy-handle = <&phy0>; + phy-mode = "gmii"; + status = "okay"; + + phy0: ethernet-phy@0 { + compatible = "ethernet-phy-id001c.c916", + "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; +}; + &extal_clk { clock-frequency = <48000000>; }; diff --git a/arch/arm64/boot/dts/renesas/r9a09g011.dtsi b/arch/arm64/boot/dts/renesas/r9a09g011.dtsi index 27810f4ad4cb..d4cc5459fbb7 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g011.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g011.dtsi @@ -62,6 +62,57 @@ clock-names = "clk"; }; + avb: ethernet@a3300000 { + compatible = "renesas,etheravb-r9a09g011","renesas,etheravb-rzv2m"; + reg = <0 0xa3300000 0 0x800>; + interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, /* ch0: Rx0 BE */ + <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, /* ch1: Rx1 NC */ + <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, /* ch18: Tx0 BE */ + <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, /* ch19: Tx1 NC */ + <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, /* DiA */ + <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, /* DiB */ + <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, /* Line1_A */ + <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>, /* Line1_B */ + <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, /* Line2_A */ + <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, /* Line2_B */ + <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>; /* Line3 MAC */ + interrupt-names = "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15", + "ch16", "ch17", "ch18", "ch19", + "ch20", "ch21", "dia", "dib", + "err_a", "err_b", "mgmt_a", "mgmt_b", + "line3"; + clocks = <&cpg CPG_MOD R9A09G011_ETH0_CLK_AXI>, + <&cpg CPG_MOD R9A09G011_ETH0_CLK_CHI>, + <&cpg CPG_MOD R9A09G011_ETH0_GPTP_EXT>; + clock-names = "axi", "chi", "gptp"; + resets = <&cpg R9A09G011_ETH0_RST_HW_N>; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disable"; + }; + cpg: clock-controller@a3500000 { compatible = "renesas,r9a09g011-cpg"; reg = <0 0xa3500000 0 0x1000>; diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi index aeacd22e9eb0..9410796c8ad6 100644 --- a/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi @@ -34,7 +34,7 @@ reg = <0x0 0x48000000 0x0 0x78000000>; }; - reg_1p8v: regulator0 { + reg_1p8v: regulator-1p8v { compatible = "regulator-fixed"; regulator-name = "fixed-1.8V"; regulator-min-microvolt = <1800000>; @@ -43,7 +43,7 @@ regulator-always-on; }; - reg_3p3v: regulator1 { + reg_3p3v: regulator-3p3v { compatible = "regulator-fixed"; regulator-name = "fixed-3.3V"; regulator-min-microvolt = <3300000>; diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi index 959a0ad1d367..78e6e2376b01 100644 --- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi @@ -23,7 +23,7 @@ reg = <0x0 0x48000000 0x0 0x38000000>; }; - reg_1p8v: regulator0 { + reg_1p8v: regulator-1p8v { compatible = "regulator-fixed"; regulator-name = "fixed-1.8V"; regulator-min-microvolt = <1800000>; @@ -32,7 +32,7 @@ regulator-always-on; }; - reg_3p3v: regulator1 { + reg_3p3v: regulator-3p3v { compatible = "regulator-fixed"; regulator-name = "fixed-3.3V"; regulator-min-microvolt = <3300000>; diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi index aa170492dd2b..6be25a8a28db 100644 --- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi @@ -29,7 +29,7 @@ #define SW_RSPI_CAN 1 #endif -#if (SW_SCIF_CAN & SW_RSPI_CAN) +#if (SW_SCIF_CAN && SW_RSPI_CAN) #error "Can not set 1 to both SW_SCIF_CAN and SW_RSPI_CAN due to HW routing" #endif diff --git a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi index a663115f5aae..cf3b3d118ef1 100644 --- a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi @@ -24,7 +24,7 @@ reg = <0x0 0x48000000 0x0 0x38000000>; }; - reg_1p8v: regulator0 { + reg_1p8v: regulator-1p8v { compatible = "regulator-fixed"; regulator-name = "fixed-1.8V"; regulator-min-microvolt = <1800000>; @@ -33,7 +33,7 @@ regulator-always-on; }; - reg_3p3v: regulator1 { + reg_3p3v: regulator-3p3v { compatible = "regulator-fixed"; regulator-name = "fixed-3.3V"; regulator-min-microvolt = <3300000>; @@ -57,6 +57,14 @@ #endif }; +#if (SW_SW0_DEV_SEL) +&adc { + pinctrl-0 = <&adc_pins>; + pinctrl-names = "default"; + status = "okay"; +}; +#endif + #if (!SW_ET0_EN_N) ð0 { pinctrl-0 = <ð0_pins>; @@ -124,6 +132,10 @@ }; &pinctrl { + adc_pins: adc { + pinmux = <RZG2L_PORT_PINMUX(6, 2, 1)>; /* ADC_TRG */ + }; + eth0_pins: eth0 { pinmux = <RZG2L_PORT_PINMUX(4, 5, 1)>, /* ET0_LINKSTA */ <RZG2L_PORT_PINMUX(4, 3, 1)>, /* ET0_MDC */ @@ -209,6 +221,13 @@ pinmux = <RZG2L_PORT_PINMUX(0, 0, 1)>; /* SD0_CD */ }; }; + + spi1_pins: rspi1 { + pinmux = <RZG2L_PORT_PINMUX(4, 0, 2)>, /* CK */ + <RZG2L_PORT_PINMUX(4, 1, 2)>, /* MOSI */ + <RZG2L_PORT_PINMUX(4, 2, 2)>, /* MISO */ + <RZG2L_PORT_PINMUX(4, 3, 2)>; /* SSL */ + }; }; #if (SW_SW0_DEV_SEL) diff --git a/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi index 0051634d7b1c..f9835c12023e 100644 --- a/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi @@ -51,6 +51,12 @@ status = "disabled"; }; +&spi1 { + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; + status = "disabled"; +}; + &ssi1 { /delete-property/ pinctrl-0; /delete-property/ pinctrl-names; diff --git a/arch/arm64/boot/dts/renesas/salvator-common.dtsi b/arch/arm64/boot/dts/renesas/salvator-common.dtsi index 31837fcd7bf0..b7c7911858b2 100644 --- a/arch/arm64/boot/dts/renesas/salvator-common.dtsi +++ b/arch/arm64/boot/dts/renesas/salvator-common.dtsi @@ -170,7 +170,7 @@ }; }; - reg_1p8v: regulator0 { + reg_1p8v: regulator-1p8v { compatible = "regulator-fixed"; regulator-name = "fixed-1.8V"; regulator-min-microvolt = <1800000>; @@ -179,7 +179,7 @@ regulator-always-on; }; - reg_3p3v: regulator1 { + reg_3p3v: regulator-3p3v { compatible = "regulator-fixed"; regulator-name = "fixed-3.3V"; regulator-min-microvolt = <3300000>; @@ -188,7 +188,7 @@ regulator-always-on; }; - reg_12v: regulator2 { + reg_12v: regulator-12v { compatible = "regulator-fixed"; regulator-name = "fixed-12V"; regulator-min-microvolt = <12000000>; @@ -832,7 +832,7 @@ frame-master = <&rsnd_endpoint0>; playback = <&ssi0>, <&src0>, <&dvc0>; - capture = <&ssi1>, <&src1>, <&dvc1>; + capture = <&ssi1>, <&src1>, <&dvc1>; }; }; diff --git a/arch/arm64/boot/dts/renesas/salvator-panel-aa104xd12.dts b/arch/arm64/boot/dts/renesas/salvator-panel-aa104xd12.dts new file mode 100644 index 000000000000..c83a30adc6ad --- /dev/null +++ b/arch/arm64/boot/dts/renesas/salvator-panel-aa104xd12.dts @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree overlay for the AA104XD12 panel connected to LVDS0 on a + * Salvator-X or Salvator-XS board + * + * Copyright 2021 Ideas on Board Oy + */ + +/dts-v1/; +/plugin/; + +&{/} { +#include "panel-aa104xd12.dtsi" +}; + +&{/panel} { + backlight = <&backlight>; + + port { + panel_in: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; +}; + +&lvds0 { + status = "okay"; + + ports { + port@1 { + lvds0_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi index 5bcb84403ef6..408871c2859d 100644 --- a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi +++ b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi @@ -206,12 +206,12 @@ clocks = <&clksndsel>; clock-names = "scki"; - VDD1-supply = <&snd_3p3v>; - VDD2-supply = <&snd_3p3v>; - VCCAD1-supply = <&snd_vcc5v>; - VCCAD2-supply = <&snd_vcc5v>; - VCCDA1-supply = <&snd_vcc5v>; - VCCDA2-supply = <&snd_vcc5v>; + VDD1-supply = <&snd_3p3v>; + VDD2-supply = <&snd_3p3v>; + VCCAD1-supply = <&snd_vcc5v>; + VCCAD2-supply = <&snd_vcc5v>; + VCCDA1-supply = <&snd_vcc5v>; + VCCDA2-supply = <&snd_vcc5v>; ports { #address-cells = <1>; @@ -438,7 +438,7 @@ bitclock-master; frame-master; dai-tdm-slot-num = <6>; - capture = <&ssi4>; + capture = <&ssi4>; }; }; }; diff --git a/arch/arm64/boot/dts/renesas/ulcb.dtsi b/arch/arm64/boot/dts/renesas/ulcb.dtsi index 90a4c0629d24..0772dfe4adff 100644 --- a/arch/arm64/boot/dts/renesas/ulcb.dtsi +++ b/arch/arm64/boot/dts/renesas/ulcb.dtsi @@ -76,7 +76,7 @@ }; }; - reg_1p8v: regulator0 { + reg_1p8v: regulator-1p8v { compatible = "regulator-fixed"; regulator-name = "fixed-1.8V"; regulator-min-microvolt = <1800000>; @@ -85,7 +85,7 @@ regulator-always-on; }; - reg_3p3v: regulator1 { + reg_3p3v: regulator-3p3v { compatible = "regulator-fixed"; regulator-name = "fixed-3.3V"; regulator-min-microvolt = <3300000>; @@ -411,7 +411,7 @@ bitclock-master; frame-master; playback = <&ssi0>, <&src0>, <&dvc0>; - capture = <&ssi1>, <&src1>, <&dvc1>; + capture = <&ssi1>, <&src1>, <&dvc1>; }; }; rsnd_port1: port@1 { diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index 18d00eae3072..ef79a672804a 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -5,6 +5,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-engicam-px30-core-ctouch2-of10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-engicam-px30-core-edimm2.2.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-evb.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-roc-cc.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-rock-pi-s.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3318-a95x-z2.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-odroid-go2.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-a1.dtb diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi b/arch/arm64/boot/dts/rockchip/px30.dtsi index 56dfbb2e2fa6..214f94fea3dc 100644 --- a/arch/arm64/boot/dts/rockchip/px30.dtsi +++ b/arch/arm64/boot/dts/rockchip/px30.dtsi @@ -528,7 +528,7 @@ i2c0: i2c@ff180000 { compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c"; reg = <0x0 0xff180000 0x0 0x1000>; - clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>; + clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>; clock-names = "i2c", "pclk"; interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/rockchip/rk3308-evb.dts b/arch/arm64/boot/dts/rockchip/rk3308-evb.dts index 9b4f855ea5d4..9fe9b0d11003 100644 --- a/arch/arm64/boot/dts/rockchip/rk3308-evb.dts +++ b/arch/arm64/boot/dts/rockchip/rk3308-evb.dts @@ -75,7 +75,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pwr_key>; - power { + key-power { gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>; linux,code = <KEY_POWER>; label = "GPIO Key Power"; diff --git a/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts b/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts new file mode 100644 index 000000000000..a71f249ed384 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts @@ -0,0 +1,253 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Akash Gajjar <akash@openedev.com> + * Copyright (c) 2019 Jagan Teki <jagan@openedev.com> + */ + +/dts-v1/; +#include "rk3308.dtsi" + +/ { + model = "Radxa ROCK Pi S"; + compatible = "radxa,rockpis", "rockchip,rk3308"; + + aliases { + ethernet0 = &gmac; + mmc0 = &emmc; + mmc1 = &sdmmc; + }; + + chosen { + stdout-path = "serial0:1500000n8"; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&green_led_gio>, <&heartbeat_led_gpio>; + + green-led { + default-state = "on"; + gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; + label = "rockpis:green:power"; + linux,default-trigger = "default-on"; + }; + + blue-led { + default-state = "on"; + gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + label = "rockpis:blue:user"; + linux,default-trigger = "heartbeat"; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-0 = <&wifi_enable_h>; + pinctrl-names = "default"; + reset-gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>; + }; + + vcc_1v8: vcc-1v8 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_io>; + }; + + vcc_io: vcc-io { + compatible = "regulator-fixed"; + regulator-name = "vcc_io"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc_ddr: vcc-ddr { + compatible = "regulator-fixed"; + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_otg: vcc5v0-otg { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&otg_vbus_drv>; + regulator-name = "vcc5v0_otg"; + regulator-always-on; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vdd_core: vdd-core { + compatible = "pwm-regulator"; + pwms = <&pwm0 0 5000 1>; + pwm-supply = <&vcc5v0_sys>; + regulator-name = "vdd_core"; + regulator-min-microvolt = <827000>; + regulator-max-microvolt = <1340000>; + regulator-init-microvolt = <1015000>; + regulator-settling-time-up-us = <250>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_log: vdd-log { + compatible = "regulator-fixed"; + regulator-name = "vdd_log"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&cpu0 { + cpu-supply = <&vdd_core>; +}; + +&emmc { + bus-width = <4>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + non-removable; + vmmc-supply = <&vcc_io>; + status = "okay"; +}; + +&gmac { + clock_in_out = "output"; + phy-supply = <&vcc_io>; + snps,reset-gpio = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 50000 50000>; + status = "okay"; +}; + +&i2c1 { + status = "okay"; +}; + +&pinctrl { + pinctrl-names = "default"; + pinctrl-0 = <&rtc_32k>; + + leds { + green_led_gio: green-led-gpio { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + heartbeat_led_gpio: heartbeat-led-gpio { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + otg_vbus_drv: otg-vbus-drv { + rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wifi_host_wake: wifi-host-wake { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; +}; + +&pwm0 { + status = "okay"; + pinctrl-0 = <&pwm0_pin_pull_down>; +}; + +&saradc { + vref-supply = <&vcc_1v8>; + status = "okay"; +}; + +&sdio { + #address-cells = <1>; + #size-cells = <0>; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + max-frequency = <1000000>; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + sd-uhs-sdr104; + status = "okay"; +}; + +&sdmmc { + cap-sd-highspeed; + status = "okay"; +}; + +&u2phy { + status = "okay"; + + u2phy_host: host-port { + phy-supply = <&vcc5v0_otg>; + status = "okay"; + }; + + u2phy_otg: otg-port { + phy-supply = <&vcc5v0_otg>; + status = "okay"; + }; +}; + +&uart0 { + status = "okay"; +}; + +&uart4 { + status = "okay"; + + bluetooth { + compatible = "realtek,rtl8723bs-bt"; + device-wake-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>; + host-wake-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; + }; +}; + +&usb_host_ehci { + status = "okay"; +}; + +&usb_host_ohci { + status = "okay"; +}; + +&usb20_otg { + dr_mode = "peripheral"; + status = "okay"; +}; + +&wdt { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts b/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts index ea0695b51ecd..415aa9ff8bd4 100644 --- a/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts +++ b/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts @@ -71,82 +71,82 @@ * |------------------------------------------------| */ - sw1 { + button-sw1 { gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_LOW>; label = "DPAD-UP"; linux,code = <BTN_DPAD_UP>; }; - sw2 { + button-sw2 { gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_LOW>; label = "DPAD-DOWN"; linux,code = <BTN_DPAD_DOWN>; }; - sw3 { + button-sw3 { gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_LOW>; label = "DPAD-LEFT"; linux,code = <BTN_DPAD_LEFT>; }; - sw4 { + button-sw4 { gpios = <&gpio1 RK_PB7 GPIO_ACTIVE_LOW>; label = "DPAD-RIGHT"; linux,code = <BTN_DPAD_RIGHT>; }; - sw5 { + button-sw5 { gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_LOW>; label = "BTN-A"; linux,code = <BTN_EAST>; }; - sw6 { + button-sw6 { gpios = <&gpio1 RK_PA5 GPIO_ACTIVE_LOW>; label = "BTN-B"; linux,code = <BTN_SOUTH>; }; - sw7 { + button-sw7 { gpios = <&gpio1 RK_PA6 GPIO_ACTIVE_LOW>; label = "BTN-Y"; linux,code = <BTN_WEST>; }; - sw8 { + button-sw8 { gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_LOW>; label = "BTN-X"; linux,code = <BTN_NORTH>; }; - sw9 { + button-sw9 { gpios = <&gpio2 RK_PA0 GPIO_ACTIVE_LOW>; label = "F1"; linux,code = <BTN_TRIGGER_HAPPY1>; }; - sw10 { + button-sw10 { gpios = <&gpio2 RK_PA1 GPIO_ACTIVE_LOW>; label = "F2"; linux,code = <BTN_TRIGGER_HAPPY2>; }; - sw11 { + button-sw11 { gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_LOW>; label = "F3"; linux,code = <BTN_TRIGGER_HAPPY3>; }; - sw12 { + button-sw12 { gpios = <&gpio2 RK_PA3 GPIO_ACTIVE_LOW>; label = "F4"; linux,code = <BTN_TRIGGER_HAPPY4>; }; - sw13 { + button-sw13 { gpios = <&gpio2 RK_PA4 GPIO_ACTIVE_LOW>; label = "F5"; linux,code = <BTN_TRIGGER_HAPPY5>; }; - sw14 { + button-sw14 { gpios = <&gpio2 RK_PA5 GPIO_ACTIVE_LOW>; label = "F6"; linux,code = <BTN_TRIGGER_HAPPY6>; }; - sw15 { + button-sw15 { gpios = <&gpio2 RK_PA6 GPIO_ACTIVE_LOW>; label = "TOP-LEFT"; linux,code = <BTN_TL>; }; - sw16 { + button-sw16 { gpios = <&gpio2 RK_PA7 GPIO_ACTIVE_LOW>; label = "TOP-RIGHT"; linux,code = <BTN_TR>; diff --git a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts index 3857d487ab84..1445b879ac7a 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts +++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts @@ -34,7 +34,7 @@ pinctrl-0 = <&reset_button_pin>; pinctrl-names = "default"; - reset { + key-reset { label = "reset"; gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>; linux,code = <KEY_RESTART>; diff --git a/arch/arm64/boot/dts/rockchip/rk3368-evb.dtsi b/arch/arm64/boot/dts/rockchip/rk3368-evb.dtsi index 15d1fc541c38..083452c67711 100644 --- a/arch/arm64/boot/dts/rockchip/rk3368-evb.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3368-evb.dtsi @@ -76,7 +76,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pwr_key>; - power { + key-power { wakeup-source; gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>; label = "GPIO Power"; diff --git a/arch/arm64/boot/dts/rockchip/rk3368-geekbox.dts b/arch/arm64/boot/dts/rockchip/rk3368-geekbox.dts index 62aa97a0b8c9..be06e6e64d18 100644 --- a/arch/arm64/boot/dts/rockchip/rk3368-geekbox.dts +++ b/arch/arm64/boot/dts/rockchip/rk3368-geekbox.dts @@ -43,7 +43,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pwr_key>; - power { + key-power { gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>; label = "GPIO Power"; linux,code = <KEY_POWER>; diff --git a/arch/arm64/boot/dts/rockchip/rk3368-orion-r68-meta.dts b/arch/arm64/boot/dts/rockchip/rk3368-orion-r68-meta.dts index 3ebe15e03cf4..7f5bba0c6001 100644 --- a/arch/arm64/boot/dts/rockchip/rk3368-orion-r68-meta.dts +++ b/arch/arm64/boot/dts/rockchip/rk3368-orion-r68-meta.dts @@ -44,7 +44,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pwr_key>; - power { + key-power { wakeup-source; gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; label = "GPIO Power"; @@ -134,7 +134,7 @@ vccio_sd: vcc-io-sd-regulator { compatible = "regulator-fixed"; - regulator-name= "vccio_sd"; + regulator-name = "vccio_sd"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; regulator-always-on; diff --git a/arch/arm64/boot/dts/rockchip/rk3368-px5-evb.dts b/arch/arm64/boot/dts/rockchip/rk3368-px5-evb.dts index 5ccaa5f7a370..29df84b81552 100644 --- a/arch/arm64/boot/dts/rockchip/rk3368-px5-evb.dts +++ b/arch/arm64/boot/dts/rockchip/rk3368-px5-evb.dts @@ -30,7 +30,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pwr_key>; - power { + key-power { gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>; label = "GPIO Power"; linux,code = <KEY_POWER>; diff --git a/arch/arm64/boot/dts/rockchip/rk3368-r88.dts b/arch/arm64/boot/dts/rockchip/rk3368-r88.dts index 959d3cc801f2..38d757c00548 100644 --- a/arch/arm64/boot/dts/rockchip/rk3368-r88.dts +++ b/arch/arm64/boot/dts/rockchip/rk3368-r88.dts @@ -37,7 +37,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pwr_key>; - power { + key-power { wakeup-source; gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>; label = "GPIO Power"; diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi index 4f0b5feaa5e6..a4c5aaf1f457 100644 --- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi @@ -1084,7 +1084,7 @@ gmac { rgmii_pins: rgmii-pins { - rockchip,pins = <3 RK_PC6 1 &pcfg_pull_none>, + rockchip,pins = <3 RK_PC6 1 &pcfg_pull_none>, <3 RK_PD0 1 &pcfg_pull_none>, <3 RK_PC3 1 &pcfg_pull_none>, <3 RK_PB0 1 &pcfg_pull_none_12ma>, @@ -1102,7 +1102,7 @@ }; rmii_pins: rmii-pins { - rockchip,pins = <3 RK_PC6 1 &pcfg_pull_none>, + rockchip,pins = <3 RK_PC6 1 &pcfg_pull_none>, <3 RK_PD0 1 &pcfg_pull_none>, <3 RK_PC3 1 &pcfg_pull_none>, <3 RK_PB0 1 &pcfg_pull_none_12ma>, @@ -1257,7 +1257,7 @@ spdif { spdif_tx: spdif-tx { - rockchip,pins = <2 RK_PC7 1 &pcfg_pull_none>; + rockchip,pins = <2 RK_PC7 1 &pcfg_pull_none>; }; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-evb.dts b/arch/arm64/boot/dts/rockchip/rk3399-evb.dts index 7b717ebec8ff..3d1e126b553f 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-evb.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-evb.dts @@ -55,7 +55,7 @@ }; edp_panel: edp-panel { - compatible ="lg,lp079qx1-sp0v"; + compatible = "lg,lp079qx1-sp0v"; backlight = <&backlight>; enable-gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>; power-supply = <&vcc3v3_s0>; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts b/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts index b340c9e246c4..c5db64f3e124 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts @@ -87,7 +87,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pwrbtn>; - power { + key-power { debounce-interval = <100>; gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; label = "GPIO Key Power"; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi index 50d459ee4831..cd074641884b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi @@ -206,7 +206,7 @@ pinctrl-names = "default"; pinctrl-0 = <&bt_host_wake_l>; - wake_on_bt: wake-on-bt { + wake_on_bt: key-wake-on-bt { label = "Wake-on-Bluetooth"; gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; linux,code = <KEY_WAKEUP>; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru-kevin.dts b/arch/arm64/boot/dts/rockchip/rk3399-gru-kevin.dts index 6863689df06f..2cc9b3386c16 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-gru-kevin.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-gru-kevin.dts @@ -92,7 +92,7 @@ pinctrl-names = "default"; pinctrl-0 = <&bt_host_wake_l>, <&cpu1_pen_eject>; - pen-insert { + switch-pen-insert { label = "Pen Insert"; /* Insert = low, eject = high */ gpios = <&gpio0 13 GPIO_ACTIVE_LOW>; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi index 1977103a5ef4..40d4053fba80 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi @@ -183,7 +183,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pen_eject_odl>; - pen-insert { + switch-pen-insert { label = "Pen Insert"; /* Insert = low, eject = high */ gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-khadas-edge.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-khadas-edge.dtsi index 46c4581deb8d..2a332763c35c 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-khadas-edge.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-khadas-edge.dtsi @@ -136,7 +136,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pwrbtn>; - power { + key-power { debounce-interval = <100>; gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; label = "GPIO Key Power"; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts index cef4d18b599d..fe5b52610010 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts @@ -46,9 +46,9 @@ gpio-keys { pinctrl-0 = <&reset_button_pin>; - /delete-node/ power; + /delete-node/ key-power; - reset { + key-reset { debounce-interval = <50>; gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_LOW>; label = "reset"; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi index 248ad41a976b..278123b4f911 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi @@ -111,7 +111,7 @@ pinctrl-names = "default"; pinctrl-0 = <&power_key>; - power { + key-power { debounce-interval = <100>; gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; label = "GPIO Key Power"; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-orangepi.dts b/arch/arm64/boot/dts/rockchip/rk3399-orangepi.dts index ed856bfcfc33..9e2e246e0bab 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-orangepi.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-orangepi.dts @@ -78,7 +78,7 @@ compatible = "gpio-keys"; autorepeat; - power { + key-power { debounce-interval = <100>; gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; label = "GPIO Power"; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts b/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts index d6b68d77d63a..194e48c755f6 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts @@ -76,7 +76,7 @@ pinctrl-names = "default"; pinctrl-0 = <&lidbtn_pin>; - lid { + switch-lid { debounce-interval = <20>; gpios = <&gpio1 RK_PA1 GPIO_ACTIVE_LOW>; label = "Lid"; @@ -92,7 +92,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pwrbtn_pin>; - power { + key-power { debounce-interval = <20>; gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; label = "Power"; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-puma-haikou.dts b/arch/arm64/boot/dts/rockchip/rk3399-puma-haikou.dts index 3ae5d727e367..04c752f49be9 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-puma-haikou.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-puma-haikou.dts @@ -49,7 +49,7 @@ sgtl5000_clk: sgtl5000-oscillator { compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency = <24576000>; + clock-frequency = <24576000>; }; dc_12v: dc-12v { diff --git a/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi index 0e45cc2d195b..acb174d3a8c5 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi @@ -54,7 +54,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pwr_key_l>; - power { + key-power { debounce-interval = <100>; gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; label = "GPIO Key Power"; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi index 45e77f86d329..78157521e944 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi @@ -20,6 +20,15 @@ stdout-path = "serial2:1500000n8"; }; + /* enable for panel backlight support */ + backlight: backlight { + compatible = "pwm-backlight"; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <5>; + pwms = <&pwm0 0 1000000 0>; + status = "disabled"; + }; + clkin_gmac: external-gmac-clock { compatible = "fixed-clock"; clock-frequency = <125000000>; @@ -33,7 +42,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pwrbtn>; - power { + key-power { debounce-interval = <100>; gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; label = "GPIO Key Power"; @@ -107,6 +116,14 @@ }; }; + avdd: avdd-regulator { + compatible = "regulator-fixed"; + regulator-name = "avdd"; + regulator-min-microvolt = <11000000>; + regulator-max-microvolt = <11000000>; + vin-supply = <&vcc3v3_s0>; + }; + vcc12v_dcin: vcc12v-dcin { compatible = "regulator-fixed"; regulator-name = "vcc12v_dcin"; @@ -400,8 +417,6 @@ vcc3v0_touch: LDO_REG2 { regulator-name = "vcc3v0_touch"; - regulator-always-on; - regulator-boot-on; regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3000000>; regulator-state-mem { @@ -490,8 +505,6 @@ vcc3v3_s0: SWITCH_REG2 { regulator-name = "vcc3v3_s0"; - regulator-always-on; - regulator-boot-on; regulator-state-mem { regulator-off-in-suspend; }; @@ -565,6 +578,19 @@ vbus-supply = <&vcc5v0_typec>; status = "okay"; }; + + /* enable for pine64 touch screen support */ + touch: touchscreen@5d { + compatible = "goodix,gt911"; + reg = <0x5d>; + interrupt-parent = <&gpio4>; + interrupts = <RK_PD5 IRQ_TYPE_EDGE_FALLING>; + AVDD28-supply = <&vcc3v0_touch>; + VDDIO-supply = <&vcc3v0_touch>; + irq-gpios = <&gpio4 RK_PD5 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio4 RK_PD6 GPIO_ACTIVE_HIGH>; + status = "disabled"; + }; }; &i2s0 { @@ -600,6 +626,42 @@ gpio1830-supply = <&vcc_3v0>; }; +/* enable for pine64 panel display support */ +&mipi_dsi { + clock-master; + status = "disabled"; + + ports { + mipi_out: port@1 { + reg = <1>; + + mipi_out_panel: endpoint { + remote-endpoint = <&mipi_in_panel>; + }; + }; + }; + + mipi_panel: panel@0 { + compatible = "feiyang,fy07024di26a30d"; + reg = <0>; + avdd-supply = <&avdd>; + backlight = <&backlight>; + dvdd-supply = <&vcc3v3_s0>; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mipi_in_panel: endpoint { + remote-endpoint = <&mipi_out_panel>; + }; + }; + }; + }; +}; + &pcie0 { ep-gpios = <&gpio2 RK_PD4 GPIO_ACTIVE_HIGH>; num-lanes = <4>; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-sapphire-excavator.dts b/arch/arm64/boot/dts/rockchip/rk3399-sapphire-excavator.dts index f6b2199a42bd..13927e7d0724 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-sapphire-excavator.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-sapphire-excavator.dts @@ -88,7 +88,7 @@ }; edp_panel: edp-panel { - compatible ="lg,lp079qx1-sp0v"; + compatible = "lg,lp079qx1-sp0v"; backlight = <&backlight>; enable-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi index 2aa0fad8f893..e6ac292ce645 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi @@ -53,7 +53,7 @@ compatible = "gpio-keys"; autorepeat; - power { + key-power { debounce-interval = <100>; gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; label = "GPIO Power"; diff --git a/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi b/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi index 01d1a75c8b4d..935b8c68a71d 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi @@ -347,7 +347,7 @@ pcie { pcie_pwr: pcie-pwr { - rockchip,pins = <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>; + rockchip,pins = <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>; }; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi b/arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi index e01668e6e5f9..0d45868132b9 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi @@ -49,7 +49,7 @@ pinctrl-0 = <&hall_int_l>; pinctrl-names = "default"; - cover { + switch-cover { label = "cover"; gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_LOW>; linux,input-type = <EV_SW>; diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts index fa953b736642..d943559b157c 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts +++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts @@ -4,6 +4,7 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/pinctrl/rockchip.h> +#include <dt-bindings/soc/rockchip,vop2.h> #include "rk3566.dtsi" / { @@ -32,9 +33,22 @@ gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>; gpio-fan,speed-map = <0 0 4500 1>; + pinctrl-names = "default"; + pinctrl-0 = <&fan_en_h>; #cooling-cells = <2>; }; + hdmi-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + leds { compatible = "gpio-leds"; @@ -125,6 +139,18 @@ vin-supply = <&vcc12v_dcin>; }; + vcc3v3_pcie_p: vcc3v3-pcie-p-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_enable_h>; + regulator-name = "vcc3v3_pcie_p"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_3v3>; + }; + vcc5v0_usb: vcc5v0_usb { compatible = "regulator-fixed"; regulator-name = "vcc5v0_usb"; @@ -201,6 +227,10 @@ status = "okay"; }; +&combphy2 { + status = "okay"; +}; + &cpu0 { cpu-supply = <&vdd_cpu>; }; @@ -262,6 +292,28 @@ status = "okay"; }; +&hdmi { + avdd-0v9-supply = <&vdda_0v9>; + avdd-1v8-supply = <&vcc_1v8>; + status = "okay"; +}; + +&hdmi_in { + hdmi_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi>; + }; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&hdmi_sound { + status = "okay"; +}; + &i2c0 { status = "okay"; @@ -492,6 +544,10 @@ status = "okay"; }; +&i2s0_8ch { + status = "okay"; +}; + &i2s1_8ch { pinctrl-names = "default"; pinctrl-0 = <&i2s1m0_sclktx @@ -509,6 +565,14 @@ }; }; +&pcie2x1 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie_reset_h>; + reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie_p>; + status = "okay"; +}; + &pinctrl { bt { bt_enable_h: bt-enable-h { @@ -524,6 +588,12 @@ }; }; + fan { + fan_en_h: fan-en-h { + rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + leds { work_led_enable_h: work-led-enable-h { rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; @@ -534,6 +604,16 @@ }; }; + pcie { + pcie_enable_h: pcie-enable-h { + rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie_reset_h: pcie-reset-h { + rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + pmic { pmic_int_l: pmic-int-l { rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; @@ -588,6 +668,7 @@ disable-wp; pinctrl-names = "default"; pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; + sd-uhs-sdr104; vmmc-supply = <&vcc3v3_sd>; vqmmc-supply = <&vccio_sd>; status = "okay"; @@ -608,6 +689,22 @@ status = "okay"; }; +&sfc { + pinctrl-0 = <&fspi_pins>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <24000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <1>; + }; +}; + /* spdif is exposed on con40 pin 18 */ &spdif { status = "okay"; @@ -723,3 +820,20 @@ phy-supply = <&vcc5v0_usb20_host>; status = "okay"; }; + +&vop { + assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; + assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp0 { + vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg = <ROCKCHIP_VOP2_EP_HDMI0>; + remote-endpoint = <&hdmi_in_vp0>; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3566.dtsi b/arch/arm64/boot/dts/rockchip/rk3566.dtsi index 0b957068ff89..6c4b17d27bdc 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3566.dtsi @@ -29,3 +29,7 @@ extcon = <&usb2phy0>; maximum-speed = "high-speed"; }; + +&vop { + compatible = "rockchip,rk3566-vop"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts index 40cf2236c0b6..1d3ffbf3cde8 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts @@ -8,6 +8,7 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/leds/common.h> #include <dt-bindings/pinctrl/rockchip.h> +#include <dt-bindings/soc/rockchip,vop2.h> #include "rk3568.dtsi" / { @@ -54,6 +55,17 @@ regulator-max-microvolt = <12000000>; }; + hdmi-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + vcc3v3_sys: vcc3v3-sys { compatible = "regulator-fixed"; regulator-name = "vcc3v3_sys"; @@ -174,6 +186,33 @@ status = "okay"; }; +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&hdmi { + avdd-0v9-supply = <&vdda0v9_image>; + avdd-1v8-supply = <&vcca1v8_image>; + status = "okay"; +}; + +&hdmi_in { + hdmi_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi>; + }; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&hdmi_sound { + status = "okay"; +}; + &i2c0 { status = "okay"; @@ -215,6 +254,7 @@ vdd_gpu: DCDC_REG2 { regulator-name = "vdd_gpu"; + regulator-always-on; regulator-init-microvolt = <900000>; regulator-initial-mode = <0x2>; regulator-min-microvolt = <500000>; @@ -264,6 +304,7 @@ vdda0v9_image: LDO_REG1 { regulator-name = "vdda0v9_image"; + regulator-always-on; regulator-min-microvolt = <900000>; regulator-max-microvolt = <900000>; @@ -359,6 +400,7 @@ vcca1v8_image: LDO_REG9 { regulator-name = "vcca1v8_image"; + regulator-always-on; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; @@ -389,11 +431,33 @@ }; }; +&i2c3 { + status = "okay"; + + hym8563: rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + interrupt-parent = <&gpio0>; + interrupts = <RK_PD3 IRQ_TYPE_EDGE_FALLING>; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "rtcic_32kout"; + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; + wakeup-source; + }; +}; + &i2c5 { /* pin 3 (SDA) + 4 (SCL) of header con2 */ status = "disabled"; }; +&i2s0_8ch { + /* hdmi sound */ + status = "okay"; +}; + &mdio1 { rgmii_phy1: ethernet-phy@0 { compatible = "ethernet-phy-ieee802.3-c22"; @@ -411,6 +475,12 @@ }; }; + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + pmic { pmic_int: pmic_int { rockchip,pins = @@ -523,6 +593,8 @@ }; &tsadc { + rockchip,hw-tshut-mode = <1>; + rockchip,hw-tshut-polarity = <0>; status = "okay"; }; @@ -587,3 +659,20 @@ phy-supply = <&vcc5v0_usb_otg>; status = "okay"; }; + +&vop { + assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; + assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp0 { + vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg = <ROCKCHIP_VOP2_EP_HDMI0>; + remote-endpoint = <&hdmi_in_vp0>; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts b/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts index 622be8be9813..6ff89ff95ad1 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts @@ -8,6 +8,7 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/leds/common.h> #include <dt-bindings/pinctrl/rockchip.h> +#include <dt-bindings/soc/rockchip,vop2.h> #include "rk3568.dtsi" / { @@ -34,6 +35,17 @@ regulator-max-microvolt = <12000000>; }; + hdmi-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + leds { compatible = "gpio-leds"; @@ -209,6 +221,28 @@ status = "okay"; }; +&hdmi { + avdd-0v9-supply = <&vdda0v9_image>; + avdd-1v8-supply = <&vcca1v8_image>; + status = "okay"; +}; + +&hdmi_in { + hdmi_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi>; + }; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&hdmi_sound { + status = "okay"; +}; + &i2c0 { status = "okay"; @@ -466,6 +500,10 @@ }; }; +&i2s0_8ch { + status = "okay"; +}; + &i2s1_8ch { rockchip,trcm-sync-tx-only; status = "okay"; @@ -635,3 +673,20 @@ phy-supply = <&vcc5v0_usb_host>; status = "okay"; }; + +&vop { + assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; + assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp0 { + vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg = <ROCKCHIP_VOP2_EP_HDMI0>; + remote-endpoint = <&hdmi_in_vp0>; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts index 0813c0c5abde..6b5093a1a6cf 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts @@ -4,6 +4,7 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/leds/common.h> #include <dt-bindings/pinctrl/rockchip.h> +#include <dt-bindings/soc/rockchip,vop2.h> #include "rk3568.dtsi" / { @@ -20,6 +21,17 @@ stdout-path = "serial2:1500000n8"; }; + hdmi-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + leds { compatible = "gpio-leds"; @@ -166,6 +178,28 @@ status = "okay"; }; +&hdmi { + avdd-0v9-supply = <&vdda0v9_image>; + avdd-1v8-supply = <&vcca1v8_image>; + status = "okay"; +}; + +&hdmi_in { + hdmi_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi>; + }; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&hdmi_sound { + status = "okay"; +}; + &i2c0 { status = "okay"; @@ -406,6 +440,10 @@ }; }; +&i2s0_8ch { + status = "okay"; +}; + &i2s1_8ch { rockchip,trcm-sync-tx-only; status = "okay"; @@ -560,3 +598,20 @@ phy-supply = <&vcc5v0_usb_host>; status = "okay"; }; + +&vop { + assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; + assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp0 { + vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg = <ROCKCHIP_VOP2_EP_HDMI0>; + remote-endpoint = <&hdmi_in_vp0>; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi index 5eafddf62edc..2bdf8c7e9765 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi @@ -137,3 +137,7 @@ phys = <&usb2phy0_otg>, <&combphy0 PHY_TYPE_USB3>; phy-names = "usb2-phy", "usb3-phy"; }; + +&vop { + compatible = "rockchip,rk3568-vop"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi index 914f13c0d399..319981c3e9f7 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi @@ -129,6 +129,11 @@ }; }; + display_subsystem: display-subsystem { + compatible = "rockchip,display-subsystem"; + ports = <&vop_out>; + }; + firmware { scmi: scmi { compatible = "arm,scmi-smc"; @@ -178,6 +183,22 @@ }; }; + hdmi_sound: hdmi-sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "HDMI"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <256>; + status = "disabled"; + + simple-audio-card,codec { + sound-dai = <&hdmi>; + }; + + simple-audio-card,cpu { + sound-dai = <&i2s0_8ch>; + }; + }; + pmu { compatible = "arm,cortex-a55-pmu"; interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>, @@ -632,6 +653,84 @@ }; }; + vop: vop@fe040000 { + reg = <0x0 0xfe040000 0x0 0x3000>, <0x0 0xfe044000 0x0 0x1000>; + reg-names = "vop", "gamma-lut"; + interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>, <&cru DCLK_VOP0>, + <&cru DCLK_VOP1>, <&cru DCLK_VOP2>; + clock-names = "aclk", "hclk", "dclk_vp0", "dclk_vp1", "dclk_vp2"; + iommus = <&vop_mmu>; + power-domains = <&power RK3568_PD_VO>; + rockchip,grf = <&grf>; + status = "disabled"; + + vop_out: ports { + #address-cells = <1>; + #size-cells = <0>; + + vp0: port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + vp1: port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + + vp2: port@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; + + vop_mmu: iommu@fe043e00 { + compatible = "rockchip,rk3568-iommu"; + reg = <0x0 0xfe043e00 0x0 0x100>, <0x0 0xfe043f00 0x0 0x100>; + interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; + status = "disabled"; + }; + + hdmi: hdmi@fe0a0000 { + compatible = "rockchip,rk3568-dw-hdmi"; + reg = <0x0 0xfe0a0000 0x0 0x20000>; + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru PCLK_HDMI_HOST>, + <&cru CLK_HDMI_SFR>, + <&cru CLK_HDMI_CEC>, + <&pmucru CLK_HDMI_REF>, + <&cru HCLK_VO>; + clock-names = "iahb", "isfr", "cec", "ref"; + pinctrl-names = "default"; + pinctrl-0 = <&hdmitx_scl &hdmitx_sda &hdmitxm0_cec>; + power-domains = <&power RK3568_PD_VO>; + reg-io-width = <4>; + rockchip,grf = <&grf>; + #sound-dai-cells = <0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + hdmi_in: port@0 { + reg = <0>; + }; + + hdmi_out: port@1 { + reg = <1>; + }; + }; + }; + qos_gpu: qos@fe128000 { compatible = "rockchip,rk3568-qos", "syscon"; reg = <0x0 0xfe128000 0x0 0x20>; @@ -752,6 +851,56 @@ reg = <0x0 0xfe1a8100 0x0 0x20>; }; + pcie2x1: pcie@fe260000 { + compatible = "rockchip,rk3568-pcie"; + reg = <0x3 0xc0000000 0x0 0x00400000>, + <0x0 0xfe260000 0x0 0x00010000>, + <0x3 0x3f000000 0x0 0x01000000>; + reg-names = "dbi", "apb", "config"; + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "sys", "pmc", "msi", "legacy", "err"; + bus-range = <0x0 0xf>; + clocks = <&cru ACLK_PCIE20_MST>, <&cru ACLK_PCIE20_SLV>, + <&cru ACLK_PCIE20_DBI>, <&cru PCLK_PCIE20>, + <&cru CLK_PCIE20_AUX_NDFT>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", "aux"; + device_type = "pci"; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc 0>, + <0 0 0 2 &pcie_intc 1>, + <0 0 0 3 &pcie_intc 2>, + <0 0 0 4 &pcie_intc 3>; + linux,pci-domain = <0>; + num-ib-windows = <6>; + num-ob-windows = <2>; + max-link-speed = <2>; + msi-map = <0x0 &gic 0x0 0x1000>; + num-lanes = <1>; + phys = <&combphy2 PHY_TYPE_PCIE>; + phy-names = "pcie-phy"; + power-domains = <&power RK3568_PD_PIPE>; + ranges = <0x01000000 0x0 0x3ef00000 0x3 0x3ef00000 0x0 0x00100000 + 0x02000000 0x0 0x00000000 0x3 0x00000000 0x0 0x3ef00000>; + resets = <&cru SRST_PCIE20_POWERUP>; + reset-names = "pipe"; + #address-cells = <3>; + #size-cells = <2>; + status = "disabled"; + + pcie_intc: legacy-interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 72 IRQ_TYPE_EDGE_RISING>; + }; + }; + sdmmc0: mmc@fe2b0000 { compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x0 0xfe2b0000 0x0 0x4000>; @@ -818,6 +967,23 @@ status = "disabled"; }; + i2s0_8ch: i2s@fe400000 { + compatible = "rockchip,rk3568-i2s-tdm"; + reg = <0x0 0xfe400000 0x0 0x1000>; + interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; + assigned-clocks = <&cru CLK_I2S0_8CH_TX_SRC>, <&cru CLK_I2S0_8CH_RX_SRC>; + assigned-clock-rates = <1188000000>, <1188000000>; + clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>; + clock-names = "mclk_tx", "mclk_rx", "hclk"; + dmas = <&dmac1 0>; + dma-names = "tx"; + resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>; + reset-names = "tx-m", "rx-m"; + rockchip,grf = <&grf>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + i2s1_8ch: i2s@fe410000 { compatible = "rockchip,rk3568-i2s-tdm"; reg = <0x0 0xfe410000 0x0 0x1000>; diff --git a/arch/arm64/boot/dts/sprd/sc9836.dtsi b/arch/arm64/boot/dts/sprd/sc9836.dtsi index 231436be0e3f..8bb8a70966d2 100644 --- a/arch/arm64/boot/dts/sprd/sc9836.dtsi +++ b/arch/arm64/boot/dts/sprd/sc9836.dtsi @@ -207,11 +207,11 @@ }; psci { - compatible = "arm,psci"; - method = "smc"; - cpu_on = <0xc4000003>; - cpu_off = <0x84000002>; - cpu_suspend = <0xc4000001>; + compatible = "arm,psci"; + method = "smc"; + cpu_on = <0xc4000003>; + cpu_off = <0x84000002>; + cpu_suspend = <0xc4000001>; }; timer { diff --git a/arch/arm64/boot/dts/sprd/sc9863a.dtsi b/arch/arm64/boot/dts/sprd/sc9863a.dtsi index 8cf4a6575980..22d81ace740a 100644 --- a/arch/arm64/boot/dts/sprd/sc9863a.dtsi +++ b/arch/arm64/boot/dts/sprd/sc9863a.dtsi @@ -552,7 +552,7 @@ ranges; sdio0: sdio@20300000 { - compatible = "sprd,sdhci-r11"; + compatible = "sprd,sdhci-r11"; reg = <0 0x20300000 0 0x1000>; interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; @@ -568,7 +568,7 @@ }; sdio3: sdio@20600000 { - compatible = "sprd,sdhci-r11"; + compatible = "sprd,sdhci-r11"; reg = <0 0x20600000 0 0x1000>; interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm64/boot/dts/sprd/whale2.dtsi b/arch/arm64/boot/dts/sprd/whale2.dtsi index 89d91abbd5d1..fece49704b5c 100644 --- a/arch/arm64/boot/dts/sprd/whale2.dtsi +++ b/arch/arm64/boot/dts/sprd/whale2.dtsi @@ -134,7 +134,7 @@ }; sdio3: sdio@50430000 { - compatible = "sprd,sdhci-r11"; + compatible = "sprd,sdhci-r11"; reg = <0 0x50430000 0 0x1000>; interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm64/boot/dts/tesla/fsd-evb.dts b/arch/arm64/boot/dts/tesla/fsd-evb.dts index 5af560c1b5e6..1db6ddf03f01 100644 --- a/arch/arm64/boot/dts/tesla/fsd-evb.dts +++ b/arch/arm64/boot/dts/tesla/fsd-evb.dts @@ -37,3 +37,7 @@ &serial_0 { status = "okay"; }; + +&ufs { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi b/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi index d4d0cb005712..d0abb9aa0e9e 100644 --- a/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi +++ b/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi @@ -8,7 +8,7 @@ * https://www.tesla.com */ -#include <dt-bindings/pinctrl/samsung.h> +#include "fsd-pinctrl.h" &pinctrl_fsys0 { gpf0: gpf0-gpio-bank { @@ -50,6 +50,20 @@ interrupt-controller; #interrupt-cells = <2>; }; + + ufs_rst_n: ufs-rst-n-pins { + samsung,pins = "gpf5-0"; + samsung,pin-function = <FSD_PIN_FUNC_2>; + samsung,pin-pud = <FSD_PIN_PULL_NONE>; + samsung,pin-drv = <FSD_PIN_DRV_LV2>; + }; + + ufs_refclk_out: ufs-refclk-out-pins { + samsung,pins = "gpf5-1"; + samsung,pin-function = <FSD_PIN_FUNC_2>; + samsung,pin-pud = <FSD_PIN_PULL_NONE>; + samsung,pin-drv = <FSD_PIN_DRV_LV2>; + }; }; &pinctrl_peric { @@ -223,107 +237,107 @@ pwm0_out: pwm0-out-pins { samsung,pins = "gpb6-1"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV2>; + samsung,pin-function = <FSD_PIN_FUNC_2>; + samsung,pin-pud = <FSD_PIN_PULL_UP>; + samsung,pin-drv = <FSD_PIN_DRV_LV2>; }; pwm1_out: pwm1-out-pins { samsung,pins = "gpb6-5"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV2>; + samsung,pin-function = <FSD_PIN_FUNC_2>; + samsung,pin-pud = <FSD_PIN_PULL_UP>; + samsung,pin-drv = <FSD_PIN_DRV_LV2>; }; hs_i2c0_bus: hs-i2c0-bus-pins { samsung,pins = "gpb0-0", "gpb0-1"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <FSD_PIN_FUNC_2>; + samsung,pin-pud = <FSD_PIN_PULL_UP>; + samsung,pin-drv = <FSD_PIN_DRV_LV1>; }; hs_i2c1_bus: hs-i2c1-bus-pins { samsung,pins = "gpb0-2", "gpb0-3"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <FSD_PIN_FUNC_2>; + samsung,pin-pud = <FSD_PIN_PULL_UP>; + samsung,pin-drv = <FSD_PIN_DRV_LV1>; }; hs_i2c2_bus: hs-i2c2-bus-pins { samsung,pins = "gpb0-4", "gpb0-5"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <FSD_PIN_FUNC_2>; + samsung,pin-pud = <FSD_PIN_PULL_UP>; + samsung,pin-drv = <FSD_PIN_DRV_LV1>; }; hs_i2c3_bus: hs-i2c3-bus-pins { samsung,pins = "gpb0-6", "gpb0-7"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <FSD_PIN_FUNC_2>; + samsung,pin-pud = <FSD_PIN_PULL_UP>; + samsung,pin-drv = <FSD_PIN_DRV_LV1>; }; hs_i2c4_bus: hs-i2c4-bus-pins { samsung,pins = "gpb1-0", "gpb1-1"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <FSD_PIN_FUNC_2>; + samsung,pin-pud = <FSD_PIN_PULL_UP>; + samsung,pin-drv = <FSD_PIN_DRV_LV1>; }; hs_i2c5_bus: hs-i2c5-bus-pins { samsung,pins = "gpb1-2", "gpb1-3"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <FSD_PIN_FUNC_2>; + samsung,pin-pud = <FSD_PIN_PULL_UP>; + samsung,pin-drv = <FSD_PIN_DRV_LV1>; }; hs_i2c6_bus: hs-i2c6-bus-pins { samsung,pins = "gpb1-4", "gpb1-5"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <FSD_PIN_FUNC_2>; + samsung,pin-pud = <FSD_PIN_PULL_UP>; + samsung,pin-drv = <FSD_PIN_DRV_LV1>; }; hs_i2c7_bus: hs-i2c7-bus-pins { samsung,pins = "gpb1-6", "gpb1-7"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <FSD_PIN_FUNC_2>; + samsung,pin-pud = <FSD_PIN_PULL_UP>; + samsung,pin-drv = <FSD_PIN_DRV_LV1>; }; uart0_data: uart0-data-pins { samsung,pins = "gpb7-0", "gpb7-1"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <FSD_PIN_FUNC_2>; + samsung,pin-pud = <FSD_PIN_PULL_NONE>; + samsung,pin-drv = <FSD_PIN_DRV_LV1>; }; uart1_data: uart1-data-pins { samsung,pins = "gpb7-4", "gpb7-5"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <FSD_PIN_FUNC_2>; + samsung,pin-pud = <FSD_PIN_PULL_NONE>; + samsung,pin-drv = <FSD_PIN_DRV_LV1>; }; spi0_bus: spi0-bus-pins { samsung,pins = "gpb4-0", "gpb4-2", "gpb4-3"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <FSD_PIN_FUNC_2>; + samsung,pin-pud = <FSD_PIN_PULL_UP>; + samsung,pin-drv = <FSD_PIN_DRV_LV1>; }; spi1_bus: spi1-bus-pins { samsung,pins = "gpb4-4", "gpb4-6", "gpb4-7"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <FSD_PIN_FUNC_2>; + samsung,pin-pud = <FSD_PIN_PULL_UP>; + samsung,pin-drv = <FSD_PIN_DRV_LV1>; }; spi2_bus: spi2-bus-pins { samsung,pins = "gpb5-0", "gpb5-2", "gpb5-3"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <FSD_PIN_FUNC_2>; + samsung,pin-pud = <FSD_PIN_PULL_UP>; + samsung,pin-drv = <FSD_PIN_DRV_LV1>; }; }; diff --git a/arch/arm64/boot/dts/tesla/fsd-pinctrl.h b/arch/arm64/boot/dts/tesla/fsd-pinctrl.h new file mode 100644 index 000000000000..6ffbda362493 --- /dev/null +++ b/arch/arm64/boot/dts/tesla/fsd-pinctrl.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Tesla FSD DTS pinctrl constants + * + * Copyright (c) 2016 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * Copyright (c) 2022 Linaro Ltd + * Author: Krzysztof Kozlowski <krzk@kernel.org> + */ + +#ifndef __DTS_ARM64_TESLA_FSD_PINCTRL_H__ +#define __DTS_ARM64_TESLA_FSD_PINCTRL_H__ + +#define FSD_PIN_PULL_NONE 0 +#define FSD_PIN_PULL_DOWN 1 +#define FSD_PIN_PULL_UP 3 + +#define FSD_PIN_DRV_LV1 0 +#define FSD_PIN_DRV_LV2 2 +#define FSD_PIN_DRV_LV3 1 +#define FSD_PIN_DRV_LV4 3 + +#define FSD_PIN_FUNC_INPUT 0 +#define FSD_PIN_FUNC_OUTPUT 1 +#define FSD_PIN_FUNC_2 2 +#define FSD_PIN_FUNC_3 3 +#define FSD_PIN_FUNC_4 4 +#define FSD_PIN_FUNC_5 5 +#define FSD_PIN_FUNC_6 6 +#define FSD_PIN_FUNC_EINT 0xf +#define FSD_PIN_FUNC_F FSD_PIN_FUNC_EINT + +#endif /* __DTS_ARM64_TESLA_FSD_PINCTRL_H__ */ diff --git a/arch/arm64/boot/dts/tesla/fsd.dtsi b/arch/arm64/boot/dts/tesla/fsd.dtsi index af39655331de..f35bc5a288c2 100644 --- a/arch/arm64/boot/dts/tesla/fsd.dtsi +++ b/arch/arm64/boot/dts/tesla/fsd.dtsi @@ -93,6 +93,13 @@ enable-method = "psci"; clock-frequency = <2400000000>; cpu-idle-states = <&CPU_SLEEP>; + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&cpucl_l2>; }; cpucl0_1: cpu@1 { @@ -102,6 +109,13 @@ enable-method = "psci"; clock-frequency = <2400000000>; cpu-idle-states = <&CPU_SLEEP>; + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&cpucl_l2>; }; cpucl0_2: cpu@2 { @@ -111,6 +125,13 @@ enable-method = "psci"; clock-frequency = <2400000000>; cpu-idle-states = <&CPU_SLEEP>; + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&cpucl_l2>; }; cpucl0_3: cpu@3 { @@ -119,6 +140,13 @@ reg = <0x0 0x003>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP>; + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&cpucl_l2>; }; /* Cluster 1 */ @@ -129,6 +157,13 @@ enable-method = "psci"; clock-frequency = <2400000000>; cpu-idle-states = <&CPU_SLEEP>; + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&cpucl_l2>; }; cpucl1_1: cpu@101 { @@ -138,6 +173,13 @@ enable-method = "psci"; clock-frequency = <2400000000>; cpu-idle-states = <&CPU_SLEEP>; + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&cpucl_l2>; }; cpucl1_2: cpu@102 { @@ -147,6 +189,13 @@ enable-method = "psci"; clock-frequency = <2400000000>; cpu-idle-states = <&CPU_SLEEP>; + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&cpucl_l2>; }; cpucl1_3: cpu@103 { @@ -156,6 +205,13 @@ enable-method = "psci"; clock-frequency = <2400000000>; cpu-idle-states = <&CPU_SLEEP>; + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&cpucl_l2>; }; /* Cluster 2 */ @@ -166,6 +222,13 @@ enable-method = "psci"; clock-frequency = <2400000000>; cpu-idle-states = <&CPU_SLEEP>; + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&cpucl_l2>; }; cpucl2_1: cpu@201 { @@ -175,6 +238,13 @@ enable-method = "psci"; clock-frequency = <2400000000>; cpu-idle-states = <&CPU_SLEEP>; + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&cpucl_l2>; }; cpucl2_2: cpu@202 { @@ -184,6 +254,13 @@ enable-method = "psci"; clock-frequency = <2400000000>; cpu-idle-states = <&CPU_SLEEP>; + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&cpucl_l2>; }; cpucl2_3: cpu@203 { @@ -193,6 +270,20 @@ enable-method = "psci"; clock-frequency = <2400000000>; cpu-idle-states = <&CPU_SLEEP>; + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&cpucl_l2>; + }; + + cpucl_l2: l2-cache0 { + compatible = "cache"; + cache-size = <0x400000>; + cache-line-size = <64>; + cache-sets = <4096>; }; idle-states { @@ -740,6 +831,35 @@ clocks = <&fin_pll>, <&clock_imem IMEM_MCT_PCLK>; clock-names = "fin_pll", "mct"; }; + + ufs: ufs@15120000 { + compatible = "tesla,fsd-ufs"; + reg = <0x0 0x15120000 0x0 0x200>, /* 0: HCI standard */ + <0x0 0x15121100 0x0 0x200>, /* 1: Vendor specified */ + <0x0 0x15110000 0x0 0x8000>, /* 2: UNIPRO */ + <0x0 0x15130000 0x0 0x100>; /* 3: UFS protector */ + reg-names = "hci", "vs_hci", "unipro", "ufsp"; + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clock_fsys0 UFS0_TOP0_HCLK_BUS>, + <&clock_fsys0 UFS0_TOP0_CLK_UNIPRO>; + clock-names = "core_clk", "sclk_unipro_main"; + freq-table-hz = <0 0>, <0 0>; + pinctrl-names = "default"; + pinctrl-0 = <&ufs_rst_n &ufs_refclk_out>; + phys = <&ufs_phy>; + phy-names = "ufs-phy"; + status = "disabled"; + }; + + ufs_phy: ufs-phy@15124000 { + compatible = "tesla,fsd-ufs-phy"; + reg = <0x0 0x15124000 0x0 0x800>; + reg-names = "phy-pma"; + samsung,pmu-syscon = <&pmu_system_controller>; + #phy-cells = <0>; + clocks = <&clock_fsys0 UFS0_MPHY_REFCLK_IXTAL26>; + clock-names = "ref_clk"; + }; }; }; diff --git a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi index d08abad0bcf4..12ab7548dc77 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi @@ -144,8 +144,8 @@ compatible = "ti,k2g-sci"; ti,host-id = <12>; mbox-names = "rx", "tx"; - mboxes= <&secure_proxy_main 12>, - <&secure_proxy_main 13>; + mboxes = <&secure_proxy_main 12>, + <&secure_proxy_main 13>; reg-names = "debug_messages"; reg = <0x00 0x44043000 0x00 0xfe0>; @@ -165,6 +165,19 @@ }; }; + crypto: crypto@40900000 { + compatible = "ti,am62-sa3ul"; + reg = <0x00 0x40900000 0x00 0x1200>; + power-domains = <&k3_pds 70 TI_SCI_PD_SHARED>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x00 0x40900000 0x00 0x40900000 0x00 0x30000>; + + dmas = <&main_pktdma 0xf501 0>, <&main_pktdma 0x7506 0>, + <&main_pktdma 0x7507 0>; + dma-names = "tx", "rx1", "rx2"; + }; + main_pmx0: pinctrl@f4000 { compatible = "pinctrl-single"; reg = <0x00 0xf4000 0x00 0x2ac>; diff --git a/arch/arm64/boot/dts/ti/k3-am625-sk.dts b/arch/arm64/boot/dts/ti/k3-am625-sk.dts index 39fb1d763037..9b4dbae9d4aa 100644 --- a/arch/arm64/boot/dts/ti/k3-am625-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am625-sk.dts @@ -13,7 +13,7 @@ #include "k3-am625.dtsi" / { - compatible = "ti,am625-sk", "ti,am625"; + compatible = "ti,am625-sk", "ti,am625"; model = "Texas Instruments AM625 SK"; aliases { @@ -43,6 +43,15 @@ #size-cells = <2>; ranges; + ramoops@9ca00000 { + compatible = "ramoops"; + reg = <0x00 0x9ca00000 0x00 0x00100000>; + record-size = <0x8000>; + console-size = <0x8000>; + ftrace-size = <0x00>; + pmsg-size = <0x8000>; + }; + secure_tfa_ddr: tfa@9e780000 { reg = <0x00 0x9e780000 0x00 0x80000>; alignment = <0x1000>; diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi index cdb530597c5e..ada00575f0f2 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi @@ -174,7 +174,7 @@ compatible = "ti,k2g-sci"; ti,host-id = <12>; mbox-names = "rx", "tx"; - mboxes= <&secure_proxy_main 12>, + mboxes = <&secure_proxy_main 12>, <&secure_proxy_main 13>; reg-names = "debug_messages"; reg = <0x00 0x44043000 0x00 0xfe0>; @@ -1301,7 +1301,7 @@ <0x00 0x20718000 0x00 0x8000>; reg-names = "m_can", "message_ram"; power-domains = <&k3_pds 99 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 99 5>, <&k3_clks 99 0>; + clocks = <&k3_clks 99 5>, <&k3_clks 99 0>; clock-names = "hclk", "cclk"; interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts index 8e7893e58b03..ad150c704623 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts @@ -13,7 +13,7 @@ #include "k3-am642.dtsi" / { - compatible = "ti,am642-evm", "ti,am642"; + compatible = "ti,am642-evm", "ti,am642"; model = "Texas Instruments AM642 EVM"; chosen { diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/ti/k3-am642-sk.dts index 59f506cbd275..2620469a7517 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts @@ -12,7 +12,7 @@ #include "k3-am642.dtsi" / { - compatible = "ti,am642-sk", "ti,am642"; + compatible = "ti,am642-sk", "ti,am642"; model = "Texas Instruments AM642 SK"; chosen { @@ -166,6 +166,15 @@ >; }; + main_uart0_pins_default: main-uart0-pins-default { + pinctrl-single,pins = < + AM64X_IOPAD(0x0238, PIN_INPUT, 0) /* (B16) UART0_CTSn */ + AM64X_IOPAD(0x023c, PIN_OUTPUT, 0) /* (A16) UART0_RTSn */ + AM64X_IOPAD(0x0230, PIN_INPUT, 0) /* (D15) UART0_RXD */ + AM64X_IOPAD(0x0234, PIN_OUTPUT, 0) /* (C16) UART0_TXD */ + >; + }; + main_usb0_pins_default: main-usb0-pins-default { pinctrl-single,pins = < AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */ @@ -268,6 +277,11 @@ status = "disabled"; }; +&main_uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_uart0_pins_default>; +}; + &main_uart1 { /* main_uart1 is reserved for firmware usage */ status = "reserved"; diff --git a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi index 6e41f2fa044a..32b797237581 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi @@ -425,7 +425,7 @@ psu: regulator@60 { compatible = "ti,tps62363"; - reg = <0x60>; + reg = <0x60>; regulator-name = "tps62363-vout"; regulator-min-microvolt = <500000>; regulator-max-microvolt = <1500000>; @@ -574,7 +574,7 @@ pinctrl-0 = <&mcu_spi0_pins_default>; #address-cells = <1>; - #size-cells= <0>; + #size-cells = <0>; ti,pindir-d0-out-d1-in; }; diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi index e749343acced..8919fede3cd7 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -690,7 +690,7 @@ pcie0_rc: pcie@5500000 { compatible = "ti,am654-pcie-rc"; - reg = <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x2000>, <0x0 0x5506000 0x0 0x1000>; + reg = <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x2000>, <0x0 0x5506000 0x0 0x1000>; reg-names = "app", "dbics", "config", "atu"; power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>; #address-cells = <3>; @@ -710,7 +710,7 @@ pcie0_ep: pcie-ep@5500000 { compatible = "ti,am654-pcie-ep"; - reg = <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x8000000>, <0x0 0x5506000 0x0 0x1000>; + reg = <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x8000000>, <0x0 0x5506000 0x0 0x1000>; reg-names = "app", "dbics", "addr_space", "atu"; power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>; ti,syscon-pcie-mode = <&pcie0_mode>; @@ -723,7 +723,7 @@ pcie1_rc: pcie@5600000 { compatible = "ti,am654-pcie-rc"; - reg = <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x2000>, <0x0 0x5606000 0x0 0x1000>; + reg = <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x2000>, <0x0 0x5606000 0x0 0x1000>; reg-names = "app", "dbics", "config", "atu"; power-domains = <&k3_pds 121 TI_SCI_PD_EXCLUSIVE>; #address-cells = <3>; @@ -743,7 +743,7 @@ pcie1_ep: pcie-ep@5600000 { compatible = "ti,am654-pcie-ep"; - reg = <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x4000000>, <0x0 0x5606000 0x0 0x1000>; + reg = <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x4000000>, <0x0 0x5606000 0x0 0x1000>; reg-names = "app", "dbics", "addr_space", "atu"; power-domains = <&k3_pds 121 TI_SCI_PD_EXCLUSIVE>; ti,syscon-pcie-mode = <&pcie1_mode>; @@ -843,9 +843,9 @@ power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 67 1>, - <&k3_clks 216 1>, - <&k3_clks 67 2>; + clocks = <&k3_clks 67 1>, + <&k3_clks 216 1>, + <&k3_clks 67 2>; clock-names = "fck", "vp1", "vp2"; /* diff --git a/arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi index 9c69d0917f69..fa11d7142006 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi @@ -12,8 +12,8 @@ mbox-names = "rx", "tx"; - mboxes= <&secure_proxy_main 11>, - <&secure_proxy_main 13>; + mboxes = <&secure_proxy_main 11>, + <&secure_proxy_main 13>; reg-names = "debug_messages"; reg = <0x44083000 0x1000>; diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts index 57497cb1ed68..5850582dd4ed 100644 --- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts @@ -10,7 +10,7 @@ #include <dt-bindings/net/ti-dp83867.h> / { - compatible = "ti,am654-evm", "ti,am654"; + compatible = "ti,am654-evm", "ti,am654"; model = "Texas Instruments AM654 Base Board"; chosen { @@ -73,13 +73,13 @@ pinctrl-names = "default"; pinctrl-0 = <&push_button_pins_default>; - sw5 { + switch-5 { label = "GPIO Key USER1"; linux,code = <BTN_0>; gpios = <&wkup_gpio0 24 GPIO_ACTIVE_LOW>; }; - sw6 { + switch-6 { label = "GPIO Key USER2"; linux,code = <BTN_1>; gpios = <&wkup_gpio0 27 GPIO_ACTIVE_LOW>; @@ -330,7 +330,7 @@ pinctrl-names = "default"; pinctrl-0 = <&main_spi0_pins_default>; #address-cells = <1>; - #size-cells= <0>; + #size-cells = <0>; ti,pindir-d0-out-d1-in; flash@0 { diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi index 1044ec6c4b0d..ff13bbeed30c 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi @@ -12,8 +12,8 @@ mbox-names = "rx", "tx"; - mboxes= <&secure_proxy_main 11>, - <&secure_proxy_main 13>; + mboxes = <&secure_proxy_main 11>, + <&secure_proxy_main 13>; reg-names = "debug_messages"; reg = <0x00 0x44083000 0x00 0x1000>; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts index 2bc26a296496..b1691ac3442d 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts @@ -26,13 +26,13 @@ pinctrl-names = "default"; pinctrl-0 = <&sw10_button_pins_default &sw11_button_pins_default>; - sw10: sw10 { + sw10: switch-10 { label = "GPIO Key USER1"; linux,code = <BTN_0>; gpios = <&main_gpio0 0 GPIO_ACTIVE_LOW>; }; - sw11: sw11 { + sw11: switch-11 { label = "GPIO Key USER2"; linux,code = <BTN_1>; gpios = <&wkup_gpio0 7 GPIO_ACTIVE_LOW>; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi index b4972dfb7da8..df08724bbf1c 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi @@ -12,8 +12,8 @@ mbox-names = "rx", "tx"; - mboxes= <&secure_proxy_main 11>, - <&secure_proxy_main 13>; + mboxes = <&secure_proxy_main 11>, + <&secure_proxy_main 13>; reg-names = "debug_messages"; reg = <0x00 0x44083000 0x0 0x1000>; diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi index 19966f72c5b3..34e7d577ae13 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi @@ -320,7 +320,7 @@ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 98 7>, <&k3_clks 98 1>; - clock-names = "clk_ahb", "clk_xin"; + clock-names = "clk_ahb", "clk_xin"; assigned-clocks = <&k3_clks 98 1>; assigned-clock-parents = <&k3_clks 98 2>; bus-width = <8>; @@ -347,7 +347,7 @@ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&k3_pds 99 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 99 8>, <&k3_clks 99 1>; - clock-names = "clk_ahb", "clk_xin"; + clock-names = "clk_ahb", "clk_xin"; assigned-clocks = <&k3_clks 99 1>; assigned-clock-parents = <&k3_clks 99 2>; bus-width = <4>; diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi index 6c5c02edb375..4d1bfabd1313 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi @@ -12,8 +12,8 @@ mbox-names = "rx", "tx"; - mboxes= <&secure_proxy_main 11>, - <&secure_proxy_main 13>; + mboxes = <&secure_proxy_main 11>, + <&secure_proxy_main 13>; reg-names = "debug_messages"; reg = <0x00 0x44083000 0x00 0x1000>; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi index 8493dd7d5f1f..e172fa05c9a0 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi @@ -239,6 +239,10 @@ clocks = <&zynqmp_clk LPD_WDT>; }; +&xilinx_ams { + clocks = <&zynqmp_clk AMS_REF>; +}; + &zynqmp_dpdma { clocks = <&zynqmp_clk DPDMA_REF>; }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts index 550b389153e6..20e83ca47b5d 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts @@ -52,7 +52,7 @@ gpio-keys { compatible = "gpio-keys"; autorepeat; - fwuen { + key-fwuen { label = "fwuen"; gpios = <&gpio 12 GPIO_ACTIVE_LOW>; }; @@ -285,5 +285,5 @@ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ - "", "", "", ""; /* 170 - 174 */ + "", "", "", ""; /* 170 - 173 */ }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts index f6aad4159ccd..d61a297a2090 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts @@ -49,7 +49,7 @@ gpio-keys { compatible = "gpio-keys"; autorepeat; - sw4 { + switch-4 { label = "sw4"; gpios = <&gpio 23 GPIO_ACTIVE_LOW>; linux,code = <KEY_POWER>; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts index 7b9a88b125d1..5fd6b70a154a 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts @@ -47,7 +47,7 @@ gpio-keys { compatible = "gpio-keys"; autorepeat; - sw19 { + switch-19 { label = "sw19"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; linux,code = <KEY_DOWN>; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts index 20b7c75bb1d3..e2dd72fe33ce 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts @@ -47,7 +47,7 @@ gpio-keys { compatible = "gpio-keys"; autorepeat; - sw19 { + switch-19 { label = "sw19"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; linux,code = <KEY_DOWN>; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts index e36df6adbeee..d685d8fbc36a 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts @@ -47,7 +47,7 @@ gpio-keys { compatible = "gpio-keys"; autorepeat; - sw19 { + switch-19 { label = "sw19"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; linux,code = <KEY_DOWN>; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi index c715a18368c2..a549265e55f6 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi @@ -874,6 +874,32 @@ timeout-sec = <10>; }; + xilinx_ams: ams@ffa50000 { + compatible = "xlnx,zynqmp-ams"; + status = "disabled"; + interrupt-parent = <&gic>; + interrupts = <0 56 4>; + reg = <0x0 0xffa50000 0x0 0x800>; + #address-cells = <1>; + #size-cells = <1>; + #io-channel-cells = <1>; + ranges = <0 0 0xffa50800 0x800>; + + ams_ps: ams_ps@0 { + compatible = "xlnx,zynqmp-ams-ps"; + status = "disabled"; + reg = <0x0 0x400>; + }; + + ams_pl: ams_pl@400 { + compatible = "xlnx,zynqmp-ams-pl"; + status = "disabled"; + reg = <0x400 0x400>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + zynqmp_dpdma: dma-controller@fd4c0000 { compatible = "xlnx,zynqmp-dpdma"; status = "disabled"; diff --git a/include/dt-bindings/clock/exynos7885.h b/include/dt-bindings/clock/exynos7885.h index 1f8701691d62..8256e7430b63 100644 --- a/include/dt-bindings/clock/exynos7885.h +++ b/include/dt-bindings/clock/exynos7885.h @@ -54,17 +54,39 @@ #define CLK_GOUT_PERI_USI0 43 #define CLK_GOUT_PERI_USI1 44 #define CLK_GOUT_PERI_USI2 45 -#define TOP_NR_CLK 46 +#define CLK_MOUT_FSYS_BUS 46 +#define CLK_MOUT_FSYS_MMC_CARD 47 +#define CLK_MOUT_FSYS_MMC_EMBD 48 +#define CLK_MOUT_FSYS_MMC_SDIO 49 +#define CLK_MOUT_FSYS_USB30DRD 50 +#define CLK_DOUT_FSYS_BUS 51 +#define CLK_DOUT_FSYS_MMC_CARD 52 +#define CLK_DOUT_FSYS_MMC_EMBD 53 +#define CLK_DOUT_FSYS_MMC_SDIO 54 +#define CLK_DOUT_FSYS_USB30DRD 55 +#define CLK_GOUT_FSYS_BUS 56 +#define CLK_GOUT_FSYS_MMC_CARD 57 +#define CLK_GOUT_FSYS_MMC_EMBD 58 +#define CLK_GOUT_FSYS_MMC_SDIO 59 +#define CLK_GOUT_FSYS_USB30DRD 60 +#define TOP_NR_CLK 61 /* CMU_CORE */ -#define CLK_MOUT_CORE_BUS_USER 1 -#define CLK_MOUT_CORE_CCI_USER 2 -#define CLK_MOUT_CORE_G3D_USER 3 -#define CLK_MOUT_CORE_GIC 4 -#define CLK_DOUT_CORE_BUSP 5 -#define CLK_GOUT_CCI_ACLK 6 -#define CLK_GOUT_GIC400_CLK 7 -#define CORE_NR_CLK 8 +#define CLK_MOUT_CORE_BUS_USER 1 +#define CLK_MOUT_CORE_CCI_USER 2 +#define CLK_MOUT_CORE_G3D_USER 3 +#define CLK_MOUT_CORE_GIC 4 +#define CLK_DOUT_CORE_BUSP 5 +#define CLK_GOUT_CCI_ACLK 6 +#define CLK_GOUT_GIC400_CLK 7 +#define CLK_GOUT_TREX_D_CORE_ACLK 8 +#define CLK_GOUT_TREX_D_CORE_GCLK 9 +#define CLK_GOUT_TREX_D_CORE_PCLK 10 +#define CLK_GOUT_TREX_P_CORE_ACLK_P_CORE 11 +#define CLK_GOUT_TREX_P_CORE_CCLK_P_CORE 12 +#define CLK_GOUT_TREX_P_CORE_PCLK 13 +#define CLK_GOUT_TREX_P_CORE_PCLK_P_CORE 14 +#define CORE_NR_CLK 15 /* CMU_PERI */ #define CLK_MOUT_PERI_BUS_USER 1 @@ -112,4 +134,18 @@ #define CLK_GOUT_WDT1_PCLK 43 #define PERI_NR_CLK 44 +/* CMU_FSYS */ +#define CLK_MOUT_FSYS_BUS_USER 1 +#define CLK_MOUT_FSYS_MMC_CARD_USER 2 +#define CLK_MOUT_FSYS_MMC_EMBD_USER 3 +#define CLK_MOUT_FSYS_MMC_SDIO_USER 4 +#define CLK_MOUT_FSYS_USB30DRD_USER 4 +#define CLK_GOUT_MMC_CARD_ACLK 5 +#define CLK_GOUT_MMC_CARD_SDCLKIN 6 +#define CLK_GOUT_MMC_EMBD_ACLK 7 +#define CLK_GOUT_MMC_EMBD_SDCLKIN 8 +#define CLK_GOUT_MMC_SDIO_ACLK 9 +#define CLK_GOUT_MMC_SDIO_SDCLKIN 10 +#define FSYS_NR_CLK 11 + #endif /* _DT_BINDINGS_CLOCK_EXYNOS_7885_H */ diff --git a/include/dt-bindings/clock/qcom,dispcc-sm8350.h b/include/dt-bindings/clock/qcom,dispcc-sm8350.h new file mode 120000 index 000000000000..0312b4544acb --- /dev/null +++ b/include/dt-bindings/clock/qcom,dispcc-sm8350.h @@ -0,0 +1 @@ +qcom,dispcc-sm8250.h
\ No newline at end of file diff --git a/include/dt-bindings/clock/qcom,gcc-ipq8074.h b/include/dt-bindings/clock/qcom,gcc-ipq8074.h index 8e2bec1c91bf..55f8322a1e50 100644 --- a/include/dt-bindings/clock/qcom,gcc-ipq8074.h +++ b/include/dt-bindings/clock/qcom,gcc-ipq8074.h @@ -367,4 +367,7 @@ #define GCC_PCIE1_AXI_MASTER_STICKY_ARES 130 #define GCC_PCIE0_AXI_SLAVE_STICKY_ARES 131 +#define USB0_GDSC 0 +#define USB1_GDSC 1 + #endif diff --git a/include/dt-bindings/clock/qcom,gpucc-sm8350.h b/include/dt-bindings/clock/qcom,gpucc-sm8350.h new file mode 100644 index 000000000000..2ca857f5bfd2 --- /dev/null +++ b/include/dt-bindings/clock/qcom,gpucc-sm8350.h @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2022, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8350_H +#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8350_H + +/* GPU_CC clocks */ +#define GPU_CC_AHB_CLK 0 +#define GPU_CC_CB_CLK 1 +#define GPU_CC_CRC_AHB_CLK 2 +#define GPU_CC_CX_APB_CLK 3 +#define GPU_CC_CX_GMU_CLK 4 +#define GPU_CC_CX_QDSS_AT_CLK 5 +#define GPU_CC_CX_QDSS_TRIG_CLK 6 +#define GPU_CC_CX_QDSS_TSCTR_CLK 7 +#define GPU_CC_CX_SNOC_DVM_CLK 8 +#define GPU_CC_CXO_AON_CLK 9 +#define GPU_CC_CXO_CLK 10 +#define GPU_CC_FREQ_MEASURE_CLK 11 +#define GPU_CC_GMU_CLK_SRC 12 +#define GPU_CC_GX_GMU_CLK 13 +#define GPU_CC_GX_QDSS_TSCTR_CLK 14 +#define GPU_CC_GX_VSENSE_CLK 15 +#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 16 +#define GPU_CC_HUB_AHB_DIV_CLK_SRC 17 +#define GPU_CC_HUB_AON_CLK 18 +#define GPU_CC_HUB_CLK_SRC 19 +#define GPU_CC_HUB_CX_INT_CLK 20 +#define GPU_CC_HUB_CX_INT_DIV_CLK_SRC 21 +#define GPU_CC_MND1X_0_GFX3D_CLK 22 +#define GPU_CC_MND1X_1_GFX3D_CLK 23 +#define GPU_CC_PLL0 24 +#define GPU_CC_PLL1 25 +#define GPU_CC_SLEEP_CLK 26 + +/* GPU_CC resets */ +#define GPUCC_GPU_CC_ACD_BCR 0 +#define GPUCC_GPU_CC_CB_BCR 1 +#define GPUCC_GPU_CC_CX_BCR 2 +#define GPUCC_GPU_CC_FAST_HUB_BCR 3 +#define GPUCC_GPU_CC_GFX3D_AON_BCR 4 +#define GPUCC_GPU_CC_GMU_BCR 5 +#define GPUCC_GPU_CC_GX_BCR 6 +#define GPUCC_GPU_CC_XO_BCR 7 + +/* GPU_CC GDSCRs */ +#define GPU_CX_GDSC 0 +#define GPU_GX_GDSC 1 + +#endif diff --git a/include/dt-bindings/clock/qcom,sm8450-camcc.h b/include/dt-bindings/clock/qcom,sm8450-camcc.h new file mode 100644 index 000000000000..7ff67acf301a --- /dev/null +++ b/include/dt-bindings/clock/qcom,sm8450-camcc.h @@ -0,0 +1,159 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_CAM_CC_SM8450_H +#define _DT_BINDINGS_CLK_QCOM_CAM_CC_SM8450_H + +/* CAM_CC clocks */ +#define CAM_CC_BPS_AHB_CLK 0 +#define CAM_CC_BPS_CLK 1 +#define CAM_CC_BPS_CLK_SRC 2 +#define CAM_CC_BPS_FAST_AHB_CLK 3 +#define CAM_CC_CAMNOC_AXI_CLK 4 +#define CAM_CC_CAMNOC_AXI_CLK_SRC 5 +#define CAM_CC_CAMNOC_DCD_XO_CLK 6 +#define CAM_CC_CCI_0_CLK 7 +#define CAM_CC_CCI_0_CLK_SRC 8 +#define CAM_CC_CCI_1_CLK 9 +#define CAM_CC_CCI_1_CLK_SRC 10 +#define CAM_CC_CORE_AHB_CLK 11 +#define CAM_CC_CPAS_AHB_CLK 12 +#define CAM_CC_CPAS_BPS_CLK 13 +#define CAM_CC_CPAS_FAST_AHB_CLK 14 +#define CAM_CC_CPAS_IFE_0_CLK 15 +#define CAM_CC_CPAS_IFE_1_CLK 16 +#define CAM_CC_CPAS_IFE_2_CLK 17 +#define CAM_CC_CPAS_IFE_LITE_CLK 18 +#define CAM_CC_CPAS_IPE_NPS_CLK 19 +#define CAM_CC_CPAS_SBI_CLK 20 +#define CAM_CC_CPAS_SFE_0_CLK 21 +#define CAM_CC_CPAS_SFE_1_CLK 22 +#define CAM_CC_CPHY_RX_CLK_SRC 23 +#define CAM_CC_CSI0PHYTIMER_CLK 24 +#define CAM_CC_CSI0PHYTIMER_CLK_SRC 25 +#define CAM_CC_CSI1PHYTIMER_CLK 26 +#define CAM_CC_CSI1PHYTIMER_CLK_SRC 27 +#define CAM_CC_CSI2PHYTIMER_CLK 28 +#define CAM_CC_CSI2PHYTIMER_CLK_SRC 29 +#define CAM_CC_CSI3PHYTIMER_CLK 30 +#define CAM_CC_CSI3PHYTIMER_CLK_SRC 31 +#define CAM_CC_CSI4PHYTIMER_CLK 32 +#define CAM_CC_CSI4PHYTIMER_CLK_SRC 33 +#define CAM_CC_CSI5PHYTIMER_CLK 34 +#define CAM_CC_CSI5PHYTIMER_CLK_SRC 35 +#define CAM_CC_CSID_CLK 36 +#define CAM_CC_CSID_CLK_SRC 37 +#define CAM_CC_CSID_CSIPHY_RX_CLK 38 +#define CAM_CC_CSIPHY0_CLK 39 +#define CAM_CC_CSIPHY1_CLK 40 +#define CAM_CC_CSIPHY2_CLK 41 +#define CAM_CC_CSIPHY3_CLK 42 +#define CAM_CC_CSIPHY4_CLK 43 +#define CAM_CC_CSIPHY5_CLK 44 +#define CAM_CC_FAST_AHB_CLK_SRC 45 +#define CAM_CC_GDSC_CLK 46 +#define CAM_CC_ICP_AHB_CLK 47 +#define CAM_CC_ICP_CLK 48 +#define CAM_CC_ICP_CLK_SRC 49 +#define CAM_CC_IFE_0_CLK 50 +#define CAM_CC_IFE_0_CLK_SRC 51 +#define CAM_CC_IFE_0_DSP_CLK 52 +#define CAM_CC_IFE_0_FAST_AHB_CLK 53 +#define CAM_CC_IFE_1_CLK 54 +#define CAM_CC_IFE_1_CLK_SRC 55 +#define CAM_CC_IFE_1_DSP_CLK 56 +#define CAM_CC_IFE_1_FAST_AHB_CLK 57 +#define CAM_CC_IFE_2_CLK 58 +#define CAM_CC_IFE_2_CLK_SRC 59 +#define CAM_CC_IFE_2_DSP_CLK 60 +#define CAM_CC_IFE_2_FAST_AHB_CLK 61 +#define CAM_CC_IFE_LITE_AHB_CLK 62 +#define CAM_CC_IFE_LITE_CLK 63 +#define CAM_CC_IFE_LITE_CLK_SRC 64 +#define CAM_CC_IFE_LITE_CPHY_RX_CLK 65 +#define CAM_CC_IFE_LITE_CSID_CLK 66 +#define CAM_CC_IFE_LITE_CSID_CLK_SRC 67 +#define CAM_CC_IPE_NPS_AHB_CLK 68 +#define CAM_CC_IPE_NPS_CLK 69 +#define CAM_CC_IPE_NPS_CLK_SRC 70 +#define CAM_CC_IPE_NPS_FAST_AHB_CLK 71 +#define CAM_CC_IPE_PPS_CLK 72 +#define CAM_CC_IPE_PPS_FAST_AHB_CLK 73 +#define CAM_CC_JPEG_CLK 74 +#define CAM_CC_JPEG_CLK_SRC 75 +#define CAM_CC_MCLK0_CLK 76 +#define CAM_CC_MCLK0_CLK_SRC 77 +#define CAM_CC_MCLK1_CLK 78 +#define CAM_CC_MCLK1_CLK_SRC 79 +#define CAM_CC_MCLK2_CLK 80 +#define CAM_CC_MCLK2_CLK_SRC 81 +#define CAM_CC_MCLK3_CLK 82 +#define CAM_CC_MCLK3_CLK_SRC 83 +#define CAM_CC_MCLK4_CLK 84 +#define CAM_CC_MCLK4_CLK_SRC 85 +#define CAM_CC_MCLK5_CLK 86 +#define CAM_CC_MCLK5_CLK_SRC 87 +#define CAM_CC_MCLK6_CLK 88 +#define CAM_CC_MCLK6_CLK_SRC 89 +#define CAM_CC_MCLK7_CLK 90 +#define CAM_CC_MCLK7_CLK_SRC 91 +#define CAM_CC_PLL0 92 +#define CAM_CC_PLL0_OUT_EVEN 93 +#define CAM_CC_PLL0_OUT_ODD 94 +#define CAM_CC_PLL1 95 +#define CAM_CC_PLL1_OUT_EVEN 96 +#define CAM_CC_PLL2 97 +#define CAM_CC_PLL3 98 +#define CAM_CC_PLL3_OUT_EVEN 99 +#define CAM_CC_PLL4 100 +#define CAM_CC_PLL4_OUT_EVEN 101 +#define CAM_CC_PLL5 102 +#define CAM_CC_PLL5_OUT_EVEN 103 +#define CAM_CC_PLL6 104 +#define CAM_CC_PLL6_OUT_EVEN 105 +#define CAM_CC_PLL7 106 +#define CAM_CC_PLL7_OUT_EVEN 107 +#define CAM_CC_PLL8 108 +#define CAM_CC_PLL8_OUT_EVEN 109 +#define CAM_CC_QDSS_DEBUG_CLK 110 +#define CAM_CC_QDSS_DEBUG_CLK_SRC 111 +#define CAM_CC_QDSS_DEBUG_XO_CLK 112 +#define CAM_CC_SBI_AHB_CLK 113 +#define CAM_CC_SBI_CLK 114 +#define CAM_CC_SFE_0_CLK 115 +#define CAM_CC_SFE_0_CLK_SRC 116 +#define CAM_CC_SFE_0_FAST_AHB_CLK 117 +#define CAM_CC_SFE_1_CLK 118 +#define CAM_CC_SFE_1_CLK_SRC 119 +#define CAM_CC_SFE_1_FAST_AHB_CLK 120 +#define CAM_CC_SLEEP_CLK 121 +#define CAM_CC_SLEEP_CLK_SRC 122 +#define CAM_CC_SLOW_AHB_CLK_SRC 123 +#define CAM_CC_XO_CLK_SRC 124 + +/* CAM_CC resets */ +#define CAM_CC_BPS_BCR 0 +#define CAM_CC_ICP_BCR 1 +#define CAM_CC_IFE_0_BCR 2 +#define CAM_CC_IFE_1_BCR 3 +#define CAM_CC_IFE_2_BCR 4 +#define CAM_CC_IPE_0_BCR 5 +#define CAM_CC_QDSS_DEBUG_BCR 6 +#define CAM_CC_SBI_BCR 7 +#define CAM_CC_SFE_0_BCR 8 +#define CAM_CC_SFE_1_BCR 9 + +/* CAM_CC GDSCRs */ +#define BPS_GDSC 0 +#define IPE_0_GDSC 1 +#define SBI_GDSC 2 +#define IFE_0_GDSC 3 +#define IFE_1_GDSC 4 +#define IFE_2_GDSC 5 +#define SFE_0_GDSC 6 +#define SFE_1_GDSC 7 +#define TITAN_TOP_GDSC 8 + +#endif diff --git a/include/dt-bindings/clock/tegra234-clock.h b/include/dt-bindings/clock/tegra234-clock.h index bab85d9ba8cd..173364a93381 100644 --- a/include/dt-bindings/clock/tegra234-clock.h +++ b/include/dt-bindings/clock/tegra234-clock.h @@ -38,6 +38,8 @@ * throughput and memory controller power. */ #define TEGRA234_CLK_EMC 31U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X */ +#define TEGRA234_CLK_HOST1X 46U /** @brief output of gate CLK_ENB_FUSE */ #define TEGRA234_CLK_FUSE 40U /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C1 */ @@ -132,6 +134,8 @@ #define TEGRA234_CLK_UARTA 155U /** @brief output of gate CLK_ENB_PEX1_CORE_6 */ #define TEGRA234_CLK_PEX1_C6_CORE 161U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_VIC */ +#define TEGRA234_CLK_VIC 167U /** @brief output of gate CLK_ENB_PEX2_CORE_7 */ #define TEGRA234_CLK_PEX2_C7_CORE 171U /** @brief output of gate CLK_ENB_PEX2_CORE_8 */ diff --git a/include/dt-bindings/mailbox/qcom-ipcc.h b/include/dt-bindings/mailbox/qcom-ipcc.h index 9296d0bb5f34..fbfa3febc66d 100644 --- a/include/dt-bindings/mailbox/qcom-ipcc.h +++ b/include/dt-bindings/mailbox/qcom-ipcc.h @@ -30,6 +30,7 @@ #define IPCC_CLIENT_PCIE1 14 #define IPCC_CLIENT_PCIE2 15 #define IPCC_CLIENT_SPSS 16 +#define IPCC_CLIENT_NSP1 18 #define IPCC_CLIENT_TME 23 #define IPCC_CLIENT_WPSS 24 diff --git a/include/dt-bindings/memory/tegra234-mc.h b/include/dt-bindings/memory/tegra234-mc.h index 8b0ddcb715ff..62987b47ce81 100644 --- a/include/dt-bindings/memory/tegra234-mc.h +++ b/include/dt-bindings/memory/tegra234-mc.h @@ -31,6 +31,8 @@ #define TEGRA234_SID_PCIE8 0x09 #define TEGRA234_SID_PCIE10 0x0b #define TEGRA234_SID_BPMP 0x10 +#define TEGRA234_SID_HOST1X 0x27 +#define TEGRA234_SID_VIC 0x34 /* * memory client IDs @@ -38,6 +40,7 @@ /* High-definition audio (HDA) read clients */ #define TEGRA234_MEMORY_CLIENT_HDAR 0x15 +#define TEGRA234_MEMORY_CLIENT_HOST1XDMAR 0x16 /* PCIE6 read clients */ #define TEGRA234_MEMORY_CLIENT_PCIE6AR 0x28 /* PCIE6 write clients */ @@ -86,6 +89,8 @@ #define TEGRA234_MEMORY_CLIENT_MGBEDWR 0x65 /* sdmmcd memory write client */ #define TEGRA234_MEMORY_CLIENT_SDMMCWAB 0x67 +#define TEGRA234_MEMORY_CLIENT_VICSRD 0x6c +#define TEGRA234_MEMORY_CLIENT_VICSWR 0x6d /* BPMP read client */ #define TEGRA234_MEMORY_CLIENT_BPMPR 0x93 /* BPMP write client */ diff --git a/include/dt-bindings/net/pcs-rzn1-miic.h b/include/dt-bindings/net/pcs-rzn1-miic.h new file mode 100644 index 000000000000..784782eaec9e --- /dev/null +++ b/include/dt-bindings/net/pcs-rzn1-miic.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2022 Schneider-Electric + * + * Clément Léger <clement.leger@bootlin.com> + */ + +#ifndef _DT_BINDINGS_PCS_RZN1_MIIC +#define _DT_BINDINGS_PCS_RZN1_MIIC + +/* + * Reefer to the datasheet [1] section 8.2.1, Internal Connection of Ethernet + * Ports to check the available combination + * + * [1] REN_r01uh0750ej0140-rzn1-introduction_MAT_20210228.pdf + */ + +#define MIIC_GMAC1_PORT 0 +#define MIIC_GMAC2_PORT 1 +#define MIIC_RTOS_PORT 2 +#define MIIC_SERCOS_PORTA 3 +#define MIIC_SERCOS_PORTB 4 +#define MIIC_ETHERCAT_PORTA 5 +#define MIIC_ETHERCAT_PORTB 6 +#define MIIC_ETHERCAT_PORTC 7 +#define MIIC_SWITCH_PORTA 8 +#define MIIC_SWITCH_PORTB 9 +#define MIIC_SWITCH_PORTC 10 +#define MIIC_SWITCH_PORTD 11 +#define MIIC_HSR_PORTA 12 +#define MIIC_HSR_PORTB 13 + +#endif diff --git a/include/dt-bindings/power/tegra234-powergate.h b/include/dt-bindings/power/tegra234-powergate.h index df1d4dd8dcf3..ae9286cef85c 100644 --- a/include/dt-bindings/power/tegra234-powergate.h +++ b/include/dt-bindings/power/tegra234-powergate.h @@ -19,5 +19,6 @@ #define TEGRA234_POWER_DOMAIN_MGBEB 18U #define TEGRA234_POWER_DOMAIN_MGBEC 19U #define TEGRA234_POWER_DOMAIN_MGBED 20U +#define TEGRA234_POWER_DOMAIN_VIC 29U #endif diff --git a/include/dt-bindings/reset/tegra234-reset.h b/include/dt-bindings/reset/tegra234-reset.h index bd58a05f1d94..d48d22b2bc7f 100644 --- a/include/dt-bindings/reset/tegra234-reset.h +++ b/include/dt-bindings/reset/tegra234-reset.h @@ -53,6 +53,7 @@ #define TEGRA234_RESET_MGBE3_PCS 87U #define TEGRA234_RESET_MGBE3_MAC 88U #define TEGRA234_RESET_UARTA 100U +#define TEGRA234_RESET_VIC 113U #define TEGRA234_RESET_PEX0_CORE_0 116U #define TEGRA234_RESET_PEX0_CORE_1 117U #define TEGRA234_RESET_PEX0_CORE_2 118U diff --git a/include/dt-bindings/soc/samsung,boot-mode.h b/include/dt-bindings/soc/samsung,boot-mode.h new file mode 100644 index 000000000000..47ef1cdd3916 --- /dev/null +++ b/include/dt-bindings/soc/samsung,boot-mode.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2022 Samsung Electronics Co., Ltd. + * Author: Chanho Park <chanho61.park@samsung.com> + * + * Device Tree bindings for Samsung Boot Mode. + */ + +#ifndef __DT_BINDINGS_SAMSUNG_BOOT_MODE_H +#define __DT_BINDINGS_SAMSUNG_BOOT_MODE_H + +/* Boot mode definitions for Exynos Auto v9 SoC */ + +#define EXYNOSAUTOV9_BOOT_FASTBOOT 0xfa +#define EXYNOSAUTOV9_BOOT_BOOTLOADER 0xfc +#define EXYNOSAUTOV9_BOOT_RECOVERY 0xff + +#endif /* __DT_BINDINGS_SAMSUNG_BOOT_MODE_H */ |