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| author |   Sonika Jindal <sonika.jindal@intel.com> | 2014-07-21 15:23:43 +0530 |
|---|---|---|
| committer |   Daniel Vetter <daniel.vetter@ffwll.ch> | 2014-07-23 07:05:44 +0200 |
| commit | 3abfce77f7229116fa56aedfe3b79ce5ccde3d72 (patch) | |
| tree | 31ab3eecf653e71b0f5dc27a70908201a7122387 | |
| parent | drm/i915: Returning the right VGA control reg for platforms (diff) | |
| download | wireguard-linux-3abfce77f7229116fa56aedfe3b79ce5ccde3d72.tar.xz wireguard-linux-3abfce77f7229116fa56aedfe3b79ce5ccde3d72.zip | |
drm/i915: Writing proper check for reading of pipe status reg
Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| -rw-r--r-- | drivers/gpu/drm/i915/intel_display.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index c18c2a71afac..2df686064bda 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -13225,7 +13225,7 @@ intel_display_capture_error_state(struct drm_device *dev) error->pipe[i].source = I915_READ(PIPESRC(i)); - if (!HAS_PCH_SPLIT(dev)) + if (HAS_GMCH_DISPLAY(dev)) error->pipe[i].stat = I915_READ(PIPESTAT(i)); } |