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| author |   Ville Syrjälä <ville.syrjala@linux.intel.com> | 2021-10-06 23:49:32 +0300 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2021-11-03 19:45:46 +0200 |
| commit | 3e9cf8f055fcb42776156fa5f5eb9a5326f160c9 (patch) | |
| tree | 00bf3119ad15baa1c4d51036c7da93078b6ee2ad | |
| parent | drm/i915: Query the vswing levels per-lane for tgl dkl phy (diff) | |
| download | wireguard-linux-3e9cf8f055fcb42776156fa5f5eb9a5326f160c9.tar.xz wireguard-linux-3e9cf8f055fcb42776156fa5f5eb9a5326f160c9.zip | |
drm/i915: Query the vswing levels per-lane for snps phy
Prepare for per-lane drive settings by querying the desired vswing
level per-lane.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211006204937.30774-12-ville.syrjala@linux.intel.com
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_snps_phy.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.c b/drivers/gpu/drm/i915/display/intel_snps_phy.c index 5e20f340730f..c2251218a39e 100644 --- a/drivers/gpu/drm/i915/display/intel_snps_phy.c +++ b/drivers/gpu/drm/i915/display/intel_snps_phy.c @@ -58,7 +58,6 @@ void intel_snps_phy_set_signal_levels(struct intel_encoder *encoder, struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); const struct intel_ddi_buf_trans *trans; enum phy phy = intel_port_to_phy(dev_priv, encoder->port); - int level = intel_ddi_level(encoder, crtc_state, 0); int n_entries, ln; trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); @@ -66,6 +65,7 @@ void intel_snps_phy_set_signal_levels(struct intel_encoder *encoder, return; for (ln = 0; ln < 4; ln++) { + int level = intel_ddi_level(encoder, crtc_state, ln); u32 val = 0; val |= REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, trans->entries[level].snps.vswing); |