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| author |   Michal Simek <michal.simek@amd.com> | 2024-01-08 16:39:17 +0100 |
|---|---|---|
| committer | Michal Simek <michal.simek@amd.com> | 2024-01-22 14:10:10 +0100 |
| commit | 46de36a489677dec18ecab6ae5761bb82adc56c7 (patch) | |
| tree | 2d3d67e8e1fdb8ea163fc691cbfc1f80bac4411c | |
| parent | arm64: zynqmp: Setup default si570 frequency to 156.25MHz (diff) | |
| download | wireguard-linux-46de36a489677dec18ecab6ae5761bb82adc56c7.tar.xz wireguard-linux-46de36a489677dec18ecab6ae5761bb82adc56c7.zip | |
arm64: zynqmp: Describe assigned-clocks for uarts
Describe assigned-clocks for both uarts. SOM is using this functionality.
Link: https://lore.kernel.org/r/21579f273554a19bc95a40f49956793b5261627f.1704728353.git.michal.simek@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
| -rw-r--r-- | arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi index ccaca29200bb..ca1248784f59 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi @@ -230,10 +230,12 @@ &uart0 { clocks = <&zynqmp_clk UART0_REF>, <&zynqmp_clk LPD_LSBUS>; + assigned-clocks = <&zynqmp_clk UART0_REF>; }; &uart1 { clocks = <&zynqmp_clk UART1_REF>, <&zynqmp_clk LPD_LSBUS>; + assigned-clocks = <&zynqmp_clk UART1_REF>; }; &dwc3_0 { |