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author | 2024-07-02 13:30:36 -0400 | |
---|---|---|
committer | 2024-07-23 17:07:11 -0400 | |
commit | 5d2c102deff63ff8980dfa848ee41858d255c291 (patch) | |
tree | 42fc47879bc8b2692c6e3d20a6f60e0736ff3c46 | |
parent | drm/amd/display: Refactoring MMHUBBUB (diff) | |
download | wireguard-linux-5d2c102deff63ff8980dfa848ee41858d255c291.tar.xz wireguard-linux-5d2c102deff63ff8980dfa848ee41858d255c291.zip |
drm/amd/display: Do 1-to-1 mapping between OPP and DSC in DML2
[why]
To determine which block instance to power-gate,
we look at the available pipe resource for both plane
and stream. On MPO, DSC3 was falsely powered on even
though only 1 stream path was enabled because
the resource mapping was not done correctly.
[how]
Acquire the correct DSC instance to power on / off based
on the instance of OPP which determines the backend
pipe index.
Reviewed-by: Swapnil Patel <swapnil.patel@amd.com>
Signed-off-by: Jerry Zuo <jerry.zuo@amd.com>
Signed-off-by: Sung Joon Kim <sungjoon.kim@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-rw-r--r-- | drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index 83aa3d8a997a..4f5b23520365 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -5166,7 +5166,7 @@ bool dc_resource_acquire_secondary_pipe_for_mpc_odm_legacy( sec_pipe->stream_res.opp = sec_pipe->top_pipe->stream_res.opp; if (sec_pipe->stream->timing.flags.DSC == 1) { #if defined(CONFIG_DRM_AMD_DC_FP) - dcn20_acquire_dsc(dc, &state->res_ctx, &sec_pipe->stream_res.dsc, pipe_idx); + dcn20_acquire_dsc(dc, &state->res_ctx, &sec_pipe->stream_res.dsc, sec_pipe->stream_res.opp->inst); #endif ASSERT(sec_pipe->stream_res.dsc); if (sec_pipe->stream_res.dsc == NULL) |