diff options
| author |   Dillon Varone <dillon.varone@amd.com> | 2025-01-08 15:25:41 -0500 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2025-02-12 21:02:57 -0500 |
| commit | 5f0d1ef6f16e150ee46cc00b8d233d9d271fe39e (patch) | |
| tree | 336d5fd68f87361398dc29e8f6a10e8297972742 | |
| parent | drm/amd/display: Add AS SDP programming for UHBR link rate. (diff) | |
| download | wireguard-linux-5f0d1ef6f16e150ee46cc00b8d233d9d271fe39e.tar.xz wireguard-linux-5f0d1ef6f16e150ee46cc00b8d233d9d271fe39e.zip | |
drm/amd/display: Populate register address for dentist for dcn401
[WHY&HOW]
Address was not previously populated which can result in incorrect
clock frequencies being read on boot.
Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
Signed-off-by: Dillon Varone <dillon.varone@amd.com>
Signed-off-by: Wayne Lin <wayne.lin@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c | 2 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h | 1 |
2 files changed, 3 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c index 8082bb877611..a3b8e3d4a429 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c @@ -24,6 +24,8 @@ #include "dml/dcn401/dcn401_fpu.h" +#define DCN_BASE__INST0_SEG1 0x000000C0 + #define mmCLK01_CLK0_CLK_PLL_REQ 0x16E37 #define mmCLK01_CLK0_CLK0_DFS_CNTL 0x16E69 #define mmCLK01_CLK0_CLK1_DFS_CNTL 0x16E6C diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h index 7a1ca1e98059..221645c023b5 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h @@ -221,6 +221,7 @@ enum dentist_divider_range { CLK_SF(CLK0_CLK_PLL_REQ, FbMult_frac, mask_sh) #define CLK_REG_LIST_DCN401() \ + SR(DENTIST_DISPCLK_CNTL), \ CLK_SR_DCN401(CLK0_CLK_PLL_REQ, CLK01, 0), \ CLK_SR_DCN401(CLK0_CLK0_DFS_CNTL, CLK01, 0), \ CLK_SR_DCN401(CLK0_CLK1_DFS_CNTL, CLK01, 0), \ |