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| author |   Sandeep Maheswaram <sanm@codeaurora.org> | 2021-08-02 10:32:56 +0530 |
|---|---|---|
| committer |   Bjorn Andersson <bjorn.andersson@linaro.org> | 2021-08-05 10:27:34 -0500 |
| commit | 6493367f8031b1e5cf0a217d6520c0d79a5d6659 (patch) | |
| tree | d57be33838790c64e2bc1c4cb5e0d85b7ad3ba66 | |
| parent | arm64: dts: qcom: sm8250: remove bus clock from the mdss node for sm8250 target (diff) | |
| download | wireguard-linux-6493367f8031b1e5cf0a217d6520c0d79a5d6659.tar.xz wireguard-linux-6493367f8031b1e5cf0a217d6520c0d79a5d6659.zip | |
arm64: dts: qcom: sc7280: Add interconnect properties for USB
Add interconnect properties in USB DT nodes for sc7280.
Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Link: https://lore.kernel.org/r/1627880576-22391-1-git-send-email-sanm@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
| -rw-r--r-- | arch/arm64/boot/dts/qcom/sc7280.dtsi | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 1d405c2f234f..b5a5685193c4 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -1246,6 +1246,10 @@ resets = <&gcc GCC_USB30_SEC_BCR>; + interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB2 0>; + interconnect-names = "usb-ddr", "apps-usb"; + usb_2_dwc3: usb@8c00000 { compatible = "snps,dwc3"; reg = <0 0x08c00000 0 0xe000>; @@ -1319,6 +1323,10 @@ resets = <&gcc GCC_USB30_PRIM_BCR>; + interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB3_0 0>; + interconnect-names = "usb-ddr", "apps-usb"; + usb_1_dwc3: usb@a600000 { compatible = "snps,dwc3"; reg = <0 0x0a600000 0 0xe000>; |