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authorHal Feng <hal.feng@starfivetech.com>2023-07-18 11:49:35 +0800
committerConor Dooley <conor.dooley@microchip.com>2023-07-25 08:41:54 +0100
commit65e4a0f33a5e125d90b1b69d56a9bbdd481e3fcf (patch)
tree9e7c72533cab5681c68b6893f60c8842892860df
parentriscv: dts: starfive: visionfive 2: Add configuration of gmac and phy (diff)
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riscv: dts: starfive: jh7100: Add temperature sensor node and thermal-zones
Add temperature sensor and thermal-zones support for the StarFive JH7100 SoC. Co-developed-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
-rw-r--r--arch/riscv/boot/dts/starfive/jh7100.dtsi37
1 files changed, 37 insertions, 0 deletions
diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi
index 4218621ea3b9..35ab54fb235f 100644
--- a/arch/riscv/boot/dts/starfive/jh7100.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi
@@ -80,6 +80,31 @@
};
};
+ thermal-zones {
+ cpu-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <15000>;
+
+ thermal-sensors = <&sfctemp>;
+
+ trips {
+ cpu_alert0 {
+ /* milliCelsius */
+ temperature = <75000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu_crit {
+ /* milliCelsius */
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+ };
+ };
+
osc_sys: osc_sys {
compatible = "fixed-clock";
#clock-cells = <0>;
@@ -248,5 +273,17 @@
resets = <&rstgen JH7100_RSTN_WDTIMER_APB>,
<&rstgen JH7100_RSTN_WDT>;
};
+
+ sfctemp: temperature-sensor@124a0000 {
+ compatible = "starfive,jh7100-temp";
+ reg = <0x0 0x124a0000 0x0 0x10000>;
+ clocks = <&clkgen JH7100_CLK_TEMP_SENSE>,
+ <&clkgen JH7100_CLK_TEMP_APB>;
+ clock-names = "sense", "bus";
+ resets = <&rstgen JH7100_RSTN_TEMP_SENSE>,
+ <&rstgen JH7100_RSTN_TEMP_APB>;
+ reset-names = "sense", "bus";
+ #thermal-sensor-cells = <0>;
+ };
};
};