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| author |   Zhao Qiang <qiang.zhao@nxp.com> | 2016-06-06 14:29:58 +0800 |
|---|---|---|
| committer |   David S. Miller <davem@davemloft.net> | 2016-06-07 15:56:30 -0700 |
| commit | 68f047e3d62ebfac24ff9be551476cf30eafb00e (patch) | |
| tree | 200ff1dc71af28400062c80c2c57cd38982e7d58 | |
| parent | net sched: indentation and other OCD stylistic fixes (diff) | |
| download | wireguard-linux-68f047e3d62ebfac24ff9be551476cf30eafb00e.tar.xz wireguard-linux-68f047e3d62ebfac24ff9be551476cf30eafb00e.zip | |
fsl/qe: add rx_sync and tx_sync for TDM mode
Rx_sync and tx_sync are used by QE-TDM mode,
add them to struct ucc_fast_info.
Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
| -rw-r--r-- | drivers/soc/fsl/qe/qe.c | 6 | ||||
| -rw-r--r-- | include/soc/fsl/qe/qe.h | 2 | ||||
| -rw-r--r-- | include/soc/fsl/qe/ucc_fast.h | 2 |
3 files changed, 10 insertions, 0 deletions
diff --git a/drivers/soc/fsl/qe/qe.c b/drivers/soc/fsl/qe/qe.c index 709fc63809e5..7026507e6f1d 100644 --- a/drivers/soc/fsl/qe/qe.c +++ b/drivers/soc/fsl/qe/qe.c @@ -239,6 +239,12 @@ enum qe_clock qe_clock_source(const char *source) if (strcasecmp(source, "none") == 0) return QE_CLK_NONE; + if (strcmp(source, "tsync_pin") == 0) + return QE_TSYNC_PIN; + + if (strcmp(source, "rsync_pin") == 0) + return QE_RSYNC_PIN; + if (strncasecmp(source, "brg", 3) == 0) { i = simple_strtoul(source + 3, NULL, 10); if ((i >= 1) && (i <= 16)) diff --git a/include/soc/fsl/qe/qe.h b/include/soc/fsl/qe/qe.h index 33b29ead3d55..f91874582ab3 100644 --- a/include/soc/fsl/qe/qe.h +++ b/include/soc/fsl/qe/qe.h @@ -80,6 +80,8 @@ enum qe_clock { QE_CLK22, /* Clock 22 */ QE_CLK23, /* Clock 23 */ QE_CLK24, /* Clock 24 */ + QE_RSYNC_PIN, /* RSYNC from pin */ + QE_TSYNC_PIN, /* TSYNC from pin */ QE_CLK_DUMMY }; diff --git a/include/soc/fsl/qe/ucc_fast.h b/include/soc/fsl/qe/ucc_fast.h index df8ea7958c63..31548b7aa50e 100644 --- a/include/soc/fsl/qe/ucc_fast.h +++ b/include/soc/fsl/qe/ucc_fast.h @@ -120,6 +120,8 @@ struct ucc_fast_info { int ucc_num; enum qe_clock rx_clock; enum qe_clock tx_clock; + enum qe_clock rx_sync; + enum qe_clock tx_sync; u32 regs; int irq; u32 uccm_mask; |