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| author |   Biju Das <biju.das.jz@bp.renesas.com> | 2024-08-05 14:17:06 +0100 |
|---|---|---|
| committer |   Geert Uytterhoeven <geert+renesas@glider.be> | 2024-08-23 15:52:19 +0200 |
| commit | 6bfd974d03a433e7fa9d5444f89851e4e4eb9779 (patch) | |
| tree | eaaf42965b8ff6ede3fbcc94fa9378a8ef5020f0 | |
| parent | arm64: dts: renesas: r9a07g043u: Add FCPVD node (diff) | |
| download | wireguard-linux-6bfd974d03a433e7fa9d5444f89851e4e4eb9779.tar.xz wireguard-linux-6bfd974d03a433e7fa9d5444f89851e4e4eb9779.zip | |
arm64: dts: renesas: r9a07g043u: Add VSPD node
Add VSPD node to RZ/G2UL SoC DTSI.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20240805131709.101679-3-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| -rw-r--r-- | arch/arm64/boot/dts/renesas/r9a07g043u.dtsi | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi index 4cfcef60680c..1b3db8df4bbc 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi @@ -129,6 +129,19 @@ }; }; + vspd: vsp@10870000 { + compatible = "renesas,r9a07g043u-vsp2", "renesas,r9a07g044-vsp2"; + reg = <0 0x10870000 0 0x10000>; + interrupts = <SOC_PERIPHERAL_IRQ(149) IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD R9A07G043_LCDC_CLK_A>, + <&cpg CPG_MOD R9A07G043_LCDC_CLK_P>, + <&cpg CPG_MOD R9A07G043_LCDC_CLK_D>; + clock-names = "aclk", "pclk", "vclk"; + power-domains = <&cpg>; + resets = <&cpg R9A07G043_LCDC_RESET_N>; + renesas,fcp = <&fcpvd>; + }; + fcpvd: fcp@10880000 { compatible = "renesas,r9a07g043u-fcpvd", "renesas,fcpv"; reg = <0 0x10880000 0 0x10000>; |