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| author |   Amit Kumar Mahapatra <amit.kumar-mahapatra@amd.com> | 2024-09-25 17:12:03 +0530 |
|---|---|---|
| committer |   Mark Brown <broonie@kernel.org> | 2024-09-30 01:12:24 +0200 |
| commit | 759541d78eb8d6ac12dab7df14d4434cf5756e14 (patch) | |
| tree | 8c2cc301f0c3490d92d3ba260622081308060b87 | |
| parent | spi: Switch back to struct platform_driver::remove() (diff) | |
| download | wireguard-linux-759541d78eb8d6ac12dab7df14d4434cf5756e14.tar.xz wireguard-linux-759541d78eb8d6ac12dab7df14d4434cf5756e14.zip | |
dt-bindings: spi: zynqmp-qspi: Include two 'reg' properties only for the Zynq UltraScale QSPI
Linear mode is only supported by the Zynq UltraScale QSPI controller,
so update the bindings to include two 'reg' properties only for the
Zynq UltraScale QSPI controller.
Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@amd.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Link: https://patch.msgid.link/20240925114203.2234735-1-amit.kumar-mahapatra@amd.com
Signed-off-by: Mark Brown <broonie@kernel.org>
| -rw-r--r-- | Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.yaml | 22 |
1 files changed, 19 insertions, 3 deletions
diff --git a/Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.yaml b/Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.yaml index e5199b109dad..04d4d3b4916d 100644 --- a/Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.yaml +++ b/Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.yaml @@ -9,9 +9,6 @@ title: Xilinx Zynq UltraScale+ MPSoC GQSPI controller maintainers: - Michal Simek <michal.simek@amd.com> -allOf: - - $ref: spi-controller.yaml# - properties: compatible: enum: @@ -19,6 +16,7 @@ properties: - xlnx,zynqmp-qspi-1.0 reg: + minItems: 1 maxItems: 2 interrupts: @@ -47,6 +45,24 @@ required: unevaluatedProperties: false +allOf: + - $ref: spi-controller.yaml# + + - if: + properties: + compatible: + contains: + const: xlnx,zynqmp-qspi-1.0 + then: + properties: + reg: + minItems: 2 + + else: + properties: + reg: + maxItems: 1 + examples: - | #include <dt-bindings/clock/xlnx-zynqmp-clk.h> |