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authorSheetal <sheetal@nvidia.com>2025-05-12 05:17:47 +0000
committerMark Brown <broonie@kernel.org>2025-05-22 11:02:12 +0100
commit7d852b34be4df61ae4327b47c39701d0f7ffcc70 (patch)
treebddf59a4660e72664bbc564dfe559972f2450446
parentASoC: tegra: AHUB: Add Tegra264 support (diff)
downloadwireguard-linux-7d852b34be4df61ae4327b47c39701d0f7ffcc70.tar.xz
wireguard-linux-7d852b34be4df61ae4327b47c39701d0f7ffcc70.zip
ASoC: tegra: Tegra264 support in isomgr_bw
Tegra264 supports max 32 channels, hence calculating the max bandwidth using the channel info from soc_data. Signed-off-by: Sheetal <sheetal@nvidia.com> Link: https://patch.msgid.link/20250512051747.1026770-12-sheetal@nvidia.com Signed-off-by: Mark Brown <broonie@kernel.org>
-rw-r--r--sound/soc/tegra/tegra_isomgr_bw.c7
1 files changed, 4 insertions, 3 deletions
diff --git a/sound/soc/tegra/tegra_isomgr_bw.c b/sound/soc/tegra/tegra_isomgr_bw.c
index 18e802bca6a6..fa979960bc09 100644
--- a/sound/soc/tegra/tegra_isomgr_bw.c
+++ b/sound/soc/tegra/tegra_isomgr_bw.c
@@ -11,8 +11,8 @@
#include "tegra_isomgr_bw.h"
#include "tegra210_admaif.h"
-/* Max possible rate is 192KHz x 16channel x 4bytes */
-#define MAX_BW_PER_DEV 12288
+#define MAX_SAMPLE_RATE 192 /* KHz*/
+#define MAX_BYTES_PER_SAMPLE 4
int tegra_isomgr_adma_setbw(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai, bool is_running)
@@ -98,7 +98,8 @@ int tegra_isomgr_adma_register(struct device *dev)
}
adma_isomgr->max_pcm_device = admaif->soc_data->num_ch;
- adma_isomgr->max_bw = STREAM_TYPE * MAX_BW_PER_DEV * adma_isomgr->max_pcm_device;
+ adma_isomgr->max_bw = STREAM_TYPE * MAX_SAMPLE_RATE * MAX_BYTES_PER_SAMPLE *
+ admaif->soc_data->max_stream_ch * adma_isomgr->max_pcm_device;
for (i = 0; i < STREAM_TYPE; i++) {
adma_isomgr->bw_per_dev[i] = devm_kzalloc(dev, adma_isomgr->max_pcm_device *