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| author |   Shubhrajyoti Datta <shubhrajyoti.datta@amd.com> | 2025-06-25 11:11:14 +0530 |
|---|---|---|
| committer |   Stephen Boyd <sboyd@kernel.org> | 2025-07-26 23:51:52 -0700 |
| commit | 7f5e9ca0a424af44a708bb4727624d56f83ecffa (patch) | |
| tree | 9630c130c3be6cd8e683d7171169783e6916a850 | |
| parent | clk: Fix typos (diff) | |
| download | wireguard-linux-7f5e9ca0a424af44a708bb4727624d56f83ecffa.tar.xz wireguard-linux-7f5e9ca0a424af44a708bb4727624d56f83ecffa.zip | |
clk: clocking-wizard: Fix the round rate handling for versal
Fix the `clk_round_rate` implementation for Versal platforms by calling
the Versal-specific divider calculation helper. The existing code used
the generic divider routine, which results in incorrect round rate.
Fixes: 7681f64e6404 ("clk: clocking-wizard: calculate dividers fractional parts")
Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>
Link: https://lore.kernel.org/r/20250625054114.28273-1-shubhrajyoti.datta@amd.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| -rw-r--r-- | drivers/clk/xilinx/clk-xlnx-clock-wizard.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/xilinx/clk-xlnx-clock-wizard.c b/drivers/clk/xilinx/clk-xlnx-clock-wizard.c index bbf7714480e7..0295a13a811c 100644 --- a/drivers/clk/xilinx/clk-xlnx-clock-wizard.c +++ b/drivers/clk/xilinx/clk-xlnx-clock-wizard.c @@ -669,7 +669,7 @@ static long clk_wzrd_ver_round_rate_all(struct clk_hw *hw, unsigned long rate, u32 m, d, o, div, f; int err; - err = clk_wzrd_get_divisors(hw, rate, *prate); + err = clk_wzrd_get_divisors_ver(hw, rate, *prate); if (err) return err; |