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| author |   Charlie Jenkins <charlie@rivosinc.com> | 2024-11-13 18:21:17 -0800 |
|---|---|---|
| committer |   Palmer Dabbelt <palmer@rivosinc.com> | 2025-01-18 12:33:36 -0800 |
| commit | 7fa00fd6ff5366b50dcba2525b9743e1612da2aa (patch) | |
| tree | e464b9edfcf4b7bb56279ae0a834554a1ba92b1b | |
| parent | riscv: hwprobe: Add thead vendor extension probing (diff) | |
| download | wireguard-linux-7fa00fd6ff5366b50dcba2525b9743e1612da2aa.tar.xz wireguard-linux-7fa00fd6ff5366b50dcba2525b9743e1612da2aa.zip | |
riscv: hwprobe: Document thead vendor extensions and xtheadvector extension
Document support for thead vendor extensions using the key
RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0 and xtheadvector extension using
the key RISCV_HWPROBE_VENDOR_EXT_XTHEADVECTOR.
Signed-off-by: Charlie Jenkins <charlie@rivosinc.com>
Reviewed-by: Evan Green <evan@rivosinc.com>
Tested-by: Yangyu Chen <cyy@cyyself.name>
Link: https://lore.kernel.org/r/20241113-xtheadvector-v11-11-236c22791ef9@rivosinc.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
| -rw-r--r-- | Documentation/arch/riscv/hwprobe.rst | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst index 955fbcd19ce9..f273ea15a8e8 100644 --- a/Documentation/arch/riscv/hwprobe.rst +++ b/Documentation/arch/riscv/hwprobe.rst @@ -293,3 +293,13 @@ The following keys are defined: * :c:macro:`RISCV_HWPROBE_MISALIGNED_VECTOR_UNSUPPORTED`: Misaligned vector accesses are not supported at all and will generate a misaligned address fault. + +* :c:macro:`RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0`: A bitmask containing the + thead vendor extensions that are compatible with the + :c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_IMA`: base system behavior. + + * T-HEAD + + * :c:macro:`RISCV_HWPROBE_VENDOR_EXT_XTHEADVECTOR`: The xtheadvector vendor + extension is supported in the T-Head ISA extensions spec starting from + commit a18c801634 ("Add T-Head VECTOR vendor extension. "). |