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authorOlof Johansson <olof@lixom.net>2014-03-11 14:21:28 -0700
committerOlof Johansson <olof@lixom.net>2014-03-11 14:21:43 -0700
commit813004a3f18d06fffa118c0be1941fc66ec6326e (patch)
treed51a0bd6f1250fa2ab7a6e2bd295a7734ee87e61
parentMerge tag 'omap-for-v3.15/dt-part2' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/dt (diff)
parentarm: dt: zynq: Add fclk-enable property to clkc node (diff)
downloadwireguard-linux-813004a3f18d06fffa118c0be1941fc66ec6326e.tar.xz
wireguard-linux-813004a3f18d06fffa118c0be1941fc66ec6326e.zip
Merge tag 'zynq-dt-for-3.15' of git://git.xilinx.com/linux-xlnx into next/dt
Merge "arm: Xilinx Zynq dt patches for v3.15" from Michal Simek: - Define fclk-enable property * tag 'zynq-dt-for-3.15' of git://git.xilinx.com/linux-xlnx: arm: dt: zynq: Add fclk-enable property to clkc node Signed-off-by: Olof Johansson <olof@lixom.net>
-rw-r--r--arch/arm/boot/dts/zynq-7000.dtsi1
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi
index 8b67b19392ec..93d1980a755d 100644
--- a/arch/arm/boot/dts/zynq-7000.dtsi
+++ b/arch/arm/boot/dts/zynq-7000.dtsi
@@ -134,6 +134,7 @@
#clock-cells = <1>;
compatible = "xlnx,ps7-clkc";
ps-clk-frequency = <33333333>;
+ fclk-enable = <0>;
clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
"cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
"dci", "lqspi", "smc", "pcap", "gem0", "gem1",