diff options
| author |   Mikko Perttunen <mperttunen@nvidia.com> | 2026-07-01 12:20:33 +0900 |
|---|---|---|
| committer |   Uwe Kleine-König <ukleinek@kernel.org> | 2026-07-14 11:29:26 +0200 |
| commit | 83a4cadc7ae5512262930bbbc2d802e8eef1dc93 (patch) | |
| tree | 46f8e4df22f13ff068729171c95dfbe0b12f6e49 | |
| parent | pwm: tegra: Avoid hard-coded max clock frequency (diff) | |
pwm: tegra: Modify read/write accessors for multi-register channel
On Tegra264, each PWM instance has two registers (per channel, of which
there is one). Update the tegra_pwm_readl/tegra_pwm_writel helper
functions to take channel (as struct pwm_device *) and offset
separately.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Tested-by: Jon Hunter <jonathanh@nvidia.com>
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Link: https://patch.msgid.link/20260701-t264-pwm-v6-4-2718f61f411f@nvidia.com
Signed-off-by: Uwe Kleine-König <ukleinek@kernel.org>
| -rw-r--r-- | drivers/pwm/pwm-tegra.c | 26 |
1 files changed, 15 insertions, 11 deletions
diff --git a/drivers/pwm/pwm-tegra.c b/drivers/pwm/pwm-tegra.c index 3eef299c51f8..55a3e8657013 100644 --- a/drivers/pwm/pwm-tegra.c +++ b/drivers/pwm/pwm-tegra.c @@ -57,6 +57,8 @@ #define TEGRA_PWM_SCALE_WIDTH 13 #define TEGRA_PWM_SCALE_SHIFT 0 +#define TEGRA_PWM_CSR_0 0 + struct tegra_pwm_soc { unsigned int num_channels; }; @@ -78,14 +80,18 @@ static inline struct tegra_pwm_chip *to_tegra_pwm_chip(struct pwm_chip *chip) return pwmchip_get_drvdata(chip); } -static inline u32 tegra_pwm_readl(struct tegra_pwm_chip *pc, unsigned int offset) +static inline u32 tegra_pwm_readl(struct pwm_device *pwm, unsigned int offset) { - return readl(pc->regs + (offset << 4)); + struct tegra_pwm_chip *chip = to_tegra_pwm_chip(pwm->chip); + + return readl(chip->regs + (pwm->hwpwm * 16) + offset); } -static inline void tegra_pwm_writel(struct tegra_pwm_chip *pc, unsigned int offset, u32 value) +static inline void tegra_pwm_writel(struct pwm_device *pwm, unsigned int offset, u32 value) { - writel(value, pc->regs + (offset << 4)); + struct tegra_pwm_chip *chip = to_tegra_pwm_chip(pwm->chip); + + writel(value, chip->regs + (pwm->hwpwm * 16) + offset); } static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, @@ -194,7 +200,7 @@ static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, } else val |= TEGRA_PWM_ENABLE; - tegra_pwm_writel(pc, pwm->hwpwm, val); + tegra_pwm_writel(pwm, TEGRA_PWM_CSR_0, val); /* * If the PWM is not enabled, turn the clock off again to save power. @@ -207,7 +213,6 @@ static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, static int tegra_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) { - struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip); int rc = 0; u32 val; @@ -215,21 +220,20 @@ static int tegra_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) if (rc) return rc; - val = tegra_pwm_readl(pc, pwm->hwpwm); + val = tegra_pwm_readl(pwm, TEGRA_PWM_CSR_0); val |= TEGRA_PWM_ENABLE; - tegra_pwm_writel(pc, pwm->hwpwm, val); + tegra_pwm_writel(pwm, TEGRA_PWM_CSR_0, val); return 0; } static void tegra_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) { - struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip); u32 val; - val = tegra_pwm_readl(pc, pwm->hwpwm); + val = tegra_pwm_readl(pwm, TEGRA_PWM_CSR_0); val &= ~TEGRA_PWM_ENABLE; - tegra_pwm_writel(pc, pwm->hwpwm, val); + tegra_pwm_writel(pwm, TEGRA_PWM_CSR_0, val); pm_runtime_put_sync(pwmchip_parent(chip)); } |