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| author |   Michael Krummsdorf <michael.krummsdorf@tq-group.com> | 2020-06-10 13:38:37 +0200 |
|---|---|---|
| committer |   Stephen Boyd <sboyd@kernel.org> | 2020-07-27 18:25:17 -0700 |
| commit | 92df3a9bf3fd975949122b1779c142c2d007a7dc (patch) | |
| tree | 39ef28ebdc7488849ad4052dc5118253f857b30b | |
| parent | Linux 5.8-rc1 (diff) | |
| download | wireguard-linux-92df3a9bf3fd975949122b1779c142c2d007a7dc.tar.xz wireguard-linux-92df3a9bf3fd975949122b1779c142c2d007a7dc.zip | |
clk: qoriq: add LS1021A core pll mux options
This allows to clock the cores with 1 GHz, 500 MHz and 250 MHz.
Signed-off-by: Michael Krummsdorf <michael.krummsdorf@tq-group.com>
Signed-off-by: Matthias Schiffer <matthias.schiffer@ew.tq-group.com>
Link: https://lore.kernel.org/r/20200610113837.27117-1-matthias.schiffer@ew.tq-group.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| -rw-r--r-- | drivers/clk/clk-qoriq.c | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/drivers/clk/clk-qoriq.c b/drivers/clk/clk-qoriq.c index 374afcab89af..5942e9874bc0 100644 --- a/drivers/clk/clk-qoriq.c +++ b/drivers/clk/clk-qoriq.c @@ -244,6 +244,14 @@ static const struct clockgen_muxinfo clockgen2_cmux_cgb = { }, }; +static const struct clockgen_muxinfo ls1021a_cmux = { + { + { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 }, + { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 }, + { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 }, + } +}; + static const struct clockgen_muxinfo ls1028a_hwa1 = { { { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 }, @@ -577,7 +585,7 @@ static const struct clockgen_chipinfo chipinfo[] = { { .compat = "fsl,ls1021a-clockgen", .cmux_groups = { - &t1023_cmux + &ls1021a_cmux }, .cmux_to_group = { 0, -1 |