diff options
| author |   Paul Barker <paul.barker.ct@bp.renesas.com> | 2024-06-25 21:03:14 +0100 |
|---|---|---|
| committer |   Geert Uytterhoeven <geert+renesas@glider.be> | 2024-08-02 11:13:24 +0200 |
| commit | 96a3f525708120379013d9d3265663c07ceb38d5 (patch) | |
| tree | f89042eb0c36188988b11e6eb23858451093289f | |
| parent | arm64: dts: renesas: rzg2ul: Enable Ethernet TXC output (diff) | |
| download | wireguard-linux-96a3f525708120379013d9d3265663c07ceb38d5.tar.xz wireguard-linux-96a3f525708120379013d9d3265663c07ceb38d5.zip | |
arm64: dts: renesas: rzg2l: Set Ethernet PVDD to 1.8V
On the RZ/G2L & RZ/V2L SMARC SOMs, the RGMII interface between the SoC
and the Ethernet PHY operates at 1.8V.
The power supply for this interface may be correctly configured in
u-boot, but the kernel should not be relying on this. Now that the
RZ/G2L pinctrl driver supports configuring the Ethernet power supply
voltage, we can simply specify the desired voltage in the device tree.
Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/20240625200316.4282-8-paul.barker.ct@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| -rw-r--r-- | arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi | 18 |
1 files changed, 14 insertions, 4 deletions
diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi index 2b5e037ea9fa..83f5642d0d35 100644 --- a/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi @@ -182,6 +182,7 @@ eth0_pins: eth0 { txc { pinmux = <RZG2L_PORT_PINMUX(20, 0, 1)>; /* ET0_TXC */ + power-source = <1800>; output-enable; }; @@ -199,14 +200,19 @@ <RZG2L_PORT_PINMUX(25, 0, 1)>, /* ET0_RXD0 */ <RZG2L_PORT_PINMUX(25, 1, 1)>, /* ET0_RXD1 */ <RZG2L_PORT_PINMUX(26, 0, 1)>, /* ET0_RXD2 */ - <RZG2L_PORT_PINMUX(26, 1, 1)>, /* ET0_RXD3 */ - <RZG2L_PORT_PINMUX(1, 0, 1)>; /* IRQ2 */ + <RZG2L_PORT_PINMUX(26, 1, 1)>; /* ET0_RXD3 */ + power-source = <1800>; + }; + + irq { + pinmux = <RZG2L_PORT_PINMUX(1, 0, 1)>; /* IRQ2 */ }; }; eth1_pins: eth1 { txc { pinmux = <RZG2L_PORT_PINMUX(29, 0, 1)>; /* ET1_TXC */ + power-source = <1800>; output-enable; }; @@ -224,8 +230,12 @@ <RZG2L_PORT_PINMUX(34, 1, 1)>, /* ET1_RXD0 */ <RZG2L_PORT_PINMUX(35, 0, 1)>, /* ET1_RXD1 */ <RZG2L_PORT_PINMUX(35, 1, 1)>, /* ET1_RXD2 */ - <RZG2L_PORT_PINMUX(36, 0, 1)>, /* ET1_RXD3 */ - <RZG2L_PORT_PINMUX(1, 1, 1)>; /* IRQ3 */ + <RZG2L_PORT_PINMUX(36, 0, 1)>; /* ET1_RXD3 */ + power-source = <1800>; + }; + + irq { + pinmux = <RZG2L_PORT_PINMUX(1, 1, 1)>; /* IRQ3 */ }; }; |