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| author |   Dmitry Osipenko <digetx@gmail.com> | 2020-08-23 17:47:23 +0300 |
|---|---|---|
| committer |   Thierry Reding <treding@nvidia.com> | 2020-09-17 18:09:38 +0200 |
| commit | a252efadf3e7ffa8f5793cb431f35bb95bdc4795 (patch) | |
| tree | fe38a27c833c1b56ae9b34a6c8027f723ed82b00 | |
| parent | ARM: tegra: acer-a500: Correct PINCTRL configuration (diff) | |
| download | wireguard-linux-a252efadf3e7ffa8f5793cb431f35bb95bdc4795.tar.xz wireguard-linux-a252efadf3e7ffa8f5793cb431f35bb95bdc4795.zip | |
ARM: tegra: acer-a500: Set WiFi MMC clock rate to 50 MHz
Previously 50MHz clock rate didn't work because of the wrong PINCTRL
configuration used for SDIO pins. Now the PINCTRL config is corrected
and the MMC clock rate could be bumped safely to 50MHz, increasing WiFi
TX throughput by 20 Mbit/s and allowing to hit the maximum 40 Mbit/s.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
| -rw-r--r-- | arch/arm/boot/dts/tegra20-acer-a500-picasso.dts | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts index bc7c1d082828..9489eedcf0c9 100644 --- a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts +++ b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts @@ -736,7 +736,7 @@ #address-cells = <1>; #size-cells = <0>; - max-frequency = <25000000>; + max-frequency = <50000000>; keep-power-in-suspend; bus-width = <4>; non-removable; |