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| author |   Jordan Crouse <jcrouse@codeaurora.org> | 2020-11-09 11:47:27 -0700 |
|---|---|---|
| committer |   Will Deacon <will@kernel.org> | 2020-11-10 12:25:49 +0000 |
| commit | a29bbb0861f487a5e144dc997a9f71a36c7a2404 (patch) | |
| tree | 44a3f82c3cf1407f0c2f22728307a8a88b95159b | |
| parent | iommu/arm-smmu: Add a way for implementations to influence SCTLR (diff) | |
| download | wireguard-linux-a29bbb0861f487a5e144dc997a9f71a36c7a2404.tar.xz wireguard-linux-a29bbb0861f487a5e144dc997a9f71a36c7a2404.zip | |
dt-bindings: arm-smmu: Add compatible string for Adreno GPU SMMU
Every Qcom Adreno GPU has an embedded SMMU for its own use. These
devices depend on unique features such as split pagetables,
different stall/halt requirements and other settings. Identify them
with a compatible string so that they can be identified in the
arm-smmu implementation specific code.
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20201109184728.2463097-4-jcrouse@codeaurora.org
Signed-off-by: Will Deacon <will@kernel.org>
| -rw-r--r-- | Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml index 503160a7b9a0..3b63f2ae24db 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml @@ -28,8 +28,6 @@ properties: - enum: - qcom,msm8996-smmu-v2 - qcom,msm8998-smmu-v2 - - qcom,sc7180-smmu-v2 - - qcom,sdm845-smmu-v2 - const: qcom,smmu-v2 - description: Qcom SoCs implementing "arm,mmu-500" @@ -40,6 +38,13 @@ properties: - qcom,sm8150-smmu-500 - qcom,sm8250-smmu-500 - const: arm,mmu-500 + - description: Qcom Adreno GPUs implementing "arm,smmu-v2" + items: + - enum: + - qcom,sc7180-smmu-v2 + - qcom,sdm845-smmu-v2 + - const: qcom,adreno-smmu + - const: qcom,smmu-v2 - description: Marvell SoCs implementing "arm,mmu-500" items: - const: marvell,ap806-smmu-500 |