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| author |   Cyan Yang <cyan.yang@sifive.com> | 2025-04-18 13:32:32 +0800 |
|---|---|---|
| committer |   Palmer Dabbelt <palmer@rivosinc.com> | 2025-05-08 11:01:43 -0700 |
| commit | a5a15e07cbb900b59fbdb927189d24d1d01ad2e7 (patch) | |
| tree | e4bfd4e19b9a606d277b7d1df21e01de33c0e488 | |
| parent | riscv: hwprobe: Add SiFive vendor extension support and probe for xsfqmaccdod and xsfqmaccqoq (diff) | |
| download | wireguard-linux-a5a15e07cbb900b59fbdb927189d24d1d01ad2e7.tar.xz wireguard-linux-a5a15e07cbb900b59fbdb927189d24d1d01ad2e7.zip | |
dt-bindings: riscv: Add xsfvfnrclipxfqf ISA extension description
Add "xsfvfnrclipxfqf" ISA extension which is provided by SiFive for
FP32-to-int8 ranged clip instructions support.
Signed-off-by: Cyan Yang <cyan.yang@sifive.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20250418053239.4351-6-cyan.yang@sifive.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
| -rw-r--r-- | Documentation/devicetree/bindings/riscv/extensions.yaml | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml index d36e7c68d69a..be203df29eb8 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -675,6 +675,12 @@ properties: See more details in https://www.sifive.com/document-file/sifive-int8-matrix-multiplication-extensions-specification + - const: xsfvfnrclipxfqf + description: + SiFive FP32-to-int8 Ranged Clip Instructions Extensions Specification. + See more details in + https://www.sifive.com/document-file/fp32-to-int8-ranged-clip-instructions + # T-HEAD - const: xtheadvector description: |