diff options
| author |   Tudor Ambarus <tudor.ambarus@linaro.org> | 2024-01-19 11:11:28 +0000 |
|---|---|---|
| committer |   Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> | 2024-01-23 13:53:18 +0100 |
| commit | af5c317a93ef168c105bd28afdd675e962244591 (patch) | |
| tree | d6fade479a32faaf5c98ef2f67c0642f46485fb7 | |
| parent | arm64: dts: exynos: gs101: define Multi Core Timer (MCT) node (diff) | |
| download | wireguard-linux-af5c317a93ef168c105bd28afdd675e962244591.tar.xz wireguard-linux-af5c317a93ef168c105bd28afdd675e962244591.zip | |
arm64: dts: exynos: gs101: remove reg-io-width from serial
Remove the reg-io-width property in order to comply with the bindings.
The entire bus (PERIC) on which the GS101 serial resides only allows
32-bit register accesses. The reg-io-width dt property is disallowed
for the "google,gs101-uart" compatible and instead the iotype is
inferred from the compatible.
Reviewed-by: Peter Griffin <peter.griffin@linaro.org>
Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Link: https://lore.kernel.org/r/20240119111132.1290455-5-tudor.ambarus@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
| -rw-r--r-- | arch/arm64/boot/dts/exynos/google/gs101.dtsi | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi index 4b09e740b58a..d6a2644d0b48 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -386,7 +386,6 @@ serial_0: serial@10a00000 { compatible = "google,gs101-uart"; reg = <0x10a00000 0xc0>; - reg-io-width = <4>; interrupts = <GIC_SPI 634 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&dummy_clk 0>, <&dummy_clk 0>; |