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| author |   Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> | 2024-03-21 16:46:30 +0530 |
|---|---|---|
| committer |   Bjorn Andersson <andersson@kernel.org> | 2024-04-21 12:31:41 -0500 |
| commit | b328bf2595db3bdba87df52ca1a9db431ee99c34 (patch) | |
| tree | 776445cd9a6bbb9ff808b1447e52e98fe009fc4e | |
| parent | arm64: dts: qcom: sc8280xp: Add PCIe bridge node (diff) | |
| download | wireguard-linux-b328bf2595db3bdba87df52ca1a9db431ee99c34.tar.xz wireguard-linux-b328bf2595db3bdba87df52ca1a9db431ee99c34.zip | |
arm64: dts: qcom: msm8998: Add PCIe bridge node
On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge
for each controller instance. Hence, add a node to represent the bridge.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240321-pcie-qcom-bridge-dts-v2-10-1eb790c53e43@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
| -rw-r--r-- | arch/arm64/boot/dts/qcom/msm8998.dtsi | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index 4dfe2d09ac28..d795b2bbe133 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -972,6 +972,16 @@ power-domains = <&gcc PCIE_0_GDSC>; iommu-map = <0x100 &anoc1_smmu 0x1480 1>; perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie_phy: phy@1c06000 { |