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| author |   Linus Walleij <linus.walleij@linaro.org> | 2022-02-11 23:32:31 +0100 |
|---|---|---|
| committer | Linus Walleij <linus.walleij@linaro.org> | 2022-02-12 18:20:03 +0100 |
| commit | b50113cbdd1340c31e85e4cfc5f5e81ce9cbb2aa (patch) | |
| tree | 413f185e8e2dedef5cfbd7663222f8e5e64c4cec | |
| parent | ARM: ixp4xx: Drop UDC info setting function (diff) | |
| download | wireguard-linux-b50113cbdd1340c31e85e4cfc5f5e81ce9cbb2aa.tar.xz wireguard-linux-b50113cbdd1340c31e85e4cfc5f5e81ce9cbb2aa.zip | |
soc: ixp4xx: Add features from regmap helper
If we want to read the CFG2 register on the expansion bus and
apply the inversion and check for some hardcoded versions this
helper comes in handy.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20220211223238.648934-7-linus.walleij@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| -rw-r--r-- | include/linux/soc/ixp4xx/cpu.h | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/include/linux/soc/ixp4xx/cpu.h b/include/linux/soc/ixp4xx/cpu.h index 88bd8de0e803..48c2e241ac83 100644 --- a/include/linux/soc/ixp4xx/cpu.h +++ b/include/linux/soc/ixp4xx/cpu.h @@ -9,6 +9,7 @@ #define __SOC_IXP4XX_CPU_H__ #include <linux/io.h> +#include <linux/regmap.h> #ifdef CONFIG_ARM #include <asm/cputype.h> #endif @@ -23,6 +24,9 @@ #define IXP46X_PROCESSOR_ID_VALUE 0x69054200 /* including IXP455 */ #define IXP46X_PROCESSOR_ID_MASK 0xfffffff0 +/* Feature register in the expansion bus controller */ +#define IXP4XX_EXP_CNFG2 0x2c + /* "fuse" bits of IXP_EXP_CFG2 */ /* All IXP4xx CPUs */ #define IXP4XX_FEATURE_RCOMP (1 << 0) @@ -89,6 +93,22 @@ u32 ixp4xx_read_feature_bits(void); void ixp4xx_write_feature_bits(u32 value); +static inline u32 cpu_ixp4xx_features(struct regmap *rmap) +{ + u32 val; + + regmap_read(rmap, IXP4XX_EXP_CNFG2, &val); + /* For some reason this register is inverted */ + val = ~val; + if (cpu_is_ixp42x_rev_a0()) + return IXP42X_FEATURE_MASK & ~(IXP4XX_FEATURE_RCOMP | + IXP4XX_FEATURE_AES); + if (cpu_is_ixp42x()) + return val & IXP42X_FEATURE_MASK; + if (cpu_is_ixp43x()) + return val & IXP43X_FEATURE_MASK; + return val & IXP46X_FEATURE_MASK; +} #else #define cpu_is_ixp42x_rev_a0() 0 #define cpu_is_ixp42x() 0 @@ -101,6 +121,10 @@ static inline u32 ixp4xx_read_feature_bits(void) static inline void ixp4xx_write_feature_bits(u32 value) { } +static inline u32 cpu_ixp4xx_features(struct regmap *rmap) +{ + return 0; +} #endif #endif /* _ASM_ARCH_CPU_H */ |