diff options
| author |   Mukesh Ojha <mukesh.ojha@oss.qualcomm.com> | 2026-05-08 13:57:28 +0530 |
|---|---|---|
| committer |   Bjorn Andersson <andersson@kernel.org> | 2026-07-15 15:13:41 -0500 |
| commit | b8d47a9d22d22631c66877a686404ce4ae53dfbb (patch) | |
| tree | 1e763c9a1e667b1a03abb8b7a9c455d0e2b971bb | |
| parent | arm64: dts: qcom: kaanapali-qrd: Add PMIC Glink node (diff) | |
arm64: dts: qcom: kaanapali: Switch SCMI perf protocol to use power-domain-cells
The SCMI protocol@13 (Performance Domain Management) node was using
performance/power domain, not a clock. This was using the older
mechanism for passing the SCMI performance domain index to
scmi-cpufreq, which predates the #power-domain-cells support added
in commit 92b2028b00ff ("cpufreq: scmi: Add support to parse
domain-id using #power-domain-cells").
Switch to #power-domain-cells to match all other Qualcomm platforms
(sm8750, glymur, hamoa) and align with the semantically correct
representation.
Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260508082729.37674-1-mukesh.ojha@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
| -rw-r--r-- | arch/arm64/boot/dts/qcom/kaanapali.dtsi | 44 |
1 files changed, 18 insertions, 26 deletions
diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/qcom/kaanapali.dtsi index ec5330297c7e..74699bc3eadb 100644 --- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi +++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi @@ -45,9 +45,8 @@ reg = <0x0 0x0>; enable-method = "psci"; next-level-cache = <&l2_0>; - power-domains = <&cpu_pd0>; - power-domain-names = "psci"; - clocks = <&pdp_scmi_perf 0>; + power-domains = <&cpu_pd0>, <&scmi_perf 0>; + power-domain-names = "psci", "perf"; #cooling-cells = <2>; l2_0: l2-cache { @@ -63,9 +62,8 @@ reg = <0x0 0x100>; enable-method = "psci"; next-level-cache = <&l2_0>; - power-domains = <&cpu_pd1>; - power-domain-names = "psci"; - clocks = <&pdp_scmi_perf 0>; + power-domains = <&cpu_pd1>, <&scmi_perf 0>; + power-domain-names = "psci", "perf"; #cooling-cells = <2>; }; @@ -75,9 +73,8 @@ reg = <0x0 0x200>; enable-method = "psci"; next-level-cache = <&l2_0>; - power-domains = <&cpu_pd2>; - power-domain-names = "psci"; - clocks = <&pdp_scmi_perf 0>; + power-domains = <&cpu_pd2>, <&scmi_perf 0>; + power-domain-names = "psci", "perf"; #cooling-cells = <2>; }; @@ -87,9 +84,8 @@ reg = <0x0 0x300>; enable-method = "psci"; next-level-cache = <&l2_0>; - power-domains = <&cpu_pd3>; - power-domain-names = "psci"; - clocks = <&pdp_scmi_perf 0>; + power-domains = <&cpu_pd3>, <&scmi_perf 0>; + power-domain-names = "psci", "perf"; #cooling-cells = <2>; }; @@ -99,9 +95,8 @@ reg = <0x0 0x400>; enable-method = "psci"; next-level-cache = <&l2_0>; - power-domains = <&cpu_pd4>; - power-domain-names = "psci"; - clocks = <&pdp_scmi_perf 0>; + power-domains = <&cpu_pd4>, <&scmi_perf 0>; + power-domain-names = "psci", "perf"; #cooling-cells = <2>; }; @@ -111,9 +106,8 @@ reg = <0x0 0x500>; enable-method = "psci"; next-level-cache = <&l2_0>; - power-domains = <&cpu_pd5>; - power-domain-names = "psci"; - clocks = <&pdp_scmi_perf 0>; + power-domains = <&cpu_pd5>, <&scmi_perf 0>; + power-domain-names = "psci", "perf"; #cooling-cells = <2>; }; @@ -123,9 +117,8 @@ reg = <0x0 0x10000>; enable-method = "psci"; next-level-cache = <&l2_1>; - power-domains = <&cpu_pd6>; - power-domain-names = "psci"; - clocks = <&pdp_scmi_perf 1>; + power-domains = <&cpu_pd6>, <&scmi_perf 1>; + power-domain-names = "psci", "perf"; #cooling-cells = <2>; l2_1: l2-cache { @@ -141,9 +134,8 @@ reg = <0x0 0x10100>; enable-method = "psci"; next-level-cache = <&l2_1>; - power-domains = <&cpu_pd7>; - power-domain-names = "psci"; - clocks = <&pdp_scmi_perf 1>; + power-domains = <&cpu_pd7>, <&scmi_perf 1>; + power-domain-names = "psci", "perf"; #cooling-cells = <2>; }; @@ -243,9 +235,9 @@ #address-cells = <1>; #size-cells = <0>; - pdp_scmi_perf: protocol@13 { + scmi_perf: protocol@13 { reg = <0x13>; - #clock-cells = <1>; + #power-domain-cells = <1>; }; }; }; |